VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras FEATURES 1 • • • • • • • • • CCD Signal Processing: – 36-MHz Correlated Double Sampling (CDS) 16-Bit Analog-to Digital Conversion: – 36-MHz Conversion Rate – No Missing Codes Ensured 80-dB Input-Referred SNR (at 12-dB Gain) Programmable Black Level Clamping Programmable Gain Amplifier (PGA): – –9 dB to +44 dB –3 dB to +18 dB by Analog Front Gain –6 dB to +26 dB by Digital Gain Timing Generator: – Fully Programmable VRATE Timing by Serial I/O – Default Timing Supports Standard Operation – Flexible VRATE Pin Assignment – HD/VD Master or Slave Mode – External Trigger, Strobe Function Support – Flexible Draft or Pixel Summing Operation RG and HG Driver: – Programmable Drivability Control – Two Horizontal Transfer Independent Drivers – One Reset Gate Driver CCD Horizontal High-Speed Clock Phase Control: – Fine Step: 0.28 ns – Wide Step: 1/3 Pixel Rate Vertical CCD Driver: – 8-Channel VDRIVER with Sub-Driver – Supports Three-Field CCD Driving – Three Level Drivers (VTRANSFER) × 5 – Two Level Drivers (VTRANSFER) × 3 – Two Level Drivers (ESHUTTER) × 1 – 450 pF to 1890 pF with 60 Ω to 240 Ω • • Flexible Voltage Operation: – AFET + TG: 2.7 V to 3.6 V – VL: –5.0 V to –9.0 V – VM: GND – VH: 11.5 V to 15.5 V – Low Power: 139 mW at 3.0 V, 36 MHz – Stand-By + Power-Save Mode: 36 mW – Stand-By Mode (MCK Off): 10 mW BGA-100 Package DESCRIPTION The VSP01M01 and VSP01M02 are complete mixed-signal ICs for charge-coupled device (CCD) signal processing with a built-in CCD timing generator, analog-to-digital converter (ADC), and CCD vertical driver. The AFE CCD channel has correlated double sampling to extract image information from the CCD output signal. Signal paths have gains ranging from –9 dB to +44 dB. The black level clamping circuit enables accurate black reference level and quick black level recovery after gain changes. An input signal clamp with CDS offset adjustment function is available. The system synchronizes the master clock, horizontal driver (HD), and vertical driver (VD). The VSP01M01 and VSP01M02 support all signal terminals required by CCD architecture. The RG driver, HG driver, and vertical driver synchronize the ADC clock phase in order to realize ideal performance. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING VSP01M01ZWD (2) BGA-100 ZWD –25°C to +85°C VSP01M01 VSP01M01GWD BGA-100 GWD –25°C to +85°C VSP01M01 VSP01M02ZWD (2) BGA-100 ZWD –25°C to +85°C VSP01M02 (1) (2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY VSP01M01ZWD Tray, 360 VSP01M01ZWDR Tape and Reel VSP01M01GWD Tray, 360 VSP01M01GWDR Tape and Reel VSP01M02ZWD Tray, 360 VSP01M02ZWDR Tape and Reel For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. The package is Pb-free. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. PARAMETER Supply voltage VSP01M01, VSP01M02 UNIT AVDD –0.3 to +4.0 V DRVDD –0.3 to +4.0 V VDD5 –0.3 to +6.0 V VL GND to –10 V VH VL + 26 V Supply voltage differences AVDD, DRVDD ±0.1 V Ground voltage differences VSS ±0.1 V Digital input voltage –0.3 to (DVDD + 0.3) V Analog input voltage –0.3 to (AVDD + 0.3) V ±10 mA Ambient temperature under bias –25 to +85 °C Storage temperature –55 to +125 °C Junction temperature +150 °C Package temperature (IR reflow, peak) +250 °C Input current (any pins except supplies) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range, unless otherwise noted. PARAMETER Analog supply voltage Digital supply voltage Driver supply voltage MIN TYP MAX AVDD 2.7 3.0 3.6 V DVDD 2.7 3.0 3.6 V VDD5 3.0 5.5 V VL –9.0 –5.0 V VH 11.5 15.5 V Digital input logic family Digital input clock frequency CMOS MCK 12 SCLK Digital output load capacitance Operating free-air temperature 2 UNIT TA –25 Submit Documentation Feedback 36 MHz 20 MHz 10 pF +85 °C Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 ELECTRICAL CHARACTERISTICS All specifications at TA = +25°C, all power supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. VSP01M01ZWD, VSP01M01GWD, VSP01M02ZWD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution VSP01M01 only 10 Bits VSP01M02 only 12 Bits CONVERSION/CLOCK RATE Conversion/clock rate 36 MHz ANALOG INPUT (CCDIN) Input signal level for full-scale out CDS gain = 0 dB, DPGA gain = 0 dB 1000 mV Maximum input range CDS gain = –3 dB, DPGA gain = 0 dB 1300 mV Input capacitance 15 Input limit –0.3 pF 3.3 V TRANSFER CHARACTERISTICS Differential nonlinearity Integral nonlinearity DNL CDS gain = 0 dB, DPGA gain = 0 dB INL CDS gain = 0 dB, DPGA gain = 0 dB No missing codes LSB ±0.5 LSB Ensured Step response settling time Full-scale step input 1 Pixel Step input from 1.8 V to 0 V 2 Pixels 9 Clocks Grounded input capacitor, PGA gain = 0 dB 76 dB Grounded input capacitor, analog gain = +12 dB 68 dB Overload recovery time Data latency Signal-to-noise ratio (1) ±0.25 CCD offset correction range –200 200 mV INPUT CLAMP Clamp on-resistance 400 Ω Clamp level 1.5 V PROGRAMMABLE ANALOG FRONT GAIN (CDS) Minimum gain Gain code = 111b –3 dB Default gain Gain code = 000b 0 dB Medium gain 1 Gain code = 001b 6 dB Medium gain 2 Gain code = 010b 12 dB Maximum gain Gain code = 011b 18 dB 0.5 dB Gain control error PROGRAMMABLE DIGITAL GAIN (DPGA) Programmable gain range –6 Gain step 26 dB 0.03125 dB 10 Bits 40.7 µs OPTICAL BLACK CLAMP LOOP Control DAC resolution Loop time constant Programmable range of clamp level Optical black clamp level (VSP01M01 only) LSB LSB OB level program step 2 LSB OBCLP level at code = 01000b OB level program step (1) 78 32 Programmable range of clamp level Optical black clamp level (VSP01M02 only) 16 OBCLP level at code = 01000b 64 312 LSB 128 LSB 8 LSB SNR = 20 log (full-scale voltage/rms noise). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 3 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, all power supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. VSP01M01ZWD, VSP01M01GWD, VSP01M02ZWD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS Logic family Input voltage Input current CMOS VT+ Low to high threshold voltage 1.7 VT– High to low threshold voltage 1.0 IIH Logic high, VIN = +3 V ±20 µA IIL Logic low, VIN = 0 V ±20 µA Input capacitance Maximum input voltage –0.3 V V 5 pF DVDD + 0.3 V DIGITAL OUTPUTS (DATA) Logic family CMOS Logic coding Output voltage Straight Binary VOH VOL Additional output data delay Logic high 2.4 V Logic low 0.4 V Output data delay code = 00b 0 ns Output data delay code = 01b 2 ns Output data delay code = 10b 4 ns Output data delay code = 11b 6 ns Logic high (VOH) IOH = 0 mA VDD5 – 0.05 V Logic high (VOH) IOH = –6.8 mA VDD5 – 0.6 HDRIVER OUTPUTS Output voltage RG, HL Logic low (VOL) IOL = 6.8 mA Output voltage (HG1A, HG1B, HG2A, HG2B) V 0.4 V Logic high (VOH) IOH = 0 mA VDD5 – 0.05 V Logic high (VOH) IOH = –13.6 mA (max), –6.8 mA (min) VDD5 – 0.6 V Logic low (VOL) IOL = 13.6 mA (max), 6.8 mA (min) 0.4 V TG OUTPUTS Output voltage (V0N-V12N, P0-P5, SUBN, FIELD, STROBE, MSHUT, SUBSW1, SUBSW2, ADCCK, HD, VD) Logic high (VOH) IOH = –1.7 mA Logic low (VOL) IOL = 1.7 mA Logic high (VOH) IOH = –1.7 mA TP output voltage (TPP, TPD) DVDD – 0.6 V 0.4 DVDD – 0.6 Logic low (VOL) IOL = 1.7 mA V V 0.4 V VDRIVER OUTPUTS Output current (V1, V2, V3A, V3B, V4, V5A, V5B, V6) (VL = –9.0 V, VM = 0 V, VH = 15.5 V) 4 IOL V1, V2, V3A, V3B, V4, V5A, V5B, V6 = –8.1 V IOM1 V1, V2, V3A, V3B, V4, V5A, V5B, V6 = –0.2 V IOM2 V1, V3A, V3B, V5A, V5B = 0.2 V IOH V1, V3A, V3B, V5A, V5B = 14.55 V IOSL SUB = –8.1 V IOSH SUB = 14.55 V Submit Documentation Feedback 10 mA –5.0 5 mA mA –7.2 5.4 mA mA –4 mA Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, all power supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. VSP01M01ZWD, VSP01M01GWD, VSP01M02ZWD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.7 3.0 3.6 V POWER SUPPLY AVDD DVDD Supply voltage VDD5 for HG1A, HG1B, HG2A, HG2B, HL, RG 3.0 5.5 V VL for V1, V2, V3A, V3B, V4, V5A, V5B, V6 –9 –5 V VH for V1, V2, V3A, V3B, V4, V5A, V5B, V6 11.5 15.5 V Power dissipation AFE Power dissipation TG + H, RDRIVER Power dissipation VDRIVER Normal operation mode: no CCD load (at 3.0 V, 38 MHz) mW 50 mW 4 mW 139 mW Standby + power-save mode (at 3.0 V, 38 MHz) 36 mW Master clock off mode (at 3.0 V) 10 mW Power dissipation (total) without CCD load Power dissipation (total) 85 TEMPERATURE RANGE Operating temperature Thermal resistance –25 θJA At 165 mW power dissipation with load +85 46.18 °C °C/W SWITCHING CHARACTERISTICS All specifications at TA = +25°C, all power supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. PARAMETER Propagation delay time Rise time Fall time Output noise voltage TEST CONDITIONS MIN TYP MAX UNIT tPLM 15 100 ns tPMH 20 100 ns tPLH 20 100 ns tPML 15 50 ns tPHM 30 50 ns tPHL 30 50 ns tTLM VL → VM 300 ns tTMH VM → VH 300 ns tTLH VL → VH 300 ns tTML VM → VL 300 ns tTHM VH → VM 300 ns tTHL VH → VL 300 ns VCLH 2.0 V VCLL 2.0 V VCMH 2.0 V VCML 2.0 V VCHL 2.0 V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 5 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com PIN CONFIGURATION VSP01M01ZWD, VSP01M01GWD BGA PACKAGE (BOTTOM VIEW) 1 2 3 4 5 6 7 8 9 10 A DAC1 V12N CH2N V6N NC V1N V0N NC NC CH0N B DAC2 V11N V10N V8N V7N CH1N NC CH3N B8 NC C CCDIN CCDGND V9N V3N V4N V2N CH5N B9 B6 B7 D COB BYP BYP2 AVDD DVSS DVSS DRVDD CH4N B4 B5 E CM BYPM REFN AVDD AVSS AVSS DRVDD B3 B1 B2 F REFP V5N NC AVDD AVSS AVSS DRVDD V2 B0 SUB G BYPD V3B TPD DVSS VL VH VDD5 VSS5 VSS5 NC H TPP SYSRST RLOAD V5A V3A STROBE VDD5 V6 RG H1A J SDATA SCLK TRIG VD SUBSW1 MSHUT SUBN HL V4 ADCCK K MCK CS HD SUBSW2 V1 FIELD V5B H2A H1B H2B PIN CONFIGURATION VSP01M02ZWD BGA PACKAGE (BOTTOM VIEW) 6 1 2 3 4 5 6 7 8 9 10 A DAC1 V12N CH2N V6N NC V1N V0N NC NC CH0N B DAC2 V11N V10N V8N V7N CH1N NC CH3N B10 B1 C CCDIN CCDGND V9N V3N V4N V2N CH5N B11 B8 B9 D COB BYP BYP2 AVDD DVSS DVSS DRVDD CH4N B6 B7 E CM BYPM REFN AVDD AVSS AVSS DRVDD B5 B3 B4 F REFP V5N NC AVDD AVSS AVSS DRVDD V2 B2 SUB G BYPD V3B TPD DVSS VL VH VDD5 VSS5 VSS5 B0 V5A V3A STROBE VDD5 V6 RG H1A H TPP SYSRST RLOAD J SDATA SCLK TRIG VD SUBSW1 MSHUT SUBN HL V4 ADCCK K MCK CS HD SUBSW2 V1 FIELD V5B H2A H1B H2B Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Table 1. TERMINAL FUNCTIONS TERMINAL (1) (2) (3) (4) NAME PIN TYPE (1) DAC1 A1 DO DAC1 output DESCRIPTION V12N A2 DO Vertical rate signal 12N CH2N A3 DO Universal vertical rate signal 2N (for V3A) V6N A4 DO Vertical rate signal 6N (for V6) NC A5 — No connection V1N A6 DO Vertical rate signal 1N (for V1) V0N A7 DO Vertical rate signal 0N NC A8 — No connection NC A9 — No connection CH0N A10 DO Universal vertical rate signal 0N DAC2 B1 DO DAC2 output V11N B2 DO Vertical rate signal 11N V10N B3 DO Vertical rate signal 10N V8N B4 DO Vertical rate signal 8N V7N B5 DO Vertical rate signal 7N CH1N B6 DO Universal vertical rate signal 1N (for V1) NC B7 — No connection CH3N B8 DO Universal vertical rate signal 3N (for V5A) B8 B9 DO Data out bit 8 (VSP01M01 only) B10 B9 DO Data out bit 10 (VSP01M02 only) NC B10 — No connection (VSP01M01 only) B1 B10 DO Data out bit 1 (VSP01M02 only) CCDIN C1 AI CCD signal input CCDGND C2 AI CCD signal input ground V9N C3 DO Vertical rate signal 9N V3N C4 DO Vertical rate signal 3N (for V3A, V3B) V4N C5 DO Vertical rate signal 4N (for V4) V2N C6 DO Vertical rate signal 2N (for V2) CH5N C7 DO Universal vertical rate signal 5N (for V5B) B9 C8 DO Data out bit 9 (MSB) (VSP01M01 only) B11 C8 DO Data out bit 11 (MSB) (VSP01M02 only) B6 C9 DO Data out bit 6 (VSP01M01 only) B8 C9 DO Data out bit 8 (VSP01M02 only) B7 C10 DO Data out bit 7 (VSP01M01 only) B9 C10 DO Data out bit 9 (VSP01M02 only) COB D1 AO OB loop feedback capacitor (2) BYP D2 AO Internal reference (3) BYP2 D3 AO Internal reference (4) AVDD D4 P Analog power supply DVSS D5 P Ground DVSS D6 P Ground Designators by type: P: power-supply and ground, DI: digital input, DO: digital output, DI/O: digital input and output, AI: analog input, AO: analog output, and VDO: VDRIVER digital output. Should be connected to ground with a bypass capacitor. The recommended value is 0.1 µF to 0.22 µF; however, actual value depends on the application environment. Refer to the OB Loop and OB Clamp Level section for more detail. Should be connected to ground with a bypass capacitor (0.1 µF). Refer to the Voltage Reference section for more detail. Should be connected to ground with a bypass capacitor. The recommended value is 400 pF to 1000 pF; however, actual value depends on the application environment. Refer to the Voltage Reference section for more detail. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 7 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Table 1. TERMINAL FUNCTIONS (continued) TERMINAL (5) (6) 8 NAME PIN TYPE (1) DRVDD D7 P CH4N D8 DO Universal vertical rate signal 4N (for V3B) B4 D9 DO Data out bit 4 (VSP01M01 only) B6 D9 DO Data out bit 6 (VSP01M02 only) B5 D10 DO Data out bit 5 (VSP01M01 only) DESCRIPTION Digital output power supply B7 D10 DO Data out bit 7 (VSP01M02 only) CM E1 AO Internal reference (3) BYPM E2 AO Internal reference (4) REFN E3 AO Internal reference (3) AVDD E4 P Analog power supply AVSS E5 P Ground AVSS E6 P Ground DRVDD E7 P Digital output power supply B3 E8 DO Data out bit 3 (VSP01M01 only) B5 E8 DO Data out bit 5 (VSP01M02 only) B1 E9 DO Data out bit 1 (VSP01M01 only) B3 E9 DO Data out bit 3 (VSP01M02 only) B2 E10 DO Data out bit 2 (VSP01M01 only) B4 E10 DO Data out bit 4 (VSP01M02 only) REFP F1 AO Internal reference (5) V5N F2 DO Vertical rate signal 5N (for V5A, V5B) NC F3 — No connection AVDD F4 P Analog power supply AVSS F5 P Ground AVSS F6 P Ground DRVDD F7 P Digital output power supply V2 F8 VDO B0 F9 DO Data out bit 0 (LSB) (VSP01M01 only) B2 F9 DO Data out bit 2 (VSP01M02 only) VDRIVER out 2 SUB F10 VDO BYPD G1 AO VDRIVER out for CCD electric shutter DLL bypass (6) V3B G2 VDO VDRIVER out 3B TPD G3 DO DVSS G4 P Test pin for SHD, CLPDM, HDIV Ground VL G5 P VDRIVER power supply VH G6 P VDRIVER power supply VDD5 G7 P Digital power supply VSS5 G8 P Digital ground VSS5 G9 P Digital ground NC G10 — No connection (VSP01M01 only) B0 G10 DO Data out bit 0 (LSB) (VSP01M02 only) TPP H1 DO Test pin for SHP, CLPOB, PBLK, HBLK SYSRST H2 DI Asynchronous reset RLOAD H3 DI Register load Should be connected to ground with a bypass capacitor (0.1 µF). Refer to the Voltage Reference section for more detail. Should be connected to ground with a bypass capacitor. The recommended value is 1000 pF to 0.1 µF; however, actual value depends on the application environment. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Table 1. TERMINAL FUNCTIONS (continued) TERMINAL NAME PIN TYPE (1) V5A H4 VDO VDRIVER out 5A V3A H5 VDO VDRIVER out 3A STROBE H6 DO VDD5 H7 P V6 H8 VDO DESCRIPTION Strobe signal Digital power supply VDRIVER out 6 RG H9 DO CCD reset gate signal H1A H10 DO CCD horizontal transfer signal 1A SDATA J1 DI Serial data SCLK J2 DI Serial data clock TRIG J3 DI External trigger VD J4 DI/O Vertical sync SUBSW1 J5 DO CCD substrate signal switch 1 MSHUT J6 DO Mechanical shutter signal SUBN J7 DO CCD electric shutter (for SUB) HL J8 DO CCD horizontal transfer signal V4 J9 VDO ADCCK J10 DO VDRIVER out 4 Clock for digital output buffer MCK K1 DI Master clock CS K2 DI Chip select HD K3 DI/O Horizontal sync SUBSW2 K4 DO CCD substrate signal switch 2 V1 K5 VDO FIELD K6 DO V5B K7 VDO H2A K8 DO CCD horizontal transfer signal 2A H1B K9 DO CCD horizontal transfer signal 1B H2B K10 DO CCD horizontal transfer signal 2B VDRIVER out 1 Field index signal VDRIVER out 5B Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 9 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com FUNCTIONAL BLOCK DIAGRAM BYP2 COB BYP BYPM REFP CM REFN BYPD VDD5 AVDD DRVDD Internal Reference Buffer Current DAC Decoder Digital Output DPGA and Output Register CCD Out Signal PBLK 16-Bit ADC CDS CCDIN ADCCK CLPOB Gain Setting SHP/SHD ADCCK CCGND Clamp CLPDM RG HL HG1A HG2A HG1 HG2 MCK SDATA Horizontal Timing Generator and Driver SCLK CS Serial Interface and Register TRIG STDBY RLOAD HDIV HBLK Drive HD VD P0-P5 V0N-V12N FIELD STROBE MSHUT SUBSW1 SUBSW2 SYSRST Vertical Timing Generator DAC OUTPUT 1 8-Bit DAC DAC OUTPUT 2 8-Bit DAC SUBN SUB SUB V1 V1 V2 V2 V3A V3A V3B V3B V4 V4 V5A V5A V5B V5B V6 V6 P1 V1N V2N P2 VDRIVER V3N P4 V4N P3 V5N P5 V6N VSS 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 TIMING CHARACTERISTICS TG HIGH-SPEED PULSE TIMING tMCKP MCK tRGW tCKP/4 tCKP/2 tMCKPG tCKP RG tH1R HG1 HL tH1F HG2 tH2R tH2F tLHR N (pix) CCD tS tPF tPR SHP tS tDR SHD tDF tADCKR tINHIBIT ADCCK tHOLD tOD B[9:0] B[11:0] B[15:0] NOTE: Dashed lines indicate programmable parameters. Figure 1. TG High-Speed Pulse Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 11 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Table 2. Timing Characteristics for Figure 1 PARAMETER (1) (2) (3) 12 MIN tMCKP MCK clock period tMCKRG MCK rising edge to RG rising edge (1) tCKP Pixel rate tRGW RG rising edge to RG falling edge (2) tH1R RG rising edge to HG1 rising edge (2) –16tCKP/100 tH1F RG rising edge to HG1 falling edge (2) tCKP/2 – 16tCKP/100 tH2R RG rising edge to HG2 rising edge (2) tCKP/2 – 16tCKP/100 tH2F (2) TYP 27.7 UNIT 83.3 ns 14 27.7 RG rising edge to HG2 falling edge MAX tCKP/4 – 16tCKP/100 ns 83.3 ns tCKP/4 + 15tCKP/100 ns 0 15tCKP/100 ns tCKP/2 tCKP/2 + 15tCKP/100 ns tCKP/2 tCKP/2 + 15tCKP/100 ns tCKP/4 –16tCKP/100 0 +15tCKP/100 ns tLHR RG rising edge to HL rising edge (2) –16tCKP/100 0 +15tCKP/100 ns tLHF RG rising edge to HL falling edge (2) tCKP/2 – 16tCKP/100 tCKP/2 tCKP/2 + 15tCKP/100 ns tPF RG rising edge to SHP falling edge (2) tCKP/4 – 16tCKP/100 tCKP/4 tCKP/4 + 15tCKP/100 + 6 ns tPR RG rising edge to SHP rising edge (2) tCKP/2 – 16tCKP/100 tCKP/2 tCKP/2 + 15tCKP/100 + 6 ns tDF RG rising edge to SHD falling edge (2) 3tCKP/4 – 24tCKP/100 3tCKP/4 – 8tCKP/100 3tCKP/4 + 7tCKP/100 + 6 ns tDR RG rising edge to SHD rising edge (2) –24tCKP/100 –8tCKP/100 7tCKP/100 + 6 ns tADCKR RG rising edge to ADCCK rising edge (3) –50tCKP/100 0 49tCKP/100 ns tS Sampling delay for SHP and SHD tINHIBIT Inhibited clock period tADC ADCCK duty tDOD Data out delay (register setting 002h) tHOLD Output hold time tOD Output delay (no load) DL Data latency 3 4 7 ns 10 ns 6 ns 50 0 0 % 2 + tDOD ns 27 + tDOD 9 (fixed) ns tCKP cycles Pulse phase can be programmed through the serial interface. RG pulse width can be programmed through the serial interface. Refer to the High-Speed Pulse Adjustment section of the TG (Timing Generator) Section for details. ADCCK phase can also be programmed as a 90-degree step through the serial interface. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 SLAVE MODE: VD, HD SPECIFICATIONS VD, HD Detect The odd field of the two-field CCD operation and the first field of the even field operation is detected by the VD and HD phase. The delay limit of the VD and HD phase is specified in Figure 2 and Figure 3. tVD VD MCK tODD HD-VD tODD VD-HD VD After HD tHD HD HD After VD HD Figure 2. VD, HD Falling Edge Detect VD MCK tODD HD-VD tODD VD-HD VD After HD HD HD After VD HD Figure 3. VD, HD Rising Edge Detect Table 3. Timing Characteristics for Figure 2 and Figure 3 (1) PARAMETER (1) MIN TYP MAX UNIT tVD VD trail-to-trail 10 τ (MCK cycles) tHD HD trail-to-trail 10 τ (MCK cycles) 0 1 6 τ (MCK cycles) 0 1 6 τ (MCK cycles) tODD HD-VD VD trail delay limit for ODD detect (register setting 02Fh[2:0]) tODD HD-VD HD trail delay limit for ODD detect (register setting 02Fh[5:3]) The VD, HD edge is detected by the rising edge of MCK. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 13 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com HCOUNTER Reset HCOUNTER is reset via HD detection. The timing is shown in Figure 4 and Figure 5. tHCNT-latency HD MCK tCH3 tCH1 N - 1 (pix) P[12:0] N (pix) Start (pix) M (H) H[11:0] M + 1 (H) Figure 4. HD Falling Edge Detect tHCNT-latency HD MCK tCH3 tCH1 N - 1 (pix) P[12:0] N (pix) Start (pix) M (H) H[11:0] M + 1 (H) Figure 5. HD Rising Edge Detect Table 4. Timing Characteristics for Figure 4 and Figure 5 (1) REGISTER PARAMETER 14 MCK EDGE 020h[2] MIN MAX UNIT tCH1 HD falling edge to MCK rising edge 0 (falling) 0 (rising) –6 1 ns tCH2 HD rising edge to MCK rising edge 1 (rising) 0 (rising) –6 1 ns tCH3 HD falling edge to MCK falling edge 0 (falling) 1 (falling) –4 3 ns tCH4 HD rising edge to MCK falling edge 1 (rising) 1 (falling) –4 3 ns tHCNT- HCOUNTER reset latency (register setting 034h[3:0]) — — LATENCY (1) VD, HD EDGE 020h[3] TYP 6 τ (MCK cycles) HCOUNTER reset timing is selected by MCK edge polarity. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 MASTER MODE: HD, VD SPECIFICATIONS The HD, VD MCK timing is shown in Figure 6 and Figure 7. VD tMCK-VD tMCK-VD MCK Figure 6. VD MCK Specification HD tMCK-HD tMCK-HD MCK Figure 7. HD MCK Specification Table 5. Timing Characteristics for Figure 6 and Figure 7 PARAMETER MIN TYP MAX UNIT tMCK-VD MCK rising edge to VD falling edge 10 ns tMCK-HD MCK rising edge to HD falling edge 10 ns SERIAL INTERFACE TIMING SPECIFICATION The serial interface has two writing modes: standard and continuous write. These modes are shown in Figure 8 and Figure 9. tXS tXH tXS CS tXHS tCKH tCKL tCKP SCLK tDS SDATA tDH Address LSB Address MSB 10 Bits Data LSB Data MSB Data Width tDLLC tDLLC tDLLC Activated Sent DATA Toggling of HA Figure 8. Standard Mode Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 15 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com CS SCLK Address LSB SDATA Address MSB Data MSB Data LSB Data Width 10 Bits Activated Sent DATA Data LSB Data MSB Data Width tDLLC tDLLC Toggling of HA tDLLC tDLLC tDLLC Figure 9. Continuous Write Mode Timing Table 6. Timing Characteristics for Figure 8 and Figure 9 PARAMETER MIN TYP MAX UNIT tCKP Clock period 50 ns tCKH Clock high pulse width 25 ns tCKL Clock low pulse width 25 ns tDS Data setup time 15 ns tDH Data hold time 15 ns tXS SLOAD to SCLK setup time 20 ns tXH SCLK to CS hold time 20 ns tXHS CS width 20 tDLLC Data load latency clock ns 10 MCK CLK Data shift operation should decode at the rising edges of SCLK while CS is low. Parallel latch timing for each mode is described in Table 7. Table 7. Parallel Latch MODE PARALLEL LATCH TIMING Standard write Rising edge of CS Continuous write End of data (MSB) In addition to the parallel latch, there are several registers dedicated to the specific features of the device; these registers are synchronized with MCK. It takes less than 10 clock cycles for the data in the parallel latch to be written to these registers. Therefore, to complete the data updates, it requires less than 10 clock cycles after parallel latching. Toggling of HA is inhibited from parallel latch. Refer to the Serial interface (SPI) section of the Common Section for details. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 EQUIVALENT CIRCUITS Figure 10 shows the HG1A, HG1B, HG2A, and HG2B high-speed driver and load model. The driver supports up to 150 pF. Figure 11 shows the RG and HL high-speed driver and load model. The driver supports up to 10 pF. Figure 10. HG Driver and Load Model RR CR 10pF Figure 11. RG Driver and Load Model Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 17 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com COMMON SECTION REGISTER/MEMORY MAP Figure 12 shows the TG register/memory map, which has 1024 words of 32-bit instruction (max). The 256-word register area enables active instruction, which requires dynamic operation. The 768-word memory area enables static instruction, which is almost fixed during a frame rate. Address Data 22 Bits (maximum) 10-Bit 000h 00 0000 0000b 6-Bit Register (active control) 192 Words (maximum) 0BFh 00 1011 1111b 0C0h 00 1100 0000b 0FFh 00 1111 1111b 100h 01 0000 0000b 16-Bit Register (reserved) 64 Words (maximum) #1 (100h) #2 (120h) #3 (140h) 17Fh 01 0111 1111b #4 (160h) 180h 01 1000 0000b VA1 (180h) Memory [vertical high-speed transfer(HS) #1-4] 128 Words (maximum) VA2 (190h) VA3 (1A0h) VA4 (1B0h) Memory (vertical timing: VA1-VA8) VA5 (1C0h) 128 Words (maximum) (1) VA6 (1D0h) VA7 (1E0h) 1FFh 01 1111 1111b VA8 (1F0h) 200h 10 0000 0000b HA Address 0 Memory (horizontal timing: HA) 512 Words (maximum) 3FFh 11 1111 1111b 511 NOTE: Shaded cells indicate the area under discussion. (1) Refer to the TG Instruction Hierarchy section of the TG (Timing Generator) Section for details. Figure 12. VSP01M01/VSP01M02 TG Register/Memory Map 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 SERIAL INTERFACE (SPI) The SPI functions and timings are controlled through the serial interface, which is composed of three signals: SDATA, SCLK, and CS. SDATA data are sequentially stored to the shift register at the rising edge of SCLK. Before a write operation, CS must go low, and remain low during writing. Refer to Serial Interface Timing Specification for further details. The serial interface command is composed of a 10-bit address and 6-bit, 16-bit, or 22-bit data. Table 8 shows the data width for each address area. Table 8. Address Data Width (1) ADDRESS (10-Bit) (1) DATA WIDTH (Bits) USAGE 000h-0BFh 6 Register 100h-17Fh 16 HS memory 180h-3FFh 22 HA and VA memory Refer to Register/Memory Map for details. The SPI has two write modes: standard and continuous. Standard Write Mode The VSP01M01 and VSP01M02 support a standard write mode, as shown in Figure 13. Normally, a serial interface command is sent by one address and data combination. The 10-bit address should primarily be sent LSB first; the following 6-bit, 16-bit, or 22-bit data should also sent LSB first. 6-bit, 16-bit, or 22-bit data are stored in the respective register by the 10-bit address at the rising edge of CS. The stored serial command data change immediately at rising edge of CS or are reserved by programmable control. If the data bit does not contain either 6-bits, 16-bits, or 22-bits at the end of the data stream, any empty data bits are ignored. CS CS SCLK SCLK SDATA A0 A9 10-Bit Address D0 D5 A0 SDATA A9 10-Bit Address 6-Bit Data D0 D21 22-Bit Data b) 22-Bit Memory Area a) 6-Bit Register Area CS SCLK SDATA A0 A9 10-Bit Address D0 D15 16-Bit Data c) 16-Bit Memory Area Figure 13. SPI Standard Write Mode Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 19 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Continuous Write Mode These devices also support a continuous write mode, as shown in Figure 14. When the input serial data are longer than one set of instructions, the following data stream is automatically recognized as the data of the next address. In this mode, 6-bit, 16-bit, or 22-bit serial command data are stored to the respective registers immediately when those data are fetched. Address and data should be sent LSB first, in the same way as standard write mode. If the data bit does not contain either 6-bits, 16-bits, or 22-bits at the end of the data stream, any empty data bits are ignored. CS SCLK SDATA A0 A9 D0 10-Bit Address D5 D0 6-Bit Data D5 D0 6-Bit Data D5 6-Bit Data a) 6-Bit Register Area CS SCLK SDATA A0 A9 D0 10-Bit Address D15 D0 16-Bit Data D15 D0 16-Bit Data D15 16-Bit Data b) 16-Bit Memory Area CS SCLK SDATA A0 A9 10-Bit Address D0 D21 22-Bit Data D0 D21 D0 22-Bit Data D21 22-Bit Data c) 22-Bit Memory Area Figure 14. SPI Continuous Write Mode 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Mode Confusion If 22 bits of data are sent to a 6-bit register area, the SPI recognizes continuous write mode, because usually only 6-bit data should be sent to 6-bit register area in standard write mode, as shown in Figure 15. The end-of-data point is recognized by the rising edge of CS. CS A0 SDATA A9 D0 D21 10-Bit Address (6-Bit Register Area) SPI Recognition A0 22-Bit Data A9 D0 10-Bit Address (Add A) D5 D0 6-Bit Data (Store to Add A) D5 D0 6-Bit Data (Store to Add A + 1) D5 D0 6-Bit Data (Store to Add A + 2) D3 Ignored Figure 15. Mode Confusion SPI recognition is shown in Table 9. Table 9. SPI Recognition DATA WIDTH (1) (2) (3) ADDRESS AREA 6-BIT 16-BIT 22-BIT 32-BIT 6-bit register Standard (1) (one word) Continuous (2) (two words) Continuous (three words) Continuous (five words) 16-bit memory Ignored Standard (one word) Standard (3) (one word) Continuous (two words) 22-bit memory Ignored Ignored Standard (one word) Standard (one word) Shaded cells indicate standard operation. Continuous = continuous write mode. Standard = standard write mode. Read and Write Batting Address 100h-3FFh is the memory area. HA, VA, and HS access this memory area to read programs. If the SPI writes to the memory area during a program read, the programmed operation is cancelled. SPI operation should be done with TG disable. If SPI operation must be done with TG enable (TG operating), the SPI must write for a no-read term (no toggling term). For the register area (000h-0FFh), this precaution is not necessary. REGISTER UPDATE The update timing of each register is specified in Table 10. Table 10. Updated Timing REGISTER ADDRESS 000h UPDATE TIMING Real time 001h-01Fh Timing specified at bits 0-2 of 000h (AFE update) 020h-035h Real time 036h[2:0] VD; refer to the CCD Timing Composition section of the TG (Timing Generator) Section for details. 036h[5:3] TRIG; refer to the CCD Timing Composition section of the TG (Timing Generator) Section for details. 037h-0FFh Timing specified at bit 3 of 000h (TG update) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 21 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com The AFE register is updated in real time by the RLOAD pin or VD, as shown in Table 11. Table 11. Update Select Register (AFE) PARAMETER REGISTER ADDRESS AFE UPDATE 000h[0] AFE UP POL 000h[2:1] DESCRIPTION 0 = Real-time update (default) 1 = Updated by RLOAD pin or VD AFE register update signal and polarity 00b = RLOAD rising edge (default) 10b = VD rising edge 01b = RLOAD falling edge 11b = VD falling edge The TG register can be updated at a specified line number through VA instruction. The update method selection is described in Table 12. In general, this function is used for SUBN control. Table 12. Update Select Register (TG) PARAMETER REGISTER ADDRESS TG UPDATE DESCRIPTION 0 = Real-time update (default) 1 = Updated by VA instruction line number Refer to the Vertical Sequence section for VA instruction details. 000h[3] MCK STOP DETECT The MCK stop detect function is supported, as shown in Table 13. If an MCK stop was detected, all register values are cleared. After an MCK stop detect, a SYSRST is required. Table 13. MCK Stop Detect Register PARAMETER REGISTER ADDRESS MCK detect 020h[4] DESCRIPTION 0 = Disabled 1 = Enabled (default) STANDBY FUNCTION For increased power savings, this device can be put into a standby mode (power-down mode) through serial interface control when the device is not in use. In this mode, all function blocks are disabled. Current consumption drops to about 2 mA. Because all the bypass capacitors discharge during this mode, a substantial time (usually on the order of 200 ms to 300 ms) is required to return from standby mode. A four-part standby is selected independently, as described in Table 14. Table 14. Standby Control Register SECTION REGISTER ADDRESS DESCRIPTION SIGNAL STATUS IN STANDBY TG 020h[0] 0 = Standby (default) 1 = Normal operation Refer to the Signal section of the TG (Timing Generator) Section. AFE 001h[0] 0 = Normal operation (default) 1 = Standby Digital output = high impedance DAC1 001h[1] 0 = Enabled 1 = Disabled (Standby) (default) Analog output = low DAC2 001h[2] 0 = Enabled 1 = Disabled (Standby) (default) — AFE standby, DAC1 standby, or DAC2 standby should be completed before TG standby if using the VD update method for the the AFE section. If the AFE standby is completed after TG standby, the AFE standby, DAC1 standby, or DAC2 standby are not activated. 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 SYSTEM RESET All parameters are reset to the respective default values when the SYSRST pin goes low asynchronously with respect to the system clock. All register and memory values are cleared by SYSRST. SYSRST should be pulled up for operation. Figure 16 shows typical SYSRST implementation with a pull-up resistor. SYSRST Figure 16. SYSRST Pin POWER-UP SEQUENCE When the device is powered up, follow this recommended sequence: 1. Turn on the power supplies for the device. 2. Apply the master clock input to the MCK, VD, and HD signals. 3. Input the serial data for the 6-bit register setting. Input SRG for 16-bit serial data. (10-bit address + 6-bit data). TG disable must be complete. (020h[0] = 0) 4. Input the serial data for VHIGH SPEED transfer toggling. Input SRG for 26-bit serial data. (10-bit address + 16-bit data) 5. Input the serial data for VRATE toggling. Input SRG for 32-bit serial data. (10-bit address + 22-bit data) 6. Input the serial data for HRATE toggling. Input SRG for 32-bit serial data. (10-bit address + 22-bit data) 7. Input the serial data for TG enable. Input SRG for 16-bit serial data. (10-bit address + 16-bit data) TG enable must be complete. (020h[0] = 1) Figure 17 shows the timing for the power-up sequence. Power SDATA CS SCLK MCK VD 1 1 HD 100 200 100 Vertical Output HG1A, HL = High, HG1B = Z High-Speed Output HG2A, RG = Low, HG2B = Z Figure 17. Power-Up Sequence Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 23 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com AFE (ANALOG FRONT-END) SECTION OVERVIEW Composition The VSP01M01/VSP01M02 are complete mixed-signal ICs that contain all of the key features associated with processing of the CCD imager output signal in video cameras, digital still cameras, security cameras, or similar applications. A simplified block diagram of the AFE section is shown in Figure 18. The AFE section includes these features: • Correlated double sampler (CDS) • Programmable gain amplifier (PGA) • Analog-to-digital converter (ADC) • Input clamp • Optical black (OB) level clamp loop • Timing control • Internal reference voltage generator It is recommended that an off-chip emitter follower buffer be placed between the CCD output and the device CCDIN input. The serial interface controls PGA gain, clock polarity setting, and operation mode. BYP2 COB Buffer Current DAC Decoder From Serial Interface Gain Control CCD Out Signal CDS 16-Bit ADC Digital Output 10-/12-/16-Bit DPGA CCDIN Clamp Internal Clocks (SHP/SHD, ADCCK, CLPOB, CLPDM) From TG Section Figure 18. Simplified Block Diagram of the AFE Section Function Table 15 shows the major functions of the AFE section. Table 15. AFE Functional Summary 24 FUNCTION RELATED REGISTER Selectable CDS (analog) gain 008h Programmable digital gain 006h, 007h SECTION Programmable Gain Programmable OB clamp level 004h Standby mode 001h[2:0] Standby Function Hot pixel rejection 005h Hot Pixel Rejection Selectable register update 000h[2:0] AFE Register Update Function Data output enable control 002h[2] Data Output Enable Submit Documentation Feedback OB Loop and OB Clamp Level Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 CORRELATED DOUBLE SAMPLER (CDS) The output signal of the CCD image sensor is sampled twice during one pixel period: once at the reference interval and again at the data interval. Subtracting these two samples extracts the video information of the pixel as well as removes any noise, which is common to both intervals. Thus, CDS is very important to reduce the reset noise and the low-frequency noise that are present on the CCD output signal. Figure 19 shows the block diagram of the CDS section. SHP, SHD, CLPDM, and CLPOB are supplied from the TG section; these signals are active low (close). SHP/SHD CINP C1 CCD Input CCDIN SHP CCGND C2 CCD GND CLPDM SHP REFP 1.5 V Figure 19. Block Diagram of CDS and Input Clamp INPUT CLAMP The buffered CCD output is capacitively coupled to this device. The purpose of the input clamp is to restore the dc component of the input signal, which was lost with the ac coupling, and to establish the desired dc bias point for the CDS. Figure 19 also shows the block diagram of the input clamp. The input level is clamped to the internal reference voltage, CM (1.25 V), during the dummy pixel interval. More specifically, the clamping function becomes active when both CLPDM and SHP are active. Immediately after power on, the clamp voltage of the input capacitor is not charged. For fast charge-up for clamp voltage, these devices provide a boost-up circuit. ANALOG-TO-DIGITAL CONVERTER (ADC) These devices provide a high-speed, 16-bit analog-to-digital converter (ADC). This ADC uses a fully differential pipelined architecture with a correction feature. The ADC error correction architecture is very advantageous to realize a better linearity for lower signal levels. Large linearity errors tend to occur at specific points in the full-scale range and the linearity improves for a signal level below that specific point. The ADC ensures 16-bit resolution across the entire full-scale range. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 25 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com OB LOOP AND OB CLAMP LEVEL This device has a built-in OB offset self-calibration circuit (OB loop) that compensates the OB level by using optical black (OB) pixels output from the CCD image sensor. A block diagram of the OB loop and OB clamp circuit is shown in Figure 20. OB Clamp Level CCDIN CDS 16-Bit ADC Data Out DPGA BYP2 Current DAC COB Decoder CPLOB Figure 20. OB Loop and OB Clamp Level CCD offset is compensated by the convergence of this calibration circuit while activating CLPOB during a period when OB pixels are output from the CCD. Note that the total number of effective pixels is (the CLPOB period –6 pixels). At the CDS circuit, CCD offset is compensated as a difference between reference level and data level of the OB pixel. These compensated signal levels are recognized as actual OB levels, and the outputs are clamped to the OB levels set by the serial interface. These OB levels are the base of black for the effective pixel period thereafter. Because DPGA, which is a gain stage, is outside the OB loop, OB levels are not affected even if the gain is changed. Converging time of the OB loop is determined by the capacitor value connected to the COB terminal and output from the current output DAC of the loop. The time constant can be obtained from Equation 1: C T= (16384 ´ IMIN) (1) Where: C is the capacitor value connected to COB, IMIN is the minimum current (0.15 µA) of the current DAC which is an equivalent current to 1 LSB of the DAC output. When C = 0.1 µF, T is 40.8 µs. Slew rate (SR) can be obtained from Equation 2: IMAX SR = C (2) Where: C is the capacitor value connected to COB, IMAX is the maximum current (76 µA) of the current DAC which is an equivalent current to 511 LSB of the DAC output. 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Immediately after power-on, the COB capacitors are not charged. For fast start-up, a COB voltage boost-up circuit is provided. The OB clamp level (digital output value) can be set externally through the serial interface by inputting a digital code to the OB clamp level register. The digital codes to be input and the corresponding OB clamp levels are shown in Table 16. Table 16. Input Code and OB Clamp Level to Be Set CLAMP LEVEL (LSB) CODE (Register = 004h) VSP01M01 (10-Bit) VSP01M02 (12-Bit) 00000b 16 64 00001b 18 72 — — — 00110b 28 112 00111b 30 120 01000b (default) 32 128 01001b 34 136 — — — 11110b 76 304 11111b 78 312 PROGRAMMABLE GAIN The VSP01M01 and VSP01M02 gain ranges from –9 dB to 44 dB. The desired gain is set as a combination of CDS gain and the digital programmable gain amplifier (DPGA). CDS gain can be programmed in the range of –3 dB to 18 dB (–3 dB, 0 dB, 6 dB, 12 dB, 18 dB). –3 dB gain supports large input levels ranging from 1 V to 1.3 V. Digital gain can be programmed in the range of –6 dB to 26 dB in 0.03125-dB steps. Both gains are controlled through the serial interface. Gain changes linearly in proportion to the setting code, as shown in Figure 21. Table 17. Programmable Gain Register (1) (1) PARAMETER REGISTER ADDRESS CDS (analog) gain 008h DPGA 006h, 007h Refer to the Configuration Register section for details. 30 25 Gain (dB) 20 15 10 5 0 -5 -10 0 128 256 384 512 640 768 896 1024 Input Code for Gain Control (0 to 1023) Figure 21. DPGA Setting Code vs Gain Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 27 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com PRE-BLANKING AND DATA LATENCY These devices have a pre-blanking function. When PBLK = low, all digital outputs are set to '0' after the latching ADCCK clocks counting from PBLK go low to accommodate the clock latency of these devices. CLOCK TIMINGS FOR THE AFE SECTION The CDS and the ADC are operated by SHP and SHD; the derivative timing clocks are generated by the on-chip timing generator. The output register and decoder are operated by ADCCK. The digital output data are synchronized with ADCCK. The timing relationship between the CCD signal, SHP, SHD, ADCCK, and the output data is described in the Timing Characteristics. CLPOB is used to activate the black level clamp loop during the OB pixel interval and CLPDM is used to activate the input clamping during the dummy pixel interval. In standby mode, ADCCK, SHP, SHD, CLPOB, and CLPDM are internally masked and pulled high. Refer to the Standby Function section of the Common Section and the Signal section of the TG (Timing Generator) Section for details. VOLTAGE REFERENCE All reference voltages and bias currents used on the device are created from an internal band-gap circuitry. The VSP01M01 and VSP01M02 have symmetrically independent voltage references. CDS and the ADC primarily use three reference voltages: REFP (1.5 V), REFN (1.0 V), and CM (1.25 V) of the individual reference. REFP and REFN are buffered on-chip. CM is derived as the mid-voltage of the register chain connecting REFP and REFN internally. Twice the difference voltage between REFP and REFN [that is, 2(REFP – REFN)] determines the ADC full-scale range. REFP, REFN, and CM should be heavily decoupled with appropriate capacitors. Refer to the Terminal Functions section for details. HOT PIXEL REJECTION Sometimes the OB pixel output signal from the CCD includes an unusual level signal that causes pixel defection. If this level reaches a full-scale level, is may affect OB level stability. These devices have a function that rejects this large unusual pixel level (hot pixel) at the OB pixel. Through this function, these devices improve the CCD yield at camera manufacturing. The rejection level for hot pixels can be programmed through the serial interface. When a hot pixel comes from the CCD, the VSP01M01 and VSP01M02 omit it and replace it with the previous pixel level from the OB level calculation. Table 18. Hot Pixel Rejection Register (1) (1) 28 PARAMETER REGISTER ADDRESS Hot pixel rejection 005h Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 AFE REGISTER UPDATE FUNCTION Some registers for the AFE section can be selected during update timing. Refer to the Register Update section of the Common Section for details. DATA OUTPUT ENABLE Data out is enabled or disabled by the Data Output Enable register, as shown in Table 19. When disabled, the output level is high impedance. Table 19. Data Output Enable Register PARAMETER REGISTER ADDRESS OE 002h[2] DESCRIPTION 0 = Enabled (default) 1 = Disabled (high impedance) DAC The VSP01M01 and VSP01M02 provide a two-channel, general-purpose, 8-bit DAC, as shown in Table 20. This DAC can be used for various applications such as CCD bias control, iris control, etc. Table 20. DAC Input Register (1) PARAMETER (1) REGISTER ADDRESS DAC1 00Ah, 00Bh DAC2 00Ch, 00Dh Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 29 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com TG (TIMING GENERATOR) SECTION OVERVIEW Composition The VSP01M01 and VSP01M02 support variable CCD timing. For horizontal and vertical sequencing, full programming is available. These devices include a counter, high-speed signal generator, VA selector for frame mode change, output controller, and a TRIG function section. High-speed signal rise and fall timing are generated through the high-speed signal generator. For each signal, enabling and initial polarity are controlled by the output controller. Counter Table 21 shows the operation of each counter. Table 21. Counter Operation COUNTER INCREASED BY RESET BY Frame Reset (VA) VA instruction TRIG Reset (HA) VD EOF (VA) TRIG VA (vertical) OUTPUT/OPERATION Frame count Line count Instruction: Frame count reset Initialize Event number start/stop EOF Call HA Address HA (horizontal) MCK HS (VHIGH SPEED transfer) MCK Event Trigger V HD EOL (HA) TRIG HS number start (HA) Repeat (HS) Pixel count Signal toggling V0N-12N, P0-5, CLPDM, CLPOB, PBLK, HBLK, HDIV, HD, VD Instruction: HS number start/stop EOL VSIGNAL toggling Repeat instruction Event number start (VA) VSIGNAL control The HA counter controls the horizontal sequence with the pixel counter. Some signal toggling is controlled by the pixel step. The VA counter controls the vertical sequence with the line counter. The VA calls the HA address by a line step. HS controls the VHIGH SPEED transfer sequence with a pixel counter. VSIGNAL toggling is controlled by a pixel step. This counter is started by the HA start command. The loop cycle continues until an HA stop command is issued. An event counter controls VHIGH-SPEED transfer for an electrical zoom function. This counter operates between the VA start and stop commands. TRIG Function Section TRIG has the following functionality: • Frame counter reset function • Load frame function • TG stop function These functions are activated by a register setting. 30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 CCD Support The VSP01M01 and VSP01M02 TG are designed for various kinds of CCD sensor operation, including IT-CCD as well as FT-CCD, IT progressive CCD, FIT-CCD, and motion CCD, as shown in Figure 22. OB OB OB Active Area OB OB OB OB OB OB FD Active Area OB Active Area OB OB HV PIX Summing Area Horizontal CCD FD Dummy Horizontal CCD Memory Area Dummy a) IT/IT Progressive c) Motion CCD FD Horizontal CCD Dummy b) CCD FT/FIT-CCD NOTE: Shaded cells indicate the area under discussion. Figure 22. CCD Support Applications The CCD operation supports these functions: • Vertical format: – IT-CCD: two, three, or four field types – IT-progressive CCD – FT-CCD – FIT-CCD – Motion CCD • Horizontal transfer format: – Four channels, two phases • Floating diffusion reset: – One floating diffusion or single phase reset Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 31 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Timing Range The VSP01M01 and VSP01M02 have a horizontal 13-bit counter and a vertical 12-bit counter. The counter synchronizes the pixel rate master clock (MCK). The reference signal (HD/VD) has flexibility that can select either the master or slave mode. The timing is programmable so that the TG generates every signal. Apply the program through the serial interface. Refer to the Register/Memory Map section of the Common Section for details. Line Counter VD 1 3 M PIX CCD 5 M PIX CCD 4095 13-Bit (8191 Pixels) x 12-Bit (4095 Lines) Timing Area 1 Pixel Counter 8191 1 1 HD Figure 23. TG Handling Time Range Operating Mode The primary operating mode consists of a combination of normal mode, monitor mode, still mode, and motion picture mode. 32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Normal Mode Normal mode operates as a basic function with an electric shutter, integration, readout, vertical transfer, and horizontal transfer. IT-CCD, FT-CCD, and progressive-CCD use a horizontal sequence (see the Horizontal Sequence section), vertical sequence (see the Vertical Sequence section), and an HBLK function (see the HBLK Function section). IT-CCD, progressive-CCD, and most of the FT-CCD use an electric shutter function (see the Electric Shutter Function section). VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P55 SUBN Figure 24. Normal Mode Timing Example Monitor Mode Monitor mode operates vertically over several pixel intervals, with an electric shutter, integration, readout, vertical transfer, and horizontal transfer. IT-CCD, FT-CCD, and progressive-CCD use a horizontal sequence (see the Horizontal Sequence section), vertical sequence (see the Vertical Sequence section), and an HBLK function (see the HBLK Function section). IT-CCD, progressive-CCD, and most of the FT-CCD use an electric shutter function (see the Electric Shutter Function section). VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P55 SUBN Figure 25. Monitor Mode Timing Example Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 33 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Still Mode Still mode operates as a smear dump operation and SUBSW control. IT-CCD, FT-CCD, and progressive-CCD use a vertical sequence (see the Vertical Sequence section), horizontal sequence (see the Horizontal Sequence section), vertical high-speed transfer sequence (see the Vertical High-Speed Transfer (HS) Sequence section), and an HBLK function (see the HBLK Function section). IT-CCD, progressive-CCD, and most of the FT-CCD uses an electric shutter function (see the Electric Shutter Function section). IT-CCD and progressive-CCD use a SUBSW function (see the SUBSW Function section) for CCD substrate bias control. VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P5 SUBN SUBSW Figure 26. Still Mode Timing Example Motion Picture Mode Motion picture mode adds up the pixels in the CCD horizontal and vertical transfer. IT-CCD is dedicated to this mode and uses a vertical sequence (see the Vertical Sequence section), horizontal sequence (see the Horizontal Sequence section), an HBLK function (see the HBLK Function section), and HDIV function (see the HDIV Function section). VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P5 SUBN Figure 27. Motion Picture Mode Timing Example 34 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Function Table 22 summarizes the primary TG section functionality. Table 22. TG Function FUNCTION RELATED REGISTER SECTION Adjustable high-speed pulse 002h, 003h, 010h-01Ah High-Speed Pulse Adjustment Programmable horizontal pattern 200h-3FFh Horizontal Sequence Programmable vertical pattern 180h-1FFh Vertical Sequence Programmable VCCD high-speed transfer pattern 100h-17Fh Electrical zoom function 030h-033h, 037h-03Eh Vertical High-Speed (HS) Transfer Sequence Sync signal selectable (master or slave) 020h Field index for two-field CCD 022h, 02Fh, 035h[0] Programmable electrical shutter 08Ch-0A3h Programmable strobe 04Ch-07Bh Strobe Function Programmable MECH shutter 040h-04Bh MSHUT Function Synchronous Function Electric Shutter Function Programmable SUBSW 07Ch-08Bh SUBSW Function Programmable frame sequence for strobe, MECH shutter, and SUBSW 021h[4], 022h[2] Frame Count Function Frame mode control by trigger 021h[3:2], 036h[5:3] Waiting mode by trigger 020h[4], 021h[1:0] Frame sequence (for strobe, MECH shutter, and SUBSW) control by trigger 021h[4:3], 022h[2] Trigger Function Standby mode 020h[0] Standby Function Programmable HG signal for horizontal blank — HBLK Function Flexible pixel summing operation 01Bh[2:0] HDIV Function Monitor out for internal signal 001h[3], 0B5h Selectable HG power 01Ch[1:0] Flexible register update 000h[3] Signal TG Register Update Function Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 35 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com SIGNAL This device has 32 vertical signals and nine horizontal signals. The universal-purpose signal has flexible usage. Refer to the Terminal Functions table for details. Pin enabling of vertical signals is set by register address 023h-028h. Pin initial polarity is set by register address 029h-02Eh. The initial polarity is applied by the VA initialize instruction. (The initial polarity is not applied by the TG operation start). Refer to the Configuration Register section for details. V13 Signals Universal Purpose (19 Signals) External Use (19 Signals) Read Out (6 Signals) Vertical (32 Signals) Sync I/O (2 Signals) Specific Purpose (13 Signals) External Use (6 Signals) Internal Use (5 Signals) Specific Purpose (9 Signals) Horizontal (9 Signals) External Use (6 Signals) Internal Use (3 Signals) Test (Monitor) (2 Signals) Universal Test Purpose (2 Signals) V0N V1N V2N V3N V4N V5N V6N V7N V8N V9N V10N V11N V12N P0 P1 P2 P3 P4 P5 HD VD SUBN FIELD STROBE MSHUT SUBSW1 SUBSW2 HDIV CLPDM CLPOB PBLK HBLK HG1A HG1B HL HG2A HG2B RG SHP SHD ADCCK TPP TPD External Use (2 Signals) Figure 28. Signal Overview 36 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Programmed Signal (Memory Assignment) The signal timing (described in Table 23) is specified by the HA (horizontal address) program. Terminal assignment numbers are used by the HA command (data[17:13]). The default output level is fixed except for an MCK stop condition. These signals are disabled with a power-up default. The CLPDM, CLPOB, PBLK, HBLK, and HDIV signal active polarity is low. Table 23. Memory Assignment Signal REGISTER ADDRESS TERMINAL NAME SIGNAL FUNCTION TERMINAL ASSIGNMENT V[0:12]N Vertical transfer signal (high-speed transfer) P[0:5] ENABLE INITIAL 00001b-01101b (1-13) 023h-025h 029h-02Bh Vertical transfer signal (general signal) 10000b-10101b (16-21) 025h-026h 02Bh-02Ch CLPDM Clump dummy signal 11000b (24) 026h[5] 02Ch[5] CLPOB Clump OB signal 11001b (25) [0] [0] PBLK Pre-blanking signal (digital out = low) 11010b (26) [1] [1] HBLK Horizontal transfer pulse blank 11011b (27) HDIV Horizontal transfer pulse divide 11100b (28) VD Vertical sync signal (master mode) 11101b (29) [4] [4] HD Horizontal sync signal (master mode) 11110b (30) [5] [5] LEVEL POWERUP DEFAULT AFE STANDBY TG STANDBY High [2] 027h [3] [2] 02Dh TRIG STOP MCK High No effect No effect Low Low [3] Decoded Signal (Register Assignment) The signal timing of Table 24 is specified by the decoder. The decoder refers to the register value of the frame number, line number, or pixel number. Default output levels are fixed except for an MCK stop condition. These signals are disabled with a power-up default. Table 24. Register Assignment Signal REGISTER ADDRESS TERMINAL NAME SIGNAL FUNCTION SUBN Electric shutter [0] [0] FIELD Field index [1] [1] ENABLE STROBE Strobe signal MSHUT Mechanical shutter SUBSW1 CCD substrate bias control 1 [4] [4] SUBSW2 CCD substrate bias control 2 [5] [5] 028h [2] INITIAL [3] 02Eh LEVEL POWER-UP DEFAULT High [2] [3] AFE STANDBY Low TG STANDBY TRIG STOP MCK High No effect Low No effect Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 37 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Phase Controlled Signal (Register Assignment) The high-speed signal timing is specified by a register. Default output levels are shown in Table 25. Table 25. Horizontal Signal REGISTER ADDRESS LEVEL ENABLE TERMINAL NAME SIGNAL FUNCTION HG2A HG2B Horizontal transfer signal 1 01Bh[3] Horizontal transfer signal 2 RG CCD reset signal SHP Reference level sampling SHD Data level sampling ADCCK ADCCK buffer DISABLE 01Bh[2] AFE STANDBY TG STANDBY TRIG STOP MCK — High 01Ch[2] Z 01Bh[4] 0 = Low 1 = High High High High — Low 01Ch[2] Z Low Low Low Low Toggling Toggling ENABLE HG1A, HL HG1B POWER-UP DEFAULT Low Always enable Toggling No effect High Low HG Drive The HG drive power for HG1A, HG1B, HG2A, and HG2B is selected by the HG power select register (01Ch[1:0]), as shown in Table 26. Table 26. HG Power Select Register TERMINAL NAME REGISTER 01Ch[1:0] HG1A 00 = Minimum HG1B 01 = Default HG2A 10 = Mid-range HG2B 11 = Maximum The HG drive power can be doubled by a connection between HGAx and HGBx. However, this setting is typically used for power dissipation. If HGBx is not used, disable and do not connect HGBx. HG1A HG1B HG2A HG2B Figure 29. HG Double Power Connection 38 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Monitor Signal The test pin (TPP, TPD) is set up by address 001h, data bit [3] = 1, as shown in Table 27. Table 28 describes TPP and TPD. Table 27. Monitor Pin Enable Register (1) (1) PARAMETER REGISTER ADDRESS VALUE Monitor pin 001h[3] 1 = Enable Refer to the Configuration Register section for details. Table 28. Test Pin Output Select REGISTER 0B5h[3:0] TPP TPD 1000b (8) SHP SHD 1001b (9) CLPOB CLPDM 1010b (10) PBLK HDIV 1011b (11) HBLK — SHP and SHD are monitored at the TG section output, as shown in Figure 30. The actual sampling point is delayed from the monitor point. The delay time is shown in Figure 30. The actual sampling point delay = delay controller value (003h[1:0] = 0 ns-6 ns) + sampling delay (3 ns). TG Section AFE Section 3-ns Delay SHP High-Speed Signal Generator Delay Controller SHD 015h-018h Sampling Circuit 003h[1:0] TPP Signal Selector TPD Figure 30. SHP/SHD Monitor Out HIGH-SPEED PULSE ADJUSTMENT The high-speed pulse can be adjusted in steps of one pixel clock cycle per 100. The assignment register for each pulse is shown in Table 29. The rising edge of the RG pulse as a reference. Table 29. High-Speed Pulse Adjustment Register REGISTER ADDRESS CONTROL ITEM TERMINAL NAME FALLING RISING RG RG 014h[4:0] — G1h G1Ah G1Bh HL 011h[4:0] 010h[4:0] G2h G2Ah G2Bh 012h[4:0] 013h[4:0] DELAY — SHP SHP 015h[4:0] 016h[4:0] SHD SHD 017h[4:0] 018h[4:0] 003h[1:0] ADCCK ADCCK — — 019h[5:0] 019h[6] Data out B0-B15 — — 002h[1:0] Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 39 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com RG Control RG control is described in Figure 31 and Table 30. tCKP tCKP/4 RG tRGW tRGW Figure 31. RG Fall Timing Table 30. RG Fall Register ADDRESS NAME DESCRIPTION RG falling edge from RG rising edge (tCKP/4 – 16tCKP/100 < tRGW < tCKP/4 + 15tCKP/100) 00 0001 0100b (014h) RG FALL[4:0] DATA (DEC) STEP 10000b 10001b — 11111b 00000b 00001b — 01110b 01111b (16) (17) — (31) (0) (1) — (14) (15) –16 –15 — –1 0 (default) 1 — 14 15 STEP is twos complement of data. 1 step = (1 pixel clock term)/100 HG1 Control HG1 control is described in Figure 32 and Table 31. tCKP RG tH1R tH1R HG1A, HG1B, HL Rising tCKP/2 HG1A, HG1B, HL Falling tCKP/2 tH1F Figure 32. HG1 Timing Table 31. HG1 Register ADDRESS 00 0001 0000b (010h) 00 0001 0001b (011h) 40 NAME DESCRIPTION HG1 RISE[4:0] HG1A, HG1B, and HL rising edge from RG rising edge (–tCKP16/100 < tH1R < tCKP15/100) Same step control as for Table 30. Default = 00000b. HG1 FALL[4:0] HG1A, HG1B, and HL falling edge from RG rising edge (tCKP/2 – 16tCKP/100 < tH1F < tCKP/2 + 15tCKP/100) Same step control as for Table 30. Default = 00000b. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 HG2 Control HG2 control is described in Figure 33 and Table 32. tCKP RG tCKP/2 tCKP/2 tH2R HG1A, HG1B, HL Rising tH2F tH2F HG1A, HG1B, HL Falling Figure 33. HG2 Timing Table 32. HG2 Register ADDRESS NAME DESCRIPTION 00 0001 0011b (013h) HG2 RISE[4:0] HG2A and HG2B rising edge from RG rising edge (tCKP/2 – 16tCKP/100 < tH2R < tCKP/2 + 15tCKP/100) Same step control as for Table 30. Default = 00000b. 00 0001 0010b (012h) HG2 FALL[4:0] HG2A and HG2B falling edge from RG rising edge (–tCKP16/100 < tH2F < tCKP15/100) Same step control as for Table 30. Default = 00000b. SHP Control SHP control is described in Figure 34 and Table 33. tCKP tCKP/4 tCKP/2 RG tPR SHP Rising tPF tPR = tPR1 + tSDLY tPF SHP Falling tPF = tPF1 + tSDLY Figure 34. SHP Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 41 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Table 33. SHP Register ADDRESS NAME 00 0001 0110b (016h) SHP RISE[4:0] SHP rising edge from RG rising edge (tCKP/2 – 16tCKP/100 < tPR1 < tCKP/2 + 15tCKP/100) Same step control as for Table 30. Default = 00000b. 00 0001 0101b (015h) SHP FALL[4:0] SHP falling edge from RG rising edge (tCKP/4 – 16tCKP/100 < tPF1 < tCKP/4 + 15tCKP/100) Same step control as for Table 30. Default = 00000b. S-DELAY[1:0] Sampling delay for SHP/SHD (0 ns < tSDLY < 6 ns) 00b = 0 ns (default) 01b = 2 ns 10b = 4 ns 11b = 6 ns 00 0000 0011b (003h) DESCRIPTION SHD Control SHD control is described in Figure 35 and Table 34. tCKP +3tCKP/4 - 8tCKP/100 -8tCKP/100 RG tDR tDR SHD Rising tDR = tDR1 + tSDLY SHD Falling tDF tDF = tDF1 + tSDLY Figure 35. SHD Timing Table 34. SHD Register ADDRESS DESCRIPTION 00 0001 1000b (018h) SHD RISE[4:0] SHD rising edge from RG rising edge (–24tCKP/100 < tDR1 < 7tCKP/100) Same step control as for Table 30. Default = 00000b. 00 0001 0111b (017h) SHD FALL[4:0] SHD falling edge from RG rising edge (3tCKP/4 – 24tCKP/100 < tDF1 < 3tCKP/4 + 7tCKP/100) Same step control as for Table 30. Default = 00000b. S-DELAY[1:0] Sampling delay for SHP/SHD (0 ns < tSDLY < 6 ns) (0 ns < tSDLY < 6 ns) 00b = 0 ns (default) 01b = 2 ns 10b = 4 ns 11b = 6 ns 00 0000 0011b (003h) 42 NAME Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 ADCCK Control ADCCK control is described in Figure 36 and Table 35. tCKP tCKP/2 tCKP/2 tADCKR tADCKR RG ADCCK Figure 36. ADCCK Delay Timing Table 35. ADCCK Delay Register ADDRESS NAME DESCRIPTION 00 0001 1001b (019h) ADCCK DELAY[5:0] ADCCK rising edge from RG rising edge (–50tMCKP/100 < tADCKR < 49tMCKP/100) Default = 00 0000b. Data[6:0] = 01Ah[0] × 26 + 019h[5:0] 00 0001 1010b (01Ah) ADCCK DELAY[6] DATA[6] 01Ah[0] 019h[5:0] (DEC) STEP 100 0000b 1 00 0000b (64) Reserved 100 1101b 1 00 1101b (77) Reserved 100 1110b 1 00 1110b (78) –50 100 1111b 1 00 1111b (79) –49 — — — — — 111 1111b 1 11 1111b (127) –1 000 0000b 0 00 0000b (0) 0 (default) 000 0001b 0 00 0001b (1) 1 — — — — — 011 0000b 0 11 0000b (48) 48 011 0001b 0 11 0001b (49) 49 011 0010b 0 11 0010b (50) Reserved 011 1111b 0 11 1111b (63) Reserved STEP is twos complement of data. 1 step = (1 pixel clock term)/100. Data Out Delay Control Data out delay control is described in Figure 37 and Table 36. tCKP ADCCK tHOLD (tDOD = 6 ns) tHOLD (tDOD = 0 ns) tDOD tOD (tDOD = 6 ns) tOD (tDOD = 0 ns) tDOD B[15:0] Figure 37. Data Out Delay Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 43 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Table 36. Data Out Delay Register ADDRESS NAME 00 0000 0010b (002h) DESCRIPTION Data out delay 00b to 11b (0 ns < tDOD < 6 ns) 00b = 0 ns (default) 01b = 2 ns 10b = 4 ns 11b = 6 ns DATA OUT DELAY[1:0] TG INSTRUCTION HIERARCHY Figure 38 shows the instruction hierarchy. The VA number corresponds to the frame template, and the HA number corresponds to the line template. Each VA has a set of HA number instructions in the vertical timing memory; each HA number has a set of toggling instructions in the horizontal memory. The frame mode is selected by a register (036h). Fixed Address Frame Data Set Data HA Address Call 0 HA Address = 0 Vertical Data Set VA1-1: HA1 Start at Line 1 (Blanking) VA1-2: HA2 Start at Line 37 (Readout1) VA1-3: HA3 Start at Line 38 (Readout2) 180h Frame Mode (VA1) 190h Frame Mode (VA2) VA1-16: HA4 Start at Line 39 (OB) 1B0h HA1-2: CPOB at Pixel 40 2 HA1-3: PBLK¯ at Pixel 51 3 HA1-4: V3N at Pixel 52 9 HA1-10: EOL at Pixel 1023 10 HA2-1: CPOB¯ at Pixel 10 11 HA2-2: CPOB at Pixel 40 12 HA2-3: PBLK¯ at Pixel 51 13 HA2-4: V1N at Pixel 100 16 HA2-7: EOL at Pixel 1023 Call HA Address = 10 Frame Mode (VA4) 128 Words 1 ¼ Frame Mode (VA3) HA1-1: CPOB¯ at Pixel 10 ¼ 16 Words 1A0h Horizontal Data Set 1C0h Frame Mode (VA5) 1D0h Frame Mode (VA6) ¼ 1E0h Frame Mode (VA7) 1F0h Frame Mode (VA8) NOTE: Line number, pixel number, and start of HA address are programmable. Figure 38. Instruction Hierarchy (Standard Sequence Sample) CCD TIMING COMPOSITION TG timing is composed of a vertical data set (VA) that contains eight frames. VA has a horizontal data set (HA), which has several numbers of lines for specific functions. Frame mode is provided by VA. Table 37 shows the frame number for each VA number. Table 37. Frame Number PARAMETER 44 FRAME VA number 1 2 3 4 5 6 7 8 Frame number 0 1 2 3 4 5 6 7 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Operated VA is updated to the Frame Now register by VD. Operated VA is updated to Frame TRIG by the TRIG signal with a Load TRIG frame function. This updating process is shown in Table 38. Table 38. Frame Mode Register PARAMETER REGISTER ADDRESS DESCRIPTION Frame now 036h[2:0] Set current frame number Default = 000b. Frame TRIG 036h[5:3] Set frame number when trigger input Default = 000b. Figure 39 shows the TG mode transition. Power Off · Power ON · Serial Code Input TG Disable TG Standby VD TG Enable Frame Now VA (n) Frame TRIG TRIG VD VA (m) Figure 39. TG Mode Transition Figure 40 shows the CCD timing composition example, which consists of frames for several operation modes. Each frame counts the line count. VD (master/slave) or TRIG (external trigger) signal the reset line counter and change during the next frame. Table 39. TRIG Frame Function Register Setting (1) (2) (1) (2) PARAMETER REGISTER ADDRESS VALUE VD frame 022h[0] 1 = Enabled TRIG frame INCR 021h[2] 1 = Enabled TRIG counter RST 021h[3] 1 = Enabled Static frame number 036h[2:0] — TRIG frame number 036h[5:3] 7 If the TRIG function is not used, TRIG Frame INCR and TRIG Counter RST should be disabled. Refer to the TRIG Function Section of this document Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 45 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Frame Number By Frame Now Register (036h[2:0]) Frame Number By Frame TRG Register (036h[5:3]) Operated VA Number VD (Master/Slave) TRIG (External) Line Counter HD 1H 1 Standard Function Monitor Mode V-Blanking HA #1 Readout HA #2 OB HA #3 0 (VA #1) VA #1 Active Signal HA #4 HA #3 HA #5 Readout HA #6 VHIGH-SPEED Transfer HA #12 Active Signal HA #7 1 VHIGH-SPEED Transfer HA #5 1 Readout HA #8 OB HA #9 Active Signal HA #10 1 OB VHIGH-SPEED Transfer E-Zoom Function Monitor Mode VA #3 7 (VA #8) 2 (VA #3) VA #3 Standard Function Still Mode VA #8 3 (VA #4) 1 OB HA #9 VBLANKING HA #11 VA #4 Figure 40. CCD Timing Composition (Example) SYNCHRONOUS FUNCTION The system follows either the HD/VD master or slave mode. Select the master/slave mode through register setting (020h[1]: 0 = Slave, 1 = Master), as shown in Table 40. The default setting is slave mode. TG also follows an external HD/VD signal. The master mode generates HD/VD timing according to HA instruction. Table 40. Sync Mode MODE REGISTER 020h[1] HD AND VD PIN Slave 0 (default) Input Master 1 Output HD AND VD TIMING HCYCLE VCYCLE Synchronous HA command EOL of HA EOF of VA Slave Mode The system synchronizes the external master clock, HD, and VD. Note that the HD and VD pins are input modes. 46 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 VD, HD Detection VD- and HD-detected edge polarity are selected by register 020h[3]. The selected edge is detected as a rising edge of MCK. VD is detected by the HD phase. If the pixel count between the VD edge and HD edge is within the selected range, VD is detected. The range is selected as shown in Table 41. Table 41. VD HD Detect Register (1) (1) PARAMETER REGISTER ADDRESS DESCRIPTION VD HD TRG edge 020h[3] 0 = Falling edge (default) 1 = Rising edge ODD HD-VD 02Fh[2:0] VD after HD detect range 0-7 pixel delay Default = 001b ODD VD-HD 02Fh[5:3] HD after VD detect range 0-8 pixel delay Default = 001b Refer to the Slave Mode: VD, HD Specifications section for details. HCOUNTER Reset HCOUNTER reset is selected by MCK edge polarity (020h[2]). Table 42 shows the register. Table 42. MCK Edge Polarity (1) (1) PARAMETER REGISTER ADDRESS VH, HD, and MCK edge 020h[2] DESCRIPTION 0 = MCK rising edge (default) 1 = MCK falling edge Refer to the Slave Mode: VD, HD Specifications section for details. Field Index Field for two-field operation is detected. The detection method is selected to the VD and HD phase or Register. The Field output signal is selected by a register, as shown in Table 43. ODD detect range is selected by register 02Fh[5:0]. More than seven enabled instructions will always odd detect. Refer to the Configuration Register and Slave Mode: VD, HD Specifications section for details. Table 43. ODD/EVEN Detect Register PARAMETER REGISTER ADDRESS DESCRIPTION Detect method 022h[3] 0 = VD/HD phase (default) 1 = Register (035h[0]) Register select 035h[0] 0 = ODD (default) 1 = EVEN Field POL 022h[4] 0 = Low at ODD, high at EVEN (default) 1 = High at ODD, low at EVEN VD even 022h[5] 0 = Disabled (default) 1 = Enabled Master Mode The system synchronizes the external master clock, internal HD, and internal VD. Note that the HD and VD pins are output modes. HD and VD timing are provided by the HA command. HCYCLE is provided by an end-of-line instruction of the HA command. VCYCLE is provided by the end-of-frame instruction of the VA command. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 47 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com HORIZONTAL SEQUENCE The horizontal sequence contains toggling information for 1H. Each word describes toggling information. The user must input 2-bit delay information, 2-bit toggling information, 5-bit terminal assignment, and 13-bit pixel count. TG decodes the pixel count and precedes each event sequentially according to the address. A maximum of four signals toggling at the same pixel counter are allowed using the 2-bit delay instruction. Horizontal Address (HA) Memory The HA memory area is shown in Table 44. Table 44. HA Memory Area PARAMETER DESCRIPTION Address 200h-3FFh Memory area 512 words Data width 22-bit Basic Functionality Table 45 defines the terminal assignment (5-bit) command and pixel address for toggling. Table 45. HA Bit Function 21 20 19 Delay 18 17 16 Toggle 15 14 13 12 11 10 9 8 7 Terminal 6 5 4 3 2 1 0 Pixel count BITS NAME 21-20 DELAY DESCRIPTION 19-18 TOGGLE 17-13 TERMINAL Terminal assignment using five bit. Terminal: V0N-12N, P0-5, CLPDM, CLPOB, PBLK, HBLK, HDIV, HD (master mode), and VD (master mode) Refer to the Signal section for details. 12-0 PIXEL CNT Toggling of the pixel count using 13 bits (10-8191). Bits below 9 are prohibited. Order in one HA part must be added order. Same pixel count is prohibited. Toggling delay pixel number using two bits (0-3) Toggling set to high/low using two bits 00b = Low, 01b = High General Instruction Table 46 details the VCCD high-speed start and end-of-line commands. Table 46. HA Instruction Bit Function 21 20 19 18 General instruction GENERAL INSTRUCTION 17 16 15 14 13 1 1 1 1 1 12 11 10 General instruction fix 9 8 7 6 5 4 3 2 1 0 Pixel count (same as for Table 45) NAME DESCRIPTION The end-of-line reset pixel counter is at the pixel number. 1111b 48 EOL Mode Pixel Number Master Target HCYCLE – 1 + register 034h[3:0] Slave 8191 0001b Start HS 1 Start VCCD high-speed transfer (HS 1) 0010b Start HS 2 Start VCCD high-speed transfer (HS 2) 0011b Start HS 3 Start VCCD high-speed transfer (HS 3) 0100b Start HS 4 Start VCCD high-speed transfer (HS 4) 0101b Stop HS Stop VCCD high-speed transfer Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 VHIGH-SPEED Transfer (HS) Instruction Two sets of commands specify the HS start/stop information and the HS toggling pixel address information. As shown in Table 47, HS start/stop information is part of the horizontal memory. Four types of HS are available using the [21:18] bit instruction. An HA programming example is shown in Table 47. Note that sync mode is a slave mode. Table 47. Horizontal Memory Example MEMORY ADDRESS FIXED [31] SEQUENTIAL [30:22] DELAY [21:20] TOGGLING [19:18] TERMINAL ASSIGNMENT [17:13] PIXEL COUNT [12:0] 1 0 0000 0000b (A1h-1h) 00b 00b 11001b (CLPOB) 0 0000 0000 1010b (10) 1 0 0000 0001b (A1h-2h) 00b 01b 11001b (CLPOB) 0 0000 0010 1000b (40) 1 0 0000 0010b (A1h-3h) 00b 00b 11011b (HBLK) 0 0000 0011 0011b (51) 1 0 0000 0011b (A1h-4h) 01b 01b 00001b (V0N flexible) 0 0000 0011 1111b (63) 1 0 0000 0100b (A1h-5h) 00b 01b 00010b (V1N flexible) 0 0000 0100 0000b (64) 1 0 0000 0101b (A1h-6h) 00b 00b 00001b (V0N flexible) 0 0000 0110 0100b (100) 1 0 0000 0110b (A1h-7h) 00b 00b 00010b (V1N flexible) 0 0000 1001 0110b (150) 1 0 0000 0111b (A1h-8h) 00b 01b 11011b (HBLK) 0 0000 1111 0001b (241) 1 0 0000 1000b (A1h-9h) 00b 00b 11000b (CLPDM) 0 0000 1111 1010b (250) 1 0 0000 1001b (A1h-10h) 00b 01b 11000b (CLPDM) 0 0001 0001 1000b (280) 1 0 0000 1010b (A1h-11h) 11111b (general instruction) 1 1111 1111 1111b (8191) 1111b (EOL) Figure 41 shows the horizontal timing. Sequentially input 22-bit data for each toggling position. HA1-10 HA1-8 HA1-9 HA1-7 HA1-6 HA1-5 HA1-4 HA1-3 HA1-2 HA1-1 CCD Format Dummy Active OB 2000 1 Active HD HG1 51 241 HBLK 10 40 CLPOB 250 CLPDM 64 280 100 V0N 64 150 V1N Figure 41. Horizontal Timing Example Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 49 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com VERTICAL SEQUENCE The vertical sequence consists of elements of the Horizontal Sequence. Each word contains a horizontal memory address and a line number, which is applied for the operation. The user must input 1-bit loading information, 9-bit HA address, and 12-bit line number. The TG decodes the line count and precedes each event sequentially according to the address. Vertical Address (VA) Memory The VA is detailed in Table 48 and Table 49. Table 48. VA Memory Area PARAMETER DESCRIPTION Address 180h-1FFh Memory area 128 words Data width 22-bit Table 49. VA Number Start Address VA NUMBER 1 2 3 4 5 6 7 8 Start address 180h 190h 1A0h 1B0h 1C0h 1D0h 1E0h 1F0h Basic Functionality Table 50 defines the HA (horizontal address) command and HA pattern apply line number command. Table 50. VA Bit Function 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 (1) (1) 50 HA ADD LINE VLOAD. BITS NAME 21 VLOAD 20-12 HA ADD 11-0 LINE DESCRIPTION Vertical timing load, fixed at '0' HA address load using 9-bit, HA address = (HA physical memory address) – 512 Line count using 12-bit (1-4095). Order in one VA must be added order. Same line count is prohibited. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 MISC Instruction Table 51 shows the vertical command apply line number command. Table 51. VA Instruction Bit Function 21 20 19 18 0 (1) (1) 17 16 15 14 13 12 X X X X X Instruction 11 10 9 8 7 Don't care 6 5 4 3 2 1 0 LINE VLOAD. BITS NAME 21 VLOAD Vertical timing load, fixed at '0' DESCRIPTION 11-0 LINE Line count using 12-bit (1-4095). Order in one VA must be added order. Same line count is not prohibited. INSTRUCTION NAME DESCRIPTION End of frame, reset line counter. In master mode, renew frame mode. 1111b EOF MODE LINE NUMBER Master Slave Target VCYCLE + 1 4095 Initialize pin output at line 1. (V0N-12N, P0-5, SUBN, CLPDM, CLPOB, PBLK, HBLK, HDIV, FIELD, STROBE, MSHUT, SUBSW1, and SUBSW2) 0001b Initialize 0010b Reserved Reserved 0011b RUPDATE Register update. Renew TG register (H037-H0A3) at line number. 0100b Start event 1 Start VCCD high-speed transfer (dynamic mode) 1 at line number. 0101b Start event 2 Start VCCD high-speed transfer (dynamic mode) 2 at line number. 0110b End event 0111b Frame counter reset Stop VCCD high-speed transfer (dynamic mode) at line number. Frame counter reset. Reset and start frame counter at line 1. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 51 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com VA programming is shown in Table 52. Sync mode is a slave mode. Table 52. Vertical Memory Example MEMORY ADDRESS SEQUENTIAL [29:22] LOAD [21] HA ADDRESS (0-511) OR INSTRUCTION [20:12] LINE COUNT [11:0] 01b 1000 0000b (VA1-0) 0 0 0000 0000b (A1h) 0000 0000 0001b (01) 01b 1000 0001b (VA1-1) 1 0 0010 0000b (initialize) 0000 0000 0001b (01) 01b 1000 0010b (VA1-2) 1 0 1110 0000b (frame count reset) 0000 0000 0001b (01) 01b 1000 0011b (VA1-3) 0 0 0001 0000b (A2h) 0000 0010 0001b (33) 01b 1000 0100b (VA1-4) 0 0 0001 1101b (A3h) 0000 0010 0010b (34) 01b 1000 0101b (VA1-5) 0 0 0011 0011b (A4h) 0000 0010 0011b (35) 01b 1000 0110b (VA1-6) 0 0 0000 0001b (A1h) 0000 0010 0100b (36) 01b 1000 0110b (VA1-7) 1 1 1110 0000b (end of frame) 1111 1111 1111b (4095) FIXED [31:30] HA1 41 42 43 45 HA1 40 44 HA1 39 HA1 HA1 38 HA1 HA1 37 HA1 36 HA1 35 32 VA1-6 HA1 31 VA1-4 HA3 HA1 30 VA1-5 HA4 HA1 29 33 HA1 28 34 HA1 27 VA1-3 HA2 HA1 HA1 HA1 4 3 HA1 HA1 HA1 1 2 VA1-0 HA1 HA1 1259 HA1 1257 HA1 1258 HA1 1256 HA1 1254 HA1 1255 HA1 1253 HD VD V0N P0 Figure 42. Vertical Timing Example VERTICAL HIGH-SPEED (HS) TRANSFER SEQUENCE The vertical high-speed (HS) transfer shifts a charge for a specified number of lines. The still mode and electric zoom use HS. Counter start of HS has three pixel delays from the Start HS command of HA. The vertical high-speed transfer has both a programmed operation mode and register dynamic mode. HS Memory HS memory is described in Table 53 and Table 54. Table 53. HS Memory Area PARAMETER DESCRIPTION Address 100h-17Fh Memory area 128 words Data width 16-bit Table 54. HS Number Start Address 52 HS NUMBER 1 2 3 4 Start address 100h 120h 140h 160h Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Basic Functionality Table 55 describes the HS basic functionality. Table 55. HS Bit Function 15 14 Delay 13 12 Toggle 11 10 9 8 7 6 5 Terminal 4 3 2 1 0 1 0 Pixel count BITS NAME 15-14 DELAY DESCRIPTION 13 TOGGLE HS delay using two bits (0-3) HS is set to high/low 0 = Low, 1 = High HS pin using four bits (1-13) 12-9 TERMINAL 8-0 PIXEL CNT TERMINAL NUMBER V 1 V0N 13 V12N HS toggling pixel using nine bits (1-511) Instruction Table 56 details the HS instruction. Table 56. HS Instruction Bit Function 15 14 13 12 11 10 9 8 7 6 5 General instruction 4 3 2 Pixel count GENERAL INSTRUCTION NAME DESCRIPTION 111 0000b Repeat Reset HS pixel counter, pixel number = target cycle – 1 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 53 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Programmed Operation Mode The VHIGH-SPEED transfer function is used to clear the VCCD. The HS pattern is supplied in the HS memory area. The pattern can be provided four types. HS start and stop timing is provided in the HA memory area. The operation continues until a decoding stop command of HA. VTOGGLING must not be provided under an HS operation. 1. Provide toggling information in HS memory. 2. Provide HS start and stop instruction in the HA memory with no VTOGGLING of HA. 3. Provide the above HA to the VA memory. VCCD Clear Example Figure 43 shows an example of a programmable operation mode. 0 HA1-1: CPOB¯ at Pixel 10 1 HA1-2: CPOB at Pixel 40 1: V2N¯ at Pixel 1 2 HA1-3: PBLK¯ at Pixel 51 2: V0N at Pixel 21 3 HA1-4: V2N at Pixel 52 (2) (1) VA1-2: HA2 Start at Line 2 (VHIGH-SPEED #1 Blank) ¼ VA1-3: HA3 Start at Line 80 (VHIGH-SPEED #1 End) ¼ VHIGH-SPEED Transfer #1 13: Repeat at Pixel 179 HA1: VHIGH-SPEED #1 Start at Pixel 561 Repeat ¼ VA1-16: HA4 Start at Line150 9 HA1-10: EOL at Pixel 1023 Call HA Address = 10 VHIGH-SPEED Transfer #1 10 HA2-1: CPOB¯ at Pixel 10 HA2-2: CPOB at Pixel 40 12 HA2-3: PBLK¯ at Pixel 51 ¼ 11 16 HA2-7: EOL at Pixel 1023 17 HA3-1: CPOB¯ at Pixel 10 18 HA3-2: CPOB at Pixel 40 19 HA3-3: PBLK¯ at Pixel 51 20 HA3-4: VHIGH-SPEED End at Pixel 2432 26 HA3-10: EOL at Pixel 1023 Do Not Provide VTOGGLING Call HA Address = 17 ¼ 16 Words Transfer #1 ¼ HA Address = 0 VA1-1: HA1 Start at Line 1 (VHIGH-SPEED #1 Start) VHIGH-SPEED Transfer Data Set (HS) Horizontal Data Set (HA) Call Vertical Data Set (VA) Start VHIGH-SPEED HA Address Note (2) VHIGH-SPEED Transfer #1 End VHIGH-SPEED (3) ¼ Transfer NOTE: Shaded cells indicate the area under discussion. (1) The HA command block is called by a VA command. (2) The HS loop sequence is started by an HA command at the selected pixel. (3) The HS loop sequence is stopped by an HA command at the selected pixel. (4) Line number, pixel number, and start of HA address are programmable. Figure 43. Programmed Operation Mode Sequence 54 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 As shown in Table 57, VHIGH-SPEED toggling pixel address information is part of the HS memory. Input toggling points for one vertical transfer and one cycle address for repeat. Table 57. V High-Speed Toggling Memory Example MEMORY ADDRESS FIXED SEQUENTIAL DELAY [15:14] SET [13] TERMINAL ASSIGNMENT [12:9] PIXEL COUNT [8:0] 01b 0000 0000b (HS 1-1) 00b 0 0011b 0 0000 0001b (1) 01b 0000 0001b (HS 1-2) 00b 1 0001b 0 0001 0101b (21) 01b 0000 0010b (HS 1-3) 01b 0 0100b 0 0010 1001b (41) 01b 0000 0011b (HS 1-4) 00b 1 0010b 0 0011 1101b (61) — — — — — — 01b 0000 0100b (HS 1-5) 11b 1 0000b (repeat) 0 1011 0011 (179) Vertical High-Speed Transfer, One Cycle 21 81 V0N 61 141 V1N 1 101 180 V2N 41 121 V3N (0) (1) Figure 44. HS One Cycle Example The HS start and stop command of HA is delayed by three pixel terms. Table 58 shows the delay. Table 58. HA and HS Pixel Count ITEM LINE NUMBER HA PIXEL COUNT HS PIXEL COUNT HA1 VHIGH-SPEED transfer start. 1 561 — VHIGH-SPEED transfer counter start and V2 pulled low. 1 564 1 — — — — HA3 VHIGH-SPEED transfer stop. 80 2432 177 VHIGH-SPEED transfer cycle end. 80 2435 180 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 55 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com High-Speed Transfer End Point High-Speed Transfer Start Point (1 H) HD 64 (80 H) 100 584 644 2336 V0N 88 124 624 2376 684 V1N 52 112 564 664 2356 V2N 176 136 604 704 2396 Vn (0) (1) (2) (639) (640) Figure 45. HS Timing Chart Example Figure 46 shows the programmed operation mode for a still picture. Line (HA Number) Pix Number VHIGH-SPEED VHIGH-SPEED Counter V0N V1N V2N Vn HD CCD Operation Mode Start HA 1 1 1 HA #1 VHIGH-SPEED Transfer #1 HA #2 HA 3 Stop HA #3 Readout HA #6 HA 5 HA #5 Active Signal HA #11 NOTE: Shaded cells indicate the area under discussion. Figure 46. Programmed Operation Mode for A Still Picture 56 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Example for Electrical Zoom Figure 47 shows the programmed operation mode for an electric zoom function. Line (HA Naumber) Pix Number VHIGH-SPEED Enable Pix Number VHIGH-SPEED Counter V0N V1N V2N Vn HD CCD Operation Mode Start HA 1 1 1 HA #1 VHIGH-SPEED Transfer #1 HA #2 Stop HA 3 HA #3 Readout HA #6 HA 5 1 HA #5 Start 1 VHIGH-SPEED Transfer #2 HA #10 HA 11 Stop HA #11 Active Signal NOTE: Shaded cells indicate the area under discussion. Figure 47. Programmed Operation Mode for An Electric Zoom Function Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 57 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Register Dynamic Operation Mode The HS changes for a specified number of lines. Specifically, the electric zoom requires a dynamic adjustment of the vertical transfer line number. In addition to the programmed operation mode, the HS enables/disables the line number memory and VEVENT counter; the VEVENT start/stop register enables the dynamic adjustment. HS enable/disable memory is included in the vertical memory area. A VEVENT start command resets the VEVENT counter (bit) at a specified line count. Follow this recommended procedure to: 1. Select the VSIGNAL for the event function. All VSIGNALS for a VHIGH-SPEED transfer must be enabled by a register setting, as shown in Table 59. 2. Select the VSIGNAL for the event counter trigger. This signal counts up the event counter, as shown in Table 60. The last signal of the VHIGH-SPEED transfer is useful. 3. Provide toggling information in the HS memory. 4. Provide HS start and stop instruction in the HA memory. Refer to the Horizontal Sequence section for details. 5. Provide Event instruction in the VA memory. Refer to the Vertical Sequence section for details. 6. Set the event count value for an event start and stop, as shown in Table 61. Table 59. VEVENT Pin Register (1) (1) PARAMETER REGISTER ADDRESS VEVENT pin 030h-032h Refer to the Configuration Register section for details. Table 60. Event Counter Trigger Select Register PARAMETER REGISTER ADDRESS TRG pin 033h[4:0] TRG edge 033h[5] DESCRIPTION Terminal number (V0N-12N) Refer to the Signal section for details. Default = 00000b. 0 = Rising edge (default) 1 = Falling edge Table 61. Event Start/Stop Register PARAMETER EVENT 1 EVENT 2 58 REGISTER ADDRESS Start 037h, 038h Stop 039h, 03Ah Start 03Bh, 03Ch Stop 03Dh, 03Eh Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Horizontal Data Set (HA) Call Vertical Data Set (VA) HA Address = 0 (1) VA1-1: HA1 Start at L ine1 (VHIGH-SPEED #1 Start) 2 HA1-3: PBLK¯ at Pixel 51 3 HA1-4: V2N¯ at Pixel 52 VA1-5: HA3 Start at Line 38 (VHIGH-SPEED #1 End) VA1-7: HA6 Start at Line 39 VA1-9: Instruction at Line 120 Start Event 2 VA1-10: HA2 Start at Line 121 (blank) VA1-11: HA11 Start at Line 157 (VHIGH-SPEED End) 2: V0N at Pixel 21 0 Note (4) 13: Repeat at Pixel 179 HA1: VHIGH-SPEED #1 Start at Pixel 561 VA1-6: Instruction at Line 38 End Event VA1-8: HA5 Start at Line 120 (VHIGH-SPEED #2 Start) 1: V2N¯ at Pixel 1 Note (3) Repeat 9 HA1-10: EOL at Pixel 1023 Call HA Address = 10 VHIGH-SPEED Transfer #1 10 HA2-1: CPOB¯ at Pixel 10 11 HA2-2: CPOB at Pixel 40 12 HA2-3: PBLK¯ at Pixel 51 Do Not Provide VTOGGLING ¼ VA1-12: Instruction at Line 157 End Event 1 ¼ Note (8) HA1-2: CPOB at Pixel 40 Event Counter VHIGH-SPEED Transfer #1 ¼ Note (7) VA1-2: Instruction at Line 1 Start Event 1 VA1-4: HA2 Start at Line 2 (blank) 1 VHIGH-SPEED Transfer Data Set (HS) ¼ Note (2) 0 HA1-1: CPOB¯ at Pixel 10 Start VHIGH-SPEED Transfer#1 ¼ HA Address VA1-13: HA4 Start at Line 158 16 HA2-7: EOL at Pixel 1023 Call HA Address = 17 VHIGH-SPEED Transfer #1 HA3-1: CPOB¯ at Pixel 10 18 HA3-2: CPOB at Pixel 40 19 HA3-3: PBLK¯ at Pixel 51 20 HA3-4: VHIGH-SPEED End at Pixel 2432 26 Stop Note (7) ¼ 17 29 Note (5) HA3-10: EOL at Pixel 1023 Note (6) Item Event # Event 1 Start 0 Event 1 Stop 29 Event 2 Start 0 Event 2 Stop 29 NOTE: Shaded cells indicate the area under discussion. (1) The HA command block is called by the VA command. (2) Event 1 is started by a VA command at same line number as that of note 1. (3) The HS loop sequence is started by an HA command at the selected pixel number. However, the vertical signal does not output. (4) The event counter is increased by one count a trigger vertical signal. (5) When the event counter reaches the value of the Event 1 Start register, the vertical signal starts to output. (6) When the event counter reaches the value of the Event 1 Stop register, the vertical signal stops outputting. (7) The HS loop sequence is stopped by an HA command at the selected pixel number. (8) The event is stopped by a VA command at the same line number as in note 7. (9) Line number, pixel number, and start of the HA address are programmable. The operation of event 2 is the same as event 1. Figure 48. Register Dynamic Operation Mode Sequence Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 59 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Table 62. Event Start/Stop (1) PARAMETER (1) EVENT NUMBER Event 1 start 0 Event 1 stop 29 Event 2 start 0 Event 2 stop 29 The operation of Event 2 is the same as Event 1. Vertical high-speed transfer has higher priority than any other vertical transfer instruction. Figure 49 shows the register dynamic operation mode for an electric zoom. Line (HA Number) Pix Number VHIGH-SPEED (HA) VHIGH-SPEED Counter V0N V1N V2N Vn HD VEVENT Counter Event Counter Number VA Line Number CCD Operation Mode 0 HA 1 0 Start 1 0 HA #1 1 1 Event #1 Event #1 VHIGH-SPEED Transfer #1 29 29 HA #2 38 Non VSIGNAL HA 3 Stop HA #3 Readout HA #6 HA 5 Start 1 0 120 HA #5 1 1 2 Event #2 Event #2 HA #2 VHIGH-SPEED Transfer #2 HA 11 Stop 29 29 HA #11 157 Non VSIGNAL NOTE: Shaded cells indicate the area under discussion. Figure 49. Register Dynamic Operation Mode for Electric Zoom Function 60 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 FRAME COUNT FUNCTION The frame counter counts up by '1' for each VD update event. The frame counter range is from 1 to 63. This counter value is controlled by the following functions: • SUBSW1 and SUBSW2 control • MSHUT control • Strobe control A counter reset is accomplished by the following operation. The counter value is '1' after reset. • VA instruction (Refer to the Vertical Sequence section for details.) • TRIG (Refer to the Trigger Function section for details.) If the counter value reaches the maximum value (63), the value can only be changed with a frame counter reset. Table 63. Frame Counter Register PARAMETER REGISTER ADDRESS Frame Counter 022h[2] DESCRIPTION 0 = Disabled (default) 1 = Enabled TG REGISTER UPDATE FUNCTION Some registers of the TG section can be selected for update timing. Refer to the Register Update section of the Common Section for details. PIXEL COUNTER PRESET The preset value of the horizontal sequence pixel counter is set, as shown in Table 64. Table 64. Pixel Counter Preset Register PARAMETER REGISTER ADDRESS Pixel Counter Preset 034h[3:0] DESCRIPTION Slave = 6 (default) Master = 0 (recommend) ELECTRIC SHUTTER FUNCTION The electric shutter is operated by the SUBN pattern setting and SUBN pattern change setting. SUBN Pattern Setting The SUBN pattern has four types of toggling positions that are stored in the registers shown in Table 65. Patterns 2 and 3 enable fine pitch integration time control. Table 65. SUBN Pattern Register (1) (1) PATTERN REGISTER ADDRESS Point 1 pixel number and polarity 08Ch-08Eh Point 2 pixel number and polarity 08Fh-091h Point 3 pixel number and polarity 092h-094h Point 4 pixel number and polarity 095h-097h Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 61 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com The SUBN pattern is specified by each point combination, as Table 66 shows. Table 66. SUBN Pattern Description PATTERN DESCRIPTION 0 Non SUBN pulse 1 Operation of point 1 and point 2 2 Operation of point 3 and point 4 3 Operation of points 1 to 4 Table 67 describes an example SUBN pattern. Figure 50 shows a four-pattern example of an electric shutter. Table 67. SUBN Pattern Example TOGGLE POINT PIXEL NUMBER POLARITY 1 50 0 2 80 1 3 180 0 4 210 1 Toggle Point 1 Toggle Point 2 Toggle Point 3 Toggle Point 4 50 80 180 210 HD Pattern 0 Pattern 1 Pattern 2 Pattern 3 Figure 50. Electric Shutter Four-Pattern Example SUBN Pattern Change The electric shutter function has four sequential registers, as shown in Table 68. For each register, the SUBN pattern is assigned among four types of patterns and is selected at the pattern change point. Table 68. SUBN Pattern Change (1) PARAMETER (1) REGISTER ADDRESS Pattern change point 1 line number and SUBN pattern number 098h-09Ah Pattern change point 2 line number and SUBN pattern number 09Bh-09Dh Pattern change point 3 line number and SUBN pattern number 09Eh-0A0h Pattern change point 4 line number and SUBN pattern number 0A1h-0A3h Refer to the Configuration Register section for details. Table 69 lists an electrical shutter example method with the register update function activated. Table 69. Register Update Setting 62 PARAMETER REGISTER ADDRESS VALUE TG Update 000h[3] 1 = VA Internal instruction (R_UPDATE) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 This example method has three cases of exposure time within one frame cycle. Table 70 lists several electrical shutter parameters. Table 70. Electrical Shutter Parameter PARAMETER LINE NUMBER SUBN operation term A Exposure time B Read out C 1 frame cycle D R_UPDATE 1 NOTE Use with calculation of Table 71 Should be provided at the VA internal instruction Table 71. SUBN Start and End Line Number (1) LINE NUMBER CASE (1) DESCRIPTION CONDITION SUBN_START SUBN_END 1 Line number 1 ≤ SUBN_Start < SUBN _End < Read_out C–B–A≥0 C–B–A C–B 2 Line number 1 ≤ SUBN _End < Read_out < SUBN _Start (C – B ≥ 0) and (C – B – A < 0) D + (C – B – A) C–B 3 Line number 1 < Read_out < SUBN _Start < SUBN _End C–B<0 D + (C – B – A) D + (C – B) Line number ≠ Read_out, and Read_out ≠ SUBN _Start ≠ SUBN _End. An actual value example is shown in Table 72. Table 72. Example Parameter PARAMETER LINE NUMBER VALUE SUBN operation term A 28 Read out C 34 1 frame cycle D 1259 Table 73. Example Parameter for Each Case (1) LINE NUMBER CASE (1) DESCRIPTION INTEGRATION TIME SUBN_START SUBN_END C – B = 32 1 Line number 1 ≤ SUBN_Start < SUBN _End < Read_out B=2 C–B–A=4 2 Line number 1 ≤ SUBN _End < Read_out < SUBN _Start B=6 D + (C – B – A) = 1259 C – B = 28 3 Line number 1 < Read_out < SUBN _Start < SUBN _End B = 1229 D + (C – B – A) = 36 D + (C – B) = 64 Actual integration time is increased less than 1H by SUBN pattern three. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 63 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Case 1: Line Number 1 ≤ SUBN_Start < SUBN _End < Read_out Table 74. Register Setting: Case 1 PATTERN CHANGE POINT LINE NUMBER SUBN PATTERN 1 1 0 (non SUBN) NOTE — 2 4 1 SUBN_Start 3 31 3 — 4 32 0 (non SUBN) SUBN_End 45 43 44 42 41 40 38 39 35 37 36 34 33 32 31 30 29 28 27 3 4 1 2 1259 1258 1257 1256 1253 1255 1254 VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P5 SUBN Fine Pitch Integration Time 0 SUBN Pattern Number 0 1 Point 1 3 Point 2 Point 3 0 Point 4 Figure 51. Electrical Shutter Timing: Case 1 Case 2: Line Number 1 ≤ SUBN_End < Read_out < SUBN _Start Table 75. Register Setting: Case 2 PATTERN CHANGE POINT LINE NUMBER SUBN PATTERN NOTE 1 1 1 — 2 27 3 — 3 28 0 (non SUBN) SUBN_End 4 1259 1 SUBN_Start 45 43 44 41 42 40 38 39 35 37 36 33 34 32 31 30 28 29 27 3 4 1 2 1259 1258 1257 1256 1253 1255 1254 VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P5 SUBN SUBN Pattern Number 0 1 Point 4 1 Point 1 3 Point 2 Fine Pitch Integration Time 0 Point 3 Figure 52. Electrical Shutter Timing: Case 2 64 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Case 3: Line Number 1 < Read_out < SUBN_Start < SUBN _End Table 76. Register Setting: Case 3 PATTERN CHANGE POINT LINE NUMBER SUBN PATTERN 1 1 0 (non SUBN) NOTE — 2 36 1 SUBN_Start 3 63 3 — 4 64 0 (non SUBN) SUBN_End 67 65 66 63 64 61 62 35 37 36 33 34 32 31 30 28 29 27 3 4 1 2 1259 1258 1257 1256 1253 1255 1254 VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P5 SUBN Fine Pitch Integration Time 0 SUBN Pattern Number 0 Point 1 1 Point 2 3 Point 3 0 Point 4 Figure 53. Electrical Shutter Timing: Case 3 SUBSW FUNCTION The still mode uses an SUBSW1 and SUBSW2 function with two toggling registers for SUBSW1 and SUBSW2, respectively. The instruction consists of a frame number, line number, and polarity, as shown in Table 77. Table 77. SUBSW Register (1) PARAMETER Point 1 SUBSW1 Point 2 Point 1 SUBSW2 Point 2 (1) REGISTER ADDRESS Line number 07Ch, 07Dh Frame number 07Eh Polarity 07Fh Line number 080h, 081h Frame number 082h Polarity 083h Line number 084h, 085h Frame number 086h Polarity 087h Line number 088h, 089h Frame number 08Ah Polarity 08Bh Refer to the Configuration Register and Frame Count Function sections for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 65 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Table 78 and Figure 54 show an example SUBSW register and operation, respectively. Table 78. SUBSW Register Example PARAMETER VALUE Point 1 SUBSW1 Point 2 Frame Number Line number 1259 Frame number 1 Polarity 1 Line number 35 Frame number 2 Polarity 0 1 2 45 43 44 41 42 40 38 39 37 36 35 34 33 31 32 30 28 29 27 3 4 1 2 1258 1259 1257 1255 1256 1254 1253 VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P5 SUBN Point 1 Point 2 SUBSW1 Figure 54. SUBSW Operation Example 66 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 MSHUT Function The mechanical shutter function has a total of two words. The instruction consists of a frame number, line number, pixel number, and polarity, as shown in Table 79. Table 79. MSHUT Register (1) PARAMETER (1) REGISTER ADDRESS Point 1 Pixel number, line number, frame number, and polarity 040h-045h Point 2 Pixel number, line number, frame number, and polarity 046h-04Bh Refer to the Configuration Register and Frame Count Function sections for details. Table 80 and Figure 55 show an example MSHUT register and operation, respectively. Table 80. MSHUT Register Example PARAMETER Point 1 Point 2 Frame Number VALUE Pixel number 900 Line number 1253 Frame number 1 Polarity 1 Pixel number 400 Line number 1259 Frame number 1 Polarity 0 1 2 45 44 43 41 42 40 38 39 37 35 36 33 34 32 31 30 29 28 27 4 3 1 (628) (629) 2 1258 1259 (626) (627) (625) 1257 1255 (623) (624) 1256 1253 1254 HD V1N CH2, CH4 Point 1 Point 2 MSHUT Figure 55. MSHUT Operation Example STROBE FUNCTION The strobe shutter function has eight words. The instruction consists of a frame number, line number, pixel number, and polarity, as shown in Table 81. Table 81. Strobe Register (1) PARAMETER (1) REGISTER ADDRESS Point 1 Pixel number, line number, frame number, and polarity Point 2 Pixel number, line number, frame number, and polarity 04Ch-051h 052h-057h Point 3 Pixel number, line number, frame number, and polarity 058h-05Dh Point 4 Pixel number, line number, frame number, and polarity 05Eh-063h Point 5 Pixel number, line number, frame number, and polarity 064h-069h Point 6 Pixel number, line number, frame number, and polarity 06Ah-06Fh Point 7 Pixel number, line number, frame number, and polarity 070h-075h Point 8 Pixel number, line number, frame number, and polarity 076h-07Bh Refer to the Configuration Register and Frame Count Function sections for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 67 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Table 82 and Figure 56 show an example strobe register and operation, respectively. Table 82. Strobe Register Example PARAMETER Point 1 Point 2 Point 3 Point 4 Frame Number VALUE Pixel number 200 Line number 1257 Frame number 1 Polarity 1 Pixel number 500 Line number 1 Frame number 2 Polarity 0 Pixel number 800 Line number 4 Frame number 2 Polarity 1 Pixel number 300 Line number 31 Frame number 2 Polarity 0 1 2 45 44 43 41 42 40 38 39 37 35 36 33 34 32 31 30 29 27 28 3 4 (629) 2 1259 (628) 1 1258 (626) (627) (625) 1257 1255 (623) (624) 1256 1253 1254 HD V1N CH2, CH4 Point 1 Point 2 Point 3 Point 4 STROBE Figure 56. Strobe Operation Example HBLK FUNCTION The horizontal blank signal (HBLK) controls the H1, H2, and HL outputs. H1 and HL are high and H2 is low during blanking time. HBLK timing is provided by HA memory command. An example HBLK timing sequence is shown in Figure 57. HD HG1A, HG1B, HL HG2A, HG2B HBLK Figure 57. Horizontal Blanking Timing Example 68 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 HDIV FUNCTION The motion picture CCD requires horizontal transfer during horizontal blanking. Select the horizontal transfer clock rate (divide H clock) from 2, 4, 6, 8, 10, or 12 by register (01Bh[2:0]). HDIV timing is provided by HA memory command. An example HDIV timing is shown in Figure 58. HD HG1A, HG1B, HL HG2A, HG2B HBLK HDIV Figure 58. Motion Picture CCD Timing Example SHP/SHD SKIPPING An SHP and SHD skipping function is supported by VSP01M01 and VSP01M02. The skipping ratio is selected by the register, as shown in Table 83. Table 83. SHP and SHD Skipping Register (1) (1) PARAMETER REGISTER ADDRESS SHP/SHD skipping 01Dh, 01Eh Refer to the Configuration Register section for details. TRIGGER FUNCTION Load TRIG Frame The TRIG frame number is operated by the falling edge of the TRIG signal. The required register setting is shown in Table 84. For an example, refer to the CCD Timing Composition section. Table 84. Load TRIG Frame Register Setting (1) (1) PARAMETER REGISTER ADDRESS VALUE TRIG frame INCR 021h[2] 1 = Enabled TRIG counter RST 021[3] 1 = Enabled TRIG frame number 036h[5:3] 1-7 Refer to the Configuration Register section for details. TG Stop TG is stopped by a TRIG signal polarity. The required register setting is shown in Table 85. Table 85. TG Stop Register Setting (1) (1) PARAMETER REGISTER ADDRESS VALUE MCK detect 020h[4] 0 = Disabled TG CLK stop 021h[1] 1 = Enabled TRIG POL 021h[0] 0 = High or 1 = Low Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 69 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Figure 59 shows a CCD timing composition example that operates the Long Time Exposure by TRIG. The falling edge of the TRIG (external trigger) signal reset line counter changes during the next frame. TG is stopped when the TRIG signal is high. Controller OUT1 OUT2 OUT3 CS SCLK SDATA OUT4 TRIG AFE Figure 59. TRIG Signal Connection Example Table 86. Long-Time Exposure by TRIG Example (1) (1) 70 PARAMETER REGISTER ADDRESS VALUE VD frame 022h[0] 1 = Enabled TRIG frame INCR 021h[2] 1 = Enabled TRIG counter RST 021h[3] 1 = Enabled Static frame number 036h[2:0] 0 or 2 TRIG frame number 036h[5:3] 6 or 7 MCK detect 020h[4] 0 = Disabled TG CLK stop 021h[1] 0 = Disabled 1 = Enabled (between A and B) TRIG POL 021h[0] 0 = High Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Frame Number By Frame Now Register (036h[2:0]) Frame Number By Frame TRG Register (036h[5:3]) VA Operation Number VD (Master) SUB TG CLK STOP (021h[1]) TRIG (External) Line Counter HD 1H Standard Function Monitor Mode 1 Disable HA #1 Readout HA #2 OB HA #3 Active Signal HA #4 Dummy HA #20 0 (VA #1) VA #1 Exposure Enable No Function Long Time Exposure Mode A Freeze B 1 Disable Standard Function Still Mode VHIGH-SPEED Transfer HA #5 Readout HA #8 OB HA #9 VA #7 6 (VA #7) Not Operational 1 VBLANKING 7 (VA #8) 2 (VA #3) VA #8 HA #10 Active Signal 1 OB HA #9 VBLANKING HA #11 VA #3 NOTE: Shaded cells indicate the area under discussion. Figure 60. Long-Time Exposure by TRIG Example Frame Counter Reset The frame counter is reset by the falling edge of the TRIG signal. The required register setting is shown in Table 87. Table 87. Frame Counter Reset Register Setting (1) (1) PARAMETER REGISTER ADDRESS VALUE Frame counter 022h[2] 1 = Enabled Frame RST 021h[4] 1 = Enabled TRIG counter RST 021h[3] 1 = Enabled Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 71 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com VDRIVER SECTION Signal Connection and Truth Table 3-State Output Table 88. 3-State Output INPUT (TG OUTPUT) OUTPUT (DEVICE PIN OUTPUT) SIGNAL NAME VxN Px V1N P1 SIGNAL NAME P2 V3N P4 P3 V5N P5 TRUTH TABLE VxN Low High Px LEVEL Low VH High VM Low Hi-Z High VL 2-State Output Table 89. 2-State Output INPUT (TG OUTPUT) OUTPUT (DEVICE PIN OUTPUT) SIGNAL NAME VxN SIGNAL NAME V2N V2 V4N V4 V6N V6 TRUTH TABLE VxN LEVEL Low VM High VL SUB 2-State Output Table 90. SUB 2-State Output INPUT (TG OUTPUT) OUTPUT (DEVICE PIN OUTPUT) SIGNAL NAME SIGNAL NAME SUBN SUB TRUTH TABLE SUBN LEVEL Low VH High VL Output Hi-Z = high impedance VH = high level VM = middle level VL = low level 72 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 CONFIGURATION REGISTER The 6-bit register area is described in Table 91. The addresses range from 000h to 0BFh. Table 91. Register Section Overview REGISTER ADDRESS SECTION Common AFE TG DEC HEX Update 0 000h Standby 1 001h Data out 2 002h S-delay 3 003h 004h OB clamp 4 Hot-pixel rejection 5 005h DPGA 6, 7 006h, 007h CDS gain 8 008h IDAC power 9 009h DAC1 input 10, 11 00Ah, 00Bh DAC2 input 12, 13 00Ch, 00Dh High-speed timing 16-24 010h-018h ADCCK rise 25, 26 019h, 01Ah HG1/HG2 27 01Bh HG drive 28 01Ch SHP/SHD pix skip 29, 30 01Dh, 01Eh TG enable and sync 32 020h TRG 33 021h Frame field 34 022h Pin enable 35-40 023h-028h Pin initialize 41-46 029h-02Eh ODD range 47 02Fh VEVENT pin 48-51 030h-033h Pixel counter 52 034h Field 53 035h Frame 54 036h 037h-03Eh UPDATE METHOD Real time Real Time, VD, or RLOAD (selected by 000h[2:0]) Real time VA initialization instruction Real time VD or FLOAD (selected by 022h[1:0]) VEVENT 55-62 Mech shut 64-75 040h-04Bh Strobe 76-123 04Ch-07Bh SUBSW1 124-131 07Ch-083h SUBSW2 132-139 084h-08Bh SUBN 140-151 08Ch-097h SUBN CHG 152-163 098h-0A3h Monitor pin select 181 0B5h TRIG is input when h021h[2] is enabled Real Time or R_Update (selected by 000h[3]) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 73 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Detailed Common Section ADDRESS SECTION Update DEC HEX 0 PARAMETER DESCRIPTION PARAMETER # OF BITS — — — — 0 = Real time 1 = External trigger (RLOAD pin or VD) [2:1] AFE UP POL 2 AFE register update signal and polarity 00b = 01b = 10b = 11b = 0 = Real time 1 = VA internal instruction (R_UPDATE) (default) Reserved Default = 00b — DESCRIPTION UPDATE METHOD BITS [3] TG update 1 TG register update timing [5:4] — 2 — VALUE RLOAD input rising edge (default) RLOAD input falling edge VD rising edge VD falling edge Real time Detailed AFE Section ADDRESS SECTION Standby 1 Data out 2 S-DELAY 3 OB clamp Hot-pixel rejection 74 DEC HEX 4 5 1 PARAMETER DESCRIPTION DESCRIPTION UPDATE METHOD BITS PARAMETER # OF BITS [0] AFE standby 1 AFE standby [1] 8-bit DAC1 standby 1 Independent 8-bit DAC1 standby [2] 8-bit DAC2 standby 1 Independent 8-bit DAC2 standby [3] Monitor pin 1 Monitor pin enable 0 = Disabled (default) 1 = Enabled [5:4] — 2 — Reserved Default = 00b [1:0] Data out delay 2 Data out delay 00b = 01b = 10b = 11b = [2] OE 1 Data output enable 0 = Enabled (default) 1 = Disabled (high impedance) [5:3] — 3 — Reserved Default = 000b [1:0] ← 2 Sampling delay for SHP/SHD internal delay circuit 00b = 01b = 10b = 11b = [5:2] — 4 — Reserved Default = 0000b 2 3 VALUE 0 = AFE functions normally (default) 1 = AFE standby Real time, VD, or RLOAD (selected by 000h[2:0]) 0 = Enabled 1 = Standby (default) 0 ns (default) 2 ns 4 ns 6 ns Real time, VD, or RLOAD (selected by 000h[2:0]) 0 ns (default) 2 ns 4 ns 6 ns Real time, VD, or RLOAD (selected by 000h[2:0]) DATA (DEC) 12-BIT 10-BIT 00000b 00001b — 00110b 00111b 01000b 01001b — 01110b 01111b — 11110b 11111b Step (0) (1) — (6) (7) (8) (9) — (14) (15) — (30) (31) — 64 72 — 112 120 128 136 — 176 184 — 304 312 8 16 18 — 28 30 32 (default) 34 — 44 46 — 76 78 2 [4:0] ← 5 OB clamp level [5] — 1 — Reserved Default = 0 [4:0] HOT PIX LEVEL 5 Hot-pixel rejection level RL (LSB) = 16 × (code[4:0] + 1) (RL is the difference from OB level of 10-bit equivalent) [5] HOT PIX EN 1 Hot-pixel rejection enable/disable 0 = Disabled (default) 1 = Enabled 4 5 Submit Documentation Feedback Real time, VD, or RLOAD (selected by 000h[2:0]) Real time, VD, or RLOAD (selected by 000h[2:0]) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Detailed AFE Section (continued) ADDRESS SECTION DEC HEX 6 6 PARAMETER BITS PARAMETER [5:0] LSB [3:0] 7 DESCRIPTION 10 MSB Digital programmable gain 7 UPDATE METHOD VALUE DATA ← DPGA DESCRIPTION # OF BITS 00 0000 0000b — 00 1100 0000b — 11 1111 1111b (DEC) GAIN (0) — (192) — (1023) –6 dB — 0 dB (default) — 26 dB Gain (dB) = data × 0.03125(dB/step) – 60.03125 dB/step [5:4] CDS gain IDAC power 8 9 10 — 3 [5:3] — 3 — Reserved Default = 000b [1:0] ← 2 IDAC output current 00b = ( ױdefault) 01b = ײ 10b = ״ 11b = [5:2] — 4 — Reserved Default = 0000b 8 9 A [5:0] LSB B C DAC2 input [5:0] [1:0] — 4 LSB 15 8 — Independent DAC2 input code E F [5:0] [5:0] Real time, VD, or RLOAD (selected by 000h[2:0]) DATA OUT (V) 0000 0000b — 1111 1111b 0.1 — 2.9 Reserved Default = 0000b DATA OUT (V) 0000 0000b — 1111 1111b 0.1 — 2.9 Out (V) = 0.01094 × data + 0.1 Default = 0 (DEC) MSB D [5:2] — Independent DAC1 input code Real time, VD, or RLOAD (selected by 000h[2:0]) Out (V) = 0.01094 × data + 0.1 Default = 0 (DEC) ← 14 8 MSB [5:2] — 000b = 0 dB (default) 001b = 6 dB 010b = 12 dB 011b = 18 dB 111b = –3 dB ← [1:0] 13 Reserved Default = 00b [2:0] DAC1 input 12 — Analog programmable gain ← 11 2 — — — 4 6 6 — — — Reserved Default = 0000b Real time, VD, or RLOAD (selected by 000h[2:0]) Real time, VD, or RLOAD (selected by 000h[2:0]) Real time, VD, or RLOAD (selected by 000h[2:0]) Reserved Default = 0 (DEC) Real time, VD, or RLOAD (selected by 000h[2:0]) Reserved Default = 0 (DEC) Real time, VD, or RLOAD (selected by 000h[2:0]) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 75 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Detailed TG Section ADDRESS SECTION DEC HEX 16 10 17 18 19 11 12 13 High-speed timing 20 21 14 15 22 16 23 17 24 18 25 19 PARAMETER DESCRIPTION BITS PARAMETER # OF BITS DESCRIPTION [4:0] HG1 rising 5 HG1A, HG1B, HL rising edge [5] — 1 Reserved [4:0] HG1 falling 5 HG1A, HG1B, HL falling edge [5] — 1 Reserved [4:0] HG2 falling 5 HG2A, HG2B, falling edge [5] — 1 Reserved [4:0] HG2 rising 5 HG2A, HG2B, rising edge [5] — 1 Reserved [4:0] RG falling 5 RG falling edge [5] — 1 Reserved [4:0] SHP falling 5 SHP falling edge [5] — 1 Reserved [4:0] SHP rising 5 SHP rising edge [5] — 1 Reserved [4:0] SHD falling 5 SHD falling edge [5] — 1 Reserved [5:0] SHD rising 5 SHD rising edge [0] — 1 Reserved UPDATE METHOD VALUE DATA (DEC) STEP 10000b 10001b — 11111b 00000b 00001b — 01110b 01111b (16) (17) — (31) (0) (default) (1) — (14) (15) –16 –15 — –1 0 (default) 1 — 14 15 Real time Step is twos complement of data. 1 step = (1 pixel clock term)/100. Data[6:0] = 01Ah[0] × 26 + 019h[5:0] [5:0] LSB 01Ah[0] ← ADCCK delay [0] 26 7 ADCCK delay MSB 1A 1 — 1 1 1 — 1 0 0 — 0 0 0 — 0 019h[5:0] (DEC) STEP 00 0000b — 00 1101b 00 1110b 00 1111b — 11 1111b 00 0000b 00 0001b — 11 0000b 11 0001b 11 0010b — 11 1111b (64) — (77) (78) (79) — (127) (0) (default) (1) — (48) (49) (50) — (63) Reserved — Reserved –50 –49 — –1 0 (default) 1 — 48 49 Reserved — Reserved Real time Step is twos complement of data. 1 step = (1 pixel clock term)/100. HG1/HG2 76 27 1B [5:1] — 5 Reserved Reserved Default = 0 (DEC) [2:0] DIV 3 High-speed pulse divide rate 000b = Divide by 16 (default) 001b = Divide by 2 — 111b = Divide by 14 [3] Enable 1 HG1A, HG2A, HG1B, HG2B, HL enable/standby 0 = Enabled (default) 1 = Standby 0 = High (default) 1 = Low Reserved Default = 0 [4] HG1 POL 1 HG1A, HG1B, HL polarity during a TG standby condition [5] — 1 Reserved Submit Documentation Feedback Real time Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Detailed TG Section (continued) ADDRESS SECTION HG drive DEC 28 29 HEX — TG enable and sync TRG 31 32 33 DESCRIPTION BITS PARAMETER # OF BITS [1:0] H current 2 H1, H2 output drive current 00b 01b 10b 11b [2] HGB enable 1 HG1B, HG2B enable/disable 0 = Disabled (Z) (default) 1 = Enabled [5:3] — 3 Reserved Reserved Default = 011b 1C DESCRIPTION [2:0] Ratio 3 RG, SHP, SHD pixel skipping ratio [5:3] Start 3 RG, SHP, SHD pixel skipping start point. Count from HD edge [0] CLPDM 1 RG, SHP, SHD pixel skipping when CLPDM is active 1D SHP/SHD PIX SKIP 30 PARAMETER 1E 1F UPDATE METHOD VALUE = = = = Minimum Default (default) Mid-range Maximum Real time DATA RATIO 000b (default) 001b 010b 011b 100b 101b 110b 111b No skip 2 pixels 3 pixels 4 pixels 5 pixels 6 pixels 7 pixels 8 pixels Pixel number Default = 000b 0 = Continue 1 = Stop (default) [1] CLPOB 1 RG, SHP, SHD pixel skipping when CLPOB is active [5:2] — 4 Reserved Reserved Default = 0000b [5:0] — 6 Reserved Reserved Default = 0 (DEC) [0] TG enable 1 TG function enable/disable 0 = TG function disabled (standby) (default) 1 = TG function enabled [1] Master/slave 1 Master/slave mode 0 = Slave mode (HD, VD input) (default) 1 = Master mode (HD, VD output) [2] VH, HD, MCK edge 1 VD, HD signal latch by MCK 0 = MCK rising edge (default) 1 = MCK falling edge [3] VD, HD, TRG edge 1 VD, HD signal trigger 0 = Falling edge (default) 1 = Rising edge [4] MCK detect 1 Detect MCK stop and set output default 0 = Disabled 1 = Enabled (default) [5] — 1 Reserved Reserved Default = 0 [0] POL 1 Trigger polarity for TG CLK STOP (021h[1]) 0 = Active high (default) 1 = Active low [1] CLK stop 1 Trigger state (021h[0]) stops MCK for TG circuit (020h[4] does not work) [2] Frame INC 1 Trigger falling edge sets the frame (defined by 036h[5:3]) when this bit is enabled 20 21 [3] Counter RST 1 Trigger falling edge resets the line and pixel counter [4] Frame RST 1 Trigger falling edge resets the frame counter when 021h[3] = 1 [5] — 1 Reserved Real time 0 = Disabled (default) 1 = Enabled Real time Real time Real time Reserved Default = 0 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 77 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Detailed TG Section (continued) ADDRESS SECTION Frame field DEC 34 35 36 HEX 23 24 38 39 40 78 25 26 27 28 DESCRIPTION BITS PARAMETER # OF BITS [0] VD 1 Restart frame by VD 0 = Disabled 1 = Enabled (default) [1] FLOAD 1 Restart frame by FLOAD of VA 0 = Disabled (default) 1 = Enabled [2] Frame, CNT, RST 1 Reset and start frame counter 0 = Disabled (default) 1 = Enabled [3] Field SET 1 Field setting selection 0 = VD/HD phase (default) 1 = Register setting [4] Field POL 1 Field polarity 0 = Low when ODD (default) 1 = High when EVEN [5] VD Even 1 VD edge trigger in EVEN field 0 = Disabled (default) 1 = Enabled [0] V0N 1 [1] V1N 1 [2] V2N 1 [3] V3N 1 Pin enable selection 0 = Disabled (default) 1 = Enabled [4] V4N 1 [5] V5N 1 [0] V6N 1 [1] V7N 1 [2] V8N 1 [3] V9N 1 Pin enable selection 0 = Disabled (default) 1 = Enabled [4] V10N 1 [5] V11N 1 [0] V12N 1 [1] — 1 [2] — 1 [3] P0 1 [4] P1 1 [5] P2 1 [0] P3 1 [1] P4 1 [2] P5 1 [3] — 1 [4] — 1 [5] CLPDM 1 [0] CLPOB 1 [1] PBLK 1 [2] HBLK 1 [3] HDIV 1 [4] VD 1 [5] HD 1 [0] Field 1 [1] SUBN 1 [2] Strobe 1 [3] MSHUT 1 [4] SUBSW1 1 [5] SUBSW2 1 22 Pin enable 37 PARAMETER DESCRIPTION VALUE UPDATE METHOD Real time Real time Pin enable selection 0 = Disabled (default) 1 = Enabled Pin enable selection 0 = Disabled (default) 1 = Enabled Pin enable selection 0 = Disabled (default) 1 = Enabled Real time Pin enable selection 0 = Disabled (default) 1 = Enabled Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Detailed TG Section (continued) ADDRESS SECTION DEC 41 42 43 HEX 29 2A 2B Pin initialization 44 45 46 ODD range 47 2C 2D 2E PARAMETER DESCRIPTION BITS PARAMETER # OF BITS [0] V0N 1 [1] V1N 1 [2] V2N 1 [3] V3N 1 [4] V4N 1 [5] V5N 1 [0] V6N 1 [1] V7N 1 [2] V8N 1 [3] V9N 1 [4] V10N 1 [5] V11N 1 [0] V12N 1 [1] — 1 [2] — 1 [3] P0 1 [4] P1 1 [5] P2 1 [0] P3 1 [1] P4 1 [2] P5 1 [3] — 1 [4] — 1 [5] CLPDM 1 [0] CLPOB 1 [1] PBLK 1 [2] HBLK 1 [3] HDIV 1 [4] VD 1 [5] HD 1 [0] Field 1 [1] SUBN 1 [2] Strobe 1 [3] MSHUT 1 [4] SUBSW1 1 [5] SUBSW2 1 [2:0] ODD HD-VD [5:3] ODD VD-HD DESCRIPTION Pin initialization polarity 0 = Low 1 = High (default) VA initializatio n instruction Pin initialization polarity 0 = Low (default) 1 = High Pin initialization polarity 0 = Low 1 = High (default) Pin initialization polarity 0 = Low (default) 1 = High 3 HD-VD delay for ODD detection 0-7 pixel delay Default = 001b 3 VD-HD delay for ODD detection 0-8 pixel delay Default = 001b 2F UPDATE METHOD VALUE Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 Real time 79 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Detailed TG Section (continued) ADDRESS SECTION DEC 48 HEX 30 VEVENT pin 49 50 31 32 VEVENT pin 51 Pixel counter Field 52 53 PARAMETER DESCRIPTION BITS PARAMETER # OF BITS [0] V0N 1 [1] V1N 1 [2] V2N 1 [3] V3N 1 [4] V4N 1 [5] V5N 1 [0] V6N 1 [1] V7N 1 [2] V8N 1 [3] V9N 1 [4] V10N 1 [5] V11N 1 [0] V12N 1 [1] — 1 [2] — 1 [5:3] — DESCRIPTION UPDATE METHOD VALUE Pin used for vertical event control 0 = Disabled (default) 1 = Enabled Pin used for vertical event control 0 = Disabled (default) 1 = Enabled 3 Reserved Reserved Default = 000b Terminal number. Refer to the Signal section for details. Default = 0 (DEC) [4:0] TRG pin 5 Vertical event trigger pin [5] TRG edge 1 Vertical event trigger 0 = Rising edge (default) 1 = Falling edge [3:0] Pixel count 4 Pin counter start offset Pixel number. Slave mode = 0110 (default) Master mode = 0 [5:4] — 2 Reserved Reserved Default = 00b [0] ODD/EVEN 1 Field index 0 = ODD (default) 1 = EVEN [5:1] — 5 Reserved Reserved Default = 0 (DEC) 3 Set current frame number 33 34 35 Real time Real time Real time Real time Frame number. Default = 000b [2:0] Frame 54 36 [5:3] VEVENT1 VEVENT2 — 80 Frame now 55 37 [5:0] LSB 56 38 [5:0] MSB 57 39 [5:0] LSB 58 3A [5:0] MSB 59 3B [5:0] LSB 60 3C [5:0] MSB 61 3D [5:0] LSB 62 3E [5:0] MSB 63 3F [5:0] 3 Set frame number when trigger input Start 12 Vertical event start 1 Stop 12 Vertical event stop 1 Frame TRG — Start 12 Vertical event start 2 Stop 12 Vertical event stop 2 6 Reserved VA FRAME NUMBER VA1 (180h) VA2 (190h) VA3 (1A0h) VA4 (1B0h) VA5 (1C0h) VA6 (1D0h) VA7 (1E0h) VA8 (1F0h) 0 1 2 3 4 5 6 7 VD or FLOAD (selected by 022h[1:0]) TRIG input when 021[2] is enabled Event number Default = 0 (DEC) Real time or R_Update (selected by 000h[3]) Reserved Default = 0 (DEC) Real time or R_Update (selected by 000h[3]) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Detailed TG Section (continued) ADDRESS SECTION MECH SHUT1 DEC HEX BITS PARAMETER 64 40 [5:0] LSB 65 41 [5:0] MID 66 42 67 43 68 44 69 MECH SHUT2 MSB LSB [5:0] MID [0] MSB [5:1] LSB [0] MSB 13 Mechanical shutter 1 toggling pix Pixel number Default = 0 (DEC) Line 12 Mechanical shutter 1 toggling line Line number Default = 0 (DEC) Frame 6 Mechanical shutter 1 toggling frame Frame number Default = 0 (DEC) 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b PIX 13 Mechanical shutter 2 toggling pix Pixel number Default = 0 (DEC) Line 12 Mechanical shutter 2 toggling line Line number Default = 0 (DEC) Frame 6 Mechanical shutter 2 toggling frame Frame number Default = 0 (DEC) LSB [5:0] MID 72 48 73 49 74 4A [0] MSB [5:1] LSB [5:0] MID [0] MSB [5:1] LSB [0] MSB [1] POL 1 Mechanical shutter 2 toggling polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b PIX 13 Strobe 1 toggling pix Pixel number Default = 0 (DEC) Line 12 Strobe 1 toggling line Line number Default = 0 (DEC) Frame 6 Strobe 1 toggling frame Frame number Default = 0 (DEC) 76 4C [5:0] LSB 77 4D [5:0] MID 78 4E 79 4F 80 50 [0] MSB [5:1] LSB [5:0] MID [0] MSB [5:1] LSB [0] MSB [1] POL 1 Strobe 1 toggling polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b PIX 13 Strobe 2 toggling pix Pixel number Default = 0 (DEC) Line 12 Strobe 2 toggling line Line number Default = 0 (DEC) Frame 6 Strobe 2 toggling frame Frame number Default = 0 (DEC) 82 52 [5:0] LSB 83 53 [5:0] MID 84 54 85 55 86 56 57 PIX Mechanical shutter 1 toggling polarity [5:0] 87 VALUE 1 47 51 DESCRIPTION POL 46 4B DESCRIPTION # OF BITS [1] 71 81 Strobe 2 45 [0] [5:1] 70 75 Strobe 1 PARAMETER [0] MSB [5:1] LSB [5:0] MID [0] MSB [5:1] LSB [0] MSB [1] POL 1 Strobe 2 toggling polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 UPDATE METHOD Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) 81 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Detailed TG Section (continued) ADDRESS SECTION DEC HEX BITS PARAMETER 88 58 [5:0] LSB 89 59 [5:0] MID 90 5A [0] MSB [5:1] LSB 91 Strobe 3 92 93 Strobe 4 5D MID [0] MSB [5:1] LSB [0] MSB Strobe 3 toggling pix Pixel number Default = 0 (DEC) Line 12 Strobe 3 toggling line Line number Default = 0 (DEC) Frame 6 Strobe 3 toggling frame Frame number Default = 0 (DEC) Strobe 3 toggling polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b PIX 13 Strobe 4 toggling pix Pixel number Default = 0 (DEC) Line 12 Strobe 4 toggling line Line number Default = 0 (DEC) Frame 6 Strobe 4 toggling frame Frame number Default = 0 (DEC) LSB [5:0] MID 96 60 97 61 98 62 [0] MSB [5:1] LSB [5:0] MID [0] MSB [5:1] LSB [0] MSB [1] POL 1 Strobe 4 toggling polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b PIX 13 Strobe 5 toggling pix Pixel number Default = 0 (DEC) Line 12 Strobe 5 toggling line Line number Default = 0 (DEC) Frame 6 Strobe 5 toggling frame Frame number Default = 0 (DEC) 100 64 [5:0] LSB 101 65 [5:0] MID 102 66 103 67 104 68 [0] MSB [5:1] LSB [5:0] MID [0] MSB [5:1] LSB [0] MSB [1] POL 1 Strobe 5 toggling polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b PIX 13 Strobe 6 toggling pix Pixel number Default = 0 (DEC) Line 12 Strobe 6 toggling line Line number Default = 0 (DEC) Frame 6 Strobe 6 toggling frame Frame number Default = 0 (DEC) 106 6A [5:0] LSB 107 6B [5:0] MID 108 6C 109 6D 110 6E 6F VALUE 1 [5:0] 69 13 DESCRIPTION POL 5F 63 PIX DESCRIPTION # OF BITS [1] 5E 111 82 5C [5:0] 95 105 Strobe 6 5B 94 99 Strobe 5 PARAMETER [0] MSB [5:1] LSB [5:0] MID [0] MSB [5:1] LSB [0] MSB [1] POL 1 Strobe 6 toggling polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b Submit Documentation Feedback UPDATE METHOD Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Detailed TG Section (continued) ADDRESS SECTION Strobe 7 DEC HEX BITS PARAMETER 112 70 [5:0] LSB 113 71 [5:0] MID 114 72 115 73 116 74 117 Strobe 8 PARAMETER 75 [0] MSB [5:1] LSB [5:0] MID [0] MSB [5:1] LSB [0] MSB VALUE PIX 13 Strobe 7 toggling pix Pixel number Default = 0 (DEC) Line 12 Strobe 7 toggling line Line number Default = 0 (DEC) Frame 6 Strobe 7 toggling frame Frame number Default = 0 (DEC) POL 1 Strobe 7 toggling polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b PIX 13 Strobe 8 toggling pix Pixel number Default = 0 (DEC) Line 12 Strobe 8 toggling line Line number Default = 0 (DEC) Frame 6 Strobe 8 toggling frame Frame number Default = 0 (DEC) 76 [5:0] LSB 119 77 [5:0] MID 120 78 121 79 122 7A 7B DESCRIPTION [1] 118 123 DESCRIPTION # OF BITS [0] MSB [5:1] LSB [5:0] MID [0] MSB [5:1] LSB [0] MSB [1] POL 1 Strobe 8 toggling polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b 12 SUBSW1-1 toggling line Line number Default = 0 (DEC) 124 7C [5:0] LSB 125 7D [5:0] MSB 126 7E [5:0] Frame 6 SUBSW1-1 toggling frame Frame number Default = 0 (DEC) [0] POL 1 SUBSW1-1 polarity 0 = Low (default) 1 = High [5:1] — 5 Reserved Reserved Default = 0 (DEC) 12 SUBSW1-2 toggling line Line number Default = 0 (DEC) Line SUBSW1-1 127 7F 128 80 [5:0] LSB 129 81 [5:0] MSB 130 82 [5:0] Frame 6 SUBSW1-2 toggling frame Frame number Default = 0 (DEC) [0] POL 1 SUBSW1-2 polarity 131 83 0 = Low (default) 1 = High [5:1] — 5 Reserved Reserved Default = 0 (DEC) 12 SUBSW2-1 toggling line Line number Default = 0 (DEC) Line SUBSW1-2 132 84 [5:0] LSB 133 85 [5:0] MSB 134 86 [5:0] Frame 6 SUBSW2-1 toggling frame Frame number Default = 0 (DEC) [0] POL 1 SUBSW2-1 polarity 135 87 0 = Low (default) 1 = High [5:1] — 5 Reserved Reserved Default = 0 (DEC) Line SUBSW2-1 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 UPDATE METHOD Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) 83 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Detailed TG Section (continued) ADDRESS SECTION PARAMETER DEC HEX BITS PARAMETER 136 88 [5:0] LSB 137 89 [5:0] MSB 138 8A [5:0] DESCRIPTION # OF BITS SUBSW2-2 toggling line Line number Default = 0 (DEC) Frame 6 SUBSW2-2 toggling frame Frame number Default = 0 (DEC) [0] POL 1 SUBSW2-2 polarity 0 = Low (default) 1 = High [5:1] — 5 Reserved Reserved Default = 0 (DEC) 13 SUBN 1 toggling pixel Pixel number Default = 0 (DEC) 8B 140 8C [5:0] LSB 141 8D [5:0] MID [0] MSB PIX SUBN 1 142 8E [1] POL 1 SUBN 1 polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b 13 SUBN 2 toggling pixel Pixel number Default = 0 (DEC) 143 8F [5:0] LSB 144 90 [5:0] MID [0] MSB PIX SUBN 2 145 91 [1] POL 1 SUBN 2 polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b 13 SUBN 3 toggling pixel Pixel number Default = 0 (DEC) 146 92 [5:0] LSB 147 93 [5:0] MID [0] MSB PIX SUBN 3 148 94 [1] POL 1 SUBN 3 polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b 13 SUBN 4 toggling pixel Pixel number Default = 0 (DEC) 149 95 [5:0] LSB 150 96 [5:0] MID [0] MSB PIX SUBN 4 151 97 POL 1 SUBN 4 polarity 0 = Low (default) 1 = High [5:2] — 4 Reserved Reserved Default = 0000b 12 Electric shutter 1 toggling line Line number Default = 0 (DEC) 98 [5:0] LSB 153 99 [5:0] MSB 154 9A Pattern 2 Electric shutter 1 SUBN Pattern number pattern Default = 00b [5:2] — 4 Reserved Reserved Default = 0000b 12 Electric shutter 2 toggling line Line number Default = 0 (DEC) 9B [5:0] LSB 156 9C [5:0] MSB 157 9D Pattern 2 Electric shutter 2 SUBN Pattern number pattern Default = 00b [5:2] — 4 Reserved Reserved Default = 0000b 12 Electric shutter 3 toggling line Line number Default = 0 (DEC) 9E [5:0] LSB 159 9F [5:0] MSB 160 Line [1:0] 158 SUBN CHG 3 Line [1:0] 155 SUBN CHG 2 84 [1] 152 SUBN CHG 1 VALUE 12 Line SUBSW2-2 139 DESCRIPTION Line [1:0] Pattern 2 Electric shutter 3 SUBN Pattern number pattern Default = 00b [5:2] — 4 Reserved A0 Reserved Default = 0000b Submit Documentation Feedback UPDATE METHOD Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 VSP01M01 VSP01M02 www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009 Detailed TG Section (continued) ADDRESS SECTION PARAMETER DEC HEX BITS 161 A1 [5:0] LSB 162 A2 [5:0] MSB SUBN CHG 4 163 PARAMETER Line DESCRIPTION # OF BITS DESCRIPTION 12 Electric shutter 4 toggling line VALUE Line number Default = 0 (DEC) [1:0] Pattern 2 Electric shutter 4 SUBN Pattern number pattern Default = 00b [5:2] — 4 Reserved Reserved Default = 0000b A3 — 164 A4 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 165 A5 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 166 A6 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 167 A7 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 168 A8 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 169 A9 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 170 AA [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 171 AB [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 172 AC [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 173 AD [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 174 AE [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 175 AF [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 176 B0 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 177 B1 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 178 B2 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 179 B3 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 180 B4 [5:0] — 6 Reserved Reserved Default = 0 (DEC) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 UPDATE METHOD Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) 85 VSP01M01 VSP01M02 SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Detailed TG Section (continued) ADDRESS SECTION Monitor pin select 86 DEC 181 HEX PARAMETER BITS PARAMETER DESCRIPTION # OF BITS DESCRIPTION VALUE [3:0] ← 4 Monitor pin selection 1000b = TPP = SHP, TPD = SHD 1001b = TPP = CLPOB, TPD = CLPDM 1010b = TPP = PBLK, TPD = HDIV 1011b = TPP =HBLK, TPD = (na) Default = 0000b [5:4] — 2 Reserved Reserved Default = 00b B5 — 182 B6 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 183 B7 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 184 B8 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 185 B9 [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 186 BA [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 187 BB [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 188 BC [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 189 BD [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 190 BE [5:0] — 6 Reserved Reserved Default = 0 (DEC) — 191 BF [5:0] — 6 Reserved Reserved Default = 0 (DEC) Submit Documentation Feedback UPDATE METHOD Real time or R_Update (selected by 000h[3]) Real time or R_Update (selected by 000h[3]) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): VSP01M01 VSP01M02 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins VSP01M01ZWD ACTIVE NFBGA ZWD 100 VSP01M01ZWDR ACTIVE NFBGA ZWD 100 Package Qty 1000 Eco Plan (2) Lead/ Ball Finish TBD Call TI Pb-Free (RoHS) SNAGCU MSL Peak Temp (3) Samples (Requires Login) Call TI Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device VSP01M01ZWDR Package Package Pins Type Drawing NFBGA ZWD 100 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 7.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.3 2.2 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VSP01M01ZWDR NFBGA ZWD 100 1000 342.0 336.0 34.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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