TI SN65HVD230

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
Digital Signal Processors
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS174T
April 2001 – Revised May 2012
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
Contents
1
TMS320F281x, TMS320C281x DSPs
1.1
1.2
2
Introduction
2.1
2.2
2.3
2.4
3
...................................................................................................................... 12
Description .................................................................................................................
Device Summary ..........................................................................................................
Pin Assignments ...........................................................................................................
2.3.1
Terminal Assignments for the GHH/ZHH Packages .......................................................
2.3.2
Pin Assignments for the PGF Package ......................................................................
2.3.3
Pin Assignments for the PBK Package ......................................................................
Signal Descriptions ........................................................................................................
Functional Overview
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
..................................................................................... 10
Features .................................................................................................................... 10
Getting Started ............................................................................................................. 11
.......................................................................................................... 26
Memory Map ...............................................................................................................
Brief Descriptions ..........................................................................................................
3.2.1
C28x CPU .......................................................................................................
3.2.2
Memory Bus (Harvard Bus Architecture) ....................................................................
3.2.3
Peripheral Bus ..................................................................................................
3.2.4
Real-Time JTAG and Analysis ................................................................................
3.2.5
External Interface (XINTF) (2812 Only) ......................................................................
3.2.6
Flash (F281x Only) .............................................................................................
3.2.7
ROM (C281x Only) .............................................................................................
3.2.8
M0, M1 SARAMs ...............................................................................................
3.2.9
L0, L1, H0 SARAMs ............................................................................................
3.2.10 Boot ROM .......................................................................................................
3.2.11 Security ..........................................................................................................
3.2.12 Peripheral Interrupt Expansion (PIE) Block .................................................................
3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI) ........................................................
3.2.14 Oscillator and PLL ..............................................................................................
3.2.15 Watchdog ........................................................................................................
3.2.16 Peripheral Clocking .............................................................................................
3.2.17 Low-Power Modes ..............................................................................................
3.2.18 Peripheral Frames 0, 1, 2 (PFn) ..............................................................................
3.2.19 General-Purpose Input/Output (GPIO) Multiplexer .........................................................
3.2.20 32-Bit CPU-Timers (0, 1, 2) ...................................................................................
3.2.21 Control Peripherals .............................................................................................
3.2.22 Serial Port Peripherals .........................................................................................
Register Map ...............................................................................................................
Device Emulation Registers ..............................................................................................
External Interface, XINTF (2812 Only) .................................................................................
3.5.1
Timing Registers ................................................................................................
3.5.2
XREVISION Register ...........................................................................................
Interrupts ....................................................................................................................
3.6.1
External Interrupts ..............................................................................................
System Control ............................................................................................................
OSC and PLL Block .......................................................................................................
3.8.1
Loss of Input Clock .............................................................................................
PLL-Based Clock Module ................................................................................................
External Reference Oscillator Clock Option ...........................................................................
Watchdog Block ...........................................................................................................
Low-Power Modes Block .................................................................................................
4
Peripherals
2
Contents
12
13
14
14
15
16
17
27
32
32
32
32
33
33
33
33
34
34
34
34
36
36
36
36
36
36
37
37
37
37
38
39
41
42
43
43
44
47
48
50
51
52
52
53
54
....................................................................................................................... 55
Copyright © 2001–2012, Texas Instruments Incorporated
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5
32-Bit CPU-Timers 0/1/2 .................................................................................................
Event Manager Modules (EVA, EVB) ...................................................................................
4.2.1
General-Purpose (GP) Timers ................................................................................
4.2.2
Full-Compare Units .............................................................................................
4.2.3
Programmable Deadband Generator ........................................................................
4.2.4
PWM Waveform Generation ..................................................................................
4.2.5
Double Update PWM Mode ...................................................................................
4.2.6
PWM Characteristics ...........................................................................................
4.2.7
Capture Unit .....................................................................................................
4.2.8
Quadrature-Encoder Pulse (QEP) Circuit ...................................................................
4.2.9
External ADC Start-of-Conversion ...........................................................................
Enhanced Analog-to-Digital Converter (ADC) Module ...............................................................
Enhanced Controller Area Network (eCAN) Module ..................................................................
Multichannel Buffered Serial Port (McBSP) Module ..................................................................
Serial Communications Interface (SCI) Module .......................................................................
Serial Peripheral Interface (SPI) Module ...............................................................................
GPIO MUX .................................................................................................................
Development Support
5.1
5.2
5.3
6
SPRS174T – APRIL 2001 – REVISED MAY 2012
........................................................................................................ 86
Device and Development Support Tool Nomenclature ............................................................... 86
Documentation Support .................................................................................................. 87
Community Resources .................................................................................................... 89
Electrical Specifications
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
6.26
6.27
55
58
61
61
61
61
61
62
62
62
62
63
68
73
77
80
83
..................................................................................................... 91
Absolute Maximum Ratings .............................................................................................. 91
Recommended Operating Conditions .................................................................................. 91
Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) ............. 92
Current Consumption ..................................................................................................... 93
Current Consumption Graphs ............................................................................................ 95
Reducing Current Consumption ......................................................................................... 97
Emulator Connection Without Signal Buffering for the DSP ......................................................... 97
Power Sequencing Requirements ....................................................................................... 98
Signal Transition Levels ................................................................................................. 100
Timing Parameter Symbology .......................................................................................... 101
General Notes on Timing Parameters ................................................................................ 101
Test Load Circuit ......................................................................................................... 101
Device Clock Table ...................................................................................................... 102
Clock Requirements and Characteristics ............................................................................. 103
6.14.1 Input Clock Requirements ................................................................................... 103
6.14.2 Output Clock Characteristics ................................................................................ 104
Reset Timing ............................................................................................................. 104
Low-Power Mode Wakeup Timing ..................................................................................... 108
Event Manager Interface ................................................................................................ 112
6.17.1 PWM Timing ................................................................................................... 112
6.17.2 Interrupt Timing ................................................................................................ 114
General-Purpose Input/Output (GPIO) – Output Timing ............................................................ 115
General-Purpose Input/Output (GPIO) – Input Timing .............................................................. 116
Serial Peripheral Interface (SPI) Master Mode Timing .............................................................. 117
Serial Peripheral Interface (SPI) Slave Mode Timing ............................................................... 122
External Interface (XINTF) Timing ..................................................................................... 126
XINTF Signal Alignment to XCLKOUT ................................................................................ 130
External Interface Read Timing ........................................................................................ 131
External Interface Write Timing ........................................................................................ 133
External Interface Ready-on-Read Timing With One External Wait State ....................................... 134
External Interface Ready-on-Write Timing With One External Wait State ....................................... 137
Copyright © 2001–2012, Texas Instruments Incorporated
Contents
3
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
6.28
6.29
6.30
6.31
6.32
6.33
6.34
www.ti.com
XHOLD and XHOLDA ...................................................................................................
XHOLD/XHOLDA Timing ...............................................................................................
On-Chip Analog-to-Digital Converter ..................................................................................
6.30.1 ADC Absolute Maximum Ratings ...........................................................................
6.30.2 ADC Electrical Characteristics Over Recommended Operating Conditions ...........................
6.30.3 Current Consumption for Different ADC Configurations .................................................
6.30.4 ADC Power-Up Control Bit Timing ..........................................................................
6.30.5 Detailed Description ..........................................................................................
6.30.5.1 Reference Voltage ................................................................................
6.30.5.2 Analog Inputs .....................................................................................
6.30.5.3 Converter ..........................................................................................
6.30.5.4 Conversion Modes ...............................................................................
6.30.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................
6.30.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) ..........................................
6.30.8 Definitions of Specifications and Terminology .............................................................
Multichannel Buffered Serial Port (McBSP) Timing .................................................................
6.31.1 McBSP Transmit and Receive Timing ......................................................................
6.31.2 McBSP as SPI Master or Slave Timing ....................................................................
Flash Timing (F281x Only) .............................................................................................
ROM Timing (C281x only) ..............................................................................................
Migrating From F281x Devices to C281x Devices ..................................................................
7
8
Revision History
Mechanical Data
4
Contents
140
141
143
143
144
145
146
146
146
146
146
146
147
148
149
150
150
153
157
159
160
.............................................................................................................. 161
.............................................................................................................. 162
Copyright © 2001–2012, Texas Instruments Incorporated
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
List of Figures
2-1
TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)............................. 14
2-2
TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View)
2-3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
..................................................... 15
TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP (Top View) .............. 16
Functional Block Diagram ....................................................................................................... 27
F2812/C2812 Memory Map ..................................................................................................... 28
F2811/C2811 Memory Map ..................................................................................................... 29
F2810/C2810 Memory Map ..................................................................................................... 29
External Interface Block Diagram .............................................................................................. 42
Interrupt Sources ................................................................................................................. 44
Multiplexing of Interrupts Using the PIE Block ............................................................................... 45
Clock and Reset Domains ...................................................................................................... 48
OSC and PLL Block .............................................................................................................. 50
Recommended Crystal/Clock Connection .................................................................................... 52
Watchdog Module ................................................................................................................ 53
CPU-Timers ....................................................................................................................... 55
CPU-Timer Interrupts Signals and Output Signal ............................................................................ 56
Event Manager A Functional Block Diagram ................................................................................. 61
Block Diagram of the F281x and C281x ADC Module ...................................................................... 64
ADC Pin Connections With Internal Reference .............................................................................. 65
ADC Pin Connections With External Reference ............................................................................. 66
eCAN Block Diagram and Interface Circuit ................................................................................... 69
eCAN Memory Map .............................................................................................................. 71
McBSP Module With FIFO ...................................................................................................... 74
Serial Communications Interface (SCI) Module Block Diagram............................................................ 79
Serial Peripheral Interface Module Block Diagram (Slave Mode).......................................................... 82
GPIO/Peripheral Pin Multiplexing .............................................................................................. 85
TMS320x281x Device Nomenclature .......................................................................................... 87
F2812/F2811/F2810 Typical Current Consumption Over Frequency ..................................................... 95
F2812/F2811/F2810 Typical Power Consumption Over Frequency ....................................................... 96
C2812/C2811/C2810 Typical Current Consumption Over Frequency .................................................... 96
C2812/C2811/C2810 Typical Power Consumption Over Frequency ...................................................... 97
Emulator Connection Without Signal Buffering for the DSP ................................................................ 98
F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence – Option 2 ....................................... 99
Output Levels.................................................................................................................... 100
Input Levels ...................................................................................................................... 100
3.3-V Test Load Circuit......................................................................................................... 101
Clock Timing ..................................................................................................................... 104
Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note D) ................................................. 106
Power-on Reset in Microprocessor Mode (XMP/MC = 1) ................................................................. 107
Warm Reset in Microcomputer Mode ........................................................................................ 107
Effect of Writing Into PLLCR Register ....................................................................................... 107
IDLE Entry and Exit Timing .................................................................................................... 108
STANDBY Entry and Exit Timing ............................................................................................. 110
HALT Wakeup Using XNMI ................................................................................................... 111
PWM Output Timing ............................................................................................................ 112
TDIRx Timing .................................................................................................................... 113
EVASOC Timing ................................................................................................................ 113
Copyright © 2001–2012, Texas Instruments Incorporated
List of Figures
5
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
www.ti.com
6-21
EVBSOC Timing ................................................................................................................ 113
6-22
External Interrupt Timing ....................................................................................................... 114
6-23
General-Purpose Output Timing .............................................................................................. 115
6-24
GPIO Input Qualifier – Example Diagram for QUALPRD = 1 ............................................................. 116
6-25
General-Purpose Input Timing ................................................................................................ 117
6-26
SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 119
6-27
SPI Master External Timing (Clock Phase = 1) ............................................................................. 121
6-28
SPI Slave Mode External Timing (Clock Phase = 0) ....................................................................... 123
6-29
SPI Slave Mode External Timing (Clock Phase = 1) ....................................................................... 125
6-30
Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 129
6-31
Example Read Access ......................................................................................................... 132
6-32
Example Write Access ......................................................................................................... 133
6-33
Example Read With Synchronous XREADY Access
6-34
Example Read With Asynchronous XREADY Access ..................................................................... 136
6-35
Write With Synchronous XREADY Access .................................................................................. 138
6-36
Write With Asynchronous XREADY Access
6-37
External Interface Hold Waveform ............................................................................................ 141
6-38
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) .................................................. 142
6-39
ADC Analog Input Impedance Model ........................................................................................ 146
6-40
ADC Power-Up Control Bit Timing
6-41
Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 147
6-42
Simultaneous Sampling Mode Timing
6-43
6-44
6-45
6-46
6-47
6-48
6
......................................................................
................................................................................
...........................................................................................
.......................................................................................
McBSP Receive Timing ........................................................................................................
McBSP Transmit Timing .......................................................................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ...................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ...................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ...................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ...................................................
List of Figures
135
139
146
148
152
152
153
154
155
156
Copyright © 2001–2012, Texas Instruments Incorporated
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
List of Tables
2-1
Hardware Features ............................................................................................................... 13
2-2
Signal Descriptions ............................................................................................................... 17
3-1
Addresses of Flash Sectors in F2812 and F2811
3-2
Addresses of Flash Sectors in F2810 ......................................................................................... 30
3-3
Wait States ........................................................................................................................ 31
3-4
Boot Mode Selection ............................................................................................................. 34
3-5
Impact of Using the Code Security Module ................................................................................... 35
3-6
Peripheral Frame 0 Registers
39
3-7
Peripheral Frame 1 Registers
39
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
...........................................................................
..................................................................................................
..................................................................................................
Peripheral Frame 2 Registers ..................................................................................................
Device Emulation Registers.....................................................................................................
XINTF Configuration and Control Register Mappings .......................................................................
XREVISION Register Bit Definitions ...........................................................................................
PIE Peripheral Interrupts ........................................................................................................
PIE Configuration and Control Registers......................................................................................
External Interrupts Registers ...................................................................................................
PLL, Clocking, Watchdog, and Low-Power Mode Registers ...............................................................
PLLCR Register Bit Definitions .................................................................................................
Possible PLL Configuration Modes ............................................................................................
F281x and C281x Low-Power Modes .........................................................................................
CPU-Timers 0, 1, 2 Configuration and Control Registers ...................................................................
Module and Signal Names for EVA and EVB ................................................................................
EVA Registers ....................................................................................................................
ADC Registers ....................................................................................................................
3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs ............................................
CAN Registers ....................................................................................................................
McBSP Registers .................................................................................................................
SCI-A Registers ..................................................................................................................
SCI-B Registers ..................................................................................................................
SPI Registers .....................................................................................................................
GPIO Mux Registers .............................................................................................................
GPIO Data Registers ............................................................................................................
TMS320x281x Peripheral Selection Guide ...................................................................................
30
40
41
43
43
45
46
47
49
51
52
54
57
58
59
67
70
72
75
78
78
81
83
84
87
6-1
TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During
Low-Power Modes at 150-MHz SYSCLKOUT ............................................................................... 93
6-2
TMS320C281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During
Low-Power Modes at 150-MHz SYSCLKOUT ............................................................................... 94
6-3
Typical Current Consumption by Various Peripherals (at 150 MHz) ...................................................... 97
6-4
Recommended “Low-Dropout Regulators” .................................................................................... 98
6-5
TMS320F281x and TMS320C281x Clock Table and Nomenclature
6-6
Input Clock Frequency ......................................................................................................... 103
6-7
XCLKIN Timing Requirements – PLL Bypassed or Enabled
6-8
XCLKIN Timing Requirements – PLL Disabled
6-9
6-10
6-11
6-12
....................................................
.............................................................
............................................................................
Possible PLL Configuration Modes ...........................................................................................
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ......................................................
Reset (XRS) Timing Requirements ..........................................................................................
IDLE Mode Timing Requirements ...........................................................................................
Copyright © 2001–2012, Texas Instruments Incorporated
List of Tables
102
103
103
103
104
104
108
7
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
6-48
6-49
6-50
6-51
6-52
6-53
6-54
6-55
6-56
6-57
6-58
6-59
6-60
8
www.ti.com
.......................................................................................
.....................................................................................
STANDBY Mode Switching Characteristics ................................................................................
HALT Mode Timing Requirements ...........................................................................................
HALT Mode Switching Characteristics ......................................................................................
PWM Switching Characteristics ..............................................................................................
Timer and Capture Unit Timing Requirements .............................................................................
External ADC Start-of-Conversion – EVA – Switching Characteristics .................................................
External ADC Start-of-Conversion – EVB – Switching Characteristics .................................................
Interrupt Switching Characteristics ..........................................................................................
Interrupt Timing Requirements ...............................................................................................
General-Purpose Output Switching Characteristics .......................................................................
General-Purpose Input Timing Requirements ..............................................................................
SPI Master Mode External Timing (Clock Phase = 0) ....................................................................
SPI Master Mode External Timing (Clock Phase = 1) ....................................................................
SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................
SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................
Relationship Between Parameters Configured in XTIMING and Duration of Pulse ...................................
XINTF Clock Configurations ...................................................................................................
External Memory Interface Read Switching Characteristics .............................................................
External Memory Interface Read Timing Requirements ..................................................................
External Memory Interface Write Switching Characteristics ..............................................................
External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) .......................
External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ............................
Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) .......................................
Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ......................................
External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ........................
Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) .......................................
Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ......................................
XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ......................................................
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) .................................................
DC Specifications ..............................................................................................................
AC Specifications ...............................................................................................................
Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ........................................
ADC Power-Up Delays .........................................................................................................
Sequential Sampling Mode Timing ...........................................................................................
Simultaneous Sampling Mode Timing .......................................................................................
McBSP Timing Requirements ................................................................................................
McBSP Switching Characteristics ...........................................................................................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ...............................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ...........................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ...............................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ...........................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ...............................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ...........................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ...............................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ...........................
Flash Endurance for A and S Temperature Material .......................................................................
IDLE Mode Switching Characteristics
108
STANDBY Mode Timing Requirements
109
List of Tables
109
111
111
112
112
113
113
114
114
115
117
118
120
122
124
126
129
131
131
133
134
134
134
134
137
137
137
141
142
144
145
145
146
147
148
150
151
153
153
154
154
155
155
156
156
157
Copyright © 2001–2012, Texas Instruments Incorporated
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
6-61
Flash Endurance for Q Temperature Material .............................................................................. 157
6-62
Flash Parameters at 150-MHz SYSCLKOUT ............................................................................... 157
6-63
Flash/OTP Access Timing ..................................................................................................... 158
6-64
Minimum Required Flash Wait States at Different Frequencies (F281x devices) ...................................... 158
6-65
ROM Access Timing............................................................................................................ 159
6-66
Minimum Required ROM Wait States at Different Frequencies (C281x devices) ...................................... 159
8-1
Thermal Resistance Characteristics for 179-Ball GHH .................................................................... 162
8-2
Thermal Resistance Characteristics for 179-Ball ZHH..................................................................... 162
8-3
Thermal Resistance Characteristics for 176-Pin PGF ..................................................................... 162
8-4
Thermal Resistance Characteristics for 128-Pin PBK
Copyright © 2001–2012, Texas Instruments Incorporated
.....................................................................
List of Tables
162
9
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
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Digital Signal Processors
Check for Samples: TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812
1
TMS320F281x, TMS320C281x DSPs
1.1
Features
1234
• High-Performance Static CMOS Technology
– 150 MHz (6.67-ns Cycle Time)
– Low-Power (1.8-V Core at 135 MHz,
1.9-V Core at 150 MHz, 3.3-V I/O) Design
• JTAG Boundary Scan Support (1)
• High-Performance 32-Bit CPU ( TMS320C28x™)
– 16 x 16 and 32 x 32 MAC Operations
– 16 x 16 Dual MAC
– Harvard Bus Architecture
– Atomic Operations
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– 4M Linear Program/Data Address Reach
– Code-Efficient (in C/C++ and Assembly)
– TMS320F24x/LF240x Processor Source Code
Compatible
• On-Chip Memory
– Flash Devices: Up to 128K x 16 Flash
(Four 8K x 16 and Six 16K x 16 Sectors)
– ROM Devices: Up to 128K x 16 ROM
– 1K x 16 OTP ROM
– L0 and L1: 2 Blocks of 4K x 16 Each SingleAccess RAM (SARAM)
– H0: 1 Block of 8K x 16 SARAM
– M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
• Boot ROM (4K x 16)
– With Software Boot Modes
– Standard Math Tables
• External Interface (2812)
– Over 1M x 16 Total Memory
– Programmable Wait States
– Programmable Read/Write Strobe Timing
– Three Individual Chip Selects
• Endianness: Little Endian
• Clock and System Control
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Watchdog Timer Module
• Three External Interrupts
• Peripheral Interrupt Expansion (PIE) Block That
Supports 45 Peripheral Interrupts
• Three 32-Bit CPU-Timers
• 128-Bit Security Key/Lock
– Protects Flash/ROM/OTP and L0/L1 SARAM
– Prevents Firmware Reverse-Engineering
• Motor Control Peripherals
– Two Event Managers (EVA, EVB)
– Compatible to 240xA Devices
• Serial Port Peripherals
– Serial Peripheral Interface (SPI)
– Two Serial Communications Interfaces
(SCIs), Standard UART
– Enhanced Controller Area Network (eCAN)
– Multichannel Buffered Serial Port (McBSP)
• 12-Bit ADC, 16 Channels
– 2 x 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single/Simultaneous Conversions
– Fast Conversion Rate: 80 ns/12.5 MSPS
• Up to 56 General-Purpose I/O (GPIO) Pins
• Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware
• Development Tools Include
– ANSI C/C++ Compiler/Assembler/Linker
– Code Composer Studio™ IDE
– DSP/BIOS™
– JTAG Scan Controllers(1)
• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
(1)
IEEE Standard 1149.1-1990 IEEE Standard Test Access Port
and Boundary-Scan Architecture
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar BGA, TMS320C28x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TI, TMS320C54x, TMS320C55x,
TMS320 are trademarks of Texas Instruments.
eZdsp is a trademark of Spectrum Digital Incorporated.
All other trademarks are the property of their respective owners.
1
2
3
4
Copyright © 2001–2012, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
• Package Options
– 179-Ball MicroStar BGA™ With External
Memory Interface (GHH, ZHH) (2812)
– 176-Pin Low-Profile Quad Flatpack (LQFP)
With External Memory Interface (PGF) (2812)
– 128-Pin LQFP Without External Memory
Interface (PBK) (2810, 2811)
1.2
SPRS174T – APRIL 2001 – REVISED MAY 2012
• Temperature Options
– A: –40°C to 85°C (GHH, ZHH, PGF, PBK)
– S: –40°C to 125°C (GHH, ZHH, PGF, PBK)
– Q: –40°C to 125°C (PGF, PBK)
[Q100 Qualification]
Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x™ device. For
more detail on each of these steps, see the following:
• Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0)
• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)
• TMS320F28x DSC Development and Experimenter’s Kits (http://www.ti.com/f28xkits)
TMS320F281x, TMS320C281x DSPs
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Copyright © 2001–2012, Texas Instruments Incorporated
11
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
2
www.ti.com
Introduction
This section provides a summary of each device’s features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
2.1
Description
The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, and TMS320C2812
devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance
solutions for demanding control applications. The functional blocks and the memory maps are described in
Section 3, Functional Overview.
Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812 are abbreviated as F2810,
F2811, and F2812, respectively. F281x denotes all three Flash devices. TMS320C2810, TMS320C2811,
and TMS320C2812 are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three
ROM devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811
devices; and 2812 denotes both F2812 and C2812 devices.
12
Introduction
Copyright © 2001–2012, Texas Instruments Incorporated
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TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
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2.2
SPRS174T – APRIL 2001 – REVISED MAY 2012
Device Summary
Table 2-1 provides a summary of each device’s features.
Table 2-1. Hardware Features (1)
TYPE (2)
F2810
F2811
F2812
C2810
C2811
C2812
Instruction Cycle (at 150 MHz)
–
6.67 ns
6.67 ns
6.67 ns
6.67 ns
6.67 ns
6.67 ns
Single-Access RAM (SARAM) (16-bit word)
–
18K
18K
18K
18K
18K
18K
3.3-V On-Chip Flash (16-bit word)
–
64K
128K
128K
–
–
–
On-Chip ROM (16-bit word)
–
–
–
–
64K
128K
128K
Code Security for On-Chip
Flash/SARAM/OTP/ROM
–
Yes
Yes
Yes
Yes
Yes
Yes
Boot ROM
–
Yes
Yes
Yes
Yes
Yes
Yes
OTP ROM (1K x 16)
–
Yes
Yes
Yes
Yes (3)
Yes (3)
Yes (3)
External Memory Interface
0
–
–
Yes
–
–
Yes
Event Managers A and B (EVA and EVB)
–
EVA,
EVB
EVA,
EVB
EVA,
EVB
EVA,
EVB
EVA,
EVB
EVA,
EVB
●
General-Purpose (GP) Timers
–
4
4
4
4
4
4
●
Compare (CMP)/PWM
0
16
16
16
16
16
16
●
Capture (CAP)/QEP Channels
0
6/2
6/2
6/2
6/2
6/2
6/2
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
16
FEATURE
Watchdog Timer
12-Bit ADC
●
0
16
16
16
16
16
32-Bit CPU Timers
Channels
–
3
3
3
3
3
3
Serial Peripheral Interface (SPI)
0
Yes
Yes
Yes
Yes
Yes
Yes
Serial Communications Interfaces A and B
(SCIA and SCIB)
0
SCIA,
SCIB
SCIA,
SCIB
SCIA,
SCIB
SCIA,
SCIB
SCIA,
SCIB
SCIA,
SCIB
Controller Area Network (CAN)
0
Yes
Yes
Yes
Yes
Yes
Yes
Multichannel Buffered Serial Port (McBSP)
0
Yes
Yes
Yes
Yes
Yes
Yes
Digital I/O Pins (Shared)
–
56
56
56
56
56
56
External Interrupts
–
3
3
3
3
3
3
Supply Voltage
–
128-pin PBK
Packaging
176-pin PGF
179-ball GHH
–
179-ball ZHH
Temperature Options
(2)
(3)
(4)
Yes
Yes
–
Yes
Yes
–
–
–
Yes
–
–
Yes
–
–
Yes
–
–
Yes
–
–
Yes
–
–
Yes
A: –40°C to 85°C
–
Yes
Yes
Yes
Yes
Yes
Yes
S: –40°C to 125°C
–
Yes
Yes
Yes
Yes
Yes
Yes
Q: –40°C to 125°C
(Q100 Qualification)
–
Yes
Yes
PGF only
Yes
Yes
PGF only
–
TMS
TMS
TMS
TMS
TMS
TMS
Product Status (4)
(1)
1.8-V Core (135 MHz), 1.9-V Core (150 MHz), 3.3-V I/O
The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature
number SPRZ193) has been posted on the Texas Instruments (TI) website. It will be updated as needed.
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides.
On C281x devices, OTP is replaced by a 1K x 16 block of ROM.
See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.
Introduction
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13
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
2.3
www.ti.com
Pin Assignments
Figure 2-1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages.
Figure 2-2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 23 shows the pin assignments for the 128-pin PBK LQFP. Table 2-2 describes the function(s) of each pin.
2.3.1
Terminal Assignments for the GHH/ZHH Packages
See Table 2-2 for a description of each terminal’s function(s).
P
XZCS0AND1 PWM8
PWM10
VSS
VDD
CAP6_
QEPI2
XD[8]
VSS
VDD
T3CTRIP_ T4CTRIP/
PDPINTB EVBSOC
N
SPISOMIA
PWM7
PWM9
XR/W
T4PWM_
T4CMP
C4TRIP
TEST2
VDD3VFL
XD[11]
XA[2]
XWE
M
SPISIMOA
XA[1]
XRD
PWM12
CAP4_
QEP3
CAP5_
QEP4
TEST1
XD[9]
X2
VSS
XA[3]
L
VDD
VSS
XD[6]
PWM11
XD[7]
C5TRIP
VDDIO
TDIRB
XD[10]
VDDIO
K
VSS
SPICLKA
XD[4]
SPISTEA
T3PWM_
T3CMP
VSS
C6TRIP
TCLKINB
X1/
XCLKIN
J
MCLKXA
MFSRA
XD[3]
VDDIO
H
VDD
MCLKRA
XD[1]
G
MDXA
MDRA
F
XMP/MC
ADCRESEXT
E
AVDDREFBG
SCITXDB
VDDIO
PWM1
SCIRXDB
PWM2
VSS
PWM3
PWM4
XD[12]
XHOLDA
PWM5
VDD
VSS
PWM6
XD[5]
XD[13]
T1PWM_
T1CMP
XA[4]
T2PWM_
T2CMP
VSS
MFSXA
XD[2]
CAP1_
QEP1
CAP2_
QEP2
CAP3_
QEPI1
XA[5]
T1CTRIP_
PDPINTA
XD[0]
VSS
XA[0]
T2CTRIP/
EVASOC
VDDIO
VDD
VSS
XA[6]
VSSA1
VDDA1
ADCINB7
C3TRIP XCLKOUT
XA[7]
TCLKINA
TDIRA
ADCADCAVSSREFBG
REFP
REFM
ADCINA5
XA[8]
C1TRIP
VSS
EMU0
TDO
TMS
XA[9]
VSS1
SCITXDA
VDD
EMU1
VSS
XA[12]
XA[10]
TDI
VDD
ADCINA3 ADCINA7 XREADY
XA[17]
VSS
XA[15]
VDD
XD[14]
TRST XZCS6AND7
VDDA2
VDD1
SCIRXDA
XA[16]
XD[15]
XA[14]
XF_
XPLLDIS
TCK
TESTSEL
XA[11]
5
6
7
8
9
10
11
12
13
14
ADCINA0 ADCINA4
3
C2TRIP
VSS
ADCINB2
2
XA[13]
XINT1_
XBIO
B
VSSAIO
VDDIO
XINT2_
ADCSOC
ADCINB3 ADCINB0 ADCINB1 ADCINA2
ADCLO
XNMI_
XINT13
XA[18]
C
VDDAIO
ADCBGREFIN XHOLD
XRS
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6
1
XZCS2
CANTXA CANRXA
D
A
VDD
4
VSSA2
VSS
Figure 2-1. TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)
14
Introduction
Copyright © 2001–2012, Texas Instruments Incorporated
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TMS320C2810, TMS320C2811, TMS320C2812
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2.3.2
SPRS174T – APRIL 2001 – REVISED MAY 2012
Pin Assignments for the PGF Package
XA[11]
TDI
XA[10]
VSS
VDD
TDO
TMS
XA[9]
C3TRIP
C2TRIP
C1TRIP
XA[8]
VSS
XCLKOUT
XA[7]
TCLKINA
TDIR
T2CTRIP/EVASOC
VDDIO
VSS
VDD
XA[6]
T1CTRIP_PDPINTA
CAP3_QEPI1
XA[5]
CAP2_QEP2
CAP1_QEP1
VSS
T2PWM_T2CMP
XA[4]
T1PWM_T1CMP
PWM6
VDD
VSS
PWM5
XD[13]
XD[12]
PWM4
PWM3
PWM2
PWM1
SCIRXDB
SCITXDB
CANRXA
The TMS320F2812 and TMS320C2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments
are shown in Figure 2-2. See Table 2-2 for a description of each pin’s function(s).
132
89
88
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
133
XZCS6AND7
TESTSEL
TRST
TCK
EMU0
XA[12]
XD[14]
XF_XPLLDIS
XA[13]
VSS
VDD
XA[14]
VDDIO
EMU1
XD[15]
XA[15]
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
XA[16]
VSS
VDD
SCITXDA
XA[17]
SCIRXDA
XA[18]
XHOLD
XRS
XREADY
VDD1
VSS1
ADCBGREFIN
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
176
XZCS2
CANTXA
VSS
XA[3]
XWE
T4CTRIP/EVBSOC
XHOLDA
VDDIO
XA[2]
T3CTRIP_PDPINTB
VSS
X1/XCLKIN
X2
VDD
XD[11]
XD[10]
TCLKINB
TDIRB
VSS
VDD3VFL
XD[9]
TEST1
TEST2
XD[8]
VDDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
VSS
CAP4_QEP3
VDD
T4PWM_T4CMP
XD[7]
T3PWM_T3CMP
VSS
XR/W
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
44
VDDAIO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
VDDA1
VSSA1
ADCRESEXT
XMP/MC
XA[0]
VSS
MDRA
XD[0]
MDXA
VDD
XD[1]
MCLKRA
MFSXA
XD[2]
MCLKXA
MFSRA
XD[3]
VDDIO
VSS
XD[4]
SPICLKA
SPISTEA
XD[5]
VDD
VSS
XD[6]
SPISIMOA
SPISOMIA
XRD
XA[1]
XZCS0AND1
1
45
Figure 2-2. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View)
Introduction
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TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
2.3.3
www.ti.com
Pin Assignments for the PBK Package
TDI
VSS
VDD
TDO
TMS
C3TRIP
C2TRIP
C1TRIP
VSS
XCLKOUT
TCLKINA
TDIRA
T2CTRIP/EVASOC
VDDIO
VDD
T1CTRIP_PDPINTA
CAP3_QEPI1
CAP2_QEP2
CAP1_QEP1
T2PWM_T2CMP
T1PWM_T1CMP
PWM6
VDD
VSS
PWM5
PWM4
PWM3
PWM2
PWM1
SCIRXDB
SCITXDB
CANRXA
The TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-pin PBK low-profile quad
flatpack (LQFP) pin assignments are shown in Figure 2-3. See Table 2-2 for a description of each pin’s
function(s).
96
65
64
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
97
TESTSEL
TRST
TCK
EMU0
XF_XPLLDIS
VDD
VSS
VDDIO
EMU1
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
VSS
VDD
SCITXDA
SCIRXDA
XRS
VDD1
VSS1
ADCBGREFIN
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
128
CANTXA
VDD
VSS
T4CTRIP/EVBSOC
T3CTRIP_PDPINTB
VSS
X1/XCLKIN
X2
VDD
TCLKINB
TDIRB
VSS
VDD3VFL
TEST1
TEST2
VDDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
CAP4_QEP3
VDD
T4PWM_T4CMP
T3PWM_T3CMP
VSS
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
VDDAIO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
VDDA1
VSSA1
ADCRESEXT
VSS
MDRA
MDXA
VDD
MCLKRA
MFSXA
MCLKXA
MFSRA
VDDIO
VSS
SPICLKA
SPISTEA
VDD
VSS
SPISIMOA
SPISOMIA
1
Figure 2-3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP
(Top View)
16
Introduction
Copyright © 2001–2012, Texas Instruments Incorporated
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TMS320C2810, TMS320C2811, TMS320C2812
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2.4
SPRS174T – APRIL 2001 – REVISED MAY 2012
Signal Descriptions
Table 2-2 specifies the signals on the F281x and C281x devices. All digital inputs are TTL-compatible. All
outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is
used.
Table 2-2. Signal Descriptions (1)
PIN NO.
NAME
179-BALL
GHH/ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z (2)
PU/PD (3)
DESCRIPTION
XINTF SIGNALS (2812 ONLY)
XA[18]
D7
158
–
O/Z
–
XA[17]
B7
156
–
O/Z
–
XA[16]
A8
152
–
O/Z
–
XA[15]
B9
148
–
O/Z
–
XA[14]
A10
144
–
O/Z
–
XA[13]
E10
141
–
O/Z
–
XA[12]
C11
138
–
O/Z
–
XA[11]
A14
132
–
O/Z
–
XA[10]
C12
130
–
O/Z
–
XA[9]
D14
125
–
O/Z
–
XA[8]
E12
121
–
O/Z
–
XA[7]
F12
118
–
O/Z
–
XA[6]
G14
111
–
O/Z
–
XA[5]
H13
108
–
O/Z
–
XA[4]
J12
103
–
O/Z
–
XA[3]
M11
85
–
O/Z
–
XA[2]
N10
80
–
O/Z
–
XA[1]
M2
43
–
O/Z
–
XA[0]
G5
18
–
O/Z
–
XD[15]
A9
147
–
I/O/Z
PU
XD[14]
B11
139
–
I/O/Z
PU
XD[13]
J10
97
–
I/O/Z
PU
XD[12]
L14
96
–
I/O/Z
PU
XD[11]
N9
74
–
I/O/Z
PU
XD[10]
L9
73
–
I/O/Z
PU
XD[9]
M8
68
–
I/O/Z
PU
XD[8]
P7
65
–
I/O/Z
PU
XD[7]
L5
54
–
I/O/Z
PU
XD[6]
L3
39
–
I/O/Z
PU
XD[5]
J5
36
–
I/O/Z
PU
XD[4]
K3
33
–
I/O/Z
PU
XD[3]
J3
30
–
I/O/Z
PU
XD[2]
H5
27
–
I/O/Z
PU
XD[1]
H3
24
–
I/O/Z
PU
XD[0]
G3
21
–
I/O/Z
PU
(1)
(2)
(3)
19-bit XINTF Address Bus
16-bit XINTF Data Bus
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are
8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3, Electrical Characteristics
Over Recommended Operating Conditions. The pullups/pulldowns are enabled in boundary scan mode.
Introduction
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TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
www.ti.com
Table 2-2. Signal Descriptions(1) (continued)
PIN NO.
NAME
XMP/MC
179-BALL
GHH/ZHH
F1
XHOLD
E7
176-PIN
PGF
17
159
128-PIN
PBK
–
–
I/O/Z (2)
I
I
PU/PD (3)
DESCRIPTION
PD
Microprocessor/Microcomputer Mode Select.
Switches between microprocessor and
microcomputer mode. When high, Zone 7 is
enabled on the external interface. When low,
Zone 7 is disabled from the external interface,
and on-chip boot ROM may be accessed
instead. This signal is latched into the
XINTCNF2 register on a reset and the user
can modify this bit in software. The state of the
XMP/MC pin is ignored after reset.
PU
External Hold Request. XHOLD, when active
(low), requests the XINTF to release the
external bus and place all buses and strobes
into a high-impedance state. The XINTF will
release the bus when any current access is
complete and there are no pending accesses
on the XINTF.
XHOLDA
K10
82
–
O/Z
–
External Hold Acknowledge. XHOLDA is
driven active (low) when the XINTF has
granted a XHOLD request. All XINTF buses
and strobe signals will be in a high-impedance
state. XHOLDA is released when the XHOLD
signal is released. External devices should
only drive the external bus when XHOLDA is
active (low).
XZCS0AND1
P1
44
–
O/Z
–
XINTF Zone 0 and Zone 1 Chip Select.
XZCS0AND1 is active (low) when an access
to the XINTF Zone 0 or Zone 1 is performed.
XZCS2
P13
88
–
O/Z
–
XINTF Zone 2 Chip Select. XZCS2 is active
(low) when an access to the XINTF Zone 2 is
performed.
XZCS6AND7
B13
133
–
O/Z
–
XINTF Zone 6 and Zone 7 Chip Select.
XZCS6AND7 is active (low) when an access
to the XINTF Zone 6 or Zone 7 is performed.
XWE
N11
84
–
O/Z
–
Write Enable. Active-low write strobe. The
write strobe waveform is specified, per zone
basis, by the Lead, Active, and Trail periods in
the XTIMINGx registers.
–
Read Enable. Active-low read strobe. The
read strobe waveform is specified, per zone
basis, by the Lead, Active, and Trail periods in
the XTIMINGx registers. NOTE: The XRD and
XWE signals are mutually exclusive.
–
Read Not Write Strobe. Normally held high.
When low, XR/W indicates write cycle is
active; when high, XR/W indicates read cycle
is active.
PU
Ready Signal. Indicates peripheral is ready to
complete the access when asserted to 1.
XREADY can be configured to be a
synchronous or an asynchronous input. See
the timing diagrams for more details.
XRD
M3
XR/W
N4
XREADY
18
B6
Introduction
42
51
161
–
–
–
O/Z
O/Z
I
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SPRS174T – APRIL 2001 – REVISED MAY 2012
Table 2-2. Signal Descriptions(1) (continued)
PIN NO.
NAME
179-BALL
GHH/ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z (2)
PU/PD (3)
DESCRIPTION
JTAG AND MISCELLANEOUS SIGNALS
X1/XCLKIN
K9
77
58
I
–
Oscillator Input – input to the internal
oscillator. This pin is also used to feed an
external clock. The 28x can be operated with
an external clock source, provided that the
proper voltage levels be driven on the
X1/XCLKIN pin. It should be noted that the
X1/XCLKIN pin is referenced to the 1.8-V (or
1.9-V) core digital power supply (VDD), rather
than the 3.3-V I/O supply (VDDIO). A clamping
diode may be used to clamp a buffered clock
signal to ensure that the logic-high level does
not exceed VDD (1.8 V or 1.9 V) or a 1.8-V
oscillator may be used.
X2
M9
76
57
O
–
Oscillator Output
XCLKOUT
F11
119
87
O
–
Output clock derived from SYSCLKOUT to be
used for external wait-state generation and as
a general-purpose clock source. XCLKOUT is
either the same frequency, 1/2 the frequency,
or 1/4 the frequency of SYSCLKOUT. At reset,
XCLKOUT = SYSCLKOUT/4. The XCLKOUT
signal can be turned off by setting bit 3
(CLKOFF) of the XINTCNF2 register to 1.
Unlike other GPIO pins, the XCLKOUT pin is
not placed in a high-impedance state during
reset.
TESTSEL
A13
134
97
I
PD
Test Pin. Reserved for TI. Must be connected
to ground.
Device Reset (in) and Watchdog Reset (out).
XRS
D6
160
113
I/O
PU
Device reset. XRS causes the device to
terminate execution. The PC will point to the
address contained at the location 0x3FFFC0.
When XRS is brought to a high level,
execution begins at the location pointed to by
the PC. This pin is driven low by the DSP
when a watchdog reset occurs. During
watchdog reset, the XRS pin will be driven low
for the watchdog reset duration of
512 XCLKIN cycles.
The output buffer of this pin is an open-drain
with an internal pullup (100 µA, typical). It is
recommended that this pin be driven by an
open-drain device.
TEST1
TEST2
M7
N7
67
66
51
50
I/O
I/O
–
Test Pin. Reserved for TI. On F281x devices,
TEST1 must be left unconnected. On C281x
devices, this pin is a “no connect (NC)”
(that is, this pin is not connected to any
circuitry internal to the device).
–
Test Pin. Reserved for TI. On F281x devices,
TEST2 must be left unconnected. On C281x
devices, this pin is a “no connect (NC)”
(that is, this pin is not connected to any
circuitry internal to the device).
Introduction
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Table 2-2. Signal Descriptions(1) (continued)
PIN NO.
NAME
179-BALL
GHH/ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z (2)
PU/PD (3)
DESCRIPTION
JTAG
JTAG test reset with internal pulldown. TRST,
when driven high, gives the scan system
control of the operations of the device. If this
signal is not connected or driven low, the
device operates in its functional mode, and the
test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it
has an internal pulldown device. TRST is an
active-high test pin and must be maintained
low at all times during normal device
operation. In a low-noise environment, TRST
may be left floating. In other instances, an
external pulldown resistor is highly
recommended. The value of this resistor
should be based on drive strength of the
debugger pods applicable to the design. A 2.2kΩ resistor generally offers adequate
protection. Since this is application-specific, it
is recommended that each target board be
validated for proper operation of the debugger
and the application.
TRST
B12
135
98
I
PD
TCK
A12
136
99
I
PU
JTAG test clock with internal pullup
TMS
D13
126
92
I
PU
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TDI
C13
131
96
I
PU
JTAG test data input (TDI) with internal pullup.
TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
D12
127
93
O/Z
–
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) is shifted out of TDO on the falling edge
of TCK.
Emulator pin 0. When TRST is driven high,
this pin is used as an interrupt to or from the
emulator system and is defined as input/output
through the JTAG scan. This pin is also used
to put the device into boundary-scan mode.
With the EMU0 pin at a logic-high state and
the EMU1 pin at a logic-low state, a rising
edge on the TRST pin would latch the device
into boundary-scan mode.
EMU0
D11
137
100
I/O/Z
PU
NOTE: An external pullup resistor is
recommended on this pin. The value of this
resistor should be based on the drive strength
of the debugger pods applicable to the design.
A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it
is recommended that each target board be
validated for proper operation of the debugger
and the application.
20
Introduction
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TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
Table 2-2. Signal Descriptions(1) (continued)
PIN NO.
NAME
179-BALL
GHH/ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z (2)
PU/PD (3)
DESCRIPTION
Emulator pin 1. When TRST is driven high,
this pin is used as an interrupt to or from the
emulator system and is defined as input/output
through the JTAG scan. This pin is also used
to put the device into boundary-scan mode.
With the EMU0 pin at a logic-high state and
the EMU1 pin at a logic-low state, a rising
edge on the TRST pin would latch the device
into boundary-scan mode.
EMU1
C9
146
105
I/O/Z
PU
NOTE: An external pullup resistor is
recommended on this pin. The value of this
resistor should be based on the drive strength
of the debugger pods applicable to the design.
A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it
is recommended that each target board be
validated for proper operation of the debugger
and the application.
ADC ANALOG INPUT SIGNALS
ADCINA7
B5
167
119
I
–
ADCINA6
D5
168
120
I
–
ADCINA5
E5
169
121
I
–
ADCINA4
A4
170
122
I
–
ADCINA3
B4
171
123
I
–
ADCINA2
C4
172
124
I
–
ADCINA1
D4
173
125
I
–
ADCINA0
A3
174
126
I
–
ADCINB7
F5
9
9
I
–
ADCINB6
D1
8
8
I
–
ADCINB5
D2
7
7
I
–
ADCINB4
D3
6
6
I
–
ADCINB3
C1
5
5
I
–
ADCINB2
B1
4
4
I
–
ADCINB1
C3
3
3
I
–
ADCINB0
C2
2
2
I
–
ADCREFP
ADCREFM
E2
E4
11
10
11
10
I/O
I/O
8-channel analog inputs for
Sample-and-Hold A. The ADC pins should not
be driven before the VDDA1, VDDA2, and VDDAIO
pins have been fully powered up.
8-channel analog inputs for
Sample-and-Hold B. The ADC pins should not
be driven before the VDDA1, VDDA2, and VDDAIO
pins have been fully powered up.
–
ADC Voltage Reference Output (2 V).
Requires a low ESR (under 1.5 Ω) ceramic
bypass capacitor of 10 µF to analog ground.
[Can accept external reference input (2 V) if
the software bit is enabled for this mode.
1–10 µF low ESR capacitor can be used in the
external reference mode.]
NOTE: Use the ADC Clock rate to derive the
ESR specification from the capacitor data
sheet that is used in the system.
–
ADC Voltage Reference Output (1 V).
Requires a low ESR (under 1.5 Ω) ceramic
bypass capacitor of 10 µF to analog ground.
[Can accept external reference input (1 V) if
the software bit is enabled for this mode.
1–10 µF low ESR capacitor can be used in the
external reference mode.]
NOTE: Use the ADC Clock rate to derive the
ESR specification from the capacitor data
sheet that is used in the system.
Introduction
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SPRS174T – APRIL 2001 – REVISED MAY 2012
www.ti.com
Table 2-2. Signal Descriptions(1) (continued)
PIN NO.
NAME
179-BALL
GHH/ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z (2)
PU/PD (3)
DESCRIPTION
ADC External Current Bias Resistor.
Use 24.9 kΩ ± 5% for ADC clock range
1–18.75 MHz; use 20 kΩ ± 5% for ADC clock
range 18.75 MHz–25 MHz.
ADCRESEXT
F2
16
16
O
–
ADCBGREFIN
E6
164
116
–
–
Test Pin. Reserved for TI. Must be left
unconnected.
AVSSREFBG
E3
12
12
–
–
ADC Analog GND
AVDDREFBG
E1
13
13
–
–
ADC Analog Power (3.3-V)
ADCLO
B3
175
127
–
–
Common Low Side Analog Input. Connect to
analog ground.
VSSA1
F3
15
15
–
–
ADC Analog GND
VSSA2
C5
165
117
–
–
ADC Analog GND
VDDA1
F4
14
14
–
–
ADC Analog 3.3-V Supply
VDDA2
A5
166
118
–
–
ADC Analog 3.3-V Supply
VSS1
C6
163
115
–
–
ADC Digital GND
VDD1
A6
162
114
–
–
ADC Digital 1.8-V (or 1.9-V) Supply
VDDAIO
B2
1
1
–
–
3.3-V Analog I/O Power Pin
VSSAIO
A2
176
128
–
–
Analog I/O Ground Pin
VDD
H1
23
20
–
–
VDD
L1
37
29
–
–
VDD
P5
56
42
–
–
VDD
P9
75
56
–
–
VDD
P12
–
63
–
–
VDD
K12
100
74
–
–
VDD
G12
112
82
–
–
VDD
C14
128
94
–
–
VDD
B10
143
102
–
–
VDD
C8
154
110
–
–
VSS
G4
19
17
–
–
VSS
K1
32
26
–
–
VSS
L2
38
30
–
–
VSS
P4
52
39
–
–
VSS
K6
58
–
–
–
VSS
P8
70
53
–
–
VSS
M10
78
59
–
–
VSS
L11
86
62
–
–
VSS
K13
99
73
–
–
VSS
J14
105
–
–
–
VSS
G13
113
–
–
–
VSS
E14
120
88
–
–
VSS
B14
129
95
–
–
VSS
D10
142
–
–
–
VSS
C10
–
103
–
–
VSS
B8
153
109
–
–
POWER SIGNALS
22
Introduction
1.8-V or 1.9-V Core Digital Power Pins. See
Section 6.2, Recommended Operating
Conditions, for voltage requirements.
Core and Digital I/O Ground Pins
Copyright © 2001–2012, Texas Instruments Incorporated
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TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
Table 2-2. Signal Descriptions(1) (continued)
PIN NO.
179-BALL
GHH/ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z (2)
PU/PD (3)
VDDIO
J4
31
25
–
–
VDDIO
L7
64
49
–
–
VDDIO
L10
81
–
–
–
VDDIO
N14
–
–
–
–
VDDIO
G11
114
83
–
–
VDDIO
E9
145
104
–
–
NAME
VDD3VFL
N8
69
52
–
–
DESCRIPTION
3 3-V I/O Digital Power Pins
3.3-V Flash Core Power Pin. This pin should
be connected to 3.3 V at all times after powerup sequence requirements have been met.
This pin is used as VDDIO in ROM parts and
must be connected to 3.3 V in ROM parts as
well.
GPIO OR PERIPHERAL SIGNALS
GPIOA OR EVA SIGNALS
GPIOA0 - PWM1 (O)
M12
92
68
I/O
PU
GPIO or PWM Output Pin #1
GPIOA1 - PWM2 (O)
M14
93
69
I/O
PU
GPIO or PWM Output Pin #2
GPIOA2 - PWM3 (O)
L12
94
70
I/O
PU
GPIO or PWM Output Pin #3
GPIOA3 - PWM4 (O)
L13
95
71
I/O
PU
GPIO or PWM Output Pin #4
GPIOA4 - PWM5 (O)
K11
98
72
I/O
PU
GPIO or PWM Output Pin #5
GPIOA5 - PWM6 (O)
K14
101
75
I/O
PU
GPIO or PWM Output Pin #6
GPIOA6 T1PWM_T1CMP (I)
J11
102
76
I/O
PU
GPIO or Timer 1 Output
GPIOA7 T2PWM_T2CMP (I)
J13
104
77
I/O
PU
GPIO or Timer 2 Output
GPIOA8 - CAP1_QEP1 (I)
H10
106
78
I/O
PU
GPIO or Capture Input #1
GPIOA9 - CAP2_QEP2 (I)
H11
107
79
I/O
PU
GPIO or Capture Input #2
GPIOA10 - CAP3_QEPI1 (I)
H12
109
80
I/O
PU
GPIO or Capture Input #3
GPIOA11 - TDIRA (I)
F14
116
85
I/O
PU
GPIO or Timer Direction
GPIOA12 - TCLKINA (I)
F13
117
86
I/O
PU
GPIO or Timer Clock Input
GPIOA13 - C1TRIP (I)
E13
122
89
I/O
PU
GPIO or Compare 1 Output Trip
GPIOA14 - C2TRIP (I)
E11
123
90
I/O
PU
GPIO or Compare 2 Output Trip
GPIOA15 - C3TRIP (I)
F10
124
91
I/O
PU
GPIO or Compare 3 Output Trip
GPIOB OR EVB SIGNALS
GPIOB0 - PWM7 (O)
N2
45
33
I/O
PU
GPIO or PWM Output Pin #7
GPIOB1 - PWM8 (O)
P2
46
34
I/O
PU
GPIO or PWM Output Pin #8
GPIOB2 - PWM9 (O)
N3
47
35
I/O
PU
GPIO or PWM Output Pin #9
GPIOB3 - PWM10 (O)
P3
48
36
I/O
PU
GPIO or PWM Output Pin #10
GPIOB4 - PWM11 (O)
L4
49
37
I/O
PU
GPIO or PWM Output Pin #11
GPIOB5 - PWM12 (O)
M4
50
38
I/O
PU
GPIO or PWM Output Pin #12
GPIOB6 T3PWM_T3CMP (I)
K5
53
40
I/O
PU
GPIO or Timer 3 Output
GPIOB7 T4PWM_T4CMP (I)
N5
55
41
I/O
PU
GPIO or Timer 4 Output
GPIOB8 - CAP4_QEP3 (I)
M5
57
43
I/O
PU
GPIO or Capture Input #4
GPIOB9 - CAP5_QEP4 (I)
M6
59
44
I/O
PU
GPIO or Capture Input #5
GPIOB10 - CAP6_QEPI2 (I)
P6
60
45
I/O
PU
GPIO or Capture Input #6
GPIOB11 - TDIRB (I)
L8
71
54
I/O
PU
GPIO or Timer Direction
GPIOB12 - TCLKINB (I)
K8
72
55
I/O
PU
GPIO or Timer Clock Input
Introduction
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Table 2-2. Signal Descriptions(1) (continued)
PIN NO.
179-BALL
GHH/ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z (2)
PU/PD (3)
GPIOB13 - C4TRIP (I)
N6
61
46
I/O
PU
GPIO or Compare 4 Output Trip
GPIOB14 - C5TRIP (I)
L6
62
47
I/O
PU
GPIO or Compare 5 Output Trip
GPIOB15 - C6TRIP (I)
K7
63
48
I/O
PU
GPIO or Compare 6 Output Trip
NAME
DESCRIPTION
GPIOD OR EVA SIGNALS
GPIOD0 T1CTRIP_PDPINTA (I)
H14
110
81
I/O
PU
GPIO or Timer 1 Compare Output Trip
GPIOD1 T2CTRIP/EVASOC (I)
G10
115
84
I/O
PU
GPIO or Timer 2 Compare Output Trip or
External ADC Start-of-Conversion EV-A
GPIOD OR EVB SIGNALS
GPIOD5 T3CTRIP_PDPINTB (I)
P10
79
60
I/O
PU
GPIO or Timer 3 Compare Output Trip
GPIOD6 T4CTRIP/EVBSOC (I)
P11
83
61
I/O
PU
GPIO or Timer 4 Compare Output Trip or
External ADC Start-of-Conversion EV-B
GPIOE0 - XINT1_XBIO (I)
D9
149
106
I/O/Z
–
GPIO or XINT1 or XBIO input
GPIOE1 XINT2_ADCSOC (I)
D8
151
108
I/O/Z
–
GPIO or XINT2 or ADC start-of-conversion
GPIOE2 - XNMI_XINT13 (I)
E8
150
107
I/O
PU
GPIOE OR INTERRUPT SIGNALS
GPIO or XNMI or XINT13
GPIOF OR SPI SIGNALS
GPIOF0 - SPISIMOA (O)
M1
40
31
I/O/Z
–
GPIO or SPI slave in, master out
GPIOF1 - SPISOMIA (I)
N1
41
32
I/O/Z
–
GPIO or SPI slave out, master in
GPIOF2 - SPICLKA (I/O)
K2
34
27
I/O/Z
–
GPIO or SPI clock
GPIOF3 - SPISTEA (I/O)
K4
35
28
I/O/Z
–
GPIO or SPI slave transmit enable
GPIOF4 - SCITXDA (O)
C7
155
111
I/O
PU
GPIO or SCI asynchronous serial port TX data
GPIOF5 - SCIRXDA (I)
A7
157
112
I/O
PU
GPIO or SCI asynchronous serial port RX data
GPIOF6 - CANTXA (O)
N12
87
64
I/O
PU
GPIO or eCAN transmit data
GPIOF7 - CANRXA (I)
N13
89
65
I/O
PU
GPIO or eCAN receive data
GPIOF OR SCI-A SIGNALS
GPIOF OR CAN SIGNALS
GPIOF OR McBSP SIGNALS
GPIOF8 - MCLKXA (I/O)
J1
28
23
I/O
PU
GPIO or McBSP transmit clock
GPIOF9 - MCLKRA (I/O)
H2
25
21
I/O
PU
GPIO or McBSP receive clock
GPIOF10 - MFSXA (I/O)
H4
26
22
I/O
PU
GPIO or McBSP transmit frame synch
GPIOF11 - MFSRA (I/O)
J2
29
24
I/O
PU
GPIO or McBSP receive frame synch
GPIOF12 - MDXA (O)
G1
22
19
I/O
–
GPIOF13 - MDRA (I)
G2
20
18
I/O
PU
24
Introduction
GPIO or McBSP transmitted serial data
GPIO or McBSP received serial data
Copyright © 2001–2012, Texas Instruments Incorporated
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SPRS174T – APRIL 2001 – REVISED MAY 2012
Table 2-2. Signal Descriptions(1) (continued)
PIN NO.
NAME
179-BALL
GHH/ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z (2)
PU/PD (3)
DESCRIPTION
GPIOF OR XF CPU OUTPUT SIGNAL
GPIOF14 XF_XPLLDIS (O)
A11
140
101
I/O
PU
This pin has three functions:
1. XF – General-purpose output pin.
2. XPLLDIS – This pin is sampled during
reset to check whether the PLL must be
disabled. The PLL will be disabled if this
pin is sensed low. HALT and STANDBY
modes cannot be used when the PLL is
disabled.
3. GPIO – GPIO function
GPIOG OR SCI-B SIGNALS
GPIOG4 - SCITXDB (O)
P14
90
66
I/O/Z
–
GPIO or SCI asynchronous serial port transmit
data
GPIOG5 - SCIRXDB (I)
M13
91
67
I/O/Z
–
GPIO or SCI asynchronous serial port receive
data
NOTE
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However, it is acceptable for an I/O pin to ramp along
with the 3.3-V supply.
Introduction
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3
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Functional Overview
Memory Bus
TINT0
CPU-Timer 0
CPU-Timer 1
Real-Time JTAG
CPU-Timer 2
TINT2
External
Interface
INT14
(B)
PIE
(96 Interrupts)
TINT1
XINT13
XNMI
GPIO Pins
G
P
I
O
M
U
X
Data (16)
INT[12:1]
INT13
M0 SARAM
1K x 16
NMI
M1 SARAM
1K x 16
SCIA/SCIB
FIFO
L0 SARAM
4K x 16
SPI
FIFO
L1 SARAM
4K x 16
McBSP
FIFO
eCAN
Address (19)
(XINTF)
(A)
External Interrupt
Control
(XINT1/2/13, XNMI)
Control
C28x CPU
Flash
128K x 16 (F2812)
128K x 16 (F2811)
64K x 16 (F2810)
EVA/EVB
16 Channels
XRS
12-Bit ADC
System Control
X1/XCLKIN
(Oscillator and PLL
+
Peripheral Clocking
+
Low-Power Modes
+
Watchdog)
X2
XF_XPLLDIS
ROM
128K x 16 (C2812)
128K x 16 (C2811)
64K x 16 (C2810)
(C)
RS
OTP
1K x 16
CLKIN
H0 SARAM
8K x 16
Memory Bus
Boot ROM
4K x 16
Peripheral Bus
Protected by the code-security module.
A.
B.
C.
45 of the possible 96 interrupts are used on the devices.
XINTF is available on the F2812 and C2812 devices only.
On C281x devices, the OTP is replaced with a 1K x 16 block of ROM.
Figure 3-1. Functional Block Diagram
26
Functional Overview
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3.1
SPRS174T – APRIL 2001 – REVISED MAY 2012
Memory Map
Block
Start Address
On-Chip Memory
Prog Space
Data Space
0x00 0000
0x00 0040
Low 64K
(24x/240x Equivalent Data Space)
0x00 0400
0x00 0800
0x00 0D00
0x00 0E00
External Memory XINTF
Prog Space
Data Space
× x 32)
M0 Vector - RAM (32
(Enabled if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARAM
(1K x 16)
×
Reserved
Peripheral Frame 0
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1, ENPIE = 1)
Reserved
Reserved
0x00 2000
XINTF Zone 0 ×(8K x 16, XZCS0AND1)
Reserved
0x00 6000
Peripheral Frame 1
(Protected)
0x00 7000
Peripheral Frame 2
(Protected)
XINTF Zone 1 (8K x 16, XZCS0AND1) (Protected)
0x00 2000
0x00 4000
Reserved
0x00 8000
L0 SARAM (4K x 16, Secure Block)
0x00 9000
L1 SARAM ×(4K x 16, Secure Block)
Reserved
0x00 A000
Reserved
XINTF Zone 2 ×(0.5M x 16, XZCS2)
0x08 0000
XINTF Zone 6 (0.5M x 16, XZCS6AND7)
0x10 0000
0x18 0000
High 64K
(24x/240x Equivalent
Program Space)
0x3D 7800
OTP (or ROM) (1K x 16, Secure Block)
0x3D 7C00
Reserved (1K)
0x3D 8000
Flash (or ROM) (128K x 16, Secure Block)
128-Bit Password
0x3F 7FF8
0x3F 8000
Reserved
H0 SARAM (8K x 16)
0x3F A000
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K x 16)
(Enabled if MP/MC = 0)
BROM Vector× - ROM (32 x 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
0x3F C000
× x 16, XZCS6AND7)
XINTF Zone 7 (16K
(Enabled if MP/MC = 1)
XINTF Vector - RAM (32 x 32)
(Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps - M0 vector, PIE vector, BROM vector, XINTF vector - should be enabled at a time.
A.
B.
C.
D.
E.
F.
G.
Memory blocks are not to scale.
Reserved locations are reserved for future expansion. Application should not access these areas.
Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
“Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 3-2. F2812/C2812 Memory Map
Functional Overview
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Block
Start Address
On-Chip Memory
Prog Space
Data Space
0x00 0000
0x00 0040
Low 64K
(24x/240x Equivalent Data Space)
0x00 0400
0x00 0800
0x00 0D00
0x00 0E00
× x 32)
M0 Vector - RAM (32
(Enabled if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARAM
(1K x 16)
×
Peripheral Frame 0
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1, ENPIE = 1)
Reserved
Reserved
0x00 2000
Reserved
0x00 6000
Peripheral Frame 1
(Protected)
0x00 7000
Peripheral Frame 2
(Protected)
Reserved
0x00 8000
L0 SARAM (4K x 16, Secure Block)
0x00 9000
L1 SARAM ×(4K x 16, Secure Block)
0x00 A000
Reserved
High 64K
(24x/240x Equivalent
Program Space)
0x3D 7800
OTP (or ROM) (1K x 16, Secure Block)
0x3D 7C00
Reserved (1K)
0x3D 8000
Flash (or ROM) (128K x 16, Secure Block)
128-Bit Password
0x3F 7FF8
0x3F 8000
H0 SARAM (8K x 16)
0x3F A000
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K x 16)
(Enabled if MP/MC = 0)
BROM Vector× - ROM (32 x 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
LEGEND:
Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.
A.
B.
C.
D.
E.
Memory blocks are not to scale.
Reserved locations are reserved for future expansion. Application should not access these areas.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
“Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-3. F2811/C2811 Memory Map
28
Functional Overview
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SPRS174T – APRIL 2001 – REVISED MAY 2012
Block
Start Address
On-Chip Memory
Prog Space
Data Space
0x00 0000
0x00 0040
Low 64K
(24x/240x Equivalent Data Space)
0x00 0400
0x00 0800
0x00 0D00
0x00 0E00
× x 32)
M0 Vector - RAM (32
(Enabled if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARAM
(1K x 16)
×
Peripheral Frame 0
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1, ENPIE = 1)
Reserved
Reserved
0x00 2000
Reserved
0x00 6000
Peripheral Frame 1
(Protected)
0x00 7000
Peripheral Frame 2
(Protected)
Reserved
0x00 8000
L0 SARAM (4K x 16, Secure Block)
0x00 9000
L1 SARAM ×(4K x 16, Secure Block)
0x00 A000
Reserved
High 64K
(24x/240x Equivalent
Program Space)
0x3D 7800
OTP (or ROM) (1K x 16, Secure Block)
0x3D 7C00
Reserved
0x3E 8000
Flash (or ROM) (64K x 16, Secure Block)
128-Bit Password
0x3F 7FF8
0x3F 8000
H0 SARAM (8K x 16)
0x3F A000
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K x 16)
(Enabled if MP/MC = 0)
BROM Vector× - ROM (32 x 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
LEGEND:
Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.
A.
B.
C.
D.
E.
Memory blocks are not to scale.
Reserved locations are reserved for future expansion. Application should not access these areas.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
“Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-4. F2810/C2810 Memory Map
Functional Overview
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Table 3-1. Addresses of Flash Sectors in F2812 and F2811
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3D 8000
0x3D 9FFF
Sector J, 8K x 16
0x3D A000
0x3D BFFF
Sector I, 8K x 16
0x3D C000
0x3D FFFF
Sector H, 16K x 16
0x3E 0000
0x3E 3FFF
Sector G, 16K x 16
0x3E 4000
0x3E 7FFF
Sector F, 16K x 16
0x3E 8000
0x3E BFFF
Sector E, 16K x 16
0x3E C000
0x3E FFFF
Sector D, 16K x 16
0x3F 0000
0x3F 3FFF
Sector C, 16K x 16
0x3F 4000
0x3F 5FFF
Sector B, 8K x 16
0x3F 6000
Sector A, 8K x 16
0x3F 7F80
0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6
0x3F 7FF7
Boot-to-Flash (or ROM) Entry Point
(program branch instruction here)
0x3F 7FF8
0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
Table 3-2. Addresses of Flash Sectors in F2810
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3E 8000
0x3E BFFF
Sector E, 16K x 16
0x3E C000
0x3E FFFF
Sector D, 16K x 16
0x3F 0000
0x3F 3FFF
Sector C, 16K x 16
0x3F 4000
0x3F 5FFF
Sector B, 8K x 16
0x3F 6000
Sector A, 8K x 16
0x3F 7F80
0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6
0x3F 7FF7
Boot-to-Flash (or ROM) Entry Point
(program branch instruction here)
0x3F 7FF8
0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
The “Low 64K” of the memory address range maps into the data space of the 240x. The “High 64K” of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will
execute only from the “High 64K”memory area. Hence, the top 32K of Flash/ROM and H0 SARAM block
can be used to run 24x/240x-compatible code (if MP/MC mode is low) or, on the 2812, code can be
executed from XINTF Zone 7 (if MP/MC mode is high).
30
Functional Overview
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SPRS174T – APRIL 2001 – REVISED MAY 2012
The XINTF consists of five independent zones. One zone has its own chip select and the remaining four
zones share two chip selects. Each zone can be programmed with its own timing (wait states) and to
either sample or ignore external ready signal. This makes interfacing to external peripherals easy and
glueless.
NOTE
The chip selects of XINTF Zone 0 and Zone 1 are merged into a single chip select
(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged into a single
chip select (XZCS6AND7). See Section 3.5, External Interface, XINTF (2812 only), for
details.
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together to enable these blocks
to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected to make
sure that operations occur as written (the penalty is extra cycles that are added to align the operations).
This mode is programmable and, by default, it will protect the selected zones.
On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows
the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on
reset is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in
software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are
affected by XMP/MC.
I/O space is not supported on the 2812 XINTF.
The wait states for the various spaces in the memory map area are listed in Table 3-3.
Table 3-3. Wait States
AREA
WAIT-STATES
M0 and M1 SARAMs
0-wait
Fixed
COMMENTS
Peripheral Frame 0
0-wait
Fixed
Peripheral Frame 1
0-wait (writes)
2-wait (reads)
Fixed
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed
L0 and L1 SARAMs
0-wait
Fixed
OTP (or ROM)
Programmable,
1-wait minimum
Programmed via the Flash registers. 1-wait-state operation is possible at a
reduced CPU frequency. See Section 3.2.6, Flash (F281x Only), for more
information.
Flash (or ROM)
Programmable,
0-wait minimum
Programmed via the Flash registers. 0-wait-state operation is possible at
reduced CPU frequency. The CSM password locations are hardwired for
16 wait states. See Section 3.2.6, Flash (F281x Only), for more information.
H0 SARAM
0-wait
Fixed
Boot-ROM
1-wait
Fixed
XINTF
Programmable,
1-wait minimum
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
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3.2
3.2.1
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Brief Descriptions
C28x CPU
The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is
source code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their
significant software investment. Additionally, the C28x is a very efficient C/C++ engine, enabling users to
develop not only their system control software in a high-level language, but also enables math algorithms
to be developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks
that typically are handled by microcontroller devices. This efficiency removes the need for a second
processor in many systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing
capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would
otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt
response with automatic context save of critical registers, resulting in a device that is capable of servicing
many asynchronous events with minimal latency. The C28x has an 8-level-deep protected pipeline with
pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting
to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for
conditional discontinuities. Special store conditional operations further improve performance.
3.2.2
Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed “Harvard Bus”, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of Memory
Bus accesses can be summarized as follows:
Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.)
3.2.3
Peripheral Bus
To enable migration of peripherals between various Texas Instruments ( TI™) DSP family of devices, the
F281x and C281x adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor “Memory Bus” into a single bus consisting of
16 address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral
bus are supported on the F281x and C281x. One version only supports 16-bit accesses (called peripheral
frame 2) and this retains compatibility with C240x-compatible peripherals. The other version supports both
16- and 32-bit accesses (called peripheral frame 1).
32
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3.2.4
SPRS174T – APRIL 2001 – REVISED MAY 2012
Real-Time JTAG and Analysis
The F281x and C281x implement the standard IEEE 1149.1 JTAG interface. Additionally, the F281x and
C281x support real-time mode of operation whereby the contents of memory, peripheral, and register
locations can be modified while the processor is running and executing code and servicing interrupts. The
user can also single step through non-time critical code while enabling time-critical interrupts to be
serviced without interference. The F281x and C281x implement the real-time mode in hardware within the
CPU. This is a unique feature to the F281x and C281x, no software monitor is required. Additionally,
special analysis hardware is provided that allows the user to set hardware breakpoint or data/address
watch-points and generate various user selectable break events when a match occurs.
3.2.5
External Interface (XINTF) (2812 Only)
This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The
chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single
chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed
with a different number of wait states, strobe signal setup and hold timing and each zone can be
programmed for extending wait states externally or not. The programmable wait-state, chip-select and
programmable strobe timing enables glueless interface to external memories and peripherals.
3.2.6
Flash (F281x Only)
The F2812 and F2811 contain 128K x 16 of embedded flash memory, segregated into four 8K x 16
sectors, and six 16K x 16 sectors. The F2810 has 64K x 16 of embedded flash, segregated into two 8K x
16 sectors, and three 16K x 16 sectors. All three devices also contain a single 1K x 16 of OTP memory at
address range 0x3D 7800–0x3D 7BFF. The user can individually erase, program, and validate a flash
sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or
the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is
provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both
program and data space; therefore, it can be used to execute code or store data information.
NOTE
The F2810/F2811/F2812 Flash and OTP wait states can be configured by the application.
This allows applications running at slower frequencies to configure the flash to use fewer
wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature
number SPRU078).
3.2.7
ROM (C281x Only)
The C2812 and C2811 contain 128K x 16 of ROM. The C2810 has 64K x 16 of ROM. In addition to this,
there is a 1K x 16 ROM block that replaces the OTP memory available in flash devices. For information on
how to submit ROM codes to TI, see the TMS320C28x CPU and Instruction Set Reference Guide
(literature number SPRU430).
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3.2.8
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M0, M1 SARAMs
All C28x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack
pointer points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2
RAM blocks and hence the mapping of data variables on the 240x devices can remain at the same
physical address on C28x devices. The M0 and M1 blocks, like all other memory blocks on C28x devices,
are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for
data variables. The partitioning is performed within the linker. The C28x device presents a unified memory
map to the programmer. This makes for easier programming in high-level languages.
3.2.9
L0, L1, H0 SARAMs
The F281x and C281x contain an additional 16K x 16 of single-access RAM, divided into three blocks
(4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block
is mapped to both program and data space.
3.2.10 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after
device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user
can select to execute code already present in the internal Flash or download new software to internal
RAM through one of several serial ports. Other boot modes exist as well. The Boot ROM also contains
standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Table 3-4 shows the
details of how various boot modes may be invoked. See the TMS320x281x DSP Boot ROM Reference
Guide (literature number SPRU095), for more information.
Table 3-4. Boot Mode Selection (1) (2)
BOOT MODE SELECTED
GPIO PU status (3)
GPIOF4
(SCITXDA)
GPIOF12
(MDXA)
GPIOF3
(SPISTEA)
GPIOF2
(SPICLK)
PU
No PU
No PU
No PU
Jump to Flash/ROM address 0x3F 7FF6.
A branch instruction must have been programmed here prior to
reset to re-direct code execution as desired.
1
x
x
x
Call SPI_Boot to load from an external serial SPI EEPROM
0
1
x
x
Call SCI_Boot to load from SCI-A
0
0
1
1
Jump to H0 SARAM address 0x3F 8000
0
0
1
0
Jump to OTP address 0x3D 7800
0
0
0
1
Call Parallel_Boot to load from GPIO Port B
0
0
0
0
(1)
(2)
(3)
Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic.
If the boot mode selected is Flash, H0, or OTP, then no external code is loaded by the bootloader.
PU = pin has an internal pullup. No PU = pin does not have an internal pullup.
3.2.11 Security
The F281x and C281x support high levels of security to protect the user firmware from being reverseengineered. The security features a 128-bit password (hardcoded for 16 wait states), which the user
programs into the flash. One code security module (CSM) is used to protect the flash/ROM/OTP and the
L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory
contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable
software that would export the secure memory contents. To enable access to the secure blocks, the user
must write the correct 128-bit ”KEY” value, which matches the value stored in the password locations
within the Flash/ROM.
34
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NOTE
•
•
•
•
When the code-security passwords are programmed, all addresses between 0x3F 7F80
and 0x3F 7FF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may
be used for code or data.
On ROM devices, addresses 0x3F 7FF2–0x3F 7FF5 and 0x3D 7BFC–0x3D 7BFF are
reserved for TI, irrespective of whether code security has been used or not. User
application should not use these locations in any way.
The 128-bit password (at 0x3F 7FF8–0x3F 7FFF) must not be programmed to zeros.
Doing so would permanently lock the device.
Table 3-5. Impact of Using the Code Security Module
ADDRESS
CODE SECURITY STATUS
Code Security Enabled
Code Security Disabled
Fill with 0x0000
Application code and data (1)
0x3F 7F80 – 0x3F 7FEF
0x3F 7FF0 – 0x3F 7FF5
0x3D 7BFC – 0x3D 7BFF
(1)
Application code and data
See the TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature
number SPRZ193) for some restrictions.
Disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY
(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN
ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO
TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR
THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANT ABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
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3.2.12 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F281x and C281x, 45 of the possible
96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed
into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector
stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched
by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical
CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is
controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE
block.
3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI)
The F281x and C281x support three masked external interrupts (XINT1, 2, 13). XINT13 is combined with
one non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the
interrupts can be selected for negative or positive edge triggering and can also be enabled/disabled
(including the XNMI). The masked interrupts also contain a 16-bit free-running up-counter, which is reset
to zero when a valid interrupt edge is detected. This counter can be used to accurately time-stamp the
interrupt.
3.2.14 Oscillator and PLL
The F281x and C281x can be clocked by an external oscillator or by a crystal attached to the on-chip
oscillator circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be
changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power
operation is desired. Refer to Section 6, Electrical Specifications, for timing details. The PLL block can be
set in bypass mode.
3.2.15 Watchdog
The F281x and C281x support a watchdog timer. The user software must regularly reset the watchdog
counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The
watchdog can be disabled if necessary.
3.2.16 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event
managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of
peripherals to be decoupled from increasing CPU clock speeds.
3.2.17 Low-Power Modes
The F281x and C281x devices are fully static CMOS devices. Three low-power modes are provided:
36
IDLE:
Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that must function during IDLE are left operating. An enabled interrupt
from an active peripheral will wake the processor from IDLE mode.
STANDBY:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event.
HALT:
Turns off the internal oscillator. This mode basically shuts down the device and places it
in the lowest possible power consumption mode. Only a reset or XNMI can wake the
device from this mode.
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3.2.18 Peripheral Frames 0, 1, 2 (PFn)
The F281x and C281x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0:
XINTF:
External Interface Configuration Registers (2812 only)
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash:
Flash Control, Programming, Erase, Verify Registers
Timers:
CPU-Timers 0, 1, 2 Registers
CSM:
Code Security Module KEY Registers
PF1:
eCAN:
eCAN Mailbox and Control Registers
PF2:
SYS:
System Control Registers
GPIO:
GPIO Mux Configuration and Control Registers
EV:
Event Manager (EVA/EVB) Control Registers
McBSP:
McBSP Control and TX/RX Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
SPI:
Serial Peripheral Interface (SPI) Control and RX/TX Registers
ADC:
12-Bit ADC Registers
3.2.19 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This multiplexing
enables use of a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are
configured as inputs. The user can then individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles to filter
unwanted noise glitches.
3.2.20 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for the DSP/BIOS Real-Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not
being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be
connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.
3.2.21 Control Peripherals
The F281x and C281x support the following peripherals that are used for embedded control and
communication:
EV:
The event manager module includes general-purpose timers, full-compare/PWM units,
capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event
managers are provided which enable two three-phase motors to be driven or four twophase motors. The event managers on the F281x and C281x are compatible to the event
managers on the 240x devices (with some minor enhancements).
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sampleand-hold units for simultaneous sampling.
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3.2.22 Serial Port Peripherals
The F281x and C281x support the following serial communication peripherals:
38
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
McBSP:
The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality
codecs for modem applications or high-quality stereo audio DAC devices. The McBSP
receive and transmit registers are supported by a 16-level FIFO that significantly reduces
the overhead for servicing this peripheral.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between
the DSP controller and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers,
display drivers, and ADCs. Multi-device communications are supported by the
master/slave operation of the SPI. On the F281x and C281x, the port supports a 16level, receive-and-transmit FIFO for reducing servicing overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F281x and C281x, the port supports a 16-level, receive-andtransmit FIFO for reducing servicing overhead.
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3.3
SPRS174T – APRIL 2001 – REVISED MAY 2012
Register Map
The F281x and C281x devices contain three peripheral register spaces. The spaces are categorized as
follows:
Peripheral Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-6.
Peripheral Frame 1:
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3-7.
Peripheral Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3-8.
Table 3-6. Peripheral Frame 0 Registers (1)
NAME
ACCESS TYPE (2)
ADDRESS RANGE
SIZE (x16)
Device Emulation Registers
0x00 0880 – 0x00 09FF
384
Reserved
0x00 0A00 – 0x00 0A7F
128
0x00 0A80 – 0x00 0ADF
96
EALLOW protected
CSM Protected
Code Security Module Registers
0x00 0AE0 – 0x00 0AEF
16
EALLOW protected
Reserved
0x00 0AF0 – 0x00 0B1F
48
XINTF Registers
0x00 0B20 – 0x00 0B3F
32
Reserved
0x00 0B40 – 0x00 0BFF
192
CPU-TIMER0/1/2 Registers
0x00 0C00 – 0x00 0C3F
64
Reserved
0x00 0C40 – 0x00 0CDF
160
PIE Registers
0x00 0CE0 – 0x00 0CFF
32
Not EALLOW protected
PIE Vector Table
0x00 0D00 – 0x00 0DFF
256
EALLOW protected
Reserved
0x00 0E00 – 0x00 0FFF
512
FLASH Registers
(1)
(2)
(3)
(3)
EALLOW protected
Not EALLOW protected
Not EALLOW protected
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS
instruction disables writes. This prevents stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-7. Peripheral Frame 1 Registers (1)
NAME
ADDRESS RANGE
SIZE (x16)
eCAN Registers
0x00 6000 – 0x00 60FF
256
(128 x 32)
Some eCAN control registers (and selected bits in
other eCAN control registers) are EALLOW-protected.
eCAN Mailbox RAM
0x00 6100 – 0x00 61FF
256
(128 x 32)
Not EALLOW-protected
Reserved
0x00 6200 – 0x00 6FFF
3584
(1)
ACCESS TYPE
The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
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Table 3-8. Peripheral Frame 2 Registers (1)
NAME
ADDRESS RANGE
SIZE (x16)
Reserved
0x00 7000 – 0x00 700F
16
System Control Registers
0x00 7010 – 0x00 702F
32
Reserved
0x00 7030 – 0x00 703F
16
SPI-A Registers
0x00 7040 – 0x00 704F
16
Not EALLOW Protected
SCI-A Registers
0x00 7050 – 0x00 705F
16
Not EALLOW Protected
Reserved
0x00 7060 – 0x00 706F
16
External Interrupt Registers
0x00 7070 – 0x00 707F
16
Reserved
0x00 7080 – 0x00 70BF
64
GPIO Mux Registers
0x00 70C0 – 0x00 70DF
32
EALLOW Protected
GPIO Data Registers
0x00 70E0 – 0x00 70FF
32
Not EALLOW Protected
Not EALLOW Protected
ADC Registers
0x00 7100 – 0x00 711F
32
Reserved
0x00 7120 – 0x00 73FF
736
EV-A Registers
0x00 7400 – 0x00 743F
64
Reserved
0x00 7440 – 0x00 74FF
192
EV-B Registers
0x00 7500 – 0x00 753F
64
Reserved
0x00 7540 – 0x00 774F
528
SCI-B Registers
0x00 7750 – 0x00 775F
16
Reserved
0x00 7760 – 0x00 77FF
160
McBSP Registers
0x00 7800 – 0x00 783F
64
Reserved
0x00 7840 – 0x00 7FFF
1984
(1)
40
ACCESS TYPE
EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
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3.4
SPRS174T – APRIL 2001 – REVISED MAY 2012
Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 3-9.
Table 3-9. Device Emulation Registers
NAME
DEVICECNF
PARTID
ADDRESS RANGE
SIZE
(x16)
0x00 0880 – 0x00 0881
2
Device Configuration Register
0x00 0882
1
Part ID Register
0x0001 or 0x0002 – F281x
0x0003 – C281x
0x0001 – Silicon Revision A
0x0002 – Silicon Revision B
0x0003 – Silicon Revisions C, D
0x0004 – Reserved
0x0005 – Silicon Revision E
0x0006 – Silicon Revision F
0x0007 – Silicon Revision G
DESCRIPTION
REVID
0x00 0883
1
Revision ID Register
PROTSTART
0x00 0884
1
Block Protection Start Address Register
PROTRANGE
0x00 0885
1
Block Protection Range Address Register
0x00 0886 – 0x00 09FF
378
Reserved
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3.5
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External Interface, XINTF (2812 Only)
This section gives a top-level view of the external interface (XINTF) that is implemented on the 2812
devices.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
external interface on the 2812 is mapped into five fixed zones shown in Figure 3-5.
Figure 3-5 shows the 2812 XINTF signals.
Data Space
Prog Space
0x00 0000
XD[15:0]
XA[18:0]
0x00 2000
0x00 4000
XINTF Zone 0
(8K x 16)
XINTF Zone 1
(8K x 16)
XZCS0
XZCS1
XZCS0AND1
0x00 6000
0x08 0000
XINTF Zone 2
(512K x 16)
XZCS2
0x10 0000
XINTF Zone 6
(512K x 16)
XZCS6
XINTF Zone 7
(16K x 16)
(mapped here if MP/MC = 1)
XZCS7
XZCS6AND7
0x18 0000
0x3F C000
0x40 0000
A.
B.
C.
D.
E.
XWE
XRD
XR/W
XREADY
XMP/MC
XHOLD
XHOLDA
(E)
XCLKOUT
The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of
XINTCNF2 register). Zones 0, 1, 2, and 6 are always enabled.
Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip
selects (XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These
features enable glueless connection to many external memories and peripherals.
The chip selects for Zone 0 and Zone 1 are ANDed internally together to form one chip select (XZCS0AND1). Any
external memory that is connected to XZCS0AND1 is dually mapped to both Zone 0 and Zone 1.
The chip selects for Zone 6 and Zone 7 are ANDed internally together to form one chip select (XZCS6AND7). Any
external memory that is connected to XZCS6AND7 is dually mapped to both Zone 6 and Zone 7. This means that if
Zone 7 is disabled (via the MP/MC mode), then any external memory is still accessible via Zone 6 address space.
XCLKOUT is also pinned out on the 2810 and 2811.
Figure 3-5. External Interface Block Diagram
42
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The operation and timing of the external interface, can be controlled by the registers listed in Table 3-10.
Table 3-10. XINTF Configuration and Control Register Mappings
ADDRESS
SIZE
(x16)
XTIMING0
0x00 0B20
2
XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register.
XTIMING1
0x00 0B22
2
XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register.
XTIMING2
0x00 0B24
2
XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register.
XTIMING6
0x00 0B2C
2
XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register.
XTIMING7
0x00 0B2E
2
XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register.
XINTCNF2
0x00 0B34
2
XINTF Configuration Register can access as two 16-bit registers or one 32-bit register.
XBANK
0x00 0B38
1
XINTF Bank Control Register
XREVISION
0x00 0B3A
1
XINTF Revision Register
NAME
3.5.1
DESCRIPTION
Timing Registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold
times to strobe signals for contention avoidance and maximizing bus efficiency. The XINTF timing
parameters can be configured individually for each zone based on the requirements of the memory or
peripheral accessed by that particular zone. This allows the programmer to maximize the efficiency of the
bus on a per-zone basis. All XINTF timing values are with respect to XTIMCLK, which is equal to or onehalf of the SYSCLKOUT rate, as shown in Figure 6-30.
For detailed information on the XINTF timing and configuration register bit fields, see the TMS320x281x
DSP External Interface (XINTF) Reference Guide (literature number SPRU067).
3.5.2
XREVISION Register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the 2812, this register will be configured as described in Table 3-11.
Table 3-11. XREVISION Register Bit Definitions
BIT(S)
15–0
NAME
REVISION
TYPE
R
RESET
DESCRIPTION
0x0004
Current XINTF Revision. For internal use/reference. Test purposes
only. Subject to change.
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Interrupts
Figure 3-6 shows how the various interrupt sources are multiplexed within the F281x and C281x devices.
Peripherals
(SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
WDINT
WAKEINT
INT1
to
INT12
96 Interrupts
(A)
LPMINT
PIE
Interrupt Control
Watchdog
Low-Power Modes
XINT1
XINT1CR[15:0]
XINT1CTR[15:0]
Interrupt Control
XINT2
XINT2CR[15:0]
C28x CPU
XINT2CTR[15:0]
TINT0
TINT2
INT14
TIMER 0
TINT1
TIMER 1
MUX
INT13
GPIO
MUX
TIMER 2
(Reserved for DSP/BIOS)
select
enable
NMI
Interrupt Control
XNMI_XINT13
XNMICR[15:0]
XNMICTR[15:0]
A.
Out of a possible 96 interrupts, 45 are currently used by peripherals.
Figure 3-6. Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. On the F281x and C281x, 45 of these are used by
peripherals as shown in Table 3-12.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.
44
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IFR[12:1]
IER[12:1]
INTM
INT1
INT2
1
MUX
INT11
INT12
(Flag)
INTx
Global
Enable
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
MUX
PIEACKx
(Enable/Flag)
CPU
0
(Enable)
(Flag)
PIEIERx[8:1]
PIEIFRx[8:1]
From
Peripherals
or
External
Interrupts
Figure 3-7. Multiplexing of Interrupts Using the PIE Block
Table 3-12. PIE Peripheral Interrupts (1)
CPU
INTERRUPTS
(1)
PIE INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
XINT2
XINT1
Reserved
PDPINTB
(EV-B)
PDPINTA
(EV-A)
INT2
Reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
INT3
Reserved
CAPINT3
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
INT4
Reserved
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
INT5
Reserved
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
INT6
Reserved
Reserved
MXINT
(McBSP)
MRINT
(McBSP)
Reserved
Reserved
SPITXINTA
(SPI)
SPIRXINTA
(SPI)
INT7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INT8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INT9
Reserved
Reserved
ECAN1INT
(CAN)
ECAN0INT
(CAN)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT10
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INT11
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INT12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Out of the 96 possible interrupts, 45 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
• No peripheral within the group is asserting interrupts.
• No peripheral interrupts are assigned to the group (example PIE group 12).
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Table 3-13. PIE Configuration and Control Registers (1)
NAME
ADDRESS
SIZE (x16)
PIECTRL
0x0000 0CE0
1
PIE, Control Register
PIEACK
0x0000 0CE1
1
PIE, Acknowledge Register
PIEIER1
0x0000 0CE2
1
PIE, INT1 Group Enable Register
PIEIFR1
0x0000 0CE3
1
PIE, INT1 Group Flag Register
PIEIER2
0x0000 0CE4
1
PIE, INT2 Group Enable Register
PIEIFR2
0x0000 0CE5
1
PIE, INT2 Group Flag Register
PIEIER3
0x0000 0CE6
1
PIE, INT3 Group Enable Register
PIEIFR3
0x0000 0CE7
1
PIE, INT3 Group Flag Register
PIEIER4
0x0000 0CE8
1
PIE, INT4 Group Enable Register
PIEIFR4
0x0000 0CE9
1
PIE, INT4 Group Flag Register
PIEIER5
0x0000 0CEA
1
PIE, INT5 Group Enable Register
PIEIFR5
0x0000 0CEB
1
PIE, INT5 Group Flag Register
PIEIER6
0x0000 0CEC
1
PIE, INT6 Group Enable Register
PIEIFR6
0x0000 0CED
1
PIE, INT6 Group Flag Register
PIEIER7
0x0000 0CEE
1
PIE, INT7 Group Enable Register
PIEIFR7
0x0000 0CEF
1
PIE, INT7 Group Flag Register
PIEIER8
0x0000 0CF0
1
PIE, INT8 Group Enable Register
PIEIFR8
0x0000 0CF1
1
PIE, INT8 Group Flag Register
PIEIER9
0x0000 0CF2
1
PIE, INT9 Group Enable Register
PIEIFR9
0x0000 0CF3
1
PIE, INT9 Group Flag Register
PIEIER10
0x0000 0CF4
1
PIE, INT10 Group Enable Register
PIEIFR10
0x0000 0CF5
1
PIE, INT10 Group Flag Register
PIEIER11
0x0000 0CF6
1
PIE, INT11 Group Enable Register
PIEIFR11
0x0000 0CF7
1
PIE, INT11 Group Flag Register
PIEIER12
0x0000 0CF8
1
PIE, INT12 Group Enable Register
PIEIFR12
0x0000 0CF9
1
PIE, INT12 Group Flag Register
Reserved
0x0000 0CFA – 0x0000 0CFF
6
Reserved
(1)
46
DESCRIPTION
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.
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3.6.1
SPRS174T – APRIL 2001 – REVISED MAY 2012
External Interrupts
Table 3-14. External Interrupts Registers
NAME
ADDRESS
SIZE (x16)
0x00 7070
1
XINT1 control register
XINT2CR
0x00 7071
1
XINT2 control register
Reserved
0x00 7072 – 0x00 7076
5
XNMICR
0x00 7077
1
XNMI control register
XINT1CTR
0x00 7078
1
XINT1 counter register
XINT2CTR
0x00 7079
1
XINT2 counter register
Reserved
0x00 707A – 0x00 707E
5
XNMICTR
0x00 707F
1
XINT1CR
DESCRIPTION
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For
more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature
number SPRU078).
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System Control
This section describes the F281x and C281x oscillator, PLL and clocking mechanisms, the watchdog
function and the low-power modes. Figure 3-8 shows the various clock and reset domains in the F281x
and C281x devices that will be discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT
Peripheral Reset
CLKIN
(A)
X1/XCLKIN
PLL
C28x CPU
OSC
Power
Modes
Control
System
Control
Registers
Peripheral Bus
I/O
eCAN
LSPCLK
Low-Speed Prescaler
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
I/O
GPIO
MUX
HSPCLK
High-Speed Prescaler
Peripheral
Registers
XF_XPLLDIS
Clock Enables
Peripheral
Registers
Peripheral
Registers
X2
High-Speed Peripherals
EV-A/B
GPIOs
I/O
HSPCLK
ADC
Registers
A.
12-Bit ADC
16 ADC Inputs
CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3-8. Clock and Reset Domains
48
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-15.
Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers (1)
NAME
ADDRESS
SIZE (x16)
Reserved
0x00 7010 – 0x00 7017
8
Reserved
0x00 7018
1
Reserved
0x00 7019
1
HISPCP
0x00 701A
1
High-Speed Peripheral Clock Prescaler Register for
HSPCLK clock
LOSPCP
0x00 701B
1
Low-Speed Peripheral Clock Prescaler Register for
LSPCLK clock
PCLKCR
0x00 701C
1
Peripheral Clock Control Register
Reserved
0x00 701D
1
LPMCR0
0x00 701E
1
Low-Power Mode Control Register 0
LPMCR1
0x00 701F
1
Low-Power Mode Control Register 1
Reserved
0x00 7020
1
PLLCR
0x00 7021
1
PLL Control Register (2)
SCSR
0x00 7022
1
System Control and Status Register
WDCNTR
0x00 7023
1
Watchdog Counter Register
Reserved
0x00 7024
1
WDKEY
0x00 7025
1
0x00 7026 – 0x00 7028
3
0x00 7029
1
0x00 702A – 0x00 702F
6
Reserved
WDCR
Reserved
(1)
(2)
DESCRIPTION
Watchdog Reset Key Register
Watchdog Control Register
All of the above registers can only be accessed by executing the EALLOW instruction.
The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio)
will not reset PLLCR.
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OSC and PLL Block
Figure 3-9 shows the OSC and PLL block on the F281x and C281x.
XF_XPLLDIS
XPLLDIS
Latch
XRS
XCLKIN
X1/XCLKIN
OSCCLK (PLL Disabled)
0
CLKIN
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
CPU
SYSCLKOUT
1
4-Bit PLL Select
X2
PLL
4-Bit PLL Select
PLL Block
Figure 3-9. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to the F281x and C281x devices using the
X1/XCLKIN and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to
the X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not
exceed VDD. The PLLCR bits [3:0] set the clocking ratio.
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Table 3-16. PLLCR Register Bit Definitions
BIT(S)
NAME
TYPE
XRS
RESET (1)
15:4
Reserved
R=0
0:0
DESCRIPTION
SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication
factor.
3:0
(1)
DIV
R/W
0,0,0,0
Bit Value
n
SYSCLKOUT
0000
PLL Bypassed
XCLKIN/2
0001
1
XCLKIN/2
0010
2
XCLKIN
0011
3
XCLKIN * 1.5
0100
4
XCLKIN * 2
0101
5
XCLKIN * 2.5
0110
6
XCLKIN * 3
0111
7
XCLKIN * 3.5
1000
8
XCLKIN * 4
1001
9
XCLKIN * 4.5
1010
10
XCLKIN * 5
1011
11
Reserved
1100
12
Reserved
1101
13
Reserved
1110
14
Reserved
1111
15
Reserved
The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is
not changed.
3.8.1
Loss of Input Clock
In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will
still issue a “limp-mode” clock. The limp-mode clock will continue to clock the CPU and peripherals at a
typical frequency of 1–4 MHz. The PLLCR register should have been written to with a non-zero value for
this feature to work.
Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog
reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop
decrementing (that is, the watchdog counter does not change with the limp-mode clock). This condition
could be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical must
implement a mechanism by which the DSP will be held in reset, should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP, should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the VDD3VFL rail.
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PLL-Based Clock Module
The F281x and C281x have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control to select different CPU clock rates. The watchdog module should be disabled before writing to the
PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
131072 XCLKIN cycles.
The PLL-based clock module provides two modes of operation:
• Crystal operation: This mode allows the use of an external crystal/resonator to provide the time base
to the device.
• External clock source operation: This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1/XCLKIN pin.
X1/XCLKIN
X2
(A)
(A)
CL1
CL2
Crystal
(a)
A.
X1/XCLKIN
X2
External Clock Signal
(Toggling 0-VDD)
NC
(b)
TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the
DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also
advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire
operating range.
Figure 3-10. Recommended Crystal/Clock Connection
Table 3-17. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled.
Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the
X1/XCLKIN pin.
XCLKIN
PLL Bypassed
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is
bypassed. However, the /2 module in the PLL block divides the clock input at the
X1/XCLKIN pin by two before feeding it to the CPU.
PLL Enabled
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the
PLL block now divides the output of the PLL by two before feeding it to the CPU.
XCLKIN/2
(XCLKIN * n) / 2
3.10 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
• Fundamental mode, parallel resonant
• CL (load capacitance) = 12 pF
• CL1 = CL2 = 24 pF
• Cshunt = 6 pF
• ESR range = 25 to 40 Ω
52
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3.11 Watchdog Block
The watchdog block on the F281x and C281x is identical to the one used on the 240x devices. The
watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the
software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset
the watchdog counter. Figure 3-11 shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR[7:0]
OSCCLK
Watchdog
Prescaler
/512
WDCLK
8-Bit
Watchdog
Counter
CLR
Clear Counter
Internal
Pullup
WDKEY[7:0]
Generate
Output Pulse
(512 OSCCLKs)
Bad Key
Watchdog
55 + AA
Key Detector
Good Key
WDRST
WDINT
XRS
Core-reset
Bad
WDCHK
Key
SCSR (WDENINT)
WDCR (WDCHK[2:0])
(A)
WDRST
A.
1
0
1
The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-11. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off the PLL clock or the oscillator clock. The
WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See
Section 3.12, Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence, so
is the WATCHDOG.
Functional Overview
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3.12 Low-Power Modes Block
The low-power modes on the F281x and C281x are similar to the 240x devices. Table 3-18 summarizes
the various modes.
Table 3-18. F281x and C281x Low-Power Modes
LPM[1:0]
OSCCLK
CLKIN
SYSCLKOUT
Normal
X,X
on
on
on
–
on (2)
XRS,
WDINT,
Any Enabled Interrupt,
XNMI,
Debugger (3)
IDLE
(1)
(2)
(3)
EXIT (1)
MODE
0,0
on
on
STANDBY
0,1
on
(watchdog still running)
off
off
XRS,
WDINT,
XINT1,
XNMI,
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
SCIRXDB,
CANRX,
Debugger (3)
HALT
1,X
off
(oscillator and PLL turned off,
watchdog not functional)
off
off
XRS,
XNMI,
Debugger (3)
The Exit column lists which signals or under what conditions the low-power mode will be exited. A low signal, on any of the signals, will
exit the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the
IDLE mode will not be exited and the device will go back into the indicated low-power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is
still functional; while on the 24x/240x, the clock is turned off.
On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode
This mode is exited by any enabled interrupt or an XNMI that is recognized
by the processor. The LPM block performs no tasks during this mode as
long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode
All other signals (including XNMI) will wake the device from STANDBY
mode if selected by the LPMCR1 register. The user will need to select
which signal(s) will wake the device. The selected signal(s) are also
qualified by the OSCCLK before waking the device. The number of
OSCCLKs is specified in the LPMCR0 register.
HALT Mode
Only the XRS and XNMI external signals can wake the device from HALT
mode. The XNMI input to the core has an enable/disable bit. Hence, it is
safe to use the XNMI signal for this function.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included). They
will be in whatever state the code left them when the IDLE instruction was executed.
54
Functional Overview
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SPRS174T – APRIL 2001 – REVISED MAY 2012
Peripherals
The integrated peripherals of the F281x and C281x are described in the following subsections:
• Three 32-bit CPU-Timers
• Two event-manager modules (EVA, EVB)
• Enhanced analog-to-digital converter (ADC) module
• Enhanced controller area network (eCAN) module
• Multichannel buffered serial port (McBSP) module
• Serial communications interface modules (SCI-A, SCI-B)
• Serial peripheral interface (SPI) module
• Digital I/O and shared pin functions
4.1
32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the F281x and C281x devices (CPU-TIMER0/1/2).
Timer 2 is reserved for DSP/BIOS. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.
These timers are different from the general-purpose (GP) timers that are present in the Event Manager
modules (EVA, EVB).
NOTE
If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application.
Reset
Timer Reload
16-Bit Timer Divide-Down
TDDRH:TDDR
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Timer Period
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
Borrow
32-Bit Counter
TIMH:TIM
Borrow
TINT
Figure 4-1. CPU-Timers
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In the F281x and C281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as
shown in Figure 4-2.
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
C28x
CPU
TINT1
INT13
CPU-TIMER 1
XINT13
INT14
A.
B.
CPU-TIMER 2
(Reserved for
DSP/BIOS)
TINT2
The timer registers are connected to the memory bus of the C28x processor.
The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-2. CPU-Timer Interrupts Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the
value in the period register “PRDH:PRD”. The counter register decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x281x
DSP System Control and Interrupts Reference Guide (literature number SPRU078).
56
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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
SIZE (x16)
TIMER0TIM
0x00 0C00
1
CPU-Timer 0, Counter Register
TIMER0TIMH
0x00 0C01
1
CPU-Timer 0, Counter Register High
TIMER0PRD
0x00 0C02
1
CPU-Timer 0, Period Register
TIMER0PRDH
0x00 0C03
1
CPU-Timer 0, Period Register High
TIMER0TCR
0x00 0C04
1
CPU-Timer 0, Control Register
Reserved
0x00 0C05
1
TIMER0TPR
0x00 0C06
1
CPU-Timer 0, Prescale Register
TIMER0TPRH
0x00 0C07
1
CPU-Timer 0, Prescale Register High
TIMER1TIM
0x00 0C08
1
CPU-Timer 1, Counter Register
TIMER1TIMH
0x00 0C09
1
CPU-Timer 1, Counter Register High
TIMER1PRD
0x00 0C0A
1
CPU-Timer 1, Period Register
TIMER1PRDH
0x00 0C0B
1
CPU-Timer 1, Period Register High
TIMER1TCR
0x00 0C0C
1
CPU-Timer 1, Control Register
Reserved
0x00 0C0D
1
TIMER1TPR
0x00 0C0E
1
CPU-Timer 1, Prescale Register
TIMER1TPRH
0x00 0C0F
1
CPU-Timer 1, Prescale Register High
TIMER2TIM
0x00 0C10
1
CPU-Timer 2, Counter Register
TIMER2TIMH
0x00 0C11
1
CPU-Timer 2, Counter Register High
TIMER2PRD
0x00 0C12
1
CPU-Timer 2, Period Register
TIMER2PRDH
0x00 0C13
1
CPU-Timer 2, Period Register High
TIMER2TCR
0x00 0C14
1
CPU-Timer 2, Control Register
Reserved
0x00 0C15
1
TIMER2TPR
0x00 0C16
1
CPU-Timer 2, Prescale Register
TIMER2TPRH
0x00 0C17
1
CPU-Timer 2, Prescale Register High
0x00 0C18 – 0x00 0C3F
40
Reserved
DESCRIPTION
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4.2
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Event Manager Modules (EVA, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units,
and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units
function identically. However, timer/unit names differ for EVA and EVB. Table 4-2 shows the module and
signal names used. Table 4-2 shows the features and functionality available for the event-manager
modules and highlights EVA nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB
starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units,
capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to
function—however, module/signal names would differ. Table 4-3 lists the EVA registers. For more
information, see the TMS320x281x DSP Event Manager (EV) Reference Guide (literature number
SPRU065).
Table 4-2. Module and Signal Names for EVA and EVB
EVENT MANAGER
MODULES
EVA
EVB
MODULE
SIGNAL
MODULE
SIGNAL
GP Timers
GP Timer 1
GP Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
GP Timer 3
GP Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
Compare Units
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Capture Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
QEP Channels
QEP1
QEP2
QEPI1
QEP1
QEP2
QEP3
QEP4
QEPI2
QEP3
QEP4
Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
Compare
C1TRIP
C2TRIP
C3TRIP
Compare
C4TRIP
C5TRIP
C6TRIP
External Clock Inputs
External Trip Inputs
External Trip Inputs
(1)
58
T1CTRIP_PDPINTA (1)
T2CTRIP/EVASOC
T3CTRIP_PDPINTB (1)
T4CTRIP/EVBSOC
In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as
PDPINTB.
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Table 4-3. EVA Registers (1)
NAME
ADDRESS
SIZE (x16)
GPTCONA
0x00 7400
1
GP Timer Control Register A
T1CNT
0x00 7401
1
GP Timer 1 Counter Register
T1CMPR
0x00 7402
1
GP Timer 1 Compare Register
T1PR
0x00 7403
1
GP Timer 1 Period Register
T1CON
0x00 7404
1
GP Timer 1 Control Register
T2CNT
0x00 7405
1
GP Timer 2 Counter Register
T2CMPR
0x00 7406
1
GP Timer 2 Compare Register
T2PR
0x00 7407
1
GP Timer 2 Period Register
T2CON
0x00 7408
1
GP Timer 2 Control Register
EXTCONA (2)
0x00 7409
1
GP Extension Control Register A
COMCONA
0x00 7411
1
Compare Control Register A
ACTRA
0x00 7413
1
Compare Action Control Register A
DBTCONA
0x00 7415
1
Dead-Band Timer Control Register A
CMPR1
0x00 7417
1
Compare Register 1
CMPR2
0x00 7418
1
Compare Register 2
CMPR3
0x00 7419
1
Compare Register 3
CAPCONA
0x00 7420
1
Capture Control Register A
CAPFIFOA
0x00 7422
1
Capture FIFO Status Register A
CAP1FIFO
0x00 7423
1
Two-Level-Deep Capture FIFO Stack 1
CAP2FIFO
0x00 7424
1
Two-Level-Deep Capture FIFO Stack 2
CAP3FIFO
0x00 7425
1
Two-Level-Deep Capture FIFO Stack 3
CAP1FBOT
0x00 7427
1
Bottom Register of Capture FIFO Stack 1
CAP2FBOT
0x00 7428
1
Bottom Register of Capture FIFO Stack 2
CAP3FBOT
0x00 7429
1
Bottom Register of Capture FIFO Stack 3
EVAIMRA
0x00 742C
1
Interrupt Mask Register A
EVAIMRB
0x00 742D
1
Interrupt Mask Register B
EVAIMRC
0x00 742E
1
Interrupt Mask Register C
EVAIFRA
0x00 742F
1
Interrupt Flag Register A
EVAIFRB
0x00 7430
1
Interrupt Flag Register B
EVAIFRC
0x00 7431
1
Interrupt Flag Register C
(1)
(2)
DESCRIPTION
The EV-B register set is identical except the address range is from 0x00 7500 to 0x00 753F. The above registers are mapped to Zone 2.
This space allows only 16-bit accesses. 32-bit accesses produce undefined results.
New register compared to 24x/240x
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GPTCONA[12:4], CAPCONA[8], EXTCONA[0]
EVAENCLK
EVATO ADC (Internal)
T1CTRIP/PDPINTA, T2CTRIP, C1TRIP, C2TRIP, C3TRIP
Control Logic
EVASOC ADC (External)
Output
Logic
Timer 1 Compare
T1PWM_T1CMP
16
T1CON[5,4]
GPTCONA[1,0]
T1CON[1]
TCLKINA
clock
GP Timer 1
HSPCLK
Prescaler
dir
T1CON[10:8]
16
TDIRA
T1CON[15:11,6,3,2]
PWM1
PWM2
PWM3
Full Compare 1
SVPWM
State
Machine
Peripheral Bus
Full Compare 2
Dead-Band
Logic
Output
Logic
PWM4
PWM5
PWM6
Full Compare 3
COMCONA[15:5,2:0]
ACTRA[15:12],
COMCONA[12],
T1CON[13:11]
DBTCONA[15:0]
ACTRA[11:0]
Output
Logic
Timer 2 Compare
T2PWM_T2CMP
16
T2CON[5,4]
T2CON[1]
GPTCONA[3,2]
TCLKINA
GP Timer 2
clock
dir
reset
HSPCLK
Prescaler
QEPCLK
16
T2CON[10:8]
T2CON[15:11,7,6,3,2,0]
CAPCONA[10,9]
QEPDIR
QEP
Logic
16
TDIRA
CAP1_QEP1
CAP2_QEP2
Capture Units
CAP3_QEPI1
Index Qual
CAPCONA[15:12,7:0]
EXTCONA[1:2]
A.
The EVB module is similar to the EVA module.
Figure 4-3. Event Manager A Functional Block Diagram
60
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4.2.1
SPRS174T – APRIL 2001 – REVISED MAY 2012
General-Purpose (GP) Timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
• A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
• A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
• A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
• A 16-bit timer-control register, TxCON, for reads or writes
• Selectable internal or external input clocks
• A programmable prescaler for internal or external clock inputs
• Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
• A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There
are three continuous modes of operations for each GP timer in up- or up/down-counting operations.
Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also
provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM
circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering
of the period and compare registers allows programmable change of the timer (PWM) period and the
compare/PWM pulse width as needed.
4.2.2
Full-Compare Units
There are three full-compare units on each event manager. These compare units use GP timer1 as the
time base and generate six outputs for compare and PWM-waveform generation using programmable
deadband circuit. The state of each of the six outputs is configured independently. The compare registers
of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse
widths as needed.
4.2.3
Programmable Deadband Generator
Deadband generation can be enabled/disabled for each compare unit output individually. The deadbandgenerator circuit produces two outputs (with or without deadband zone) for each compare unit output
signal. The output states of the deadband generator are configurable and changeable as needed by way
of the double-buffered ACTRx register.
4.2.4
PWM Waveform Generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
4.2.5
Double Update PWM Mode
The F281x and C281x Event Manager supports “Double Update PWM Mode.” This mode refers to a PWM
operation mode in which the position of the leading edge and the position of the trailing edge of a PWM
pulse are independently modifiable in each PWM period. To support this mode, the compare register that
determines the position of the edges of a PWM pulse must allow (buffered) compare value update once at
the beginning of a PWM period and another time in the middle of a PWM period. The compare registers in
F281x and C281x Event Managers are all buffered and support three compare value reload/update (value
in buffer becoming active) modes. These modes have earlier been documented as compare value reload
conditions. The reload condition that supports double update PWM mode is reloaded on Underflow
(beginning of PWM period) OR Period (middle of PWM period). Double update PWM mode can be
achieved by using this condition for compare value reload.
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PWM Characteristics
Characteristics of the PWMs are as follows:
• 16-bit registers
• Wide range of programmable deadband for the PWM output pairs
• Change of the PWM carrier frequency for PWM frequency wobbling as needed
• Change of the PWM pulse widths within and after each PWM period as needed
• External-maskable power and drive-protection interrupts
• Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and fourspace vector PWM waveforms
• Minimized CPU overhead using auto-reload of the compare and period registers
• The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after
PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the
COMCONx register.
– PDPINTA pin status is reflected in bit 8 of COMCONA register.
– PDPINTB pin status is reflected in bit 8 of COMCONB register.
• EXTCON register bits provide options to individually trip control for each PWM pair of signals
4.2.7
Capture Unit
The capture unit provides a logging function for different events or transitions. The values of the selected
GP timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are
detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit
consists of three capture circuits.
Capture units include the following features:
• One 16-bit capture control register, CAPCONx (R/W)
• One 16-bit capture FIFO status register, CAPFIFOx
• Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
• Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
• Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All
inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input
must hold at its current level to meet the input qualification circuitry requirements. The input pins
CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]
• User-specified transition (rising edge, falling edge, or both edges) detection
• Three maskable interrupt flags, one for each capture unit
• The capture pins can also be used as general-purpose interrupt pins, if they are not used for the
capture function.
4.2.8
Quadrature-Encoder Pulse (QEP) Circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the onchip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed onchip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or
decremented by the rising and falling edges of the two input signals (four times the frequency of either
input pulse).
With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly,
with EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.
4.2.9
External ADC Start-of-Conversion
EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC
interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.
62
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4.3
SPRS174T – APRIL 2001 – REVISED MAY 2012
Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 4-4. The ADC module
consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module
include:
• 12-bit ADC core with built-in S/H
• Analog input: 0.0 V to 3.0 V (voltages above 3.0 V produce full-scale conversion results)
• Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
• 16-channel, MUXed inputs
• Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion
can be programmed to select any 1 of 16 input channels
• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state
sequencer (that is, two cascaded 8-state sequencers)
• Sixteen result registers (individually addressable) to store conversion values
– The digital value of the input analog voltage is derived by:
Digital Value = 0,
Digital Value = 4096 ´
when input £ 0 V
Input Analog Voltage - ADCLO
3
Digital Value = 4095,
•
•
•
•
•
when 0 V < input < 3 V
when input ³ 3 V
Multiple triggers as sources for the start-of-conversion (SOC) sequence
– S/W – software immediate start
– EVA – Event manager A (multiple event sources within EVA)
– EVB – Event manager B (multiple event sources within EVB)
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
The ADC module in the F281x and C281x has been enhanced to provide flexible interface to event
managers A and B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion
rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent
8-channel modules to service event managers A and B. The two independent 8-channel modules can be
cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers,
there is only one converter in the ADC module. Figure 4-4 shows the block diagram of the F281x and
C281x ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module
has the choice of selecting any one of the respective eight channels available through an analog MUX. In
the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,
once the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to
perform oversampling algorithms. This gives increased resolution over traditional single-sampled
conversion results.
Peripherals
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System
Control Block
SYSCLKOUT
High-Speed
Prescaler
C28x
HSPCLK
ADCENCLK
Analog
MUX
Result Registers
Result Reg 0
ADCINA0
70A8h
Result Reg 1
S/H
ADCINA7
12-Bit
ADC
Module
Result Reg 7
70AFh
Result Reg 8
70B0h
Result Reg 15
70B7h
ADCINB0
S/H
ADCINB7
ADC Control Registers
S/W
EVA
SOC
Sequencer 1
Sequencer 2
SOC
S/W
EVB
ADCSOC
Figure 4-4. Block Diagram of the F281x and C281x ADC Module
To obtain the specified accuracy of the ADC, proper board layout is critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to
minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper
isolation techniques must be used to isolate the ADC module power pins (VDDA1/VDDA2, AVDDREFBG)
from the digital supply. For better accuracy and ESD protection, unused ADC inputs should be connected
to analog ground.
Notes:
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is
controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as
follows:
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register
will still function. This is necessary to make sure all registers and modes go into their default reset
state. The analog module will, however, be in a low-power inactive state. As soon as reset goes high,
then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then
the clocks to the registers will be enabled and the analog module will be enabled. There will be a
certain time delay (ms range) before the ADC is stable and can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC
module is powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the
clock to the CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off
indirectly.
64
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SPRS174T – APRIL 2001 – REVISED MAY 2012
Figure 4-5 shows the ADC pin-biasing for internal reference and Figure 4-6 shows the ADC pin-biasing for
external reference.
ADC 16-Channel Analog Inputs
Test Pin
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCBGREFIN
ADCRESEXT
ADC Reference Positive Output
ADCREFP
ADC Reference Medium Output
ADCREFM
ADC Reference Power
ADC Analog I/O Power
24.9 k /20 k
(B)
(C)
10 μF
(C)
10 μF
ADCREFP and ADCREFM should not
be loaded by external circuitry
VDDA1
Analog 3.3 V
VDDA2
Analog 3.3 V
VSSA1
VSSA2
Analog 3.3 V
AVDDREFBG
AVSSREFBG
VDDAIO
Analog 3.3 V
VSSAIO
VDD1
ADC Digital Power
VSS1
A.
B.
C.
D.
E.
Connect to Analog Ground
(A)
ADC External Current Bias Resistor
ADC Analog Power
Analog input 0-3 V with respect to ADCLO
Analog Ground
1.8 V can use the same 1.8-V (or 1.9-V) supply as
the digital core but separate the two with a
ferrite bead or a filter
Digital Ground
Provide access to this pin in PCB layouts. Intended for test purposes only.
Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz.
TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent ceramic capacitor
External decoupling capacitors are recommended on all power pins.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4-5. ADC Pin Connections With Internal Reference
NOTE
The temperature rating of any recommended component must match the rating of the end
product.
Peripherals
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Test Pin
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCBGREFIN
ADC External Current Bias Resistor
ADCRESEXT
ADC Reference Positive Input
ADCREFP
2V
ADC Reference Medium Input
ADCREFM
1V
ADC 16-Channel Analog Inputs
Analog Input 0-3 V With Respect to ADCLO
Connect to Analog Ground
24.9 k /20 k
(C)
1 μF - 10 μF
1 μF - 10 μF
ADC Analog Power
VDDA1
VDDA2
VSSA1
VSSA2
Analog 3.3 V
Analog 3.3 V
ADC Reference Power
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Analog I/O Power
VDDAIO
VSSAIO
Analog 3.3 V
Analog Ground
VDD1
VSS1
1.8 V can use the same 1.8-V (or 1.9-V)
Digital Ground
supply as the digital core but separate the
two with a ferrite bead or a filter
External decoupling capacitors are recommended on all power pins.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz.
It is recommended that buffered external references be provided with a voltage difference of (ADCREFP –
ADCREFM) = 1 V ± 0.1% or better.
External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of
external reference is critical for overall gain. The voltage ADCREFP – ADCREFM will determine the overall accuracy.
Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the
TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more
information.
ADC Digital Power
A.
B.
C.
D.
(D)
Figure 4-6. ADC Pin Connections With External Reference
66
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SPRS174T – APRIL 2001 – REVISED MAY 2012
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-4.
Table 4-4. ADC Registers (1)
NAME
ADDRESS
SIZE (x16)
ADCTRL1
0x00 7100
1
ADC Control Register 1
ADCTRL2
0x00 7101
1
ADC Control Register 2
ADCMAXCONV
0x00 7102
1
ADC Maximum Conversion Channels Register
ADCCHSELSEQ1
0x00 7103
1
ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2
0x00 7104
1
ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3
0x00 7105
1
ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4
0x00 7106
1
ADC Channel Select Sequencing Control Register 4
ADCASEQSR
0x00 7107
1
ADC Auto-Sequence Status Register
ADCRESULT0
0x00 7108
1
ADC Conversion Result Buffer Register 0
ADCRESULT1
0x00 7109
1
ADC Conversion Result Buffer Register 1
ADCRESULT2
0x00 710A
1
ADC Conversion Result Buffer Register 2
ADCRESULT3
0x00 710B
1
ADC Conversion Result Buffer Register 3
ADCRESULT4
0x00 710C
1
ADC Conversion Result Buffer Register 4
ADCRESULT5
0x00 710D
1
ADC Conversion Result Buffer Register 5
ADCRESULT6
0x00 710E
1
ADC Conversion Result Buffer Register 6
ADCRESULT7
0x00 710F
1
ADC Conversion Result Buffer Register 7
ADCRESULT8
0x00 7110
1
ADC Conversion Result Buffer Register 8
ADCRESULT9
0x00 7111
1
ADC Conversion Result Buffer Register 9
ADCRESULT10
0x00 7112
1
ADC Conversion Result Buffer Register 10
ADCRESULT11
0x00 7113
1
ADC Conversion Result Buffer Register 11
ADCRESULT12
0x00 7114
1
ADC Conversion Result Buffer Register 12
ADCRESULT13
0x00 7115
1
ADC Conversion Result Buffer Register 13
ADCRESULT14
0x00 7116
1
ADC Conversion Result Buffer Register 14
ADCRESULT15
0x00 7117
1
ADC Conversion Result Buffer Register 15
ADCTRL3
0x00 7118
1
ADC Control Register 3
ADCST
0x00 7119
1
ADC Status Register
0x00 711C – 0x00 711F
4
Reserved
(1)
DESCRIPTION
The above registers are Peripheral Frame 2 Registers.
Peripherals
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SPRS174T – APRIL 2001 – REVISED MAY 2012
4.4
www.ti.com
Enhanced Controller Area Network (eCAN) Module
The CAN module has the following features:
• Fully compliant with CAN protocol, version 2.0B
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
• Low-power mode
• Programmable wake-up on bus activity
• Automatic reply to a remote request message
• Automatic retransmission of a frame in case of loss of arbitration or error
• 32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)
• Self-test mode
– Operates in a loopback mode receiving its own message. A “dummy” acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE: For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.
The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for details.
68
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SPRS174T – APRIL 2001 – REVISED MAY 2012
eCAN0INT
eCAN1INT
Controls Address
Data
Enhanced CAN Controller
32
Message Controller
Mailbox RAM
(512 Bytes)
32-Message Mailbox
of 4 x 32-Bit Words
Memory Management
Unit
32
CPU Interface,
Receive Control Unit,
Timer Management Unit
32
eCAN Memory
(512 Bytes)
Registers and
Message Objects Control
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4-7. eCAN Block Diagram and Interface Circuit
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Table 4-5. 3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs
PART
NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
SN65HVD230
3.3 V
Standby
Adjustable
Yes
–
–40°C to 85°C
SN65HVD230Q
3.3 V
Standby
Adjustable
Yes
–
–40°C to 125°C
SN65HVD231
3.3 V
Sleep
Adjustable
Yes
–
–40°C to 85°C
SN65HVD231Q
3.3 V
Sleep
Adjustable
Yes
–
–40°C to 125°C
SN65HVD232
3.3 V
None
None
None
–
–40°C to 85°C
SN65HVD232Q
3.3 V
None
None
None
–
–40°C to 125°C
SN65HVD233
3.3 V
Standby
Adjustable
None
Diagnostic Loopback
–40°C to 125°C
SN65HVD234
3.3 V
Standby
and
Sleep
Adjustable
None
–
–40°C to 125°C
SN65HVD235
3.3 V
Standby
Adjustable
None
Autobaud Loopback
–40°C to 125°C
None
Built-in Isolation
Low Prop Delay
Thermal Shutdown
Failsafe Operation
Dominant Time-out
–55°C to 105°C
ISO1050
70
TA
Peripherals
3–5.5 V
None
None
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SPRS174T – APRIL 2001 – REVISED MAY 2012
eCAN Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN Memory (512 Bytes)
6000h
Received Message Pending - CANRMP
Control and Status Registers
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
Global Acceptance Mask - CANGAM
Message Object Time Stamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Master Control - CANMC
Error and Status - CANES
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
eCAN Memory RAM (512 Bytes)
6100h-6107h
Mailbox 0
6108h-610Fh
Mailbox 1
6110h-6117h
Mailbox 2
6118h-611Fh
Mailbox 3
6120h-6127h
Mailbox 4
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
Mailbox 28
61E8h-61EFh
Mailbox 29
61F0h-61F7h
Mailbox 30
61F8h-61FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
61E8h-61E9h
Message Identifier - MSGID
61EAh-61EBh
Message Control - MSGCTRL
61ECh-61EDh
Message Data Low - MDL
61EEh-61EFh
Message Data High - MDH
Figure 4-8. eCAN Memory Map
NOTE
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO,
and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be
enabled for this.
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The CAN registers listed in Table 4-6 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 4-6. CAN Registers (1)
NAME
ADDRESS
SIZE (x32)
CANME
0x00 6000
1
Mailbox enable
CANMD
0x00 6002
1
Mailbox direction
CANTRS
0x00 6004
1
Transmit request set
CANTRR
0x00 6006
1
Transmit request reset
CANTA
0x00 6008
1
Transmission acknowledge
CANAA
0x00 600A
1
Abort acknowledge
CANRMP
0x00 600C
1
Receive message pending
CANRML
0x00 600E
1
Receive message lost
CANRFP
0x00 6010
1
Remote frame pending
CANGAM
0x00 6012
1
Global acceptance mask
CANMC
0x00 6014
1
Master control
CANBTC
0x00 6016
1
Bit-timing configuration
CANES
0x00 6018
1
Error and status
CANTEC
0x00 601A
1
Transmit error counter
CANREC
0x00 601C
1
Receive error counter
CANGIF0
0x00 601E
1
Global interrupt flag 0
CANGIM
0x00 6020
1
Global interrupt mask
CANGIF1
0x00 6022
1
Global interrupt flag 1
CANMIM
0x00 6024
1
Mailbox interrupt mask
CANMIL
0x00 6026
1
Mailbox interrupt level
CANOPC
0x00 6028
1
Overwrite protection control
CANTIOC
0x00 602A
1
TX I/O control
CANRIOC
0x00 602C
1
RX I/O control
CANTSC
0x00 602E
1
Time stamp counter (Reserved in SCC mode)
CANTOC
0x00 6030
1
Time-out control (Reserved in SCC mode)
CANTOS
0x00 6032
1
Time-out status (Reserved in SCC mode)
(1)
72
DESCRIPTION
These registers are mapped to Peripheral Frame 1.
Peripherals
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4.5
SPRS174T – APRIL 2001 – REVISED MAY 2012
Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
• Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices, except the DMA features
• Full-duplex communication
• Double-buffered data registers which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
• 8-bit data transfers with LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
• Support A-bis mode
• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
• Works with SPI-compatible devices
• Two 16 x 16-level FIFO for Transmit channel
• Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
• T1/E1 framers
• MVIP switching-compatible and ST-BUS-compliant devices including:
– MVIP framers
– H.100 framers
– SCSA framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
– IIS-compliant devices
• McBSP clock rate = CLKG = CLKSRG/(1 + CLKGDIV) , where CLKSRG source could be LSPCLK,
CLKX, or CLKR. (2)
(2)
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is
less than the I/O buffer speed limit—20-MHz maximum.
Peripherals
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Figure 4-9 shows the block diagram of the McBSP module with FIFO, interfaced to the F281x and C281x
version of Peripheral Frame 2.
Peripheral Write Bus
TX FIFO
Interrupt
MXINT
To CPU
TX FIFO _15
TX FIFO _15
TX FIFO _1
TX FIFO _1
TX FIFO _0
TX FIFO _0
TX Interrupt Logic
McBSP Transmit
Interrupt Select Logic
TX FIFO Registers
16
LSPCLK
16
DXR2 Transmit Buffer
McBSP Registers
and
Control Logic
DXR1 Transmit Buffer
16
16
Compand Logic
XSR2
XSR1
RSR2
RSR1
16
16
FSX
CLKX
DX
DR
CLKR
Expand Logic
FSR
McBSP
RBR2 Register
RBR1 Register
16
16
DRR2 Receive Buffer
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
MRINT
To CPU
RX Interrupt Logic
RX FIFO
Interrupt
16
RX FIFO _15
RX FIFO _15
RX FIFO _1
RX FIFO _1
RX FIFO _0
RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
Figure 4-9. McBSP Module With FIFO
74
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SPRS174T – APRIL 2001 – REVISED MAY 2012
Table 4-7 provides a summary of the McBSP registers.
Table 4-7. McBSP Registers
NAME
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
DESCRIPTION
DATA REGISTERS, RECEIVE, TRANSMIT (1)
–
–
–
0x0000
McBSP Receive Buffer Register
–
–
–
0x0000
McBSP Receive Shift Register
–
–
–
0x0000
McBSP Transmit Shift Register
DRR2
00
R
0x0000
McBSP Data Receive Register 2
•
Read First if the word size is greater than 16 bits,
else ignore DRR2
DRR1
01
R
0x0000
McBSP Data Receive Register 1
•
Read Second if the word size is greater than 16 bits,
else read DRR1 only
DXR2
02
W
0x0000
McBSP Data Transmit Register 2
•
Write First if the word size is greater than 16 bits,
else ignore DXR2
DXR1
03
W
0x0000
McBSP Data Transmit Register 1
•
Write Second if the word size is greater than 16 bits,
else write to DXR1 only
SPCR2
04
R/W
0x0000
McBSP Serial Port Control Register 2
SPCR1
05
R/W
0x0000
McBSP Serial Port Control Register 1
RCR2
06
R/W
0x0000
McBSP Receive Control Register 2
RCR1
07
R/W
0x0000
McBSP Receive Control Register 1
XCR2
08
R/W
0x0000
McBSP Transmit Control Register 2
XCR1
09
R/W
0x0000
McBSP Transmit Control Register 1
SRGR2
0A
R/W
0x0000
McBSP Sample Rate Generator Register 2
SRGR1
0B
R/W
0x0000
McBSP Sample Rate Generator Register 1
McBSP CONTROL REGISTERS
MULTICHANNEL CONTROL REGISTERS
(1)
MCR2
0C
R/W
0x0000
McBSP Multichannel Register 2
MCR1
0D
R/W
0x0000
McBSP Multichannel Register 1
RCERA
0E
R/W
0x0000
McBSP Receive Channel Enable Register Partition A
RCERB
0F
R/W
0x0000
McBSP Receive Channel Enable Register Partition B
XCERA
10
R/W
0x0000
McBSP Transmit Channel Enable Register Partition A
XCERB
11
R/W
0x0000
McBSP Transmit Channel Enable Register Partition B
PCR
12
R/W
0x0000
McBSP Pin Control Register
RCERC
13
R/W
0x0000
McBSP Receive Channel Enable Register Partition C
RCERD
14
R/W
0x0000
McBSP Receive Channel Enable Register Partition D
XCERC
15
R/W
0x0000
McBSP Transmit Channel Enable Register Partition C
XCERD
16
R/W
0x0000
McBSP Transmit Channel Enable Register Partition D
RCERE
17
R/W
0x0000
McBSP Receive Channel Enable Register Partition E
RCERF
18
R/W
0x0000
McBSP Receive Channel Enable Register Partition F
XCERE
19
R/W
0x0000
McBSP Transmit Channel Enable Register Partition E
XCERF
1A
R/W
0x0000
McBSP Transmit Channel Enable Register Partition F
RCERG
1B
R/W
0x0000
McBSP Receive Channel Enable Register Partition G
RCERH
1C
R/W
0x0000
McBSP Receive Channel Enable Register Partition H
XCERG
1D
R/W
0x0000
McBSP Transmit Channel Enable Register Partition G
XCERH
1E
R/W
0x0000
McBSP Transmit Channel Enable Register Partition H
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
Peripherals
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Table 4-7. McBSP Registers (continued)
NAME
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
DESCRIPTION
FIFO MODE REGISTERS (applicable only in FIFO mode)
FIFO Data Registers (2)
DRR2
00
R
0x0000
McBSP Data Receive Register 2 – Top of receive FIFO
•
Read First FIFO pointers will not advance
DRR1
01
R
0x0000
McBSP Data Receive Register 1 – Top of receive FIFO
•
Read Second for FIFO pointers to advance
DXR2
02
W
0x0000
McBSP Data Transmit Register 2 – Top of transmit FIFO
•
Write First FIFO pointers will not advance
DXR1
03
W
0x0000
McBSP Data Transmit Register 1 – Top of transmit FIFO
•
Write Second for FIFO pointers to advance
MFFTX
20
R/W
0xA000
McBSP Transmit FIFO Register
MFFRX
21
R/W
0x201F
McBSP Receive FIFO Register
MFFCT
22
R/W
0x0000
McBSP FIFO Control Register
MFFINT
23
R/W
0x0000
McBSP FIFO Interrupt Register
MFFST
24
R/W
0x0000
McBSP FIFO Status Register
FIFO Control Registers
(2)
76
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
Peripherals
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4.6
SPRS174T – APRIL 2001 – REVISED MAY 2012
Serial Communications Interface (SCI) Module
The F281x and C281x devices include two serial communications interface (SCI) modules. The SCI
modules support digital communications between the CPU and other asynchronous peripherals that use
the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and
each has its own separate enable and interrupt bits. Both can be operated independently or
simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds
through a 16-bit baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
• Baud rate programmable to 64K different rates (3)
Baud rate =
=
•
•
•
•
•
•
•
•
•
•
LSPCLK
(BRR + 1) * 8
when BRR ¹ 0
LSPCLK
16
when BRR = 0
Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
Max bit rate = 75 MHz/16 = 4.688 x 106 b/s
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When
a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as
zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 16-level transmit/receive FIFO
(3)
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is
less than the I/O buffer speed limit—20 MHz maximum.
Peripherals
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The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9.
Table 4-8. SCI-A Registers
NAME
ADDRESS
SIZE (x16)
SCICCRA
0x00 7050
1
SCI-A Communications Control Register
SCICTL1A
0x00 7051
1
SCI-A Control Register 1
SCIHBAUDA
0x00 7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x00 7053
1
SCI-A Baud Register, Low Bits
SCICTL2A
0x00 7054
1
SCI-A Control Register 2
SCIRXSTA
0x00 7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x00 7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x00 7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
0x00 7059
1
SCI-A Transmit Data Buffer Register
SCIFFTXA (1)
0x00 705A
1
SCI-A FIFO Transmit Register
(1)
0x00 705B
1
SCI-A FIFO Receive Register
SCIFFCTA (1)
0x00 705C
1
SCI-A FIFO Control Register
SCIPRIA
0x00 705F
1
SCI-A Priority Control Register
SCIFFRXA
(1)
DESCRIPTION
These registers are new registers for the FIFO mode.
Table 4-9. SCI-B Registers (1)
ADDRESS
SIZE (x16)
SCICCRB
NAME
0x00 7750
1
SCI-B Communications Control Register
SCICTL1B
0x00 7751
1
SCI-B Control Register 1
SCIHBAUDB
0x00 7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x00 7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x00 7754
1
SCI-B Control Register 2
SCIRXSTB
0x00 7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x00 7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x00 7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
0x00 7759
1
SCI-B Transmit Data Buffer Register
(2)
0x00 775A
1
SCI-B FIFO Transmit Register
SCIFFRXB (2)
0x00 775B
1
SCI-B FIFO Receive Register
SCIFFCTB (2)
0x00 775C
1
SCI-B FIFO Control Register
SCIPRIB
0x00 775F
1
SCI-B Priority Control Register
SCIFFTXB
(1)
(2)
78
DESCRIPTION
Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
Peripherals
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Figure 4-10 shows the SCI module block diagram.
SCICTL1.1
Frame Format and Mode
SCITXD
TXSHF
Register
Parity
Even/Odd
Enable
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
SCICTL2.7
Transmitter-Data
Buffer Register
TXWAKE
SCICTL1.3
SCICTL2.0
TXINT
TX FIFO _0
TX Interrupt Logic
TX FIFO _1
WUT
-----
TX FIFO _15
TX
FIFO
Interrupts
SCITXBUF.7-0
TX FIFO Registers
SCIFFENA
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
LSPCLK
TX INT ENA
8
1
SCITXD
TXENA
To CPU
SCI TX Interrupt Select Logic
AutoBaud Detect Logic
SCIFFTX.14
SCIRXD
SCIRXD
RXSHF Register
RXWAKE
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
8
Baud Rate
LSbyte
Register
SCICTL1.0
SCICTL2.1
RXRDY
Receive-Data
Buffer Register
SCIRXBUF.7-0
RX/BK INT ENA
SCIRXST.6
BRKDT
8
SCIRXST.5
RX FIFO _15
-----
RX FIFO _1
RX FIFO _0
RX
FIFO
Interrupts
RX Interrupt Logic
To CPU
SCIRXBUF.7-0
RX FIFO Registers
RXFFOVF
SCIRXST.7
SCIRXST.4 - 2
RX Error
FE OE PE
RXINT
SCIFFRX.15
RX Error
RX ERR INT ENA
SCI RX Interrupt Select Logic
SCICTL1.6
Figure 4-10. Serial Communications Interface (SCI) Module Block Diagram
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4.7
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Serial Peripheral Interface (SPI) Module
The F281x and C281x devices include the four-pin serial peripheral interface (SPI) module. The SPI is a
high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to
sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI
is used for communications between the DSP controller and external peripherals or another processor.
Typical applications include external I/O or peripheral expansion through devices such as shift registers,
display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of
the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
• Two operational modes: master and slave
• Baud rate: 125 different programmable rates
Baud rate =
=
•
•
•
•
•
LSPCLK
(SPIBRR + 1)
when SPIBRR ¹ 0
LSPCLK
4
when SPIBRR = 0, 1, 2, 3
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted
such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When
a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as
zeros. Writing to the upper byte has no effect.
Enhanced features:
• 16-level transmit/receive FIFO
• Delayed transmit control
80
Peripherals
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The SPI port operation is configured and controlled by the registers listed in Table 4-10.
Table 4-10. SPI Registers (1)
NAME
ADDRESS
SIZE (x16)
SPICCR
0x00 7040
1
SPI Configuration Control Register
SPICTL
0x00 7041
1
SPI Operation Control Register
SPISTS
0x00 7042
1
SPI Status Register
SPIBRR
0x00 7044
1
SPI Baud Rate Register
SPIRXEMU
0x00 7046
1
SPI Receive Emulation Buffer Register
SPIRXBUF
0x00 7047
1
SPI Serial Input Buffer Register
SPITXBUF
0x00 7048
1
SPI Serial Output Buffer Register
SPIDAT
0x00 7049
1
SPI Serial Data Register
SPIFFTX
0x00 704A
1
SPI FIFO Transmit Register
SPIFFRX
0x00 704B
1
SPI FIFO Receive Register
SPIFFCT
0x00 704C
1
SPI FIFO Control Register
SPIPRI
0x00 704F
1
SPI Priority Control Register
(1)
DESCRIPTION
These registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
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Figure 4-11 is a block diagram of the SPI in slave mode.
SPIFFENA
SPIFFTX.14
Overrun
INT ENA
Receiver
Overrun Flag
RX FIFO Registers
SPIRXBUF
RX FIFO _0
RX FIFO _1
----RX FIFO _15
SPISTS.7
SPICTL.4
RX
FIFO
Interrupt
RX Interrupt
Logic
16
SPIINT/SPIRXINT
SPIFFOVF
FLAG
SPIRXBUF Buffer Register
To CPU
SPIFFRX.15
TX FIFO Registers
SPITXBUF
TX
FIFO
Interrupt
TX Interrupt
Logic
TX FIFO _15
----TX FIFO _1
TX FIFO _0
16
SPI
INT FLAG
SPITXINT
SPI
INT ENA
SPISTS.6
SPICTL.0
16
SPITXBUF Buffer Register
16
M
M
S
SPIDAT Data Register
S
SW1
SPISIMO
M
M
SPIDAT.15 - 0
S
S
SW2
SPISOMI
Talk
SPICTL.1
(A)
SPISTE
State Control
Master/Slave
SPI Char
SPICCR.3 - 0
3
2
1
0
SW3
M
SPI Bit Rate
LSPCLK
SPIBRR.6 - 0
6
A.
5
4
3
SPICTL.2
S
2
1
0
S
Clock
Polarity
SPICCR.6
Clock
Phase
SPICTL.3
SPICLK
M
SPISTE is driven low by the master for a slave device.
Figure 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode)
82
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4.8
SPRS174T – APRIL 2001 – REVISED MAY 2012
GPIO MUX
The GPIO Mux registers are used to select the operation of shared pins on the F281x and C281x devices.
The pins can be individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals
(via the GPxMUX registers). If selected for “Digital I/O”mode, registers are provided to configure the pin
direction (via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the
GPxQUAL) registers). Table 4-11 lists the GPIO Mux Registers.
Table 4-11. GPIO Mux Registers (1) (2) (3)
ADDRESS
SIZE (x16)
GPAMUX
NAME
0x00 70C0
1
GPIO A Mux Control Register
GPADIR
0x00 70C1
1
GPIO A Direction Control Register
GPAQUAL
0x00 70C2
1
GPIO A Input Qualification Control Register
Reserved
0x00 70C3
1
GPBMUX
0x00 70C4
1
GPIO B Mux Control Register
GPBDIR
0x00 70C5
1
GPIO B Direction Control Register
GPBQUAL
0x00 70C6
1
GPIO B Input Qualification Control Register
Reserved
0x00 70C7
1
Reserved
0x00 70C8
1
Reserved
0x00 70C9
1
Reserved
0x00 70CA
1
Reserved
0x00 70CB
1
GPDMUX
0x00 70CC
1
GPIO D Mux Control Register
GPDDIR
0x00 70CD
1
GPIO D Direction Control Register
GPDQUAL
0x00 70CE
1
GPIO D Input Qualification Control Register
Reserved
0x00 70CF
1
GPEMUX
0x00 70D0
1
GPIO E Mux Control Register
GPEDIR
0x00 70D1
1
GPIO E Direction Control Register
GPEQUAL
0x00 70D2
1
GPIO E Input Qualification Control Register
Reserved
0x00 70D3
1
GPFMUX
0x00 70D4
1
GPIO F Mux Control Register
GPFDIR
0x00 70D5
1
GPIO F Direction Control Register
Reserved
0x00 70D6
1
Reserved
0x00 70D7
1
GPGMUX
0x00 70D8
1
GPIO G Mux Control Register
GPGDIR
0x00 70D9
1
GPIO G Direction Control Register
Reserved
0x00 70DA
1
Reserved
0x00 70DB
1
Reserved
0x00 70DC – 0x00 70DF
4
(1)
(2)
(3)
DESCRIPTION
Reserved locations return undefined values and writes are ignored.
Not all inputs support input signal qualification.
These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
Peripherals
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If configured for ”Digital I/O” mode, additional registers are provided for setting individual I/O signals (via
the GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling
individual I/O signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals
(via the GPxDAT registers). Table 4-12 lists the GPIO Data Registers. For more information, see the
TMS320x281x DSP System Control and Interrupts Reference Guide (literature number SPRU078).
Table 4-12. GPIO Data Registers (1) (2)
NAME
ADDRESS
SIZE (x16)
GPADAT
0x00 70E0
1
GPIO A Data Register
GPASET
0x00 70E1
1
GPIO A Set Register
GPACLEAR
0x00 70E2
1
GPIO A Clear Register
GPATOGGLE
0x00 70E3
1
GPIO A Toggle Register
GPBDAT
0x00 70E4
1
GPIO B Data Register
GPBSET
0x00 70E5
1
GPIO B Set Register
GPBCLEAR
0x00 70E6
1
GPIO B Clear Register
GPBTOGGLE
0x00 70E7
1
GPIO B Toggle Register
Reserved
0x00 70E8
1
Reserved
0x00 70E9
1
Reserved
0x00 70EA
1
Reserved
0x00 70EB
1
GPDDAT
0x00 70EC
1
GPIO D Data Register
GPDSET
0x00 70ED
1
GPIO D Set Register
GPDCLEAR
0x00 70EE
1
GPIO D Clear Register
GPDTOGGLE
0x00 70EF
1
GPIO D Toggle Register
GPEDAT
0x00 70F0
1
GPIO E Data Register
GPESET
0x00 70F1
1
GPIO E Set Register
GPECLEAR
0x00 70F2
1
GPIO E Clear Register
GPETOGGLE
0x00 70F3
1
GPIO E Toggle Register
GPFDAT
0x00 70F4
1
GPIO F Data Register
GPFSET
0x00 70F5
1
GPIO F Set Register
GPFCLEAR
0x00 70F6
1
GPIO F Clear Register
GPFTOGGLE
0x00 70F7
1
GPIO F Toggle Register
GPGDAT
0x00 70F8
1
GPIO G Data Register
GPGSET
0x00 70F9
1
GPIO G Set Register
GPGCLEAR
0x00 70FA
1
GPIO G Clear Register
0x00 70FB
1
GPIO G Toggle Register
0x00 70FC – 0x00 70FF
4
GPGTOGGLE
Reserved
(1)
(2)
84
DESCRIPTION
Reserved locations will return undefined values and writes will be ignored.
These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.
Peripherals
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Figure 4-12 shows how the various register bits select the various modes of operation for GPIO function.
GPxDAT/SET/CLEAR/TOGGLE
Register Bit(s)
Digital I/O
GPxQUAL
Register
GPxMUX
Register Bit
0
Peripheral I/O
HighImpedance
Control
GPxDIR
Register Bit
0
1
MUX
1
MUX
SYSCLKOUT
Input Qualification
High-Impedance
Enable (1)
XRS
Internal (Pullup or Pulldown)
PIN
A.
B.
In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only
gives the value written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the
GPxDAT register, provided the corresponding direction bit is zero (input mode).
Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification
sampling period. The sampling window is 6 samples wide and the output is only changed when all samples are the
same (all 0's or all 1's). This feature removes unwanted spikes from the input signal.
Figure 4-12. GPIO/Peripheral Pin Multiplexing
NOTE
The input function of the GPIO pin and the input path to the peripheral are always enabled. It
is the output function of the GPIO pin that is multiplexed with the output path of the primary
(peripheral) function. Since the output buffer of a pin connects back to the input buffer, any
GPIO signal present at the pin will be propagated to the peripheral module as well.
Therefore, when a pin is configured for GPIO operation, the corresponding peripheral
functionality (and interrupt-generating capability) must be disabled. Otherwise, interrupts may
be inadvertently triggered. This is especially critical when the PDPINTA and PDPINTB pins
are used as GPIO pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) will
put PWM pins in a high-impedance state. The CxTRIP and TxCTRIP pins will also put the
corresponding PWM pins in high impedance, if they are driven low (as GPIO pins) and bit
EXTCONx.0 = 1.
Peripherals
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5
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Development Support
Texas Instruments ( TI™) offers an extensive line of development tools for the C28x™ generation of
DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of F281x- and C281x-based applications:
Software Development Tools
• Code Composer Studio™ Integrated Development Environment (IDE)
– C/C++ Compiler
– Code generation tools
– Assembler/Linker
– Cycle Accurate Simulator
• Application algorithms
• Sample applications code
Hardware Development Tools
• 2812 eZdsp
• JTAG-based emulators – SPI515, XDS510PP, XDS510PP Plus, XDS510 USB
• Universal 5-V dc power supply
• Documentation and cables
5.1
Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSP devices and support tools. Each TMS320 DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F2812GHH). Texas Instruments recommends
two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully
qualified production devices/tools (TMS/TMDS).
TMX
Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not
completed quality and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
86
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TMS320C2810, TMS320C2811, TMS320C2812
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SPRS174T – APRIL 2001 – REVISED MAY 2012
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PBK) and temperature range (for example, A). Figure 5-1 provides a legend
for reading the complete device name for any TMS320x281x family member.
TMS 320
F
2810
PBK
PREFIX
TMX = experimental device
TMP = prototype device
TMS = qualified device
A
TEMPERATURE RANGE
A = −40°C to 85°C
S = −40°C to 125°C
Q = −40°C to 125°C (Q100 qualification)
(A)
DEVICE FAMILY
TM
320 = TMS320 DSP Family
TECHNOLOGY
F = Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O)
C = ROM (1.8-V/1.9-V Core/3.3-V I/O)
PACKAGE TYPE
TM
GHH = 179-ball MicroStar BGA
ZHH = 179-ball MicroStar BGA (lead-free)
PGF = 176-pin LQFP
PBK = 128-pin LQFP
DEVICE
2810
2811
2812
A. BGA = Ball Grid Array
LQFP = Low-Profile Quad Flatpack
Figure 5-1. TMS320x281x Device Nomenclature
5.2
Documentation Support
Extensive documentation supports all of the TMS320™ DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications.
Table 5-1 shows the peripheral reference guides appropriate for use with the devices in this data manual.
See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) for more
information on types of peripherals.
Table 5-1. TMS320x281x Peripheral Selection Guide
LIT. NO.
TYPE (1)
2812
2811,
2810
TMS320x281x DSP System Control and Interrupts
SPRU078
–
x
x
TMS320x281x DSP External Interface (XINTF)
SPRU067
0
x
TMS320x281x Enhanced Controller Area Network (eCAN)
SPRU074
0
x
x
TMS320x281x DSP Event Manager (EV)
SPRU065
0
x
x
TMS320x281x DSP Analog-to-Digital Converter (ADC)
SPRU060
0
x
x
TMS320x281x DSP Multichannel Buffered Serial Port (McBSP)
SPRU061
0
x
x
TMS320x281x Serial Communications Interface (SCI)
SPRU051
0
x
x
TMS320x281x Serial Peripheral Interface
SPRU059
0
x
x
TMS320x281x DSP Boot ROM
SPRU095
–
x
x
PERIPHERAL
(1)
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices which do not affect the basic functionality of the module. These device-specific differences are listed in the
peripheral reference guides.
Development Support
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The following documents are available on the TI website (http://www.ti.com):
88
SPRU430
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing
unit (CPU) and the assembly language instructions of the TMS320C28x™ fixed-point digital
signal processors (DSPs). It also describes emulation features available on these DSPs.
SPRU060
TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide describes the
ADC module. The module is a 12-bit pipelined ADC. The analog circuits of this converter,
referred to as the core in this document, include the front-end analog multiplexers (MUXs),
sample-and-hold (S/H) circuits, the conversion core, voltage regulators, and other analog
supporting circuits. Digital circuits, referred to as the wrapper in this document, include
programmable conversion sequencer, result registers, interface to analog circuits, interface
to device peripheral bus, and interface to other on-chip modules.
SPRU095
TMS320x281x DSP Boot ROM Reference Guide describes the purpose and features of the
bootloader (factory-programmed boot-loading software). It also describes other contents of
the device on-chip boot ROM and identifies where all of the information is located within that
memory.
SPRU065
TMS320x281x DSP Event Manager (EV) Reference Guide describes the EV modules that
provide a broad range of functions and features that are particularly useful in motion control
and motor control applications. The EV modules include general-purpose (GP) timers, fullcompare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits.
SPRU067
TMS320x281x DSP External Interface (XINTF) Reference Guide describes the external
interface (XINTF) of the 281x digital signal processors (DSPs).
SPRU061
TMS320x281x DSP Multichannel Buffered Serial Port (McBSP) Reference Guide
describes the McBSP available on the 281x devices. The McBSPs allow direct interface
between a DSP and other devices in a system.
SPRU078
TMS320x281x DSP System Control and Interrupts Reference Guide describes the
various interrupts and system control features of the 281x digital signal processors (DSPs).
SPRU074
TMS320x281x Enhanced Controller Area Network (eCAN) Reference Guide describes
the eCAN that uses established protocol to communicate serially with other controllers in
electrically noisy environments. With 32 fully configurable mailboxes and time-stamping
feature, the eCAN module provides a versatile and robust serial communication interface.
The eCAN module implemented in the C28x DSP is compatible with the CAN 2.0B standard
(active).
SPRU566
TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference
guides of the 28x digital signal processors (DSPs).
SPRU051
TMS320x281x Serial Communications Interface (SCI) Reference Guide describes the
SCI that is a two-wire asynchronous serial port, commonly known as a UART. The SCI
modules support digital communications between the CPU and other asynchronous
peripherals that use the standard non-return-to-zero (NRZ) format.
SPRU059
TMS320x281x Serial Peripheral Interface Reference Guide describes the SPI—a highspeed synchronous serial input/output (I/O) port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI is used for communications between the DSP
controller and external peripherals or another controller.
Development Support
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SPRS174T – APRIL 2001 – REVISED MAY 2012
SPRA550
3.3V DSP for Digital Motor Control Application Report. The application report first
describes a scenario of a 3.3-V-only motor controller indicating that for most applications, no
significant issue of interfacing between 3.3 V and 5 V exists. Cost-effective 3.3-V/5-V
interfacing techniques are then discussed for the situations where such interfacing is
needed. On-chip 3.3-V analog-to-digital converter (ADC) versus 5-V ADC is also discussed.
Guidelines for component layout and printed circuit board (PCB) design that can reduce
system noise and EMI effects are summarized in the last section.
SPRU608
TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000™ IDE, that simulates the
instruction set of the C28x core.
SPRU625
TMS320C28x DSP/BIOS 5.x Application Programming Interface (API) Reference Guide
describes development using DSP/BIOS™.
SPRU513
TMS320C28x Assembly Language Tools v5.0 User’s Guide describes the assembly
language tools (assembler and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic debugging directives
for the TMS320C28x™ device.
SPRU514
TMS320C28x Optimizing C/C++ Compiler v5.0 User’s Guide describes the
TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code
and produces TMS320™ DSP assembly language source code for the TMS320C28x device.
SPRA876
Programming Examples for the TMS320F281x eCAN Application Report contains
several programming examples to illustrate how the eCAN module is set up for different
modes of operation. The objective is to help you come up to speed quickly in programming
the eCAN. All programs have been extensively commented to aid easy understanding. The
CANalyzer tool from Vector CANtech, Inc. was used to monitor and control the bus
operation. All projects and CANalyzer configuration files are included in the spra876.zip file.
SPRA989
F2810, F2811, and F2812 ADC Calibration Application Report describes a method for
improving the absolute accuracy of the 12-bit analog-to-digital converter (ADC) found on the
F2810/F2811/F2812 devices. Due to inherent gain and offset errors, the absolute accuracy
of the ADC is impacted. The methods described in this application note can improve the
absolute accuracy of the ADC to achieve levels better than 0.5%. This application note is
accompanied by an example program (ADCcalibration, spra989.zip) that executes from RAM
on the F2812 eZdsp.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320™ DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320™ DSP customers on product information.
Updated information on the TMS320™ DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810,
TMS320C2811,TMS320C2812 Digital Signal Processors Data Manual (literature number SPRS174), click
on the Submit Documentation Feedback link at the bottom of the page. For questions and support, contact
the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
5.3
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
Development Support
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TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
90
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TMS320C2810, TMS320C2811, TMS320C2812
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6
SPRS174T – APRIL 2001 – REVISED MAY 2012
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320F281x and TMS320C281x DSPs.
Absolute Maximum Ratings (1)
6.1
Supply voltage range (VDDIO, VDD3VFL, VDDA1, VDDA2, VDDAIO, and AVDDREFBG)
–0.3 V to 4.6 V
Supply voltage range (VDD, VDD1)
–0.5 V to 2.5 V
Input voltage range, VIN
–0.3 V to 4.6 V
Output voltage range, VO
–0.3 V to 4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VDDIO) (2)
±20 mA
Output clamp current, IOK (VO < 0 or VO > VDDIO)
Operating ambient temperature ranges, TA
±20 mA
(3)
–40°C to 85°C
S version (GHH, ZHH, PGF, PBK) (3)
–40°C to 125°C
Q version (PGF, PBK) (3)
–40°C to 125°C
A version (GHH, ZHH, PGF, PBK)
Junction temperature range, TJ
–40°C to 150°C
Storage temperature range, Tstg (3)
–65°C to 150°C
(1)
(2)
(3)
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges. Stresses beyond those
listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated under Section 6.2, Recommended Operating Conditions,
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are
with respect to VSS.
Continuous clamp current per pin is ±2 mA
Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the IC Package Thermal Metrics Application Report (literature number SPRA953) and the Reliability
Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).
Recommended Operating Conditions (1)
6.2
VDDIO
MIN
NOM
MAX
UNIT
3.14
3.3
3.47
V
1.8 V (135 MHz)
1.71
1.8
1.89
1.9 V (150 MHz)
1.81
1.9
2
3.14
3.3
3.47
V
3.14
3.3
3.47
V
Device supply voltage, I/O
VDD, VDD1
Device supply voltage, CPU
VSS
Supply ground
VDDA1, VDDA2,
AVDDREFBG,
VDDAIO
ADC supply voltage
VDD3VFL
Flash programming supply voltage
fSYSCLKOUT
Device clock frequency
(system clock)
VDD = 1.9 V ± 5%
2
150
VDD = 1.8 V ± 5%
2
135
High-level input voltage
All inputs except X1/XCLKIN
2
VDDIO
0.7VDD
VDD
VIH
0
X1/XCLKIN (@ 50 µA max)
VIL
Low-level input voltage
All inputs except X1/XCLKIN
IOH
IOL
TA
(1)
(2)
V
0.8
X1/XCLKIN (@ 50 µA max)
MHz
V
V
0.3VDD
High-level output source current,
VOH = 2.4 V
All I/Os except Group 2
–4
Group 2 (2)
–8
Low-level output sink current,
VOL = VOL MAX
All I/Os except Group 2
4
Group 2 (2)
8
Ambient temperature
V
A version
–40
85
S version
–40
125
Q version
–40
125
mA
mA
°C
See Section 6.8 for power sequencing of VDDIO, VDDAIO, VDD, VDDA1/VDDA2/AVDDREFBG, and VDD3VFL.
Group 2 pins are as follows: XINTF pins, T1CTRIP_PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.
Electrical Specifications
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6.3
www.ti.com
Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VOL
Low-level output voltage
IOL = IOL MAX
IIL (1)
Input current
(low level)
With pullup
VDDIO = 3.3 V, VIN = 0 V
With pulldown
VDDIO = 3.3 V, VIN = 0 V
MIN
IOH = IOH MAX
IOH = 50 µA
IIL
(2)
IIH
Input current
(low level)
Input current
(high level)
With pullup
VDDIO = 3.3 V,
VIN = 0 V
TYP
MAX
2.4
UNIT
V
VDDIO – 0.2
–80
–140
0.4
V
–190
µA
±2
(3)
All I/Os (including
XRS) except EVB
–80
–140
–190
GPIOB/EVB
–13
–25
–35
With pulldown
VDDIO = 3.3 V, VIN = 0 V
With pullup
VDDIO = 3.3 V, VIN = VDD
With pulldown (4)
VDDIO = 3.3 V, VIN = VDD
µA
±2
±2
28
50
IOZ
Leakage current (for pins without internal
PU/PD), high-impedance state (off-state)
Ci
Input capacitance
2
pF
Co
Output capacitance
3
pF
(1)
(2)
(3)
(4)
92
VO = VDDIO or 0 V
µA
80
±2
µA
Applicable to C281x devices
Applicable to F281x devices
The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5.
The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST.
Electrical Specifications
Copyright © 2001–2012, Texas Instruments Incorporated
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TMS320C2810, TMS320C2811, TMS320C2812
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6.4
SPRS174T – APRIL 2001 – REVISED MAY 2012
Current Consumption
Table 6-1. TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating
Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
MODE
TEST CONDITIONS
Operational
All peripheral clocks are enabled. All
PWM pins are toggled at 100 kHz.
Data is continuously transmitted out of
the SCIA, SCIB, and CAN ports. The
hardware multiplier is exercised. Code
is running out of flash with 5 waitstates.
IDLE
•
•
•
Flash is powered down
XCLKOUT is turned off
All peripheral clocks are on,
except ADC
STANDBY
•
•
•
•
•
•
HALT
•
(1)
(2)
(3)
(4)
IDDIO (1)
IDD
TYP
MAX
(3)
TYP
MAX
IDDA (2)
IDD3VFL
(3)
TYP
MAX
(3)
TYP
MAX (3)
195 mA (4)
230 mA
15 mA
30 mA
40 mA
45 mA
40 mA
50 mA
125 mA
150 mA
5 mA
10 mA
2 µA
4 µA
1 µA
20 µA
Flash is powered down
Peripheral clocks are turned off
Pins without an internal PU/PD are
tied high/low
5 mA
10 mA
5 µA
20 µA
2 µA
4 µA
1 µA
20 µA
Flash is powered down
Peripheral clocks are turned off
Pins without an internal PU/PD are
tied high/low
Input clock is disabled
70 µA
5 µA
20 µA
2 µA
4 µA
1 µA
20 µA
IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA includes current into VDDA1, VDDA2, AVDDREFBG, and VDDAIO pins.
MAX numbers are at 125°C, and MAX voltage (VDD = 1.89 V; VDDIO, VDD3VFL, VDDA = 3.47 V).
IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1.
NOTE
HALT and STANDBY modes cannot be used when the PLL is disabled.
Electrical Specifications
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TMS320C2810, TMS320C2811, TMS320C2812
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Table 6-2. TMS320C281x Current Consumption by Power-Supply Pins Over Recommended Operating
Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
MODE
TEST CONDITIONS
Operational
All peripheral clocks are enabled. All PWM
pins are toggled at 100 kHz.
Data is continuously transmitted out of the
SCIA, SCIB, and CAN ports. The hardware
multiplier is exercised. Code is running out of
ROM with 5 wait-states.
IDLE
•
•
XCLKOUT is turned off
All peripheral clocks are on, except ADC
STANDBY
•
•
HALT
•
•
•
(1)
(2)
(3)
(4)
94
IDDIO (1)
IDD
TYP
MAX
(3)
TYP
MAX
IDDA (2)
(3)
TYP
MAX (3)
210 mA (4)
260 mA
20 mA
30 mA
40 mA
50 mA
140 mA
165 mA
20 mA
30 mA
5 µA
10 µA
Peripheral clocks are turned off
Pins without an internal PU/PD are tied
high/low
5 mA
10 mA
5 µA
20 µA
5 µA
10 µA
Peripheral clocks are turned off
Pins without an internal PU/PD are tied
high/low
Input clock is disabled
70 µA
5 µA
10 µA
1 µA
IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA includes current into VDDA1, VDDA2, AVDDREFBG, and VDDAIO pins.
MAX numbers are at 125°C, and MAX voltage (VDD = 1.89 V; VDDIO, VDD3VFL, VDDA = 3.47 V).
IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1.
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6.5
SPRS174T – APRIL 2001 – REVISED MAY 2012
Current Consumption Graphs
250
Current (mA)
200
150
100
50
0
0
20
40
60
80
100
120
140
160
SYSCLKOUT (MHz)
IDD
A.
B.
C.
D.
IDD3VFL
IDDIO
Total 3.3-V current
IDDA
Test conditions are as defined in Table 6-1 for operational currents.
IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn
by VDD1.
IDDA represents the current drawn by VDDA1 and VDDA2 rails.
Total 3.3-V current is the sum of IDDIO, IDD3VFL, and IDDA. It includes a small amount of current (<1 mA) drawn
by VDDAIO.
Figure 6-1. F2812/F2811/F2810 Typical Current Consumption Over Frequency
700
600
Power (mW)
500
400
300
200
100
0
0
20
40
60
80
100
120
140
160
SYSCLKOUT (MHz)
Total Power
Figure 6-2. F2812/F2811/F2810 Typical Power Consumption Over Frequency
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250
Current (mA)
200
150
100
50
0
0
20
40
60
80
100
120
140
160
SYSCLKOUT (MHz)
IDD
A.
B.
C.
D.
IDDIO
IDDA
Total 3.3-V current
Test conditions are as defined in Table 6-2 for operational currents.
IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn
by VDD1.
IDDA represents the current drawn by VDDA1 and VDDA2 rails.
Total 3.3-V current is the sum of IDDIO and IDDA. It includes a small amount of current (<1 mA) drawn by VDDAIO.
Figure 6-3. C2812/C2811/C2810 Typical Current Consumption Over Frequency
600
500
Power (mW)
400
300
200
100
0
0
20
40
60
80
100
120
140
160
SYSCLKOUT (MHz)
Total Power
Figure 6-4. C2812/C2811/C2810 Typical Power Consumption Over Frequency
96
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6.6
SPRS174T – APRIL 2001 – REVISED MAY 2012
Reducing Current Consumption
28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a
given application. Table 6-3 indicates the typical reduction in current consumption achieved by turning off
the clocks to various peripherals.
Table 6-3. Typical Current Consumption by Various Peripherals (at 150 MHz) (1)
(1)
(2)
6.7
PERIPHERAL MODULE
IDD CURRENT REDUCTION (mA)
eCAN
12
EVA
6
EVB
6
ADC
8 (2)
SCI
4
SPI
5
McBSP
13
All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible
only after the peripheral clocks are turned on.
This number represents the current drawn by the digital portion of the ADC module. Turning off the
clock to the ADC module results in the elimination of the current drawn by the analog portion of the
ADC (IDDA) as well.
Emulator Connection Without Signal Buffering for the DSP
Figure 6-5 shows the connection between the DSP and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-5 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.
6 inches or less
VDDIO
EMU0
EMU1
TRST
TMS
TDI
TDO
TCK
VDDIO
13
14
2
1
3
7
11
9
EMU0
PD
5
EMU1
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
4
6
8
10
12
TCK_RET
DSP
JTAG Header
Figure 6-5. Emulator Connection Without Signal Buffering for the DSP
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6.8
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Power Sequencing Requirements
TMS320F2812/F2811/F2810 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the
CPU, Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during power up,
there are some requirements to be met while powering up/powering down the device. The current F2812
silicon reference schematics (Spectrum Digital Incorporated eZdsp board) suggests two options for the
power sequencing circuit.
Power sequencing is not needed for C281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can ramp
together. C281x can also be used on boards that have F281x power sequencing implemented; however, if
the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail reaches at least
1 V.
• Option 1:
In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1
(1.8 V or 1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC
(VDDA1/VDDA2/AVDDREFBG) modules are ramped up. While option 1 is still valid, TI has simplified the
requirement. Option 2 is the recommended approach.
• Option 2:
Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then
ramp 1.8 V (or 1.9 V) (VDD/VDD1) supply pins.
1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset
signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the
modules inside the device. See Figure 6-11 for power-on reset timing.
• Power-Down Sequencing:
During power-down, the device reset should be asserted low (8 µs, minimum) before the VDD supply
reaches 1.5 V. This will help to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies
ramping down. It is recommended that the device reset control from “Low-Dropout (LDO)” regulators or
voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing
(with the aid of additional external components) may be used to meet the power sequencing
requirement. See www.spectrumdigital.com for F2812 eZdsp™ schematics and updates.
Table 6-4. Recommended “Low-Dropout Regulators”
SUPPLIER
PART NUMBER
Texas Instruments
TPS75005
DESCRIPTION
Dual 500-mA low-dropout regulator (LDO) with sequencing for
C2000 (3 Voltage Rail Monitors)
NOTE
The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V.
98
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(C)
2.5 V
VDD_3.3V
(E)
3.3 V
3.3 V
1.8 V
(or 1.9 V)
1.8 V
(or 1.9 V)
(A)
<10 ms
VDD_1.8V
1.5 V
(B)
>1 ms
(D)
>8 μs
(F)
XRS
XRS
Power-Up Sequence
A.
B.
C.
D.
E.
F.
G.
H.
Power-Down Sequence
VDD_3.3V – VDDIO, VDD3VFL, VDDAIO, VDDA1, VDDA2, AVDDREFBG
VDD_1.8V – VDD, VDD1
1.8-V (or 1.9-V) supply should ramp after the 3.3-V supply reaches at least 2.5 V.
Reset (XRS) should remain low until supplies and clocks are stable. See Figure 6-11, Power-on Reset in
Microcomputer Mode (XMP/MC = 0), for minimum requirements.
Voltage supervisor or LDO reset control will trip reset (XRS) first when the 3.3-V supply is off regulation. Typically, this
occurs a few milliseconds before the 1.8-V (or 1.9-V) supply reaches 1.5 V.
Keeping reset low (XRS) at least 8 µs prior to the 1.8-V (or 1.9-V) supply reaching 1.5 V will keep the flash module in
complete reset before the supplies ramp down.
Since the state of GPIO pins is undefined until the 1.8-V (or 1.9-V) supply reaches at least 1 V, this supply should be
ramped as quickly as possible (after the 3.3-V supply reaches at least 2.5 V).
Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up.
Figure 6-6. F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence – Option 2
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6.9
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Signal Transition Levels
Note that some of the signals use different reference voltages, see the recommended operating conditions
table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of
0.4 V.
Figure 6-7 shows output levels.
2.4 V (VOH)
0.4 V (VOL)
Figure 6-7. Output Levels
Output transition times are specified as follows:
• For a high-to-low transition, the level at which the output is said to be no longer high is below VOH(MIN)
and the level at which the output is said to be low is VOL(MAX) and lower.
• For a low-to-high transition, the level at which the output is said to be no longer low is above VOL(MAX)
and the level at which the output is said to be high is VOH(MIN) and higher.
Figure 6-8 shows the input levels.
2.0 V (VIH)
0.8 V (VIL)
Figure 6-8. Input Levels
Input transition times are specified as follows:
• For a high-to-low transition on an input signal, the level at which the input is said to be no longer high
is below VIH(MIN) and the level at which the input is said to be low is VIL(MAX) and lower.
• For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
above VIL(MAX) and the level at which the input is said to be high is VIH(MIN) and higher.
NOTE
See the individual timing diagrams for levels used for testing timing parameters.
100
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SPRS174T – APRIL 2001 – REVISED MAY 2012
6.10 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
f
fall time
X
Unknown, changing, or don't care level
h
hold time
Z
High impedance
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
6.11 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.12 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
42 W
Data Sheet Timing Reference Point
3.5 nH
Transmission Line
(A)
Output
Under
Test
Z0 = 50 W
4.0 pF
A.
Device Pin
1.85 pF
(A)
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
Figure 6-9. 3.3-V Test Load Circuit
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6.13 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the F281x and C281x DSPs. Table 6-5 lists the cycle times of various clocks.
Table 6-5. TMS320F281x and TMS320C281x Clock Table and Nomenclature
MIN
On chip oscillator clock
Frequency
SYSCLKOUT
XCLKOUT
tc(SCO), Cycle time
Frequency
tc(XCO), Cycle time
Frequency
tc(HCO), Cycle time
HSPCLK
tc(LCO), Cycle time
tc(ADCCLK), Cycle time (2)
ns
35
MHz
6.67
250
ns
MHz
4
150
6.67
500
ns
2
150
MHz
6.67
2000
ns
0.5
150
MHz
6.67
13.3 (1)
75
13.3
(1)
tc(CKG), Cycle time
37.5 (1)
tc(XTIM), Cycle time
150
MHz
75
MHz
ns
40
ns
25
MHz
20
MHz
20
MHz
50
ns
50
Frequency
XTIMCLK
ns
26.6 (1)
Frequency
McBSP
UNIT
20
Frequency
tc(SPC), Cycle time
SPI clock
MAX
50
Frequency
ADC clock
NOM
28.6
Frequency
LSPCLK
102
Frequency
tc(CI), Cycle time
XCLKIN
(1)
(2)
tc(OSC), Cycle time
ns
6.67
Frequency
ns
150
MHz
This is the default reset value if SYSCLKOUT = 150 MHz.
The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be
SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
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SPRS174T – APRIL 2001 – REVISED MAY 2012
6.14 Clock Requirements and Characteristics
6.14.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 6-6. Input Clock Frequency
PARAMETER
fx
Input clock frequency
MIN
MAX
Resonator
20
Crystal
20
35
Without PLL
4
150
With PLL
5
100
XCLKIN
fl
TYP
Limp mode clock frequency
UNIT
35
2
MHz
MHz
Table 6-7. XCLKIN Timing Requirements – PLL Bypassed or Enabled
NO.
MIN
MAX
UNIT
6.67
250
ns
6
ns
6
ns
60
%
C8
tc(CI)
Cycle time, XCLKIN
C9
tf(CI)
Fall time, XCLKIN
C10
tr(CI)
Rise time, XCLKIN
C11
tw(CIL)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
40
C12
tw(CIH)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
40
60
%
MIN
MAX
UNIT
6.67
250
ns
Up to 30 MHz
6
ns
30 MHz to 150 MHz
2
Up to 30 MHz
6
Table 6-8. XCLKIN Timing Requirements – PLL Disabled
NO.
C8
tc(CI)
Cycle time, XCLKIN
C9
tf(CI)
Fall time, XCLKIN
C10
tr(CI)
Rise time, XCLKIN
C11
tw(CIL)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
30 MHz to 150 MHz
C12
tw(CIH)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
ns
2
XCLKIN ≤ 120 MHz
40
60
120 < XCLKIN ≤ 150 MHz
45
55
XCLKIN ≤ 120 MHz
40
60
120 < XCLKIN ≤ 150 MHz
45
55
%
%
Table 6-9. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled.
Clock input to the CPU (CLKIN) is directly derived from the clock signal present at
the X1/XCLKIN pin.
XCLKIN
PLL Bypassed
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is
bypassed. However, the /2 module in the PLL block divides the clock input at the
X1/XCLKIN pin by two before feeding it to the CPU.
XCLKIN/2
PLL Enabled
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the
PLL block now divides the output of the PLL by two before feeding it to the CPU.
(XCLKIN * n) / 2
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6.14.2 Output Clock Characteristics
Table 6-10. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
NO.
PARAMETER
MIN
C1
tc(XCO)
Cycle time, XCLKOUT
C3
tf(XCO)
Fall time, XCLKOUT
2
C4
tr(XCO)
Rise time, XCLKOUT
2
C5
tw(XCOL)
Pulse duration, XCLKOUT low
H–2
C6
tw(XCOH)
Pulse duration, XCLKOUT high
H–2
C7
tp
PLL lock time (4)
(1)
(2)
(3)
(4)
6.67
TYP
MAX
UNIT
(3)
ns
ns
ns
H+2
ns
H+2
ns
131072tc(CI)
ns
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
The PLL must be used for maximum frequency operation.
This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
C10
C8
XCLKIN
C9
(A)
C6
C3
C1
C4
XCLKOUT
A.
C5
(A)(B)
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in
Figure 6-10 is intended to illustrate the timing parameters only and may differ based on configuration.
XCLKOUT configured to reflect SYSCLKOUT.
B.
Figure 6-10. Clock Timing
6.15 Reset Timing
Table 6-11. Reset (XRS) Timing Requirements (1)
MIN
NOM
MAX
UNIT
tw(RSL1)
Pulse duration, stable XCLKIN to XRS high
tw(RSL2)
Pulse duration, XRS low
tw(WDRS)
Pulse duration, reset pulse generated by
watchdog
512tc(CI)
cycles
td(EX)
Delay time, address/data valid after XRS
high
32tc(CI)
cycles
tOSCST (2)
Oscillator start-up time
tsu(XPLLDIS)
Setup time for XPLLDIS pin
16tc(CI)
cycles
th(XPLLDIS)
Hold time for XPLLDIS pin
16tc(CI)
cycles
th(XMP/MC)
Hold time for XMP/MC pin
16tc(CI)
cycles
(3)
cycles
th(boot-mode)
(1)
(2)
(3)
104
Hold time for boot-mode pins
Warm reset
8tc(CI)
cycles
8tc(CI)
cycles
1
2520tc(CI)
10
ms
If external oscillator/clock source are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.
Dependent on crystal/resonator and board design.
The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the
TMS320x281x DSP Boot ROM Reference Guide (literature number SPRU095) and the TMS320x281x DSP System Control and
Interrupts Reference Guide (literature number SPRU078) for further information.
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VDDIO, VDD3VFL
(A)
2.5 V
VDDAn , VDDAIO
(3.3 V)
VDD, VDD1
[1.8 V (or 1.9 V)]
0.3 V
XCLKIN
X1
XCLKOUT
XCLKIN/8
(B)
User-Code Dependent
tOSCST
tw(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/
Data/
Control
td(EX)
User-Code Execution Phase
User-Code Dependent
tsu(XPLLDIS)
th(XPLLDIS)
XPLLDIS Sampling
XF/XPLLDIS
(Don’t Care)
GPIOF14
th(XMP/MC)
XMP/MC
(Don’t Care)
(C)
th(boot-mode)
Boot-Mode Pins
(D)
User-Code Dependent
GPIO Pins as Input
Peripheral/GPIO Function
Based on Boot Code
Boot-ROM Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A.
B.
C.
D.
VDDAn – VDDA1/VDDA2 and AVDDREFBG
Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at
XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.
After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and
then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN
cycles from boot ROM execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is
based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or
without PLL enabled.
The state of the GPIO pins is undefined (that is, they could be input or output) until the 1.8-V (or 1.9-V) supply
reaches at least 1 V and 3.3-V supply reaches 2.5 V.
Figure 6-11. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note D)
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VDDIO, VDD3VFL
VDDAn, VDDAIO
(3.3 V)
VDD, VDD1
[1.8 V (or 1.9 V)]
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2.5 V
0.3 V
XCLKIN
X1
tOSCST
XCLKOUT
XCLKIN/8
(A)
User-Code Dependent
tw(RSL)
XRS
td(EX)
Address/
Data/
Control
Address/Data/Control Valid Execution
Begins From External Boot Address 0x3FFFC0
(Don’t Care)
XPLLDIS Sampling
GPIOF14/XF (User-Code Dependent)
(Don’t Care)
XF/XPLLDIS
th(XPLLDIS)
tsu(XPLLDIS)
XMP/MC
th(XMP/MC)
User-Code Dependent
I/O Pins
(B)
A.
B.
(Don’t Care)
Input Configuration (State Depends on Internal PU/PD)
Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at
XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.
The state of the GPIO pins is undefined (that is, they could be input or output) until the 1.8-V (or 1.9-V) supply
reaches at least 1 V and 3.3-V supply reaches 2.5 V.
Figure 6-12. Power-on Reset in Microprocessor Mode (XMP/MC = 1)
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XCLKIN
X1
XCLKOUT
XCLKIN/8
(XCLKIN * 5)
User-Code Dependent
tw(RSL2)
XRS
Address/
Data/
Control
XF/XPLLDIS
XMP/MC
(Don’t Care)
User-Code Execution
tsu(XPLLDIS)
th(XPLLDIS)
(Don’t Care)
GPIOF14/XF
XPLLDIS Sampling
th(XMP/MC)
(Don’t Care)
Boot-ROM Execution Starts
Boot-Mode Pins
User-Code Execution Phase
td(EX)
Peripheral/GPIO Function
GPIO Pins as Input
GPIOF14
User-Code Dependent
(Don’t Care)
th(boot-mode)
(A)
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A.
After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and
then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN
cycles from boot ROM execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is
based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or
without PLL enabled.
Figure 6-13. Warm Reset in Microcomputer Mode
X1/XCLKIN
Write to PLLCR
SYSCLKOUT
XCLKIN * 2
XCLKIN/2
XCLKIN * 4
(Current
CPU Frequency)
[CPU Frequency While PLL is Stabilizing
With the Desired Frequency.
This Period (PLL Lock-up Time, tp)
is 131 072 XCLKIN Cycles Long.]
(Changed CPU Frequency)
Figure 6-14. Effect of Writing Into PLLCR Register
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6.16 Low-Power Mode Wakeup Timing
Table 6-12. IDLE Mode Timing Requirements
MIN
tw(WAKE-INT)
(1)
Pulse duration, external wake-up signal
Without input qualifier
NOM
MAX
2tc(SCO)
cycles
1tc(SCO) + IQT (1)
With input qualifier
UNIT
Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
Table 6-13. IDLE Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, external wake signal to program execution resume (1)
•
td(WAKE-IDLE)
•
•
Wake-up from Flash
– Flash module in active state
Without input qualifier
Wake-up from Flash
– Flash module in sleep state
Without input qualifier
Wake-up from SARAM
Without input qualifier
8tc(SCO)
8tc(SCO) + IQT (2)
With input qualifier
1050tc(SCO)
1050tc(SCO) + IQT (2)
With input qualifier
8tc(SCO)
8tc(SCO) + IQT (2)
With input qualifier
(1)
(2)
cycles
cycles
cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up) signal involves additional latency.
Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
td(WAKE-IDLE)
A0-A15
XCLKOUT
(A)
tw(WAKE-INT)
WAKE INT
A.
B.
(B)
XCLKOUT = SYSCLKOUT
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-15. IDLE Entry and Exit Timing
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Table 6-14. STANDBY Mode Timing Requirements
MIN
tw(WAKE-INT)
(1)
Pulse duration, external wake-up
signal
Without input qualifier
With input qualifier
NOM
MAX
12tc(CI)
UNIT
cycles
(2 + QUALSTDBY) * tc(CI) (1)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 6-15. STANDBY Mode Switching Characteristics
PARAMETER
td(IDLE-XCOH)
TEST CONDITIONS
Delay time, IDLE instruction
executed to XCLKOUT high
MIN
32tc(SCO)
TYP
MAX
UNIT
45tc(SCO)
cycles
Delay time, external wake signal to program execution
resume (1)
•
td(WAKE-STBY)
•
•
Wake-up from Flash
– Flash module in active
state
Without input qualifier
Wake-up from Flash
– Flash module in sleep
state
Without input qualifier
Wake-up from SARAM
Without input qualifier
With input qualifier
With input qualifier
With input qualifier
(1)
12tc(CI)
12tc(CI) + tw(WAKE-INT)
cycles
1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)
12tc(CI)
12tc(CI) + tw(WAKE-INT)
cycles
cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up) signal involves additional latency.
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A
C
E
B
Device
Status
STANDBY
D
F
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/XCLKIN
td(IDLE-XCOH)
XCLKOUT
32 SYSCLKOUT Cycles
A.
B.
C.
D.
E.
F.
IDLE instruction is executed to put the device into STANDBY mode.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
•
16 cycles, when DIVSEL = 00 or 01
•
32 cycles, when DIVSEL = 10
•
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in
progress and its access time is longer than this number, then it will fail. It is recommended that STANDBY mode be
entered from SARAM without an XINTF access in progress.
Clocks to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
The external wake-up signal is driven active.
After a latency period, the STANDBY mode is exited.
Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-16. STANDBY Entry and Exit Timing
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Table 6-16. HALT Mode Timing Requirements
MIN
NOM
MAX
UNIT
tw(WAKE-XNMI)
Pulse duration, XNMI wakeup signal
2tc(CI)
cycles
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
8tc(CI)
cycles
Table 6-17. HALT Mode Switching Characteristics
PARAMETER
td(IDLE-XCOH)
Delay time, IDLE instruction executed to XCLKOUT high
tp
PLL lock-up time
MIN
TYP
32tc(SCO)
45tc(SCO)
MAX
UNIT
cycles
131072tc(CI)
cycles
1125tc(SCO)
cycles
35tc(SCO)
cycles
Delay time, PLL lock to program execution resume
td(WAKE)
•
Wake up from flash
– Flash module in sleep state
•
Wake up from SARAM
A
C
E
B
Device
Status
D
HALT
HALT
PLL Lock-up Time
Wake-up Latency
Flushing Pipeline
G
F
Normal
Execution
XNMI
tw(WAKE-XNMI)
tp
td(wake)
X1/XCLKIN
td(IDLE-XCOH)
XCLKOUT
Oscillator Start-up Time
(H)
32 SYSCLKOUT Cycles
A.
B.
C.
D.
E.
F.
G.
H.
IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned
off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.
Clocks to the peripherals are turned off and the internal oscillator and PLL are shut down. The device is now in HALT
mode and consumes absolute minimum power.
When XNMI is driven active, the oscillator is turned on; but the PLL is not activated. The pulse duration of 2tc(CI) is
applicable when an external oscillator is used. If the internal oscillator is used, the oscillator wake-up time should be
added to this parameter.
When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
Normal operation resumes.
XCLKOUT = SYSCLKOUT
Figure 6-17. HALT Wakeup Using XNMI
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6.17 Event Manager Interface
6.17.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
Table 6-18. PWM Switching Characteristics (1) (2)
PARAMETER
TEST CONDITIONS
tw(PWM) (3)
Pulse duration, PWMx output high/low
td(PWM)XCO
Delay time, XCLKOUT high to PWMx
output switching
(1)
(2)
(3)
MIN
MAX
25
UNIT
ns
XCLKOUT = SYSCLKOUT/4
10
ns
MAX
UNIT
See the GPIO output timing for fall/rise times for PWM pins.
PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period.
Table 6-19. Timer and Capture Unit Timing Requirements (1) (2)
MIN
Without input qualifier
2tc(SCO)
tw(TDIR)
Pulse duration, TDIRx low/high
tw(CAP)
Pulse duration, CAPx input low/high
With input qualifier
1tc(SCO) + IQT (3)
tw(TCLKINL)
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
40
60
%
tw(TCLKINH)
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
40
60
%
tc(TCLKIN)
Cycle time, TCLKINx
(1)
(2)
(3)
cycles
1tc(SCO) + IQT (3)
With input qualifier
Without input qualifier
2tc(SCO)
cycles
4tc(HCO)
ns
The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling
period is 2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the
qualification sampling period is 1 × 2 = 2 SYSCLKOUT cycles (that is, the input is sampled every 2 SYSCLKOUT cycles). Six such
samples will be taken over five sampling windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width
that is needed is 5 × 2 = 10 SYSCLKOUT cycles. However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide
pulse ensures reliable recognition.
Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
XCLKOUT
(A)
td(PWM)XCO
tw(PWM)
PWMx
A.
XCLKOUT = SYSCLKOUT
Figure 6-18. PWM Output Timing
XCLKOUT
(A)
tw(TDIR)
TDIRx
A.
XCLKOUT = SYSCLKOUT
Figure 6-19. TDIRx Timing
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Table 6-20. External ADC Start-of-Conversion – EVA – Switching Characteristics (1)
PARAMETER
td(XCOH-EVASOCL)
Delay time, XCLKOUT high to EVASOC low
tw(EVASOCL)
Pulse duration, EVASOC low
(1)
MIN
MAX
UNIT
1tc(SCO)
cycle
32tc(HCO)
ns
XCLKOUT = SYSCLKOUT
XCLKOUT
td(XCOH-EVASOCL)
tw(EVASOCL)
EVASOC
Figure 6-20. EVASOC Timing
Table 6-21. External ADC Start-of-Conversion – EVB – Switching Characteristics (1)
PARAMETER
td(XCOH-EVBSOCL)
Delay time, XCLKOUT high to EVBSOC low
tw(EVBSOCL)
Pulse duration, EVBSOC low
(1)
MIN
MAX
UNIT
1tc(SCO)
cycle
32tc(HCO)
ns
XCLKOUT = SYSCLKOUT
XCLKOUT
td(XCOH-EVBSOCL)
tw(EVBSOCL)
EVBSOC
Figure 6-21. EVBSOC Timing
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6.17.2 Interrupt Timing
Table 6-22. Interrupt Switching Characteristics
PARAMETER
MIN
td(PDP-PWM)HZ
Delay time, PDPINTx low to PWM highimpedance state
Without input qualifier
td(TRIP-PWM)HZ
Delay time, CxTRIP/TxCTRIP signals low to
PWM high-impedance state
Without input qualifier
td(INT)
Delay time, INT low/high to interrupt-vector fetch
(1)
MAX
12
1tc(SCO) + IQT + 12 (1)
With input qualifier
3 * tc(SCO)
2tc(SCO) + IQT (1)
With input qualifier
IQT + 12tc(SCO) (1)
UNIT
ns
ns
ns
Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
Table 6-23. Interrupt Timing Requirements
MIN
With no qualifier
tw(INT)
Pulse duration, INT input low/high
tw(PDP)
Pulse duration, PDPINTx input low
tw(CxTRIP)
Pulse duration, CxTRIP input low
tw(TxCTRIP)
Pulse duration, TxCTRIP input low
(1)
MAX
2tc(SCO)
1tc(SCO) + IQT (1)
With qualifier
With no qualifier
2tc(SCO)
1tc(SCO) + IQT (1)
With qualifier
With no qualifier
2tc(SCO)
1tc(SCO) + IQT (1)
With qualifier
With no qualifier
2tc(SCO)
1tc(SCO) + IQT (1)
With qualifier
UNIT
cycles
cycles
cycles
cycles
Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
XCLKOUT
(A)
tw(PDP), tw(CxTRIP), tw(TxCTRIP)
TxCTRIP,
CxTRIP,
PDPINTx
(B)
td(PDP-PWM)HZ, td(TRIP-PWM)HZ
(C)
PWM
tw(INT)
XNMI,
XINT1, XINT2
td(INT)
Interrupt Vector
A0-A15
A.
B.
C.
XCLKOUT = SYSCLKOUT
TxCTRIP – T1CTRIP, T2CTRIP, T3CTRIP, T4CTRIP
CxTRIP – C1TRIP, C2TRIP, C3TRIP, C4TRIP, C5TRIP, or C6TRIP
PDPINTx – PDPINTA or PDPINTB
PWM refers to all the PWM pins in the device (that is, PWMn and TnPWM pins or PWM pin pair relevant to each
CxTRIP pin). The state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit.
Figure 6-22. External Interrupt Timing
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6.18 General-Purpose Input/Output (GPIO) – Output Timing
Table 6-24. General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
UNIT
cycle
td(XCOH-GPO)
Delay time, XCLKOUT high to GPIO low/high
All GPIOs
1tc(SCO)
tr(GPO)
Rise time, GPIO switching low to high
All GPIOs
10
tf(GPO)
Fall time, GPIO switching high to low
All GPIOs
10
ns
fGPO
Toggling frequency, GPO pins
20
MHz
XCLKOUT
ns
(A)
td(XCOH-GPO)
GPIO
tf(GPO)
A.
tr(GPO)
XCLKOUT = SYSCLKOUT
Figure 6-23. General-Purpose Output Timing
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6.19 General-Purpose Input/Output (GPIO) – Input Timing
See Note (A)
GPIO
Signal
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
Sampling period, determined by GPxQUAL
[QUALPRD]
Sampling Window
(SYSCLKOUT cycle x 2 x QUALPRD) x 5
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
Output
From Qualifier
A.
B.
This glitch is ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can
vary from 00 to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value “n”, the
qualification sampling period is 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycle, the GPIO pin will be
sampled). Six consecutive samples must be of the same value for a given input to be recognized.
For the qualifier to detect the change, the input must be stable for 10 SYSCLKOUT cycles or greater. In other words,
the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would enable five sampling periods for
detection to occur. Since external signals are driven asynchronously, a 13-SYSCLKOUT-wide pulse provides reliable
recognition.
Figure 6-24. GPIO Input Qualifier – Example Diagram for QUALPRD = 1
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Table 6-25. General-Purpose Input Timing Requirements
MIN
tw(GPI)
(1)
Pulse duration GPIO
low/high
All GPIOs
With no qualifier
With qualifier
MAX
2tc(SCO)
1tc(SCO) + IQT (1)
UNIT
cycles
Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
XCLKOUT
GPIOxn
tw(GPI)
Figure 6-25. General-Purpose Input Timing
NOTE
The pulse width requirement for general-purpose input is applicable for the XBIO and
ADCSOC pins as well.
6.20 Serial Peripheral Interface (SPI) Master Mode Timing
Table 6-26 lists the master mode timing (clock phase = 0) and Table 6-27 lists the timing (clock
phase = 1). Figure 6-26 and Figure 6-27 show the timing waveforms.
Electrical Specifications
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Table 6-26. SPI Master Mode External Timing (Clock Phase = 0) (1) (2)
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
NO.
1
2
(3)
3
(3)
4
(3)
5
(3)
8
(3)
9
(3)
(1)
(2)
(3)
118
SPI WHEN (SPIBRR + 1) IS ODD AND
SPIBRR > 3
UNIT
MIN
MAX
MIN
MAX
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
tc(SPC)M
Cycle time, SPICLK
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M – 0.5tc(LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M – 0.5tc(LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO)
td(SPCH-SIMO)M
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
–10
10
–10
10
td(SPCL-SIMO)M
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
–10
10
–10
10
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M – 10
0.5tc(SPC)M + 0.5tc(LCO) – 10
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 10
0.5tc(SPC)M + 0.5tc(LCO) – 10
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
0
0
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
0
0
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25tc(SPC)M – 10
0.5tc(SPC)M – 0.5tc(LCO) – 10
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
0.25tc(SPC)M – 10
0.5tc(SPC)M – 0.5tc(LCO) – 10
ns
ns
ns
ns
ns
ns
ns
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
• Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX.
• Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX.
Electrical Specifications
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
SPISOMI
Master In Data
Must Be Valid
(A)
SPISTE
A.
In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving
edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-26. SPI Master Mode External Timing (Clock Phase = 0)
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Table 6-27. SPI Master Mode External Timing (Clock Phase = 1) (1) (2)
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
NO.
1
2
(3)
3
(3)
6 (3)
7 (3)
10
(3)
11
(3)
(1)
(2)
(3)
120
SPI WHEN (SPIBRR + 1) IS ODD AND
SPIBRR > 3
UNIT
MIN
MAX
MIN
MAX
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
tc(SPC)M
Cycle time, SPICLK
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M – 0.5tc(LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M – 0.5tc(LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO)
tsu(SIMO-SPCH)M
Setup time, SPISIMO data valid
before SPICLK high
(clock polarity = 0)
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
tsu(SIMO-SPCL)M
Setup time, SPISIMO data valid
before SPICLK low
(clock polarity = 1)
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
0
0
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
0
0
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
0.25tc(SPC)M – 10
0.5tc(SPC)M – 10
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
0.25tc(SPC)M – 10
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
• Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX.
• Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX.
Electrical Specifications
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
Master Out Data Is Valid
SPISIMO
Data Valid
10
11
Master In Data
Must Be Valid
SPISOMI
(A)
SPISTE
A.
In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays
active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-27. SPI Master External Timing (Clock Phase = 1)
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6.21 Serial Peripheral Interface (SPI) Slave Mode Timing
Table 6-28 lists the slave mode timing (clock phase = 0) and Table 6-29 lists the timing (clock phase = 1).
Figure 6-28 and Figure 6-29 show the timing waveforms.
Table 6-28. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2)
NO.
12
MIN
tc(SPC)S
13 (3) tw(SPCH)S
Cycle time, SPICLK
MAX
4tc(LCO)
ns
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S – 10
0.5tc(SPC)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S – 10
0.5tc(SPC)S
14 (3) tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S – 10
0.5tc(SPC)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S – 10
0.5tc(SPC)S
tw(SPCH)S
15 (3) td(SPCH-SOMI)S
td(SPCL-SOMI)S
16 (3) tv(SPCL-SOMI)S
tv(SPCH-SOMI)S
19 (3) tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
20 (3) tv(SPCL-SIMO)S
tv(SPCH-SIMO)S
(1)
(2)
(3)
122
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
0.375tc(SPC)S – 10
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.375tc(SPC)S – 10
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
0.75tc(SPC)S
Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)
0.75tc(SPC)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
0
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)
0.5tc(SPC)S
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)
0.5tc(SPC)S
UNIT
ns
ns
ns
ns
ns
ns
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
• Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX.
• Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX.
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO
SPISIMO Data
Must Be Valid
(A)
SPISTE
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-28. SPI Slave Mode External Timing (Clock Phase = 0)
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Table 6-29. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2)
NO.
12
13 (3)
14 (3)
17 (3)
18 (3)
21 (3)
22 (3)
(1)
(2)
(3)
124
MIN
MAX
tc(SPC)S
Cycle time, SPICLK
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S – 10
8tc(LCO)
0.5tc(SPC)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S – 10
0.5tc(SPC)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S – 10
0.5tc(SPC)S
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S – 10
0.5tc(SPC)S
tsu(SOMI-SPCH)S
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
0.125tc(SPC)S
tsu(SOMI-SPCL)S
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
0.125tc(SPC)S
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
0.75tc(SPC)S
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
0.75tc(SPC)S
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
0
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)S
UNIT
ns
ns
ns
ns
ns
ns
ns
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
• Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX.
• Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX.
Electrical Specifications
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISOMI Data Is Valid
Data Valid
21
22
SPISIMO
SPISIMO Data
Must Be Valid
(A)
SPISTE
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-29. SPI Slave Mode External Timing (Clock Phase = 1)
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6.22 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 6-30 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-30. Relationship Between Parameters Configured in XTIMING and Duration of Pulse (1) (2)
DURATION (ns)
DESCRIPTION
X2TIMING = 0
X2TIMING = 1
LR
Lead period, read access
XRDLEAD × tc(XTIM)
(XRDLEAD × 2) × tc(XTIM)
AR
Active period, read access
(XRDACTIVE + WS + 1) × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
TR
Trail period, read access
XRDTRAIL × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
LW
Lead period, write access
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
AW
Active period, write access
(XWRACTIVE + WS + 1) × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
XWRTRAIL × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
TW
(1)
(2)
Trail period, write access
tc(XTIM) – Cycle time, XTIMCLK
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No
internal device hardware is included to detect illegal settings.
●
If the XREADY signal is ignored (USEREADY = 0), then:
1.
LR ≥ tc(XTIM)
Lead:
LW ≥ tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions (no hardware to
detect illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥1
≥0
≥0
≥1
≥0
≥0
0, 1
Examples of valid and invalid timing when not sampling XREADY (no hardware to detect illegal XTIMING
configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Valid
1
0
0
1
0
0
0, 1
126
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●
SPRS174T – APRIL 2001 – REVISED MAY 2012
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0),
then:
1.
LR ≥ tc(XTIM)
Lead:
LW ≥ tc(XTIM)
2.
AR ≥ 2 × tc(XTIM)
Active:
AW ≥ 2 × tc(XTIM)
NOTE: Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (no hardware to
detect illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥1
≥1
≥0
≥1
≥1
≥0
0, 1
Examples of valid and invalid timing when using synchronous XREADY (no hardware to detect illegal
XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Invalid
1
0
0
1
0
0
0, 1
Valid
1
1
0
1
1
0
0, 1
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If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1,
READYMODE = 1), then:
1.
LR ≥ tc(XTIM)
Lead:
LW ≥ tc(XTIM)
2.
AR ≥ 2 × tc(XTIM)
Active:
AW ≥ 2 × tc(XTIM)
NOTE: Restriction does not include external hardware wait states
3.
LR + AR ≥ 4 × tc(XTIM)
Lead + Active:
LW + AW ≥ 4 × tc(XTIM)
NOTE: Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions (no hardware to
detect illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥1
≥2
0
≥1
≥2
0
0, 1
or (no hardware to detect illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥2
≥1
0
≥2
≥1
0
0, 1
Examples of valid and invalid timing when using asynchronous XREADY (no hardware to detect illegal
XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Invalid
1
0
0
1
0
0
0, 1
Invalid
1
1
0
1
1
0
0
Valid
1
1
0
1
1
0
1
Valid
1
2
0
1
2
0
0, 1
Valid
2
1
0
2
1
0
0, 1
128
Electrical Specifications
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Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-31.
Table 6-31. XINTF Clock Configurations
MODE
SYSCLKOUT
XTIMCLK
XCLKOUT
1
Example:
150 MHz
SYSCLKOUT
150 MHz
SYSCLKOUT
150 MHz
2
Example:
150 MHz
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
3
Example:
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
4
Example:
150 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6-30.
XTIMING0
XTIMING1
LEAD/ACTIVE/TRAIL
XTIMING2
XTIMING6
XTIMING7
XBANK
C28x
CPU
SYSCLKOUT
/2
1
(A)
0
XTIMCLK
/2
1
(A)
1
0
XCLKOUT
0
0
XINTCNF2
(XTIMCLK)
(A)
XINTCNF2
(CLKMODE)
XINTCNF2
(CLKOFF)
Default value after reset
Figure 6-30. Relationship Between XTIMCLK and SYSCLKOUT
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6.23 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock
XTIMCLK. Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to the
rising edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or onehalf the frequency of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the
rising edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change
state either on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables,
the notation XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising
edge (high) or XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of
XCLKOUT, the notation XCOH is used.
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be
aligned can be determined based on the number of XTIMCLK cycles from the start of the access to the
point at which the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with
respect to the rising edge of XCLKOUT. If this number is odd, then the signal will change with respect to
the falling edge of XCLKOUT. Examples include the following:
• Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
•
XR/W active-low
XRDL
XRD active-low
XWEL
XWE active-low
XRDH
XRD inactive-high
XWEH
XWE inactive-high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total
number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
130
XRNWL
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the
total number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If
the number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment
will be with respect to the falling edge of XCLKOUT.
Examples:
•
Zone chip-select active-low
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if
the total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK
cycles is odd, then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
•
XZCSL
Electrical Specifications
XZCSH
Zone chip-select inactive-high
XRNWH
XR/W inactive-high
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6.24 External Interface Read Timing
Table 6-32. External Memory Interface Read Switching Characteristics
PARAMETER
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active-low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive-high
td(XCOH-XA)
MIN
MAX
UNIT
1
ns
3
ns
Delay time, XCLKOUT high to address valid
2
ns
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active-low
1
ns
td(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive-high
–2
1
ns
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive-high
(1)
ns
th(XA)XRD
Hold time, address valid after XRD inactive-high
(1)
ns
(1)
–2
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6-33. External Memory Interface Read Timing Requirements
MIN
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active-low
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive-high
th(XD)XRD
Hold time, read data valid after XRD inactive-high
(1)
MAX
UNIT
(LR + AR) – 14 (1)
ns
(1)
ns
AR – 12
12
ns
0
ns
LR = Lead period, read access. AR = Active period, read access. See Table 6-30.
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Trail
Active
Lead
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOHL-XZCSH)
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
XR/W
ta(A)
th(XD)XRD
ta(XRD)
DIN
XD[0:15]
XREADY
A.
B.
C.
D.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
For USEREADY = 0, the external XREADY input signal is ignored.
XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6-31. Example Read Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥1
≥0
≥0
0
0
N/A (1)
N/A (1)
N/A (1)
N/A (1)
(1)
132
N/A = “Don’t care” for this example
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SPRS174T – APRIL 2001 – REVISED MAY 2012
6.25 External Interface Write Timing
Table 6-34. External Memory Interface Write Switching Characteristics
PARAMETER
MIN
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active-low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive-high
td(XCOH-XA)
MAX
UNIT
1
ns
3
ns
Delay time, XCLKOUT high to address valid
2
ns
td(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE low
2
ns
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE high
2
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
1
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
1
ns
ten(XD)XWEL
Enable time, data bus driven from XWE low
td(XWEL-XD)
Delay time, data valid after XWE active-low
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive-high
(1)
th(XD)XWE
Hold time, write data valid after XWE inactive-high
(2)
tdis(XD)XRNW
Maximum time for DSP to release the data bus after XR/W inactive-high
(1)
(2)
–2
–2
0
ns
4
TW – 2
ns
ns
ns
4
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = Trail period, write access. See Table 6-30.
Active
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
XD[0:15]
DOUT
XREADY
A.
B.
C.
D.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
For USEREADY = 0, the external XREADY input signal is ignored.
XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6-32. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
N/A
(1)
(1)
XRDACTIVE
N/A
(1)
XRDTRAIL
N/A
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
0
0
≥1
≥0
≥0
N/A (1)
(1)
N/A = “Don’t care” for this example
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6.26 External Interface Ready-on-Read Timing With One External Wait State
Table 6-35. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active-low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive-high
td(XCOH-XA)
MIN
MAX
UNIT
1
ns
3
ns
Delay time, XCLKOUT high to address valid
2
ns
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active-low
1
ns
td(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive-high
–2
1
ns
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive-high
(1)
ns
th(XA)XRD
Hold time, address valid after XRD inactive-high
(1)
ns
(1)
–2
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6-36. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active-low
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive-high
th(XD)XRD
Hold time, read data valid after XRD inactive-high
(1)
MAX
UNIT
(LR + AR) – 14 (1)
ns
(1)
ns
AR – 12
12
ns
0
ns
LR = Lead period, read access. AR = Active period, read access. See Table 6-30.
Table 6-37. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) (1)
MIN
MAX
UNIT
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low
15
ns
th(XRDYsynchL)
Hold time, XREADY (synchronous) low
12
ns
te(XRDYsynchH)
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (synchronous) high before XCLKOUT high/low
th(XRDYsynchH)XZCSH
Hold time, XREADY (synchronous) held high after zone chip-select high
(1)
3
ns
15
ns
0
ns
The first XREADY (synchronous) sample occurs with respect to E in Figure 6-33:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to
be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample (n), the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
Table 6-38. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) (1)
MIN
tsu(XRDYAsynchL)XCOHL
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
th(XRDYAsynchL)
Hold time, XREADY (asynchronous) low
te(XRDYAsynchH)
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
tsu(XRDYAsynchH)XCOHL
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
th(XRDYAsynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip-select high
(1)
134
MAX
UNIT
11
ns
8
ns
3
ns
11
ns
0
ns
The first XREADY (asynchronous) sample occurs with respect to E in Figure 6-34:
E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM)
When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found
to be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYAsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
Electrical Specifications
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WS (Synch)
See Notes (A) and (B)
Active
Lead
See Note (C)
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
ta(XRD)
XWE
XR/W
ta(A)
th(XD)XRD
XD[0:15]
DIN
tsu(XRDYsynchL)XCOHL
te(XRDYsynchH)
th(XRDYsynchL)
th(XRDYsynchH)XZCSH
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
See Note (D)
See Note (E)
Legend:
= Don’t care. Signal can be high or low during this time.
A.
B.
C.
D.
E.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
where n is the sample number (n = 1, 2, 3, and so forth).
Figure 6-33. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥1
3
≥1
1
0
N/A (1)
N/A (1)
N/A (1)
0 = XREADY
(Synch)
(1)
N/A = “Don’t care” for this example
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See
Notes (A)
and (B)
WS (Async)
Active
Lead
See Note (C)
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
ta(XRD)
XR/W
ta(A)
th(XD)XRD
XD[0:15]
DIN
tsu(XRDYasynchL)XCOHL
te(XRDYasynchH)
th(XRDYasynchL)
th(XRDYasynchH)XZCSH
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note (D)
See Note (E)
Legend:
= Don’t care. Signal can be high or low during this time.
A.
B.
C.
D.
E.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYAsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM)
Figure 6-34. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥1
3
≥1
1
0
N/A (1)
N/A (1)
N/A (1)
1 = XREADY
(Async)
(1)
136
N/A = “Don’t care” for this example
Electrical Specifications
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SPRS174T – APRIL 2001 – REVISED MAY 2012
6.27 External Interface Ready-on-Write Timing With One External Wait State
Table 6-39. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active-low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive-high
td(XCOH-XA)
MIN
MAX
UNIT
1
ns
3
ns
Delay time, XCLKOUT high to address valid
2
ns
td(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE low
2
ns
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE high
2
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
1
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
1
ns
ten(XD)XWEL
Enable time, data bus driven from XWE low
td(XWEL-XD)
Delay time, data valid after XWE active-low
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive-high
(1)
th(XD)XWE
Hold time, write data valid after XWE inactive-high
(2)
tdis(XD)XRNW
Maximum time for DSP to release the data bus after XR/W inactive-high
(1)
(2)
–2
–2
0
ns
4
TW – 2
ns
ns
ns
4
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = trail period, write access. See Table 6-30.
Table 6-40. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) (1)
MIN
MAX
UNIT
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low
15
ns
th(XRDYsynchL)
Hold time, XREADY (synchronous) low
12
ns
te(XRDYsynchH)
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (synchronous) high before XCLKOUT high/low
th(XRDYsynchH)XZCSH
Hold time, XREADY (synchronous) held high after zone chip-select high
(1)
3
ns
15
ns
0
ns
The first XREADY (synchronous) sample occurs with respect to E in Figure 6-35:
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to
be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
Table 6-41. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) (1)
MIN
tsu(XRDYasynchL)XCOHL
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
th(XRDYasynchL)
Hold time, XREADY (asynchronous) low
te(XRDYasynchH)
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
tsu(XRDYasynchH)XCOHL
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
th(XRDYasynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip-select high
(1)
MAX
UNIT
11
ns
8
ns
3
ns
11
ns
0
ns
The first XREADY (synchronous) sample occurs with respect to E in Figure 6-36:
E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found
to be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
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See
Notes (A)
and (B)
WS (Synch)
See Note (C)
Trail
Active
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOHL-XZCSH)
th(XRDYsynchH)XZCSH
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYsynchL)XCOHL
te(XRDYsynchH)
th(XRDYsynchL)
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
See Note (D)
See Note (E)
Legend:
= Don’t care. Signal can be high or low during this time.
A.
B.
C.
D.
E.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number (n = 1, 2, 3 and so forth).
Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 6-35. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A (1)
N/A (1)
N/A (1)
1
0
≥1
3
≥1
0 = XREADY
(Synch)
(1)
138
N/A = “Don’t care” for this example
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See
Notes (A)
and (B)
WS (Async)
See Note (C)
Trail
Active
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOHL-XZCSH)
th(XRDYasynchH)XZCSH
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
td(XWEL-XD)
th(XD)XWEH
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
te(XRDYasynchH)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note (D)
See Note (E)
Legend:
= Don’t care. Signal can be high or low during this time.
A.
B.
C.
D.
E.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number (n = 1, 2, 3 and so forth).
Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 6-36. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A (1)
N/A (1)
N/A (1)
1
0
≥1
3
≥1
1 = XREADY
(Async)
(1)
N/A = “Don’t care” for this example
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6.28 XHOLD and XHOLDA
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the
bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active
low.
When HOLD mode is enabled and XHOLDA is active-low (external bus grant active), the CPU can still
execute code from internal memory. If an access is made to the external interface, the CPU is stalled until
the XHOLD signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[18:0]
XZCS0AND1
XD[15:0]
XZCS2
XWE, XRD
XZCS6AND7
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
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6.29 XHOLD/XHOLDA Timing
Table 6-42. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) (1) (2)
MIN
MAX
UNIT
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
4tc(XTIM)
ns
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
5tc(XTIM)
ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
3tc(XTIM)
ns
td(HH-BV)
Delay time, XHOLD high to Bus valid
4tc(XTIM)
ns
(1)
(2)
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
td(HL-Hiz)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HAL)
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XA[18:0]
XD[15:0]
td(HH-BV)
High-Impedance
High-Impedance
Valid
Valid
See Note (A)
A.
B.
Valid
See Note (B)
All pending XINTF accesses are completed.
Normal XINTF operation resumes.
Figure 6-37. External Interface Hold Waveform
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Table 6-43. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) (1) (2) (3)
MIN
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
td(HH-HAH)
td(HH-BV)
(1)
(2)
(3)
MAX
UNIT
4tc(XTIM) + tc(XCO)
ns
4tc(XTIM) + 2tc(XCO)
ns
Delay time, XHOLD high to XHOLDA high
4tc(XTIM)
ns
Delay time, XHOLD high to Bus valid
6tc(XTIM)
ns
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of
XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the
maximum value specified.
XCLKOUT
(1/2 XTIMCLK)
td(HL-HAL)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HiZ)
td(HH-BV)
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
High-Impedance
XA[18:0]
High-Impedance
Valid
XD[15:0]
Valid
See Note (A)
A.
B.
Valid
High-Impedance
See Note (B)
All pending XINTF accesses are completed.
Normal XINTF operation resumes.
Figure 6-38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
142
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6.30 On-Chip Analog-to-Digital Converter
6.30.1 ADC Absolute Maximum Ratings
Unless otherwise noted, the list of absolute maximum ratings are specified over operating conditions.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
Supply voltage range (VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG)
–0.3 V to 4.6 V
Supply voltage range (VSS1 to VDD1)
–0.3 V to 2.5 V
Analog Input (ADCIN) Clamp Current, total (max)
(1)
±20 mA (1)
The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDA or below VSS. The continuous
clamp current per pin is ±2 mA.
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6.30.2 ADC Electrical Characteristics Over Recommended Operating Conditions
Table 6-44. DC Specifications (1)
PARAMETER
MIN
Resolution
TYP
MAX
12
Bits
1
ADC clock (2)
UNIT
kHz
25
MHz
1–18.75 MHz ADC clock
±1.5
LSB
1–18.75 MHz ADC clock
±1
LSB
–80
80
LSB
F281x
–200
200
C281x
–80
80
If ADCREFP – ADCREFM = 1 V ± 0.1%
–50
ACCURACY
INL (Integral nonlinearity)
(3)
DNL (Differential nonlinearity) (3)
Offset error (4)
Overall gain error with internal reference (5)
Overall gain error with external reference (6)
Channel-to-channel offset variation
Channel-to-channel Gain variation
50
LSB
LSB
±8
LSB
±8
LSB
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO) (7)
0
ADCLO
–5
Input capacitance
0
3
V
5
mV
±5
µA
10
Input leakage current
3
pF
INTERNAL VOLTAGE REFERENCE (5)
Accuracy, ADCVREFP
1.9
2
2.1
V
Accuracy, ADCVREFM
0.95
1
1.05
V
Voltage difference, ADCREFP – ADCREFM
Temperature coefficient
Reference noise
1
V
50
PPM/°C
100
µV
EXTERNAL VOLTAGE REFERENCE (6)
Accuracy, ADCVREFP
1.9
2
2.1
V
Accuracy, ADCVREFM
0.95
1
1.05
V
Input voltage difference, ADCREFP – ADCREFM
0.99
1
1.01
V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
144
Tested at 12.5-MHz ADCCLK.
If SYSCLKOUT ≤ 25 MHz, ADC clock ≤ SYSCLKOUT/2.
The INL degrades for frequencies beyond 18.75 MHz–25 MHz. Applications that require these sampling rates should use a 20K resistor
as bias resistor on the ADCRESEXT pin. This improves overall linearity and typical current drawn by the ADC will be a few mA more
than 24.9-kΩ bias. The ADC module in C281x devices can operate at 24.9k bias on ADCRESEXT pin for the full range 1–25 MHz.
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
A single internal band gap reference (±5% accuracy) sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error will be the combination of the
gain error shown here and the voltage reference accuracy (ADCREFP – ADCREFM). A software-based calibration procedure is
recommended for better accuracy. See the F2810, F2811, and F2812 ADC Calibration Application Report (literature number SPRA989)
and Section 5.2, Documentation Support, for relevant documents.
In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP – ADCREFM) will
determine the overall accuracy.
Voltages above VDDA + 0.3 V or below VSS – 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
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Table 6-45. AC Specifications
PARAMETER
MIN
TYP
MAX
UNIT
SINAD
Signal-to-noise ratio + distortion
62
dB
SNR
Signal-to-noise ratio
62
dB
THD (100 kHz)
Total harmonic distortion
–68
dB
ENOB (SNR)
Effective number of bits
10.1
Bits
SFDR
Spurious free dynamic range
69
dB
6.30.3 Current Consumption for Different ADC Configurations
Table 6-46. Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) (1)
IDDA (TYP) (2)
IDDAIO (TYP)
40 mA
1 µA
7 mA
0
1 µA
(2)
0.5 mA
0
1 µA
(1)
IDD1 (TYP)
ADC OPERATING MODE/CONDITIONS
Mode A (Operational Mode):
•
BG and REF enabled
•
PWD disabled
5 µA
Mode B:
•
ADC clock enabled
•
BG and REF enabled
•
PWD enabled
5 µA
Mode C:
•
ADC clock enabled
•
BG and REF disabled
•
PWD enabled
0
Mode D:
•
ADC clock disabled
•
BG and REF disabled
•
PWD enabled
0
Test Conditions:
• SYSCLKOUT = 150 MHz
• ADC module clock = 25 MHz
• ADC performing a continuous conversion of all 16 channels in Mode A
IDDA – includes current into VDDA1/VDDA2 and AVDDREFBG
Rs
Source
Signal
ADCIN0
ac
Ron
1 kW
Switch
Cp
10 pF
Ch
1.25 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron): 1 kW
Sampling Capacitor (Ch): 1.25 pF
Parasitic Capacitance (Cp): 10 pF
Source Resistance (Rs): 50 W
Figure 6-39. ADC Analog Input Impedance Model
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6.30.4 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
td(BGR)
PWDNADC
td(PWD)
Request for
ADC Conversion
Figure 6-40. ADC Power-Up Control Bit Timing
Table 6-47. ADC Power-Up Delays (1)
td(BGR)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) are to be set to 1 before the ADCPWDN bit is
enabled.
td(PWD)
Delay time for power-down control to be stable. Bit 5 of the ADCTRL3 register
(ADCPWDN) is to be set to 1 before any ADC conversions are initiated.
(1)
MIN
TYP
MAX
UNIT
7
8
10
ms
20
50
1
ms
µs
These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If
conversions are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at
the same time.
6.30.5 Detailed Description
6.30.5.1 Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP
is set to 2.0 V and ADCVREFM is set to 1.0 V.
6.30.5.2 Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at
a time. These inputs are software-selectable.
6.30.5.3 Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with
low power consumption.
6.30.5.4 Conversion Modes
The conversion can be performed in two different conversion modes:
• Sequential sampling mode (SMODE = 0)
• Simultaneous sampling mode (SMODE = 1)
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6.30.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the
selected channel on every Sample/Hold pulse. The conversion time and latency of the Result register
update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result
register update. The selected channels will be sampled at every falling edge of the Sample/Hold pulse.
The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks
wide (maximum).
Sample n+2
Sample n+1
Sample n
Analog Input on
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
tdschx_n+1
td(SH)
tdschx_n
ADC Event Trigger from EV
or Other Sources
tSH
Figure 6-41. Sequential Sampling Mode (Single-Channel) Timing
Table 6-48. Sequential Sampling Mode Timing
SAMPLE n
td(SH)
Delay time from event
trigger to sampling
tSH
Sample/
Hold width/
Acquisition width
td(schx_n)
Delay time for first
result to appear in the
Result register
td(schx_n+1)
Delay time for
successive results to
appear in the Result
register
SAMPLE n + 1
AT 25-MHz
ADC CLOCK,
tc(ADCCLK) = 40 ns
REMARKS
2.5tc(ADCCLK)
(1 + Acqps) * tc(ADCCLK)
40 ns with Acqps = 0
4tc(ADCCLK)
160 ns
(2 + Acqps) * tc(ADCCLK)
Acqps value = 0–15
ADCTRL1[8:11]
80 ns
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6.30.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB),
software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions
on two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result
register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the
Result register update. The selected channels will be sampled simultaneously at the falling edge of the
Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum)
or 16 ADC clocks wide (maximum).
NOTE
In Simultaneous Mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, and so forth).
Sample n
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bv
Sample n+2
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
tSH
ADC Event Trigger from EV
or Other Sources
td(SH)
tdschA0_n+1
tdschA0_n
tdschB0_n+1
tdschB0_n
Figure 6-42. Simultaneous Sampling Mode Timing
Table 6-49. Simultaneous Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25-MHz
ADC CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event
trigger to sampling
tSH
Sample/Hold width/
Acquisition Width
(1 + Acqps) * tc(ADCCLK)
40 ns with Acqps = 0
td(schA0_n)
Delay time for first
result to appear in
Result register
4tc(ADCCLK)
160 ns
td(schB0_n)
Delay time for first
result to appear in
Result register
5tc(ADCCLK)
200 ns
td(schA0_n+1)
Delay time for
successive results to
appear in Result
register
(3 + Acqps) * tc(ADCCLK)
120 ns
td(schB0_n+1)
Delay time for
successive results to
appear in Result
register
(3 + Acqps) * tc(ADCCLK)
120 ns
148
Electrical Specifications
REMARKS
2.5tc(ADCCLK)
Acqps value = 0–15
ADCTRL1[8:11]
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6.30.8 Definitions of Specifications and Terminology
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is
defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of
each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volt. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last
transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code transitions and the ideal difference between
first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(SINAD - 1.76)
N=
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus,
effective number of bits for a device for sine wave inputs at a given input frequency can be calculated
directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
Electrical Specifications
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6.31 Multichannel Buffered Serial Port (McBSP) Timing
6.31.1 McBSP Transmit and Receive Timing
Table 6-50. McBSP Timing Requirements (1) (2)
NO.
MIN
MAX
1
McBSP module clock (CLKG, CLKX, CLKR) range
kHz
20
(3)
MHz
1
ms
50
McBSP module cycle time (CLKG, CLKX, CLKR) range
UNIT
ns
M11
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
M12
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P–7
M13
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
7
ns
M14
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
7
ns
M15
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
M16
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
M17
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
M18
th(CKRL-DRV)
Hold time, DR valid after CLKR low
M19
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
M20
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
(1)
(2)
(3)
150
CLKR int
18
CLKR ext
2
CLKR int
0
CLKR ext
6
CLKR int
18
CLKR ext
2
CLKR int
0
CLKR ext
6
CLKX int
18
CLKX ext
2
CLKX int
0
CLKX ext
6
ns
ns
ns
ns
ns
ns
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV).
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching
speed.
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (20 MHz).
Electrical Specifications
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Table 6-51. McBSP Switching Characteristics (1) (2)
NO.
PARAMETER
UNIT
Cycle time, CLKR/X
CLKR/X int
2P
M2
tw(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D – 5 (3)
D + 5 (3)
ns
M3
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C – 5 (3)
C + 5 (3)
ns
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance following last
data bit
CLKX int
8
CLKX ext
14
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX int
9
CLKX ext
28
td(CKXH-DXV)
Delay time, CLKX high to DX valid.
DXENA = 0
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY = 01b or 10b) modes.
DXENA = 1
Enable time, CLKX high to DX driven.
M8
ten(CKXH-DX)
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY = 01b or 10b) modes.
Delay time, FSX high to DX valid.
M9
td(FXH-DXV)
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY = 00b) mode.
Enable time, FSX high to DX driven.
M10
(2)
(3)
MAX
tc(CKRX)
M7
(1)
MIN
M1
ten(FXH-DX)
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY = 00b) mode.
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
ns
CLKR int
0
4
CLKR ext
3
27
CLKX int
0
4
CLKX ext
3
27
CLKX int
8
CLKX ext
14
CLKX int
P+8
CLKX ext
P + 14
CLKX int
ns
ns
ns
0
CLKX ext
6
CLKX int
P
CLKX ext
P+6
ns
FSX int
8
FSX ext
14
FSX int
P+8
FSX ext
P + 14
FSX int
ns
ns
0
FSX ext
6
FSX int
P
FSX ext
P+6
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
2P = 1/CLKG in ns.
C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n-1)
(n-2)
M17
DR
(RDATDLY=01b)
(n-3)
(n-4)
(n-2)
(n-3)
M18
Bit (n-1)
M17
M18
DR
(RDATDLY=10b)
Bit (n-1)
(n-2)
Figure 6-43. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
M14
CLKX
M5
M5
FSX (int)
M19
M20
FSX (ext)
M9
DX
(XDATDLY=00b)
M7
M10
Bit 0
Bit (n-1)
(n-2)
(n-3)
(n-4)
(n-2)
(n-3)
M7
M8
DX
(XDATDLY=01b)
Bit 0
Bit (n-1)
M7
M6
DX
(XDATDLY=10b)
M8
Bit (n-1)
Bit 0
(n-2)
Figure 6-44. McBSP Transmit Timing
152
Electrical Specifications
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6.31.2 McBSP as SPI Master or Slave Timing
Table 6-52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
MASTER
NO.
(1)
MIN
M30
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
M31
th(CKXL-DRV)
Hold time, DR valid after CLKX low
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
M33
tc(CKX)
Cycle time, CLKX
SLAVE
MAX
MIN
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
8P + 10
ns
16P
ns
2P
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) (1)
NO.
(1)
MASTER
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
M24
th(CKXL-FXL)
Hold time, FSX low after CLKX low
2P
ns
M25
td(FXL-CKXH)
Delay time, FSX low to CLKX high
P
ns
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
6
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
M32
LSB
M33
MSB
CLKX
M24
M25
FSX
M28
DX
M29
Bit(n-1)
Bit 0
M30
DR
Bit 0
(n-2)
(n-3)
(n-4)
M31
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Electrical Specifications
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Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
MASTER
NO.
MIN
M39
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
M40
th(CKXH-DRV)
Hold time, DR valid after CLKX high
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
M42
tc(CKX)
Cycle time, CLKX
(1)
SLAVE
MAX
MIN
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
16P + 10
ns
16P
ns
2P
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) (1)
NO.
MASTER
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
M34
th(CKXL-FXL)
Hold time, FSX low after CLKX low
P
ns
M35
td(FXL-CKXH)
Delay time, FSX low to CLKX high
2P
ns
M37
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX low
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
(1)
P+6
7P + 6
ns
6
4P + 6
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
LSB
M42
MSB
M41
CLKX
M34
M35
FSX
M37
DX
M38
Bit(n-1)
Bit 0
M39
DR
Bit 0
(n-2)
(n-3)
(n-4)
M40
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
154
Electrical Specifications
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Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
MASTER
NO.
(1)
MIN
M49
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
M50
th(CKXH-DRV)
Hold time, DR valid after CLKX high
M51
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M52
tc(CKX)
Cycle time, CLKX
SLAVE
MAX
MIN
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
8P + 10
ns
16P
ns
2P
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) (1)
NO.
(1)
MASTER
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
M43
th(CKXH-FXL)
Hold time, FSX low after CLKX high
2P
ns
M44
td(FXL-CKXL)
Delay time, FSX low to CLKX low
P
ns
M47
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
6
6P + 6
ns
M48
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
LSB
MSB
M51
M52
CLKX
M43
M44
FSX
M47
DX
M48
Bit(n-1)
Bit 0
M49
DR
Bit 0
(n-2)
(n-3)
(n-4)
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Electrical Specifications
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Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
MASTER
NO.
MIN
M58
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
M59
th(CKXL-DRV)
Hold time, DR valid after CLKX low
M60
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M61
tc(CKX)
Cycle time, CLKX
(1)
SLAVE
MAX
MIN
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
16P + 10
ns
16P
ns
2P
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
NO.
MASTER
PARAMETER
MIN
M53
th(CKXH-FXL)
Hold time, FSX low after CLKX high
M54
td(FXL-CKXL)
Delay time, FSX low to CLKX low
2P
M55
td(CLKXH-DXV)
Delay time, CLKX high to DX valid
–2
M56
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
M57
td(FXL-DXV)
Delay time, FSX low to DX valid
(1)
SLAVE
MAX
MIN
MAX
P
UNIT
ns
ns
0
3P + 6 5P + 20
ns
P+6
7P + 6
ns
6
4P + 6
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
M60
LSB
M61
MSB
CLKX
M53
M54
FSX
M56
DX
M57
M55
Bit(n-1)
Bit 0
M58
DR
Bit 0
(n-2)
(n-3)
(n-4)
M59
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
156
Electrical Specifications
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6.32 Flash Timing (F281x Only)
Table 6-60. Flash Endurance for A and S Temperature Material (1)
ERASE/PROGRAM
TEMPERATURE
Nf
Flash endurance for the array (Write/Erase cycles)
0°C to 85°C (ambient)
NOTP
OTP endurance for the array (Write cycles)
0°C to 85°C (ambient)
(1)
(2)
MIN
TYP
20000 (2)
50000 (2)
MAX
UNIT
cycles
1
write
Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
The Write/Erase cycle numbers of 20000 (MIN) and 50000 (TYP) are applicable only for silicon revision G. For older silicon revisions,
the Write/Erase cycle numbers of 100 (MIN) and 1000 (TYP) are applicable.
Table 6-61. Flash Endurance for Q Temperature Material (1)
ERASE/PROGRAM
TEMPERATURE
Nf
NOTP
(1)
(2)
Flash endurance for the array (Write/Erase cycles)
–40°C to 125°C (ambient)
OTP endurance for the array (Write cycles)
–40°C to 125°C (ambient)
MIN
TYP
20000 (2)
50000 (2)
MAX
UNIT
cycles
1
write
Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
The Write/Erase cycle numbers of 20000 (MIN) and 50000 (TYP) are applicable only for silicon revision G. For older silicon revisions,
the Write/Erase cycle numbers of 100 (MIN) and 1000 (TYP) are applicable.
Table 6-62. Flash Parameters at 150-MHz SYSCLKOUT (1)
PARAMETER
16-Bit Word
Program Time
8K Sector
16K Sector
Erase Time (3)
TYP
35
Using Flash API v2.10
50
Using Flash API v1 (2)
170
Using Flash API v2.10
250
Using Flash API v1 (2)
320
Using Flash API v2.10
500
8K Sector
10
16K Sector
11
IDD3VFLP
VDD3VFL current consumption during the Erase/Program cycle
IDDP
VDD current consumption during Erase/Program cycle
IDDIOP
VDDIO current consumption during Erase/Program cycle
(1)
(2)
(3)
MIN
Using Flash API v1 (2)
Erase
75
Program
35
MAX
UNIT
µs
ms
ms
s
mA
140
mA
20
mA
Typical parameters as seen at room temperature including function call overhead, with all peripherals off.
Flash API v1.00 is useable on rev. C silicon only.
The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Electrical Specifications
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SPRS174T – APRIL 2001 – REVISED MAY 2012
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Table 6-63. Flash/OTP Access Timing
PARAMETER
MIN
MAX
UNIT
ta(fp)
Paged Flash access time
36
ns
ta(fr)
Random Flash access time
36
ns
ta(OTP)
OTP access time
60
ns
Table 6-64. Minimum Required Flash Wait States at Different Frequencies (F281x devices)
(1)
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
PAGE
WAIT STATE (1)
RANDOM
WAIT STATE (1)
150
6.67
5
5
8
120
8.33
4
4
7
100
10
3
3
5
75
13.33
2
2
4
50
20
1
1
2
30
33.33
1
1
1
25
40
0
1
1
15
66.67
0
1
1
4
250
0
1
1
(2)
OTP
Formulas to compute page wait state and random wait state:
éæ t a(fp) ö ù
÷ - 1ú (round up to the next highest integer, or 0, whichever is larger)
Flash Page Wait State = êç
ç
÷
ëêè t c(SCO) ø ûú
éæ t a(fr) ö ù
÷ - 1ú (round up to the next highest integer, or 1, whichever is larger)
Flash Random Wait State = êç
êëçè t c(SCO) ÷ø úû
éæ t a(OTP) ö ù
÷ - 1ú (round up to the next highest integer, or 1, whichever is larger)
OTP Wait State = êç
ç
÷
ëêè t c(SCO) ø ûú
(2)
158
Random wait state must be greater than or equal to 1.
Electrical Specifications
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TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
6.33 ROM Timing (C281x only)
Table 6-65. ROM Access Timing
PARAMETER
MIN
MAX
UNIT
ta(rp)
Paged ROM access time
23
ns
ta(rr)
Random ROM access time
23
ns
ta(ROM)
ROM (OTP area) access time (1)
60
ns
(1)
In C281x devices, a 1K × 16 ROM block replaces the OTP block found in Flash devices.
Table 6-66. Minimum Required ROM Wait States at Different Frequencies (C281x devices)
(1)
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
PAGE WAIT STATE (1)
RANDOM WAIT STATE (1)
150
6.67
3
3
120
8.33
2
2
100
10
2
2
75
13.33
1
1
50
20
1
1
30
33.33
0
1
25
40
0
1
15
66.67
0
1
4
250
0
1
(2)
Formulas to compute page wait state and random wait state:
éæ t a(rp) ö ù
÷ - 1ú (round up to the next highest integer, or 0, whichever is larger)
ROM Page Wait State = êç
êëçè t c(SCO) ÷ø úû
éæ t a(rr) ö ù
÷ - 1ú (round up to the next highest integer, or 1, whichever is larger)
ROM Random Wait State = êç
êëçè t c(SCO) ÷ø úû
(2)
Random wait state must be greater than or equal to 1.
Electrical Specifications
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SPRS174T – APRIL 2001 – REVISED MAY 2012
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6.34 Migrating From F281x Devices to C281x Devices
The migration issues to be considered while migrating from the F281x devices to C281x devices are as
follows:
• The 1K OTP memory available in F281x devices has been replaced by 1K ROM in C281x devices.
• Power sequencing is not needed for C281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can
ramp together. C281x can also be used on boards that have F281x power sequencing implemented;
however, if the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail
reaches at least 1 V.
• Current consumption differs for F281x and C281x devices for all four possible modes. See the
appropriate electrical section for exact numbers.
• The VDD3VFL pin is the 3.3-V flash core power pin in F281x devices but is a VDDIO pin in C281x devices.
• F281x and C281x devices are pin-compatible and code-compatible; however, they are electrically
different with different EMI/ESD profiles. Before ramping production with C281x devices, evaluate
performance of the hardware design with both devices.
• Addresses 0x3D 7BFC through 0x3D 7BFF in the OTP and addresses 0x3F 7FF2 through 0x3F 7FF5
in the main ROM array are reserved for ROM part-specific information and are not available for user
applications.
• The ADC module in C281x devices can operate at 24.9k bias on ADCRESEXT pin for the full range
1–25 MHz. While migrating the F281x designs to C281x, use a 24.9k resistor for biasing the ADC.
• The paged and random wait-state specifications for the flash and ROM parts are different. While
migrating from flash to ROM parts, the same wait-state values must be used for best performance
compatibility (for example, in applications that use software delay loops or where precise interrupt
latencies are critical).
• The PART-ID register value is different for Flash and ROM parts.
For errata applicable to 281x devices, see the TMS320F2810, TMS320F2811, TMS320F2812,
TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature number SPRZ193).
160
Electrical Specifications
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TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
7
SPRS174T – APRIL 2001 – REVISED MAY 2012
Revision History
This data sheet revision history highlights the technical changes made to the SPRS174S device-specific
data sheet to make it an SPRS174T revision.
Scope: See table below.
LOCATION
Section 1.1
ADDITIONS, DELETIONS, AND MODIFICATIONS
Features:
•
Added "Endianness: Little Endian" feature
Table 6-4
Recommended “Low-Dropout Regulators”:
•
Replaced TPS767D301 with TPS75005
•
Added DESCRIPTION column
Table 6-59
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1):
•
Added parameter M55, td(CLKXH-DXV), Delay time, CLKX high to DX valid
Table 6-62
Flash Parameters at 150-MHz SYSCLKOUT:
•
Added footnote about flash memory being in an erased state when the device is shipped
Revision History
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TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
8
www.ti.com
Mechanical Data
Table 8-1 through Table 8-4 provide the thermal resistance characteristics for the various packages.
Table 8-1. Thermal Resistance Characteristics for 179-Ball GHH
PARAMETER
179-GHH PACKAGE
UNIT
PsiJT
0.658
°C/W
ΘJA
42.57
°C/W
ΘJC
16.08
°C/W
Table 8-2. Thermal Resistance Characteristics for 179-Ball ZHH
PARAMETER
179-ZHH PACKAGE
UNIT
PsiJT
0.658
°C/W
ΘJA
42.57
°C/W
ΘJC
16.08
°C/W
Table 8-3. Thermal Resistance Characteristics for 176-Pin PGF
PARAMETER
176-PGF PACKAGE
UNIT
PsiJT
0.247
°C/W
ΘJA
41.88
°C/W
ΘJC
9.73
°C/W
Table 8-4. Thermal Resistance Characteristics for 128-Pin PBK
PARAMETER
128-PBK PACKAGE
UNIT
PsiJT
0.271
°C/W
ΘJA
41.65
°C/W
ΘJC
10.76
°C/W
The following mechanical package diagram(s) reflect the most current released mechanical data available
for the designated device(s).
162
Mechanical Data
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
(Requires Login)
TMS320C2810PBKA
ACTIVE
LQFP
PBK
128
TBD
Call TI
Call TI
TMS320C2810PBKQ
ACTIVE
LQFP
PBK
128
TBD
Call TI
Call TI
TMS320C2811PBKA
ACTIVE
LQFP
PBK
128
TBD
Call TI
Call TI
TMS320C2811PBKQ
ACTIVE
LQFP
PBK
128
TBD
Call TI
Call TI
TMS320C2812PGFA
ACTIVE
LQFP
PGF
176
TBD
Call TI
Call TI
TMS320F2810PBKA
ACTIVE
LQFP
PBK
128
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TMS320F2810PBKQ
ACTIVE
LQFP
PBK
128
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TMS320F2810PBKS
ACTIVE
LQFP
PBK
128
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TMS320F2811PBKA
ACTIVE
LQFP
PBK
128
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TMS320F2811PBKQ
ACTIVE
LQFP
PBK
128
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TMS320F2811PBKS
ACTIVE
LQFP
PBK
128
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TMS320F2812GHHA
ACTIVE
BGA
MICROSTAR
GHH
179
160
TBD
SNPB
Level-3-220C-168 HR
TMS320F2812GHHAR
ACTIVE
BGA
MICROSTAR
GHH
179
1000
TBD
SNPB
Level-3-220C-168 HR
TMS320F2812GHHQ
ACTIVE
BGA
MICROSTAR
GHH
179
160
TBD
SNPB
Level-3-220C-168 HR
TMS320F2812GHHS
ACTIVE
BGA
MICROSTAR
GHH
179
160
TBD
SNPB
Level-3-220C-168 HR
TMS320F2812PGFA
ACTIVE
LQFP
PGF
176
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TMS320F2812PGFQ
ACTIVE
LQFP
PGF
176
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TMS320F2812PGFS
ACTIVE
LQFP
PGF
176
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TMS320F2812ZHHA
ACTIVE
BGA
MICROSTAR
ZHH
179
160
Green (RoHS
& no Sb/Br)
Addendum-Page 1
SNAGCU
Samples
Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Sep-2012
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TMS320F2812ZHHAR
ACTIVE
BGA
MICROSTAR
ZHH
179
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TMS320F2812ZHHS
ACTIVE
BGA
MICROSTAR
ZHH
179
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F2812 :
• Catalog: SM320F2812
• Enhanced Product: SM320F2812-EP
• Military: SMJ320F2812
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2012
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
OCTOBER 1994
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
88
133
0,27
0,17
0,08 M
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
SQ
25,80
0,25
0,05 MIN
0°−ā 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134 / B 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
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