TI SM320F28335-HT

SM320F28335-HT
Digital Signal Controller (DSC)
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Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS682B
December 2010 – Revised May 2012
SM320F28335-HT
www.ti.com
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Contents
1
SM320F28335 DSC
1.1
1.2
2
Introduction
2.1
2.2
2.3
3
3.6
3.7
Peripherals
4.1
4.2
4.3
4.4
4.5
4.6
4.7
.......................................................................................................... 33
Memory Maps ..............................................................................................................
Brief Descriptions ..........................................................................................................
3.2.1
C28x CPU .......................................................................................................
3.2.2
Memory Bus (Harvard Bus Architecture) ....................................................................
3.2.3
Peripheral Bus ..................................................................................................
3.2.4
Real-Time JTAG and Analysis ................................................................................
3.2.5
External Interface (XINTF) ....................................................................................
3.2.6
Flash .............................................................................................................
3.2.7
M0, M1 SARAMs ...............................................................................................
3.2.8
L0, L1, L2, L3, L4, L5, L6, L7 SARAMs .....................................................................
3.2.9
Boot ROM .......................................................................................................
3.2.10 Security ..........................................................................................................
3.2.11 Peripheral Interrupt Expansion (PIE) Block .................................................................
3.2.12 External Interrupts (XINT1-XINT7, XNMI) ...................................................................
3.2.13 Oscillator and PLL ..............................................................................................
3.2.14 Watchdog ........................................................................................................
3.2.15 Peripheral Clocking .............................................................................................
3.2.16 Low-Power Modes ..............................................................................................
3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ...........................................................................
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer .........................................................
3.2.19 32-Bit CPU-Timers (0, 1, 2) ...................................................................................
3.2.20 Control Peripherals .............................................................................................
3.2.21 Serial Port Peripherals .........................................................................................
Register Map ...............................................................................................................
Device Emulation Registers ..............................................................................................
Interrupts ....................................................................................................................
3.5.1
External Interrupts ..............................................................................................
System Control ............................................................................................................
3.6.1
OSC and PLL Block ............................................................................................
3.6.1.1
External Reference Oscillator Clock Option ....................................................
3.6.1.2
PLL-Based Clock Module .........................................................................
3.6.1.3
Loss of Input Clock ................................................................................
3.6.2
Watchdog Block .................................................................................................
Low-Power Modes Block .................................................................................................
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3.3
3.4
3.5
2
...................................................................................................................... 12
Pin Assignments ........................................................................................................... 13
Die Layout .................................................................................................................. 18
Signal Descriptions ........................................................................................................ 25
Functional Overview
3.1
3.2
4
............................................................................................................. 10
Features .................................................................................................................... 10
SUPPORTS EXTREME TEMPERATURE APPLICATIONS ......................................................... 10
....................................................................................................................... 58
DMA Overview .............................................................................................................
32-Bit CPU-Timers 0/1/2 .................................................................................................
Enhanced PWM Modules (ePWM1/2/3/4/5/6) .........................................................................
High-Resolution PWM (HRPWM) .......................................................................................
Enhanced CAP Modules (eCAP1/2/3/4/5/6) ...........................................................................
Enhanced QEP Modules (eQEP1/2) ....................................................................................
Analog-to-Digital Converter (ADC) Module ............................................................................
4.7.1
ADC Connections if the ADC Is Not Used ..................................................................
Contents
34
38
38
38
38
39
39
39
39
39
40
40
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66
66
69
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74
Copyright © 2010–2012, Texas Instruments Incorporated
SM320F28335-HT
www.ti.com
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.7.2
ADC Registers ..................................................................................................
4.7.3
ADC Calibration .................................................................................................
Multichannel Buffered Serial Port (McBSP) Module ..................................................................
Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) ....................................
Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) ..........................................
Serial Peripheral Interface (SPI) Module (SPI-A) .....................................................................
Inter-Integrated Circuit (I2C) .............................................................................................
GPIO MUX .................................................................................................................
External Interface (XINTF) ...............................................................................................
74
75
76
79
84
87
90
91
98
Device Support ................................................................................................................ 100
Electrical Specifications ................................................................................................... 100
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
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5
6
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Absolute Maximum Ratings ............................................................................................
Recommended Operating Conditions .................................................................................
Electrical Characteristics ................................................................................................
Current Consumption ....................................................................................................
6.4.1
Reducing Current Consumption .............................................................................
6.4.2
Current Consumption Graphs ...............................................................................
6.4.3
Thermal Design Considerations .............................................................................
Emulator Connection Without Signal Buffering for the DSP .......................................................
Timing Parameter Symbology ..........................................................................................
6.6.1
General Notes on Timing Parameters ......................................................................
6.6.2
Test Load Circuit ..............................................................................................
6.6.3
Device Clock Table ...........................................................................................
Clock Requirements and Characteristics .............................................................................
Power Sequencing .......................................................................................................
6.8.1
Power Management and Supervisory Circuit Solutions ..................................................
General-Purpose Input/Output (GPIO) ................................................................................
6.9.1
GPIO - Output Timing ........................................................................................
6.9.2
GPIO - Input Timing ..........................................................................................
6.9.3
Sampling Window Width for Input Signals .................................................................
6.9.4
Low-Power Mode Wakeup Timing ..........................................................................
Enhanced Control Peripherals .........................................................................................
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing .......................................................
6.10.2 Trip-Zone Input Timing .......................................................................................
External Interrupt Timing ................................................................................................
I2C Electrical Specification and Timing ...............................................................................
Serial Peripheral Interface (SPI) Timing ..............................................................................
6.13.1 Master Mode Timing ..........................................................................................
6.13.2 SPI Slave Mode Timing ......................................................................................
External Interface (XINTF) Timing .....................................................................................
6.14.1 USEREADY = 0 ...............................................................................................
6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) .............................................
6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................
6.14.4 XINTF Signal Alignment to XCLKOUT .....................................................................
6.14.5 External Interface Read Timing .............................................................................
6.14.6 External Interface Write Timing .............................................................................
6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................
6.14.8 External Interface Ready-on-Write Timing With One External Wait State .............................
6.14.9 XHOLD and XHOLDA Timing ...............................................................................
On-Chip Analog-to-Digital Converter ..................................................................................
6.15.1 ADC Power-Up Control Bit Timing ..........................................................................
6.15.2 Definitions ......................................................................................................
6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................
Copyright © 2010–2012, Texas Instruments Incorporated
Contents
100
102
102
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3
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
6.16
6.17
www.ti.com
6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) ..........................................
6.15.5 Detailed Descriptions .........................................................................................
Multichannel Buffered Serial Port (McBSP) Timing .................................................................
6.16.1 McBSP Transmit and Receive Timing ......................................................................
6.16.2 McBSP as SPI Master or Slave Timing ....................................................................
Flash Timing ..............................................................................................................
152
153
154
154
156
160
7
Thermal/Mechanical Data .................................................................................................. 162
Revision History ....................................................................................................................... 163
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4
Contents
Copyright © 2010–2012, Texas Instruments Incorporated
SM320F28335-HT
www.ti.com
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
List of Figures
2-1
181-Pin GB ........................................................................................................................ 13
2-2
SM320F28335 Die Layout ...................................................................................................... 18
3-1
Functional Block Diagram
3-2
Memory Map ...................................................................................................................... 35
3-3
External and PIE Interrupt Sources ............................................................................................ 48
3-4
External Interrupts ................................................................................................................ 48
3-5
Multiplexing of Interrupts Using the PIE Block
3-7
3-8
3-9
3-10
3-11
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
...............................................................................
Clock and Reset Domains ......................................................................................................
OSC and PLL Block Diagram...................................................................................................
Using a 3.3-V External Oscillator...............................................................................................
Using a 1.9-V External Oscillator...............................................................................................
Using the Internal Oscillator ....................................................................................................
Watchdog Module ................................................................................................................
DMA Functional Block Diagram ................................................................................................
CPU-Timers .......................................................................................................................
CPU-Timer Interrupt Signals and Output Signal .............................................................................
Multiple PWM Modules ..........................................................................................................
ePWM Submodules Showing Critical Internal Signal Interconnections ...................................................
eCAP Functional Block Diagram ...............................................................................................
eQEP Functional Block Diagram ...............................................................................................
Block Diagram of the ADC Module ............................................................................................
ADC Pin Connections With Internal Reference ..............................................................................
ADC Pin Connections With External Reference .............................................................................
McBSP Module ..................................................................................................................
eCAN Block Diagram and Interface Circuit ...................................................................................
eCAN-A Memory Map ...........................................................................................................
eCAN-B Memory Map ...........................................................................................................
Serial Communications Interface (SCI) Module Block Diagram............................................................
SPI Module Block Diagram (Slave Mode) ....................................................................................
I2C Peripheral Module Interfaces ..............................................................................................
GPIO MUX Block Diagram ......................................................................................................
Qualification Using Sampling Window .........................................................................................
External Interface Block Diagram ..............................................................................................
Typical 16-bit Data Bus XINTF Connections .................................................................................
Typical 32-bit Data Bus XINTF Connections .................................................................................
SM320F28335 Operating Life Derating Chart ..............................................................................
Typical Operational Current Versus Frequency for TA = 25°C ...........................................................
Typical Operational Current Versus Frequency for TA = 210°C ..........................................................
Emulator Connection Without Signal Buffering for the DSP ..............................................................
3.3-V Test Load Circuit.........................................................................................................
Clock Timing .....................................................................................................................
Power-on Reset .................................................................................................................
Warm Reset .....................................................................................................................
Example of Effect of Writing Into PLLCR Register .........................................................................
General-Purpose Output Timing ..............................................................................................
Sampling Mode .................................................................................................................
General-Purpose Input Timing ................................................................................................
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3-6
......................................................................................................
Copyright © 2010–2012, Texas Instruments Incorporated
List of Figures
33
49
52
53
54
54
54
56
59
60
60
62
65
68
69
72
73
74
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5
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
www.ti.com
6-13
IDLE Entry and Exit Timing .................................................................................................... 118
6-14
STANDBY Entry and Exit Timing Diagram .................................................................................. 119
6-15
HALT Wake-Up Using GPIOn................................................................................................. 121
6-16
PWM Hi-Z Characteristics ..................................................................................................... 122
6-17
ADCSOCAO or ADCSOCBO Timing
6-18
External Interrupt Timing ....................................................................................................... 124
6-19
SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 127
6-20
SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 129
6-21
SPI Slave Mode External Timing (Clock Phase = 0) ....................................................................... 131
6-22
SPI Slave Mode External Timing (Clock Phase = 1) ....................................................................... 132
6-23
Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 135
6-24
Example Read Access ......................................................................................................... 137
6-25
Example Write Access ......................................................................................................... 138
6-26
......................................................................
Example Read With Asynchronous XREADY Access .....................................................................
Write With Synchronous XREADY Access ..................................................................................
Write With Asynchronous XREADY Access ................................................................................
External Interface Hold Waveform ............................................................................................
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ..................................................
ADC Power-Up Control Bit Timing ...........................................................................................
ADC Analog Input Impedance Model ........................................................................................
Sequential Sampling Mode (Single-Channel) Timing ......................................................................
Simultaneous Sampling Mode Timing .......................................................................................
McBSP Receive Timing ........................................................................................................
McBSP Transmit Timing .......................................................................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ...................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ...................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ...................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ...................................................
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6
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6-27
........................................................................................
Example Read With Synchronous XREADY Access
List of Figures
124
140
141
143
144
146
147
149
150
151
152
156
156
157
158
159
160
Copyright © 2010–2012, Texas Instruments Incorporated
SM320F28335-HT
www.ti.com
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
List of Tables
.............................................................................................................. 12
.............................................................................................................. 13
Bare Die Information ............................................................................................................. 18
Die Pad Information .............................................................................................................. 19
Signal Descriptions ............................................................................................................... 25
Addresses of Flash Sectors .................................................................................................... 36
Handling Security Code Locations ............................................................................................. 36
Wait-states ........................................................................................................................ 37
Boot Mode Selection ............................................................................................................. 40
Peripheral Frame 0 Registers .................................................................................................. 45
Peripheral Frame 1 Registers .................................................................................................. 45
Peripheral Frame 2 Registers .................................................................................................. 46
Peripheral Frame 3 Registers .................................................................................................. 46
Device Emulation Registers..................................................................................................... 46
PIE Peripheral Interrupts ....................................................................................................... 49
PIE Configuration and Control Registers...................................................................................... 50
External Interrupt Registers ..................................................................................................... 51
PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 53
PLLCR Bit Descriptions ......................................................................................................... 55
CLKIN Divide Options ........................................................................................................... 55
Possible PLL Configuration Modes ............................................................................................ 55
Low-Power Modes ............................................................................................................... 57
CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 61
ePWM Control and Status Registers (default configuration in PF1) ....................................................... 63
ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible) ............................. 64
eCAP Control and Status Registers ........................................................................................... 68
eQEP Control and Status Registers ........................................................................................... 70
ADC Registers ................................................................................................................... 74
McBSP Register Summary ...................................................................................................... 78
3.3-V eCAN Transceivers ...................................................................................................... 80
CAN Register Map .............................................................................................................. 83
SCI-A Registers .................................................................................................................. 85
SCI-B Registers .................................................................................................................. 85
SCI-C Registers ................................................................................................................. 85
SPI-A Registers................................................................................................................... 88
I2C-A Registers ................................................................................................................... 91
GPIO Registers .................................................................................................................. 93
GPIO-A Mux Peripheral Selection Matrix .................................................................................... 94
GPIO-B Mux Peripheral Selection Matrix .................................................................................... 95
GPIO-C Mux Peripheral Selection Matrix .................................................................................... 96
XINTF Configuration and Control Register Mapping ........................................................................ 99
Current Consumption by Power Supply Pins ............................................................................... 103
Typical Current Consumption by Various Peripherals (at 150 MHz) .................................................... 105
Clocking Nomenclature for TC = -55°C to 125°C (150-MHz Devices) ................................................... 110
Clocking Nomenclature for TC = 210°C (100-MHz Devices) .............................................................. 110
Input Clock Frequency ......................................................................................................... 111
XCLKIN Timing Requirements - PLL Enabled ............................................................................. 111
2-1
Hardware Features
2-2
Pin Out Information
2-3
2-4
2-5
3-1
3-2
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
6-1
6-2
6-3
6-4
6-5
6-6
司
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有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
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专
3-3
Copyright © 2010–2012, Texas Instruments Incorporated
List of Tables
7
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
www.ti.com
.............................................................................
......................................................
Power Management and Supervisory Circuit Solutions ...................................................................
Reset (XRS) Timing Requirements ..........................................................................................
General-Purpose Output Switching Characteristics ........................................................................
General-Purpose Input Timing Requirements ..............................................................................
IDLE Mode Timing Requirements ...........................................................................................
IDLE Mode Switching Characteristics .......................................................................................
STANDBY Mode Timing Requirements .....................................................................................
STANDBY Mode Switching Characteristics ................................................................................
HALT Mode Timing Requirements ...........................................................................................
HALT Mode Switching Characteristics ......................................................................................
ePWM Timing Requirements .................................................................................................
ePWM Switching Characteristics ............................................................................................
Trip-Zone input Timing Requirements .......................................................................................
High Resolution PWM Characteristics at SYSCLKOUT = (60 - 120 MHz)..............................................
Enhanced Capture (eCAP) Timing Requirement ..........................................................................
eCAP Switching Characteristics .............................................................................................
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements ..................................................
eQEP Switching Characteristics .............................................................................................
External ADC Start-of-Conversion Switching Characteristics .............................................................
External Interrupt Timing Requirements ....................................................................................
External Interrupt Switching Characteristics ................................................................................
I2C Timing ......................................................................................................................
SPI Master Mode External Timing (Clock Phase = 0) ....................................................................
SPI Master Mode External Timing (Clock Phase = 1) ....................................................................
SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................
SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................
Relationship Between Parameters Configured in XTIMING and Duration of Pulse ...................................
XINTF Clock Configurations ...................................................................................................
External Interface Read Timing Requirements .............................................................................
External Interface Read Switching Characteristics .........................................................................
External Interface Write Switching Characteristics .........................................................................
External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ...................................
External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) .......................................
Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) .......................................
Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) .......................................
External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ...................................
Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) .......................................
Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ......................................
XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ......................................................
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) .................................................
ADC Electrical Characteristics (over recommended operating conditions) ............................................
ADC Power-Up Delays .........................................................................................................
Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ..............................
Sequential Sampling Mode Timing ...........................................................................................
Simultaneous Sampling Mode Timing .......................................................................................
McBSP Timing Requirements ................................................................................................
6-7
XCLKIN Timing Requirements - PLL Disabled
111
6-8
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
111
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
6-48
6-49
6-50
6-51
6-52
6-53
6-54
8
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
6-16
List of Tables
112
114
115
116
118
118
118
119
120
120
122
122
122
123
123
123
123
123
124
124
124
125
126
128
129
131
132
135
136
136
137
139
139
139
139
142
142
142
145
146
148
149
149
151
152
154
Copyright © 2010–2012, Texas Instruments Incorporated
SM320F28335-HT
www.ti.com
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
...........................................................................................
6-55
McBSP Switching Characteristics
6-56
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................ 156
6-57
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ............................ 156
6-58
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................ 157
6-59
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ............................ 157
6-60
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................ 158
6-61
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ............................ 158
6-62
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................ 159
6-63
...........................
Flash Endurance ...............................................................................................................
Flash Parameters at 150-MHz SYSCLKOUT ...............................................................................
Flash/OTP Access Timing .....................................................................................................
Minimum Required Flash/OTP Wait-States at Different Frequencies ...................................................
Thermal Model of 181-Pin GB ................................................................................................
6-65
6-66
6-67
7-1
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6-64
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
Copyright © 2010–2012, Texas Instruments Incorporated
List of Tables
154
159
160
160
160
161
162
9
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
www.ti.com
Digital Signal Controller (DSC)
1
SM320F28335 DSC
1.1
Features
• High-Performance Static CMOS Technology
– Up to 150 MHz for TC = -55°C to 125°C
and Up to 100 MHZ for TC = 210°C
– 1.9-V Core, 3.3-V I/O Design
• High-Performance 32-Bit CPU
– IEEE-754 Single-Precision Floating-Point
Unit (FPU) )
– 16 x 16 and 32 x 32 MAC Operations
– 16 x 16 Dual MAC
– Harvard Bus Architecture
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– Code-Efficient (in C/C++ and Assembly)
• Six Channel DMA Controller (for ADC, McBSP,
ePWM, XINTF, and SARAM)
• 16-bit or 32-bit External Interface (XINTF)
– Over 2M x 16 Address Reach
• On-Chip Memory
– 256K x 16 Flash, 34K x 16 SARAM
– 1K x 16 OTP ROM
• Boot ROM (8K x 16)
– With Software Boot Modes (via SCI, SPI,
CAN, I2C, McBSP, XINTF, and Parallel I/O)
– Standard Math Tables
• Clock and System Control
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Watchdog Timer Module
• GPIO0 to GPIO63 Pins Can Be Connected to
One of the Eight External Core Interrupts
• Peripheral Interrupt Expansion (PIE) Block That
Supports All 58 Peripheral Interrupts
• 128-Bit Security Key/Lock
– Protects Flash/OTP/RAM Blocks
– Prevents Firmware Reverse Engineering
• Enhanced Control Peripherals
– Up to 18 PWM Outputs
– Up to 6 HRPWM Outputs With 150 ps MEP
12
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•
•
Resolution
– Up to 6 Event Capture Inputs
– Up to 2 Quadrature Encoder Interfaces
– Up to 8 32-bit/Nine 16-bit Timers
Three 32-Bit CPU Timers
Serial Port Peripherals
– Up to 2 CAN Modules
– Up to 3 SCI (UART) Modules
– Up to 2 McBSP Modules (Configurable as
SPI)
– One SPI Module
– One Inter-Integrated-Circuit (I2C) Bus
12-Bit ADC, 16 Channels
– 80-ns Conversion Rate
– 2 x 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single/Simultaneous Conversions
– Internal or External Reference
Up to 88 Individually Programmable,
Multiplexed GPIO Pins With Input Filtering
JTAG Boundary Scan Support (1)
Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware
Development Support Includes
– ANSI C/C++ Compiler/Assembler/Linker
– Code Composer Studio™ IDE
– DSP/BIOS™
– Digital Motor Control and Digital Power
Software Libraries
Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
Package Option
– Ceramic Pin Grid Array (GB)
Temperature Range:
– –55°C to 210°C
1.2
•
•
•
•
•
•
•
•
•
•
•
(1)
IEEE Standard 1149.1-1990 Standard Test Access Port and
Boundary Scan Architecture
SUPPORTS EXTREME TEMPERATURE APPLICATIONS
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio, DSP/BIOS are trademarks of Texas Instruments.
Copyright © 2010–2012, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
SM320F28335-HT
www.ti.com
•
•
•
•
•
(2)
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Available in Extreme (–55°C/210°C)
Temperature Range (2)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with
design and process enhancements to maximize performance over extended temperatures.
Custom temperature ranges available
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SM320F28335 DSC
11
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
2
www.ti.com
Introduction
The SM320F28335 is a highly integrated, high-performance solution for demanding control applications.
Throughout this document, the device is abbreviated as F28335. Table 2-1 provides a summary of
features.
Table 2-1. Hardware Features
FEATURE
F28335
–
6.66 ns
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Instruction cycle
TC = -55°C to 125°C
TYPE (1)
TC = 210°C
–
10 ns
Floating-point Unit
–
Yes
3.3-V on-chip flash (16-bit word)
–
256K
Single-access RAM (SARAM) (16-bit word)
–
34K
One-time programmable (OTP) ROM
(16-bit word)
–
1K
Code security for on-chip flash/SARAM/OTP blocks
–
Yes
Boot ROM (8K X16)
–
Yes
16/32-bit External Interface (XINTF)
1
Yes
6-channel Direct Memory Access (DMA)
0
Yes
PWM outputs
0
ePWM1/2/3/4/5/6
HRPWM channels
0
ePWM1A/2A/3A/4A/5A/6A
32-bit Capture inputs or auxiliary PWM outputs
0
6
32-bit QEP channels (four inputs/channel)
0
2
Watchdog timer
–
Yes
2
12.5
No. of channels
12-Bit ADC
16
MSPS
Conversion time
80 ns
32-Bit CPU timers
–
3
Multichannel Buffered Serial Port (McBSP)/SPI
1
2
Serial Peripheral Interface (SPI)
0
1
Serial Communications Interface (SCI)
0
3
Enhanced Controller Area Network (eCAN)
0
2
Inter-Integrated Circuit (I2C)
0
1
General Purpose I/O pins (shared)
–
88
External interrupts
–
8
181-pin GB
–
Yes
–55°C to 210°C
–
Yes
Packaging
Temperature range
(1)
12
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module.
Introduction
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2.1
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Pin Assignments
The 181-pin ceramic pin grid array (CPGA) terminal assignments are shown in Figure 2-1. Table 2-2 gives
the pin out information and Table 2-5 describes the function(s) of each pin.
1.400 (35,56) TYP
0.100 (2,54) TYP
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R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Bottom View
Figure 2-1. 181-Pin GB
Table 2-2. Pin Out Information
PIN
FUNCTION
A1
NC
M1
ADCINA0
L1
ADCINA1
K1
ADCINA2
J1
ADCINA3
P2
ADCINA4
N2
ADCINA5
M2
ADCINA6
L2
ADCINA7
M6
ADCINB0
M7
ADCINB1
R2
ADCINB2
R3
ADCINB3
R4
ADCINB4
R5
ADCINB5
R6
ADCINB6
R7
ADCINB7
N1
ADCLO
P3
ADCREFIN
P4
ADCREFM
P5
ADCREFP
P6
ADCRESEXT
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Introduction
13
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
www.ti.com
Table 2-2. Pin Out Information (continued)
R11
EMU0
R12
EMU1
F1
GPIO0/EPWM1A
G1
GPIO1/EPWM1B/ECAP6/MFSRB
E4
GPIO10/EPWM6A/CANRXB/ADCSOCBO
F4
GPIO11/EPWM6B/SCIRXDB/ECAP4
G4
GPIO12/TZ1/CANTXB/MDXB
J4
GPIO13/TZ2/CANRXB/MDRB
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K4
GPIO14/TX3/XHOLD/SCITXDB/MCLKXB
L4
GPIO15/TZ4/XHOLDA/SCIRXDB/MFSXB
M4
GPIO16//SPISIMOA/CANTXB/TZ5
J3
GPIO17/SPIOMIA/CANRXB/TZ6
N7
GPIO18/SPICLKA/SCITXDB/CANRXA
M8
GPIO19/SPISTEA/SCIRXDB/CANTXA
H1
GPIO2/EPWM2A
M9
GPIO20/EQEP1A/MDXA/CANTXB
M10
GPIO21/EQEP1B/MDRA/CANRXB
M11
GPIO22/EQEP1S/MCLKXA/SCITXDB
L8
14
GPIO23/EQEP1I/MFSXA/SCIRXDB
M12
GPIO24/ECAP1/EQEP2A.MDXB
N8
GPIO25/ECAP2/EQEP2B/MDRB
N11
GPIO26/ECAP3/EQEP2I/MCLKXB
N12
GPIO27/ECAP4/EQEP2S/MFSX
A9
GPIO28/SCIRXDA/XZCS6
C1
GPIO29/SCITXDA/XA19
E2
GPIO3/EPWM2B/ECAP5/MCLKRB
B1
GPIO30/CANRXA/XA18
A2
GPIO31/CANTXA/XA17
N13
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
P8
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
B13
GPIO34/ECAP1/XREADY
C11
GPIO35/SCITXDA/XR/1
B10
GPIO36/SCIRXDA/XZCS0
C9
GPIO37/ECAP2/XZCS7
A13
GPIO38/nXWEO
A3
GPIO39/XA16
F2
GPIO4/EPWM3A
D8
GPIO40/XA0/XWE1
D7
GPIO41/XA1
D6
GPIO42/XA2
D4
GPIO43/XA3
C8
GPIO44/XA4
C7
GPIO45/XA5
C4
GPIO46/XA6
C3
GPIO47/XA7
R14
GPIO48/ECAP5/XD31
P15
GPIO49/ECAP6/XD30
G2
GPIO5/EPWM3B/MFSRA/ECAP1
Introduction
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Table 2-2. Pin Out Information (continued)
N15
GPIO50/EQEP1A/XD29
M15
GPIO51/EQEP1B/XD28
J15
GPIO52/EQEP1S/XD27
H15
GPIO53/EQEP1I/XD26
N14
GPIO54/SPISIMOA/XD25
M14
GPIO55/SPISOMIA/XD24
L14
GPIO56/SPICLKA/XD23
K14
GPIO57/SPISTEA/XD22
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J14
GPIO58/MCLKRA/XD21
H12
GPIO59/MFSRA/XD20
H2
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
H11
GPIO60/MCLKRB/XD19
G12
GPIO61/MFSRB/XD18
F12
GPIO62/SCIRXDC/XD17
E12
GPIO63/SCITXDC/XD16
D12
GPIO64/XD15
G13
GPIO65/XD14
D13
GPIO66/XD13
F14
GPIO67/XD12
E14
GPIO68/XD11
D14
GPIO69/XD10
F3
GPIO7/EPWM4B/MCLKRA/ECAP2
G15
GPIO70/XD9
F15
GPIO71/XD8
E15
GPIO72/XD7
D15
GPIO73/XD6
C15
GPIO74/XD5
B15
GPIO75/XD4
D11
GPIO76/XD3
D10
GPIO77/XD2
D9
GPIO78/XD1
A14
GPIO79/XD0
G3
GPIO8/EPWM5A/CANTXB/ADCSOCAO
B8
GPIO80/XA8
B7
GPIO81/XA9
B6
GPIO82/XA10
B3
GPIO83/XA11
B2
GPIO84/XA12
A6
GPIO85/XA13
A5
GPIO86/XA14
A4
GPIO87/XA15
H3
GPIO9/EPWM5B/SCITXDB/ECAP3
R13
TCK
P9
TDI
P10
TDO
P14
TEST1
R8
TEST2
P12
TMS
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Introduction
15
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
www.ti.com
Table 2-2. Pin Out Information (continued)
P11
TRSTn
A11
VDD
B14
VDD
B4
VDD
B9
VDD
D5
VDD
E1
VDD
E3
VDD
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16
F13
VDD
H14
VDD
H5
VDD
J12
VDD
K3
VDD
N6
VDD
M3
VDD1A18
N4
VDD2A18
R10
VDD3VFL
K2
VDDA2
M5
VDDAIO
A8
VDDIO
B12
VDDIO
C6
VDDIO
D2
VDDIO
G14
VDDIO
K15
VDDIO
L12
VDDIO
N10
VDDIO
A10
VSS
A7
VSS
B11
VSS
B5
VSS
C12
VSS
C13
VSS
C14
VSS
C2
VSS
C5
VSS
D1
VSS
D3
VSS
E13
VSS
E8
VSS
H13
VSS
H4
VSS
K12
VSS
L13
VSS
L15
VSS
L3
VSS
N5
VSS
N9
VSS
Introduction
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Table 2-2. Pin Out Information (continued)
R9
VSS
N3
VSS1AGND
P7
VSS2AGND
J2
VSSA2
P1
VSSAIO
K13
X1
M13
X2
J13
XCLKIN
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A12
XCLKOUT
C10
XRD
P13
XRSn
A15
NC
R1
NC
R15
NC
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17
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
2.2
www.ti.com
Die Layout
The SM320F28335 die layout is shown in Figure 2-2. See Table 2-3 for a description of each pad's
function.
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Figure 2-2. SM320F28335 Die Layout
Table 2-3. Bare Die Information
18
DIE SIZE
DIE PAD SIZE
DIE PAD
COORDINATES
DIE
THICKNESS
DIE PAD
COMPOSITION
BACKSIDE
FINISH
BACKSIDE
POTENTIAL
238.228 x 235.252
(mils)
55.0 x 65.0
(microns)
See Table 2-4
11.0 mils
AlCu/TiN
Silicon with
backgrind
Ground
Introduction
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Table 2-4. Die Pad Information
DIE PAD CO-ORDINATES (microns)
PAD CENTER (microns)
PAD SIZE (microns)
SIGNAL
NAME
Xmin
Ymin
Xmax
Ymax
Xc
Yc
X
Y
1
GPIO30
183.995
10.08
239.015
75.18
211.505
42.63
55.02
65.1
2
GPIO29
307.965
10.08
362.985
75.18
335.475
42.63
55.02
65.1
3
VSS
422.135
10.08
477.155
75.18
449.645
42.63
55.02
65.1
4
VSS
484.925
10.08
539.945
75.18
512.435
42.63
55.02
65.1
5
VSS
547.715
10.08
602.735
75.18
575.225
42.63
55.02
65.1
6
VSS
610.505
10.08
665.525
75.18
638.015
42.63
55.02
65.1
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
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PAD
VSS
673.295
10.08
728.315
75.18
700.805
42.63
55.02
65.1
VDD
736.085
10.08
791.105
75.18
763.595
42.63
55.02
65.1
VDD
798.875
10.08
853.895
75.18
826.385
42.63
55.02
65.1
VDD
861.665
10.08
916.685
75.18
889.175
42.63
55.02
65.1
VDD
924.455
10.08
979.475
75.18
951.965
42.63
55.02
65.1
VDD
987.245
10.08
1042.265
75.18
1014.755
42.63
55.02
65.1
GPIO0
1057.245
10.08
1112.265
75.18
1084.755
42.63
55.02
65.1
GPIO1
1137.045
10.08
1192.065
75.18
1164.555
42.63
55.02
65.1
GPIO2
1216.845
10.08
1271.865
75.18
1244.355
42.63
55.02
65.1
VSS
1286.845
10.08
1341.865
75.18
1314.355
42.63
55.02
65.1
VDDIO
1356.845
10.08
1411.865
75.18
1384.355
42.63
55.02
65.1
GPIO3
1436.645
10.08
1491.665
75.18
1464.155
42.63
55.02
65.1
GPIO4
1516.445
10.08
1571.465
75.18
1543.955
42.63
55.02
65.1
GPIO5
1596.245
10.08
1651.265
75.18
1623.755
42.63
55.02
65.1
GPIO6
1676.045
10.08
1731.065
75.18
1703.555
42.63
55.02
65.1
VSS
1746.045
10.08
1801.065
75.18
1773.555
42.63
55.02
65.1
VDD
1808.835
10.08
1863.855
75.18
1836.345
42.63
55.02
65.1
VDD
1871.625
10.08
1926.645
75.18
1899.135
42.63
55.02
65.1
VDD
1934.415
10.08
1989.435
75.18
1961.925
42.63
55.02
65.1
VDD
1997.205
10.08
2052.225
75.18
2024.715
42.63
55.02
65.1
VDD
2059.995
10.08
2115.015
75.18
2087.505
42.63
55.02
65.1
GPIO7
2129.995
10.08
2185.015
75.18
2157.505
42.63
55.02
65.1
GPIO8
2209.795
10.08
2264.815
75.18
2237.305
42.63
55.02
65.1
GPIO9
2289.595
10.08
2344.615
75.18
2317.105
42.63
55.02
65.1
GPIO10
2369.395
10.08
2424.415
75.18
2396.905
42.63
55.02
65.1
GPIO11
2449.195
10.08
2504.215
75.18
2476.705
42.63
55.02
65.1
GPIO12
2528.995
10.08
2584.015
75.18
2556.505
42.63
55.02
65.1
VSS
2598.995
10.08
2654.015
75.18
2626.505
42.63
55.02
65.1
VSS
2661.785
10.08
2716.805
75.18
2689.295
42.63
55.02
65.1
VSS
2724.575
10.08
2779.595
75.18
2752.085
42.63
55.02
65.1
VSS
2787.365
10.08
2842.385
75.18
2814.875
42.63
55.02
65.1
VSS
2850.155
10.08
2905.175
75.18
2877.665
42.63
55.02
65.1
39
VDD
2912.945
10.08
2967.965
75.18
2940.455
42.63
55.02
65.1
40
VDD
2975.735
10.08
3030.755
75.18
3003.245
42.63
55.02
65.1
41
VDD
3038.525
10.08
3093.545
75.18
3066.035
42.63
55.02
65.1
42
VDD
3101.315
10.08
3156.335
75.18
3128.825
42.63
55.02
65.1
43
VDD
3164.105
10.08
3219.125
75.18
3191.615
42.63
55.02
65.1
44
GPIO13
3234.105
10.08
3289.125
75.18
3261.615
42.63
55.02
65.1
45
GPIO14
3313.905
10.08
3368.925
75.18
3341.415
42.63
55.02
65.1
46
GPIO15
3393.705
10.08
3448.725
75.18
3421.215
42.63
55.02
65.1
31
32
33
34
35
36
37
38
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-HT
Introduction
19
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
www.ti.com
Table 2-4. Die Pad Information (continued)
47
GPIO16
3473.505
10.08
3528.525
75.18
3501.015
42.63
55.02
65.1
48
GPIO17
3553.305
10.08
3608.325
75.18
3580.815
42.63
55.02
65.1
49
VDD
3623.305
10.08
3678.325
75.18
3650.815
42.63
55.02
65.1
50
VDD
3686.095
10.08
3741.115
75.18
3713.605
42.63
55.02
65.1
51
VDD
3748.885
10.08
3803.905
75.18
3776.395
42.63
55.02
65.1
52
VDD
3811.675
10.08
3866.695
75.18
3839.185
42.63
55.02
65.1
53
VDD
3874.465
10.08
3929.485
75.18
3901.975
42.63
55.02
65.1
54
VSS
3937.395
10.08
3992.415
75.18
3964.905
42.63
55.02
65.1
VDD1A18
4065.705
10.08
4120.725
75.18
4093.215
42.63
55.02
56
VSS1AGND
4191.425
10.08
4246.445
75.18
4218.935
42.63
55.02
65.1
57
VSSA2
4317.6
10.08
4372.62
75.18
4345.11
42.63
55.02
65.1
VDDA2
4444.685
10.08
4499.705
75.18
4472.195
42.63
55.02
65.1
59
ADCINA7
4575.305
10.08
4630.325
75.18
4602.815
42.63
55.02
65.1
60
ADCINA6
4704.91
10.08
4759.93
75.18
4732.42
42.63
55.02
65.1
61
ADCINA5
4838.47
10.08
4893.49
75.18
4865.98
42.63
55.02
65.1
62
ADCINA4
4947.565
10.08
5002.585
75.18
4975.075
42.63
55.02
65.1
63
ADCINA3
5094.81
10.08
5149.83
75.18
5122.32
42.63
55.02
65.1
64
ADCINA2
5208.28
10.08
5263.3
75.18
5235.79
42.63
55.02
65.1
65
ADCINA1
5350.555
10.08
5405.575
75.18
5378.065
42.63
55.02
65.1
66
ADCINA0
5475.26
10.08
5530.28
75.18
5502.77
42.63
55.02
65.1
67
ADCLO
5598.39
10.08
5653.41
75.18
5625.9
42.63
55.02
65.1
VSSAIO
5727.435
10.08
5782.455
75.18
5754.945
42.63
55.02
65.1
58
68
69
65.1
VDDAIO
5891.83
188.51
5956.93
243.53
5924.38
216.02
65.1
55.02
70
ADCINB0
5891.83
283.22
5956.93
338.24
5924.38
310.73
65.1
55.02
71
ADCINB1
5891.83
402.815
5956.93
457.835
5924.38
430.325
65.1
55.02
72
ADCINB2
5891.83
507.99
5956.93
563.01
5924.38
535.5
65.1
55.02
73
ADCINB3
5891.83
626.255
5956.93
681.275
5924.38
653.765
65.1
55.02
74
ADCINB4
5891.83
726.775
5956.93
781.795
5924.38
754.285
65.1
55.02
75
ADCINB5
5891.83
846.895
5956.93
901.915
5924.38
874.405
65.1
55.02
76
ADCINB6
5891.83
961.73
5956.93
1016.75
5924.38
989.24
65.1
55.02
77
ADCINB7
5891.83
1061.935
5956.93
1116.955
5924.38
1089.445
65.1
55.02
78
ADCREFIN
5891.83
1159.69
5956.93
1214.71
5924.38
1187.2
65.1
55.02
79
ADCREFM
5891.83
1274.525
5956.93
1329.545
5924.38
1302.035
65.1
55.02
80
ADCREFP
5891.83
1383.13
5956.93
1438.15
5924.38
1410.64
65.1
55.02
81
ADCRESEXT
5891.83
1498.07
5956.93
1553.09
5924.38
1525.58
65.1
55.02
82
VSS2AGND
5891.83
1610.14
5956.93
1665.16
5924.38
1637.65
65.1
55.02
83
VDD2A18
5891.83
1720.53
5956.93
1775.55
5924.38
1748.04
65.1
55.02
84
VSS
5891.83
1848.595
5956.93
1903.615
5924.38
1876.105
65.1
55.02
VSS
5891.83
1914.535
5956.93
1969.555
5924.38
1942.045
65.1
55.02
VSS
5891.83
1980.475
5956.93
2035.495
5924.38
2007.985
65.1
55.02
87
VSS
5891.83
2046.415
5956.93
2101.435
5924.38
2073.925
65.1
55.02
88
VSS
5891.83
2112.355
5956.93
2167.375
5924.38
2139.865
65.1
55.02
89
VDD
5891.83
2178.295
5956.93
2233.315
5924.38
2205.805
65.1
55.02
90
VDD
5891.83
2244.235
5956.93
2299.255
5924.38
2271.745
65.1
55.02
91
VDD
5891.83
2310.175
5956.93
2365.195
5924.38
2337.685
65.1
55.02
92
VDD
5891.83
2376.115
5956.93
2431.135
5924.38
2403.625
65.1
55.02
93
VDD
5891.83
2442.055
5956.93
2497.075
5924.38
2469.565
65.1
55.02
94
GPIO18
5891.83
2512.055
5956.93
2567.075
5924.38
2539.565
65.1
55.02
85
86
20
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
55
Introduction
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-HT
SM320F28335-HT
www.ti.com
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Table 2-4. Die Pad Information (continued)
95
GPIO19
5891.83
2591.855
5956.93
2646.875
5924.38
2619.365
65.1
55.02
96
GPIO20
5891.83
2671.655
5956.93
2726.675
5924.38
2699.165
65.1
55.02
97
GPIO21
5891.83
2751.455
5956.93
2806.475
5924.38
2778.965
65.1
55.02
98
GPIO22
5891.83
2831.255
5956.93
2886.275
5924.38
2858.765
65.1
55.02
99
GPIO23
5891.83
2911.055
5956.93
2966.075
5924.38
2938.565
65.1
55.02
100
GPIO24
5891.83
2990.855
5956.93
3045.875
5924.38
3018.365
65.1
55.02
101
GPIO25
5891.83
3070.655
5956.93
3125.675
5924.38
3098.165
65.1
55.02
102
VSS
5891.83
3140.655
5956.93
3195.675
5924.38
3168.165
65.1
55.02
104
105
106
107
108
109
110
111
112
113
114
115
116
117
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
103
VDDIO
5891.83
3210.655
5956.93
3265.675
5924.38
3238.165
65.1
55.02
GPIO26
5891.83
3290.455
5956.93
3345.475
5924.38
3317.965
65.1
55.02
GPIO27
5891.83
3370.255
5956.93
3425.275
5924.38
3397.765
65.1
55.02
GPIO32
5891.83
3450.055
5956.93
3505.075
5924.38
3477.565
65.1
55.02
GPIO33
5891.83
3529.855
5956.93
3584.875
5924.38
3557.365
65.1
55.02
NC
5891.83
3609.655
5956.93
3664.675
5924.38
3637.165
65.1
55.02
TDI
5891.83
3689.455
5956.93
3744.475
5924.38
3716.965
65.1
55.02
TDO
5891.83
3769.255
5956.93
3824.275
5924.38
3796.765
65.1
55.02
NC
5891.83
3893.225
5956.93
3948.245
5924.38
3920.735
65.1
55.02
TRSTN
5891.83
3973.025
5956.93
4028.045
5924.38
4000.535
65.1
55.02
TMS
5891.83
4052.825
5956.93
4107.845
5924.38
4080.335
65.1
55.02
VSS
5891.83
4122.825
5956.93
4177.845
5924.38
4150.335
65.1
55.02
XRSN
5891.83
4192.825
5956.93
4247.845
5924.38
4220.335
65.1
55.02
NC
5891.83
4298.21
5956.93
4353.23
5924.38
4325.72
65.1
55.02
TEST1
5891.83
4378.01
5956.93
4433.03
5924.38
4405.52
65.1
55.02
NC
5891.83
4457.81
5956.93
4512.83
5924.38
4485.32
65.1
55.02
TEST2
5891.83
4537.61
5956.93
4592.63
5924.38
4565.12
65.1
55.02
VSS
5891.83
4607.61
5956.93
4662.63
5924.38
4635.12
65.1
55.02
VSS
5891.83
4673.55
5956.93
4728.57
5924.38
4701.06
65.1
55.02
VSS
5891.83
4739.49
5956.93
4794.51
5924.38
4767
65.1
55.02
VSS
5891.83
4805.43
5956.93
4860.45
5924.38
4832.94
65.1
55.02
VSS
5891.83
4871.37
5956.93
4926.39
5924.38
4898.88
65.1
55.02
125
VDD3VFL
5891.83
4941.37
5956.93
4996.39
5924.38
4968.88
65.1
55.02
126
EMU0
5891.83
5021.17
5956.93
5076.19
5924.38
5048.68
65.1
55.02
118
119
120
121
122
123
124
127
128
129
130
EMU1
5891.83
5145.14
5956.93
5200.16
5924.38
5172.65
65.1
55.02
NC
5891.83
5269.11
5956.93
5324.13
5924.38
5296.62
65.1
55.02
TCK
5891.83
5348.91
5956.93
5403.93
5924.38
5376.42
65.1
55.02
NC
5891.83
5428.71
5956.93
5483.73
5924.38
5456.22
65.1
55.02
GPIO48
5891.83
5508.825
5956.93
5563.845
5924.38
5536.335
65.1
55.02
GPIO49
5727.995
5716.83
5783.015
5781.93
5755.505
5749.38
55.02
65.1
GPIO50
5604.025
5716.83
5659.045
5781.93
5631.535
5749.38
55.02
65.1
GPIO51
5480.055
5716.83
5535.075
5781.93
5507.565
5749.38
55.02
65.1
135
NC
5356.085
5716.83
5411.105
5781.93
5383.595
5749.38
55.02
65.1
136
VSS
5241.915
5716.83
5296.935
5781.93
5269.425
5749.38
55.02
65.1
137
VDDIO
5171.915
5716.83
5226.935
5781.93
5199.425
5749.38
55.02
65.1
138
GPIO52
5092.115
5716.83
5147.135
5781.93
5119.625
5749.38
55.02
65.1
139
GPIO53
4968.145
5716.83
5023.165
5781.93
4995.655
5749.38
55.02
65.1
140
GPIO54
4844.175
5716.83
4899.195
5781.93
4871.685
5749.38
55.02
65.1
141
GPIO55
4720.205
5716.83
4775.225
5781.93
4747.715
5749.38
55.02
65.1
142
VSS
4606.035
5716.83
4661.055
5781.93
4633.545
5749.38
55.02
65.1
131
132
133
134
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-HT
Introduction
21
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
www.ti.com
Table 2-4. Die Pad Information (continued)
143
GPIO56
4536.035
5716.83
4591.055
5781.93
4563.545
5749.38
55.02
65.1
144
GPIO57
4412.065
5716.83
4467.085
5781.93
4439.575
5749.38
55.02
65.1
145
GPIO58
4288.095
5716.83
4343.115
5781.93
4315.605
5749.38
55.02
65.1
146
VDD
4173.925
5716.83
4228.945
5781.93
4201.435
5749.38
55.02
65.1
147
X2
4112.5
5716.83
4167.52
5781.93
4140.01
5749.38
55.02
65.1
148
VSS
4051.075
5716.83
4106.095
5781.93
4078.585
5749.38
55.02
65.1
149
X1
3989.65
5716.83
4044.67
5781.93
4017.16
5749.38
55.02
65.1
150
XCLKIN
3919.65
5716.83
3974.67
5781.93
3947.16
5749.38
55.02
65.1
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
VSS
3849.65
5716.83
3904.67
5781.93
3877.16
5749.38
55.02
65.1
VDDIO
3779.65
5716.83
3834.67
5781.93
3807.16
5749.38
55.02
65.1
VSS
3709.65
5716.83
3764.67
5781.93
3737.16
5749.38
55.02
65.1
VDD
3648.225
5716.83
3703.245
5781.93
3675.735
5749.38
55.02
65.1
VDD
3586.8
5716.83
3641.82
5781.93
3614.31
5749.38
55.02
65.1
VDD
3525.375
5716.83
3580.395
5781.93
3552.885
5749.38
55.02
65.1
VDD
3463.95
5716.83
3518.97
5781.93
3491.46
5749.38
55.02
65.1
VDD
3402.525
5716.83
3457.545
5781.93
3430.035
5749.38
55.02
65.1
GPIO59
3332.525
5716.83
3387.545
5781.93
3360.035
5749.38
55.02
65.1
GPIO60
3208.555
5716.83
3263.575
5781.93
3236.065
5749.38
55.02
65.1
GPIO61
3084.585
5716.83
3139.605
5781.93
3112.095
5749.38
55.02
65.1
GPIO62
2960.615
5716.83
3015.635
5781.93
2988.125
5749.38
55.02
65.1
GPIO63
2836.645
5716.83
2891.665
5781.93
2864.155
5749.38
55.02
65.1
GPIO64
2712.675
5716.83
2767.695
5781.93
2740.185
5749.38
55.02
65.1
GPIO65
2588.705
5716.83
2643.725
5781.93
2616.215
5749.38
55.02
65.1
VDD
2474.535
5716.83
2529.555
5781.93
2502.045
5749.38
55.02
65.1
VDD
2413.11
5716.83
2468.13
5781.93
2440.62
5749.38
55.02
65.1
VDD
2351.685
5716.83
2406.705
5781.93
2379.195
5749.38
55.02
65.1
VDD
2290.26
5716.83
2345.28
5781.93
2317.77
5749.38
55.02
65.1
VDD
2228.835
5716.83
2283.855
5781.93
2256.345
5749.38
55.02
65.1
VSS
2167.41
5716.83
2222.43
5781.93
2194.92
5749.38
55.02
65.1
GPIO66
2097.41
5716.83
2152.43
5781.93
2124.92
5749.38
55.02
65.1
VSS
1983.24
5716.83
2038.26
5781.93
2010.75
5749.38
55.02
65.1
VDDIO
1913.24
5716.83
1968.26
5781.93
1940.75
5749.38
55.02
65.1
GPIO67
1833.44
5716.83
1888.46
5781.93
1860.95
5749.38
55.02
65.1
GPIO68
1709.47
5716.83
1764.49
5781.93
1736.98
5749.38
55.02
65.1
GPIO69
1585.5
5716.83
1640.52
5781.93
1613.01
5749.38
55.02
65.1
VSS
1471.33
5716.83
1526.35
5781.93
1498.84
5749.38
55.02
65.1
VSS
1409.905
5716.83
1464.925
5781.93
1437.415
5749.38
55.02
65.1
VSS
1348.48
5716.83
1403.5
5781.93
1375.99
5749.38
55.02
65.1
VSS
1287.055
5716.83
1342.075
5781.93
1314.565
5749.38
55.02
65.1
VSS
1225.63
5716.83
1280.65
5781.93
1253.14
5749.38
55.02
65.1
183
VDD
1164.205
5716.83
1219.225
5781.93
1191.715
5749.38
55.02
65.1
184
VDD
1102.78
5716.83
1157.8
5781.93
1130.29
5749.38
55.02
65.1
185
VDD
1041.355
5716.83
1096.375
5781.93
1068.865
5749.38
55.02
65.1
186
VDD
979.93
5716.83
1034.95
5781.93
1007.44
5749.38
55.02
65.1
187
VDD
918.505
5716.83
973.525
5781.93
946.015
5749.38
55.02
65.1
188
GPIO70
848.505
5716.83
903.525
5781.93
876.015
5749.38
55.02
65.1
189
GPIO71
724.535
5716.83
779.555
5781.93
752.045
5749.38
55.02
65.1
190
GPIO72
600.565
5716.83
655.585
5781.93
628.075
5749.38
55.02
65.1
172
173
174
175
176
177
178
179
180
181
182
22
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151
Introduction
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Table 2-4. Die Pad Information (continued)
GPIO73
476.595
5716.83
531.615
5781.93
504.105
5749.38
55.02
65.1
192
GPIO74
352.625
5716.83
407.645
5781.93
380.135
5749.38
55.02
65.1
193
GPIO75
228.165
5716.83
283.185
5781.93
255.675
5749.38
55.02
65.1
194
GPIO76
10.08
5552.995
75.18
5608.015
42.63
5580.505
65.1
55.02
195
GPIO77
10.08
5429.025
75.18
5484.045
42.63
5456.535
65.1
55.02
196
GPIO78
10.08
5305.055
75.18
5360.075
42.63
5332.565
65.1
55.02
197
GPIO79
10.08
5181.085
75.18
5236.105
42.63
5208.595
65.1
55.02
198
GPIO38
10.08
5057.115
75.18
5112.135
42.63
5084.625
65.1
55.02
199
XCLKOUT
10.08
4933.145
75.18
4988.165
42.63
4960.655
65.1
55.02
200
VDD
10.08
4818.975
75.18
4873.995
42.63
4846.485
65.1
55.02
VDD
10.08
4753.175
75.18
4808.195
42.63
4780.685
65.1
55.02
VDD
10.08
4687.375
75.18
4742.395
42.63
4714.885
65.1
55.02
VDD
10.08
4621.575
75.18
4676.595
42.63
4649.085
65.1
55.02
VDD
10.08
4555.775
75.18
4610.795
42.63
4583.285
65.1
55.02
VSS
10.08
4489.975
75.18
4544.995
42.63
4517.485
65.1
55.02
GPIO28
10.08
4419.975
75.18
4474.995
42.63
4447.485
65.1
55.02
GPIO34
10.08
4296.005
75.18
4351.025
42.63
4323.515
65.1
55.02
VDDIO
10.08
4216.205
75.18
4271.225
42.63
4243.715
65.1
55.02
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
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191
VSS
10.08
4146.205
75.18
4201.225
42.63
4173.715
65.1
55.02
GPIO36
10.08
4076.205
75.18
4131.225
42.63
4103.715
65.1
55.02
VDD
10.08
3962.035
75.18
4017.055
42.63
3989.545
65.1
55.02
VDD
10.08
3896.235
75.18
3951.255
42.63
3923.745
65.1
55.02
VDD
10.08
3830.435
75.18
3885.455
42.63
3857.945
65.1
55.02
VDD
10.08
3764.635
75.18
3819.655
42.63
3792.145
65.1
55.02
VDD
10.08
3698.835
75.18
3753.855
42.63
3726.345
65.1
55.02
VSS
10.08
3633.035
75.18
3688.055
42.63
3660.545
65.1
55.02
GPIO35
10.08
3563.035
75.18
3618.055
42.63
3590.545
65.1
55.02
XRDN
10.08
3439.065
75.18
3494.085
42.63
3466.575
65.1
55.02
GPIO37
10.08
3315.095
75.18
3370.115
42.63
3342.605
65.1
55.02
VSS
10.08
3200.925
75.18
3255.945
42.63
3228.435
65.1
55.02
GPIO40
10.08
3130.925
75.18
3185.945
42.63
3158.435
65.1
55.02
GPIO41
10.08
3006.955
75.18
3061.975
42.63
3034.465
65.1
55.02
GPIO42
10.08
2882.985
75.18
2938.005
42.63
2910.495
65.1
55.02
VDD
10.08
2768.815
75.18
2823.835
42.63
2796.325
65.1
55.02
VDD
10.08
2703.015
75.18
2758.035
42.63
2730.525
65.1
55.02
VDD
10.08
2637.215
75.18
2692.235
42.63
2664.725
65.1
55.02
VDD
10.08
2571.415
75.18
2626.435
42.63
2598.925
65.1
55.02
VDD
10.08
2505.615
75.18
2560.635
42.63
2533.125
65.1
55.02
VSS
10.08
2439.815
75.18
2494.835
42.63
2467.325
65.1
55.02
GPIO43
10.08
2369.815
75.18
2424.835
42.63
2397.325
65.1
55.02
231
GPIO44
10.08
2245.845
75.18
2300.865
42.63
2273.355
65.1
55.02
232
GPIO45
10.08
2121.875
75.18
2176.895
42.63
2149.385
65.1
55.02
233
VDDIO
10.08
1997.905
75.18
2052.925
42.63
2025.415
65.1
55.02
234
VSS
10.08
1927.905
75.18
1982.925
42.63
1955.415
65.1
55.02
235
GPIO46
10.08
1857.905
75.18
1912.925
42.63
1885.415
65.1
55.02
236
GPIO47
10.08
1733.935
75.18
1788.955
42.63
1761.445
65.1
55.02
237
GPIO80
10.08
1609.965
75.18
1664.985
42.63
1637.475
65.1
55.02
238
GPIO81
10.08
1485.995
75.18
1541.015
42.63
1513.505
65.1
55.02
230
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Introduction
23
SM320F28335-HT
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
www.ti.com
Table 2-4. Die Pad Information (continued)
239
GPIO82
10.08
1362.025
75.18
1417.045
42.63
1389.535
65.1
55.02
240
VSS
10.08
1247.855
75.18
1302.875
42.63
1275.365
65.1
55.02
241
VDD
10.08
1182.055
75.18
1237.075
42.63
1209.565
65.1
55.02
242
GPIO83
10.08
1112.055
75.18
1167.075
42.63
1139.565
65.1
55.02
243
GPIO84
10.08
988.085
75.18
1043.105
42.63
1015.595
65.1
55.02
244
VDDIO
10.08
864.115
75.18
919.135
42.63
891.625
65.1
55.02
245
VSS
10.08
794.115
75.18
849.135
42.63
821.625
65.1
55.02
246
GPIO85
10.08
724.115
75.18
779.135
42.63
751.625
65.1
55.02
248
249
250
251
24
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247
GPIO86
10.08
600.145
75.18
655.165
42.63
627.655
65.1
55.02
GPIO87
10.08
476.175
75.18
531.195
42.63
503.685
65.1
55.02
GPIO39
10.08
352.205
75.18
407.225
42.63
379.715
65.1
55.02
GPIO31
10.08
228.165
75.18
283.185
42.63
255.675
65.1
55.02
Test Pad
4.9
5722.08
69.93
5787.11
37.415
5754.595
65.03
65.03
Introduction
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2.3
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Signal Descriptions
Table 2-5 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available
in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All pins capable of producing an
XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured
for XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise
indicated). All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled
on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0-GPIO11 pins are not
enabled at reset. The pullups on GPIO12-GPIO34 are enabled upon reset.
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Table 2-5. Signal Descriptions
NAME
DESCRIPTION
(1)
JTAG
TRST
TCK
TMS
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of
the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset
signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An
external pulldown resistor is recommended on this pin. The value of this resistor should be based on drive strength of
the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board be validated for proper operation of the debugger and
the application. (I, ↓)
JTAG test clock with internal pullup (I, ↑)
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the
rising edge of TCK. (I, ↑)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a
rising edge of TCK. (I, ↑)
TDI
TDO
EMU0
EMU1
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of
TDO on the falling edge of TCK. (O/Z 8 mA drive)
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode.
With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would
latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the
drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate.
Since this is application-specific, it is recommended that each target board be validated for proper operation of the
debugger and the application.
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode.
With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would
latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the
drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate.
Since this is application-specific, it is recommended that each target board be validated for proper operation of the
debugger and the application.
FLASH
VDD3VFL
TEST1
TEST2
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
XCLKOUT
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or onefourth the frequency of SYSCLKOUT. This is controlled by bits 18:16 (XTIMCLK) and bit 2 (CLKMODE) in the
XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting
XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a
reset. (O/Z, 8 mA drive).
XCLKIN
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the X1 pin must be
tied to GND. If a crystal/resonator is used (or if an external 1.9-V oscillator is used to feed clock to X1 pin), this pin
must be tied to GND. (I)
(1)
I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
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Table 2-5. Signal Descriptions (continued)
NAME
DESCRIPTION
(1)
X1
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be
connected across X1 and X2. The X1 pin is referenced to the 1.9-V core digital power supply. A 1.9-V external
oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V
external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)
X2
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not
used it must be left unconnected. (O)
XRS
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the
location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This
pin is driven low by the DSC when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin be driven by an
open-drain device.
RESET
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ADC SIGNALS
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCLO
ADCRESEXT
ADCREFIN
ADCREFP
ADCREFM
ADC Group A, Channel 7 input (I)
ADC Group A, Channel 6 input (I)
ADC Group A, Channel 5 input (I)
ADC Group A, Channel 4 input (I)
ADC Group A, Channel 3 input (I)
ADC Group A, Channel 2 input (I)
ADC Group A, Channel 1 input (I)
ADC Group A, Channel 0 input (I)
ADC Group B, Channel 7 input (I)
ADC Group B, Channel 6 input (I)
ADC Group B, Channel 5 input (I)
ADC Group B, Channel 4 input (I)
ADC Group B, Channel 3 input (I)
ADC Group B, Channel 2 input (I)
ADC Group B, Channel 1 input (I)
ADC Group B, Channel 0 input (I)
Low Reference (connect to analog ground) (I)
ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
External reference input (I)
Internal Reference Positive Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor of 2.2 μF to
analog ground. (O)
Internal Reference Medium Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor of 2.2 μF to
analog ground. (O)
CPU AND I/O POWER PINS
VDDA2
ADC Analog Power Pin
VSSA2
ADC Analog Ground Pin
VDDAIO
ADC Analog I/O Power Pin
VSSAIO
ADC Analog I/O Ground Pin
VDD1A18
ADC Analog Power Pin
VSS1AGND
ADC Analog Ground Pin
VDD2A18
ADC Analog Power Pin
VSS2AGND
ADC Analog Ground Pin
VDD
CPU and Logic Digital Power Pin
VDDIO
Digital I/O Power Pin
VSS
Digital Ground Pin
26
Introduction
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Table 2-5. Signal Descriptions (continued)
NAME
DESCRIPTION
(1)
GPIOA AND PERIPHERAL SIGNALS
GPIO0
EPWM1A
-
General purpose input/output 0 (I/O/Z)
Enhanced PWM1 Output A and HRPWM channel (O)
-
GPIO1
EPWM1B
ECAP6
MFSRB
General purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
GPIO3
EPWM2B
ECAP5
MCLKRB
GPIO4
EPWM3A
GPIO5
EPWM3B
MFSRA
ECAP1
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GPIO2
EPWM2A
-
General purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
General purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
General purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
General purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
General purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
EPWM4B
MCLKRA
ECAP2
General purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
Enhanced capture input/output 2 (I/O)
GPIO8
EPWM5A
CANTXB
ADCSOCAO
GPIO9
EPWM5B
SCITXDB
ECAP3
GPIO10
EPWM6A
CANRXB
ADCSOCBO
GPIO11
EPWM6B
SCIRXDB
ECAP4
GPIO12
TZ1
CANTXB
MDXB
General Purpose Input/Output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
ADC start-of-conversion A (O)
General purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
Enhanced capture input/output 3 (I/O)
General purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
ADC start-of-conversion B (O)
General purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
General purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB
General purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14
General purpose input/output 14 (I/O/Z)
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
www.ti.com
Table 2-5. Signal Descriptions (continued)
NAME
DESCRIPTION
(1)
TZ3/XHOLD
Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface (XINTF) to
release the external bus and place all buses and strobes into a high-impedance state. To prevent this from
happening when TZ3 signal goes active, disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the
XINTF bus will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by
default, unless they are enabled by the code. The XINTF will release the bus when any current access is complete
and there are no pending accesses on the XINTF. (I)
SCITXDB
MCLKXB
SCI-B Transmit (I)
McBSP-B transmit clock (I/O)
GPIO15
General purpose input/output 15 (I/O/Z)
SCIRXDB
MFSXB
GPIO16
SPISIMOA
CANTXB
TZ5
GPIO17
SPISOMIA
CANRXB
TZ6
GPIO18
SPICLKA
SCITXDB
CANRXA
GPIO19
SPISTEA
SCIRXDB
CANTXA
GPIO20
EQEP1A
MDXA
CANTXB
GPIO21
EQEP1B
MDRA
CANRXB
GPIO22
EQEP1S
MCLKXA
SCITXDB
GPIO23
EQEP1I
MFSXA
SCIRXDB
GPIO24
ECAP1
EQEP2A
MDXB
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TZ4/XHOLDA
Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the direction chosen in the
GPADIR register. If the pin is configured as an input, then TZ4 function is chosen. If the pin is configured as an
output, then XHOLDA function is chosen. XHOLDA is driven active (low) when the XINTF has granted an XHOLD
request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the
XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). (I/0)
SCI-B receive (I)
McBSP-B transmit frame synch (I/O)
General purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
General purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
General purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
Enhanced CAN-A receive (I)
General purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
Enhanced CAN-A transmit (O)
General purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
General purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
General purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
General purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
General purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB
General purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB
General purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
28
Introduction
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Table 2-5. Signal Descriptions (continued)
NAME
DESCRIPTION
General purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6
General purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
GPIO29
SCITXDA
XA19
General purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18
GPIO31
CANTXA
XA17
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
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GPIO27
ECAP4
EQEP2S
MFSXB
General purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
General purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
General purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
General-Purpose Input/Output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY
General-Purpose Input/Output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal
GPIO35
SCITXDA
XR/W
GPIO36
SCIRXDA
XZCS0
GPIO37
ECAP2
XZCS7
GPIO38
XWE0
GPIO39
XA16
GPIO40
XA0/XWE1
GPIO41
XA1
GPIO42
XA2
(1)
General-Purpose Input/Output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
General-Purpose Input/Output 36 (I/O/Z)
SCI receive data (I)
External Interface zone 0 chip select (O)
General-Purpose Input/Output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
General-Purpose Input/Output 38 (I/O/Z)
External Interface Write Enable 0 (O)
General-Purpose Input/Output 39 (I/O/Z)
External Interface Address Line 16 (O)
General-Purpose Input/Output 40 (I/O/Z)
External Interface Address Line 0/External Interface Write Enable 1 (O)
General-Purpose Input/Output 41 (I/O/Z)
External Interface Address Line 1 (O)
General-Purpose Input/Output 42 (I/O/Z)
External Interface Address Line 2 (O)
GPIO43
XA3
General-Purpose Input/Output 43 (I/O/Z)
External Interface Address Line 3 (O)
GPIO44
XA4
General-Purpose Input/Output 44 (I/O/Z)
External Interface Address Line 4 (O)
GPIO45
XA5
General-Purpose Input/Output 45 (I/O/Z)
External Interface Address Line 5 (O)
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www.ti.com
Table 2-5. Signal Descriptions (continued)
NAME
DESCRIPTION
GPIO46
XA6
General-Purpose Input/Output 46 (I/O/Z)
External Interface Address Line 6 (O)
GPIO47
XA7
General-Purpose Input/Output 47 (I/O/Z)
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31
General-Purpose Input/Output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (I/O/Z)
GPIO50
EQEP1A
XD29
GPIO51
EQEP1B
XD28
GPIO52
EQEP1S
XD27
GPIO53
EQEP1I
XD26
GPIO54
SPISIMOA
XD25
GPIO55
SPISOMIA
XD24
GPIO56
SPICLKA
XD23
GPIO57
SPISTEA
XD22
GPIO58
MCLKRA
XD21
GPIO59
MFSRA
XD20
GPIO60
MCLKRB
XD19
GPIO61
MFSRB
XD18
GPIO62
SCIRXDC
XD17
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GPIO49
ECAP6
XD30
General-Purpose Input/Output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (I/O/Z)
General-Purpose Input/Output 50 (I/O/Z)
Enhanced QEP 1input A (I)
External Interface Data Line 29 (I/O/Z)
General-Purpose Input/Output 51 (I/O/Z)
Enhanced QEP 1input B (I)
External Interface Data Line 28 (I/O/Z)
General-Purpose Input/Output 52 (I/O/Z)
Enhanced QEP 1Strobe (I/O)
External Interface Data Line 27 (I/O/Z)
General-Purpose Input/Output 53 (I/O/Z)
Enhanced CAP1 lndex (I/O)
External Interface Data Line 26 (I/O/Z)
General-Purpose Input/Output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (I/O/Z)
General-Purpose Input/Output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (I/O/Z)
General-Purpose Input/Output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (I/O/Z)
General-Purpose Input/Output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (I/O/Z)
General-Purpose Input/Output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (I/O/Z)
General-Purpose Input/Output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (I/O/Z)
General-Purpose Input/Output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (I/O/Z)
General-Purpose Input/Output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (I/O/Z)
General-Purpose Input/Output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (I/O/Z)
GPIO63
SCITXDC
XD16
General-Purpose Input/Output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (I/O/Z)
GPIO64
XD15
General-Purpose Input/Output 64 (I/O/Z)
External Interface Data Line 15 (I/O/Z)
GPIO65
XD14
General-Purpose Input/Output 65 (I/O/Z)
External Interface Data Line 14 (I/O/Z)
30
(1)
Introduction
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Table 2-5. Signal Descriptions (continued)
NAME
DESCRIPTION
GPIO66
XD13
General-Purpose Input/Output 66 (I/O/Z)
External Interface Data Line 13 (I/O/Z)
GPIO67
XD12
General-Purpose Input/Output 67 (I/O/Z)
External Interface Data Line 12 (I/O/Z)
GPIO68
XD11
General-Purpose Input/Output 68 (I/O/Z)
External Interface Data Line 11 (I/O/Z)
GPIO70
XD9
GPIO71
XD8
GPIO72
XD7
GPIO73
XD6
GPIO74
XD5
GPIO75
XD4
GPIO76
XD3
GPIO77
XD2
GPIO78
XD1
GPIO79
XD0
GPIO80
XA8
GPIO81
XA9
GPIO82
XA10
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GPIO69
XD10
(1)
General-Purpose Input/Output 69 (I/O/Z)
External Interface Data Line 10 (I/O/Z)
General-Purpose Input/Output 70 (I/O/Z)
External Interface Data Line 9 (I/O/Z)
General-Purpose Input/Output 71 (I/O/Z)
External Interface Data Line 8 (I/O/Z)
General-Purpose Input/Output 72 (I/O/Z)
External Interface Data Line 7 (I/O/Z)
General-Purpose Input/Output 73 (I/O/Z)
External Interface Data Line 6 (I/O/Z)
General-Purpose Input/Output 74 (I/O/Z)
External Interface Data Line 5 (I/O/Z)
General-Purpose Input/Output 75 (I/O/Z)
External Interface Data Line 4 (I/O/Z)
General-Purpose Input/Output 76 (I/O/Z)
External Interface Data Line 3 (I/O/Z)
General-Purpose Input/Output 77 (I/O/Z)
External Interface Data Line 2 (I/O/Z)
General-Purpose Input/Output 78 (I/O/Z)
External Interface Data Line 1 (I/O/Z)
General-Purpose Input/Output 79 (I/O/Z)
External Interface Data Line 0 (I/O/Z)
General-Purpose Input/Output 80 (I/O/Z)
External Interface Address Line 8 (O)
General-Purpose Input/Output 81 (I/O/Z)
External Interface Address Line 9 (O)
General-Purpose Input/Output 82 (I/O/Z)
External Interface Address Line 10 (O)
GPIO83
XA11
General-Purpose Input/Output 83 (I/O/Z)
External Interface Address Line 11 (O)
GPIO84
XA12
General-Purpose Input/Output 84 (I/O/Z)
External Interface Address Line 12 (O)
GPIO85
XA13
General-Purpose Input/Output 85 (I/O/Z)
External Interface Address Line 13 (O)
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Table 2-5. Signal Descriptions (continued)
NAME
DESCRIPTION
GPIO86
XA14
General-Purpose Input/Output 86 (I/O/Z)
External Interface Address Line 14 (O)
GPIO87
XA15
General-Purpose Input/Output 87 (I/O/Z)
External Interface Address Line 15 (O)
XRD
External Interface Read Enable
(1)
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32
Introduction
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3
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Functional Overview
M0 SARAM 1Kx16
(0-Wait)
L0 SARAM 4K x 16
(0-Wait, Dual Map)
M1 SARAM 1Kx16
(0-Wait)
L1 SARAM 4K x 16
(0-Wait, Dual Map)
OTP 1K x 16
Memory Bus
L2 SARAM 4K x 16
(0-Wait, Dual Map)
Flash
256K x 16
8 Sectors
Code
Security
Module
L3 SARAM 4K x 16
(0-Wait, Dual Map)
TEST2
L4 SARAM 4K x 16
(0-W Data, 1-W Prog)
Pump
TEST1
PSWD
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L5 SARAM 4K x 16
(0-W Data, 1-W Prog)
Boot ROM
8K x 16
Flash
Wrapper
L6 SARAM 4K x 16
(0-W Data, 1-W Prog)
L7 SARAM 4K x 16
(0-W Data, 1-W Prog)
Memory Bus
XD31:0
FPU
TCK
XHOLDA
XHOLD
XREADY
88 GPIOs
32-bit CPU
(150 MHZ @ 1.9 V)
(100 MHz @ 1.8 V)
XINTF
XR/W
GPIO
MUX
XZCS0
TDO
TRST
EMU0
XZCS7
EMU1
XWE0
XA0/XWE1
XA19:1
DMA Bus
Memory Bus
XZCS6
XCLKIN
CPU Timer 0
DMA
6 Ch
OSC,
PLL,
LPM,
WD
CPU Timer 1
PIE
(Interrupts)
XRD
8 External Interrupts
GPIO
MUX
A7:0
Memory Bus
12-Bit
ADC
2-S/H
B7:0
X1
X2
XRS
CPU Timer 2
XCLKOUT
88 GPIOs
TDI
TMS
XINTF
DMA Bus
REFIN
32-bit peripheral bus
(DMA accessible)
16-bit peripheral bus
FIFO
(16 Levels)
EPWM-1/../6
McBSP-A/B
ECAP-1/../6
CAN-A/B
(32-mbox)
EQEP-1/2
CANTXx
CANRXx
EQEPxI
EQEPxS
EQEPxB
ESYNCI
ESYNCO
EPWMxB
TZx
EPWMxA
MFSRx
MFSXx
MCLKRx
MRXx
MCLKXx
MDXx
HRPWM-1/../6
SCLx
SDAx
I2C
SPISTEx
SPICLKx
SPISOMIx
SPI-A
SPISIMOx
SCIRXDx
SCITXDx
SCI-A/B/C
EQEPxA
FIFO
(16 Levels)
ECAPx
FIFO
(16 Levels)
32-bit peripheral bus
GPIO MUX
88 GPIOs
Secure zone
Figure 3-1. Functional Block Diagram
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3.1
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Memory Maps
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In Figure 3-2 the following applies:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps
are restricted to data memory only. A user program cannot access these memory maps in program
space.
• Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline
order.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
• Locations 0x38 0080 - 0x38 008F contain the ADC calibration routine. It is not programmable by the
user.
• If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.
34
Functional Overview
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Block
Start Address
On-Chip Memory
Prog Space
Data Space
0x00 0000
External Memory XINTF
Prog Space
Data Space
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
0x00 0040
M0 SARAM (1K x 16)
0x00 0400
M1 SARAM (1K x 16)
0x00 0800
Peripheral Frame 0
0x00 0D00
PIE Vector - RAM
(256 x16)
(Enabled if
VMAP = 1,
ENPIE =1)
Reserved
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Low 64K
(24x/240x Equivalent Data Space)
Reserved
0x00 0E00
Peripheral Frame 0
0x00 2000
XINTF Zone 0 (4K x 16,XZCS0)
(Protected) DMA Accessible
Reserved
0x00 5000
0x00 4000
0x00 5000
Peripheral Frame 3
(Protected) DMA Accessible
0x00 6000
Peripheral Frame 1
(Protected)
Reserved
0x00 7000
Peripheral Frame 2
(Protected)
0x00 8000
0x00 9000
0x00 A000
0x00 B000
0x00 C000
0x00 D000
0x00 E000
0x00 F000
L0 SARAM (4K x16, Secure Zone Dual Mapped)
L1 SARAM (4K x 16, Secure Zone Dual Mapped)
Reserved
L2 SARAM (4Kx16, Secure Zone, Dual Mapped)
L3 SARAM (4Kx16, Secure Zone, Dual Mapped)
L4 SARAM (4Kx16, DMA Accessible)
L5 SARAM (4Kx16, DMA Accessible)
L6 SARAM (4Kx16, DMA Accessible)
L7 SARAM (4Kx16, DMA Accessible)
0x01 0000
Reserved
XINTF Zone 6 (1 M x 16, XZCS6)(DMA Accessible)
XINTF Zone 7 (1 M x 16, XZCS7)(DMA Accessible)
0x30 0000
0x33 FFF8
0x34 0000
0x38 0080
0x38 0090
0x38 0400
0x38 0800
0x10 0000
0x20 0000
0x30 0000
FLASH (256 K x 16, Secure Zone)
128-bit Password
Reserved
ADC Calibration Data
Reserved
User OTP (1K x 16, Secure Zone)
Reserved
High 64K
(24x/240x Equivalent
Program Space)
0x3F 8000
0x3F 9000
0x3F A000
0x3F B000
L0 SARAM (4K x 16, Secure Zone Dual Mapped)
L1 SARAM (4K x 16, Secure Zone Dual Mapped)
Reserved
L2 SARAM (4K x 16, Secure Zone Dual Mapped)
L3 SARAM (4K x 16, Secure Zone Dual Mapped)
0x3F C000
Reserved
0x3F E000
Boot ROM (8K x 16)
0x3F FFC0
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector- should be enabled at a time.
Figure 3-2. Memory Map
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Table 3-1. Addresses of Flash Sectors
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x30 0000 - 0x30 7FFF
Sector H (32K x 16)
0x30 8000 - 0x30 FFFF
Sector G (32K x 16)
0x31 0000 - 0x31 7FFF
Sector F (32K x 16)
0x31 8000 - 0x31 FFFF
Sector E (32K x 16)
Sector D (32K x 16)
Sector C (32K x 16)
0x33 0000 - 0x33 7FFF
Sector B (32K x 16)
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0x32 0000 - 0x32 7FFF
0x32 8000 - 0x32 FFFF
0x33 8000 - 0x33 FF7F
Sector A (32K x 16)
0x33 FF80 - 0x33 FFF5
Program to 0x0000 when using the
Code Security Module
0x33 FFF6 - 0x33 FFF7
Boot-to-Flash Entry Point
(program branch instruction here)
0x33 FFF8 - 0x33 FFFF
Security Password
(128-Bit) (Do Not Program to all zeros)
NOTE
•
When the code-security passwords are programmed, all addresses between 0x33FF80
and 0x33FFF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
• If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may be
used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and
should not contain program code. .
Table 3-2 shows how to handle these memory locations.
Table 3-2. Handling Security Code Locations
ADDRESS
FLASH
Code security enabled
0x33FF80 - 0x33FFEF
0x33FFF0 - 0x33FFF5
Fill with 0x0000
Code security disabled
Application code and data
Reserved for data only
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these
blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected so as to
make sure that operations occur as written (the penalty is extra cycles are added to align the operations).
This mode is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-3.
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Table 3-3. Wait-states
Area
Wait-States (DMA) (1)
Wait-States (CPU)
Comments
M0 and M1 SARAMs
0-wait
Peripheral Frame 0
0-wait (writes)
Fixed
Peripheral Frame 3
0-wait (writes)
0-wait (writes)
2-wait (reads)
1-wait (reads)
Peripheral Frame 1
0-wait (writes)
Cycles can be extended by peripheral generated ready.
2-wait (reads)
Consecutive writes to the CAN will experience a 1-cycle
pipeline hit.
0-wait (writes)
Fixed. Cycles cannot be extended by the peripheral.
0-wait (reads)
1-wait (reads)
Assumes no conflicts between CPU and DMA.
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Peripheral Frame 2
2-wait (reads)
L0 SARAM
L1 SARAM
0-wait data and
program
Assumes no CPU conflicts
L2 SARAM
L3 SARAM
L4 SARAM
0-wait data (read)
0-wait data (write)
L5 SARAM
0-wait data (write)
0-wait data (read)
L6 SARAM
1-wait program (read)
L7 SARAM
1-wait program (write)
XINTF
Programmable
Programmable
Assumes no conflicts between CPU and DMA.
Programmed via the XTIMING registers or extendable via
external XREADY signal to meet system timing requirements.
1-wait is minimum wait states allowed on external waveforms
for both reads and writes on XINTF.
0-wait minimum writes 0-wait minimum writes 0-wait minimum for writes assumes write buffer enabled and
with write buffer
with write buffer enabled not full.
enabled
Assumes no conflicts between CPU and DMA. When DMA and
CPU attempt simultaneous conflict, 1-cycle delay is added for
arbitration.
OTP
FLASH
Programmable
Programmed via the Flash registers.
1-wait minimum
1-wait is minimum number of wait states allowed. 1-wait-state
operation is possible at a reduced CPU frequency.
Programmable
Programmed via the Flash registers.
1-wait Paged min
0-wait minimum for paged access is not allowed
1-wait Random min
Random ≥ Paged
(1)
FLASH Password
16-wait fixed
Boot-ROM
1-wait
Wait states of password locations are fixed.
0-wait speed is not possible.
The DMA has a base of 4 cycles/word.
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3.2
3.2.1
www.ti.com
Brief Descriptions
C28x CPU
3.2.2
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The C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x
DSCs, but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient
C/C++ engine, enabling users to develop their system control software in a high-level language. It also
enables math algorithms to be developed using C/C++. The device is as efficient in DSP math tasks as it
is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the
need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable
the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt
response with automatic context save of critical registers, resulting in a device that is capable of servicing
many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with
pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to
expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for
conditional discontinuities. Special store conditional operations further improve performance.
Memory Bus (Harvard Bus Architecture)
As with many DSC type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory
bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory
bus.)
Data Reads
Lowest:
3.2.3
Program
Reads
(Simultaneous program reads and fetches cannot occur on the memory
bus.)
Fetches
(Simultaneous program reads and fetches cannot occur on the memory
bus.)
Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSC family of devices, the
F28335 adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16
address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus
are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports DMA access
and both 16- and 32-bit accesses (called peripheral frame 3).
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3.2.4
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Real-Time JTAG and Analysis
The F28335 implements the standard IEEE 1149.1 JTAG interface. Additionally, the device supports realtime mode of operation whereby the contents of memory, peripheral and register locations can be
modified while the processor is running and executing code and servicing interrupts. The user can also
single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The device implements the real-time mode in hardware within the CPU. This is a feature
unique to the F28335, requiring no software monitor. Additionally, special analysis hardware is provided
that allows setting of hardware breakpoint or data/address watch-points and generate various userselectable break events when a match occurs.
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3.2.5
External Interface (XINTF)
This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The
chip-select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be
programmed with a different number of wait states, strobe signal setup and hold timing and each zone can
be programmed for extending wait states externally or not. The programmable wait-state, chip-select and
programmable strobe timing enables glueless interface to external memories and peripherals.
3.2.6
Flash
The F28335 contains 256K × 16 of embedded flash memory, segregated into eight 32K × 16 sectors and
a single 1K × 16 of OTP memory at address range 0x380400 – 0x3807FF. The user can individually
erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not
possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other
sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance.
The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or
store data information. Note that addresses 0x33FFF0 – 0x33FFF5 are reserved for data variables and
should not contain program code.
NOTE
The Flash and OTP wait-states can be configured by the application. This allows applications
running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
3.2.7
M0, M1 SARAMs
The F28335 contains these two blocks of single access memory, each 1K × 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute
code or for data variables. The partitioning is performed within the linker. The C28x device presents a
unified memory map to the programmer. This makes for easier programming in high-level languages.
3.2.8
L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
The F28335 contains an additional 32K × 16 of single-access RAM, divided into 8 blocks (L0-L7 with 4K
each). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is mapped
to both program and data space. L4, L5, L6, and L7 are DMA accessible.
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3.2.9
www.ti.com
Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.
Table 3-4. Boot Mode Selection
MODE
D
C
B
A
9
8
7
6
5
4
3
2
1
0
(1)
GPIO86/XA14
GPIO85/XA13
MODE (1)
GPIO84/XA12
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F
E
GPIO87/XA15
1
1
1
1
Jump to Flash
1
1
1
0
SCI-A boot
1
1
0
1
SPI-A boot
1
1
0
0
I2C-A boot
1
0
1
1
eCAN-A boot
1
0
1
0
McBSP-A boot
1
0
0
1
Jump to XINTF x16
1
0
0
0
Jump to XINTF x32
0
1
1
1
Jump to OTP
0
1
1
0
Parallel GPIO I/O boot
0
1
0
1
Parallel XINTF boot
0
1
0
0
Jump to SARAM
0
0
1
1
Branch to check boot mode
0
0
1
0
Branch to Flash, skip ADC calibration
0
0
0
1
Branch to SARAM, skip ADC
calibration
0
0
0
0
Branch to SCI, skip ADC calibration
All four GPIO pins have an internal pullup.
NOTE
Modes 0, 1, and 2 in Table 3-4 are for TI debug only. Skipping the ADC calibration function
in an application will cause the ADC to operate outside of the stated specifications
3.2.10 Security
The devices support high levels of security to protect the user firmware from being reverse engineered.
The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the
flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1/L2/L3 SARAM
blocks. The security feature prevents unauthorized users from examining the memory contents via the
JTAG port, executing code from external memory or trying to boot-load some undesirable software that
would export the secure memory contents. To enable access to the secure blocks, the user must write the
correct 128-bit KEY value, which matches the value stored in the password locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent
unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, L0,
L1, L2 or L3 memory while the emulator is connected will trip the ECSL and break the emulation
connection. To allow emulation of secure code, while maintaining the CSM protection against secure
memory reads, the user must write the correct value into the lower 64 bits of the KEY register, which
matches the value stored in the lower 64 bits of the password locations within the flash. Note that dummy
reads of all 128 bits of the password in the flash must still be performed. If the lower 64 bits of the
password locations are all ones (unprogrammed), then the KEY value does not need to match.
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When initially debugging a device with the password locations in flash programmed (i.e., secured), the
emulator takes some time to take control of the CPU. During this time, the CPU will start running and may
execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will
trip and cause the emulator connection to be cut. Two solutions to this problem exist:
1. The first is to use the Wait-In-Reset emulation mode, which will hold the device in reset until the
emulator takes control. The emulator must support this mode for this option.
2. The second option is to use the “Branch to check boot mode” boot option. This will sit in a loop and
continuously poll the boot mode select pins. The user can select this boot mode and then exit this
mode once the emulator is connected by re-mapping the PC to another address or by changing the
boot mode selection pin to the desired boot mode.
NOTE
•
When the code-security passwords are programmed, all addresses between 0x33FF80
and 0x33FFF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
• If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may be
used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and
should not contain program code. .
The 128-bit password (at 0x33 FFF8 – 0x33 FFFF) must not be programmed to zeros. Doing
so would permanently lock the device.
disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY
(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN
ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO
TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR
THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
3.2.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F28335, 58 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12
CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
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3.2.12 External Interrupts (XINT1-XINT7, XNMI)
The devices support eight masked external interrupts (XINT1-XINT7, XNMI). XNMI can be connected to
the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or
both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). XINT1,
XINT2, and XNMI also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the
281x devices, there are no dedicated pins for the external interrupts. XINT1 XINT2, and XNMI interrupts
can accept inputs from GPIO0 – GPIO31 pins. XINT3 – XINT7 interrupts can accept inputs from
GPIO32 – GPIO63 pins.
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3.2.13 Oscillator and PLL
The device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.14 Watchdog
The devices contain a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog
can be disabled if necessary.
3.2.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN)
and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.
3.2.16 Low-Power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT:
42
Turns off the internal oscillator. This mode basically shuts down the device and
places it in the lowest possible power consumption mode. A reset or external signal
can wake the device from this mode.
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3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash:
Flash Waitstate Registers
XINTF:
External Interface Registers
DMA
DMA Registers
Timers:
CPU-Timers 0, 1, 2 Registers
CSM:
Code Security Module KEY Registers
ADC:
ADC Result Registers (dual-mapped)
eCAN:
eCAN Mailbox and Control Registers
GPIO:
GPIO MUX Configuration and Control Registers
ePWM:
Enhanced Pulse Width Modulator Module and Registers (dual mapped)
eCAP:
Enhanced Capture Module and Registers
eQEP:
Enhanced Quadrature Encoder Pulse Module and Registers
SYS:
System Control Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
SPI:
Serial Port Interface (SPI) Control and RX/TX Registers
ADC:
ADC Status, Control, and Result Register
I2C:
Inter-Integrated Circuit Module and Registers
XINT
External Interrupt Registers
McBSP
Multichannel Buffered Serial Port Registers
ePWM:
Enhanced Pulse Width Modulator Module and Registers (dual mapped)
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PIE:
PF1:
PF2:
PF3:
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
3.2.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. It is connected to INT14 of the CPU. If DSP/BIOS
is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be
connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.
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3.2.20 Control Peripherals
The F28335 supports the following peripherals which are used for embedded control and communication:
The enhanced PWM peripheral supports independent/complementary PWM
generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support HRPWM
features. The ePWM registers are supported by the DMA to reduce the overhead
for servicing this peripheral.
eCAP:
The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
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ePWM:
eQEP:
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit
timer.
This peripheral has a watchdog timer to detect motor stall and input error detection
logic to identify simultaneous edge transition in QEP signals.
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling. The ADC registers are supported
by the DMA to reduce the overhead for servicing this peripheral.
3.2.21 Serial Port Peripherals
The devices support the following serial communication peripherals:
44
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
McBSP:
The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phonequality codecs for modem applications or high-quality stereo audio DAC devices.
The McBSP receive and transmit registers are supported by the DMA to significantly
reduce the overhead for servicing this peripheral. Each McBSP module can be
configured as an SPI as required.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications
between the DSC and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multi-device communications are
supported by the master/slave operation of the SPI. On the F28335, the SPI
contains a 16-level receive and transmit FIFO for reducing interrupt servicing
overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port,
commonly known as UART. The SCI contains a 16-level receive and transmit FIFO
for reducing interrupt servicing overhead.
I2C:
The inter-integrated circuit (I2C) module provides an interface between a DSC and
other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus)
specification version 2.1 and connected by way of an I2C-bus. External components
attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the
DSC through the I2C module. On the F28335, the I2C contains a 16-level receive
and transmit FIFO for reducing interrupt servicing overhead.
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3.3
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-5.
Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 3-6.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 3-7.
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Peripheral Frame 3: These are peripherals that are mapped to the 32-bit DMA-accessible
peripheral bus. See Table 3-8.
Table 3-5. Peripheral Frame 0 Registers (1)
ADDRESS RANGE
SIZE (×16)
ACCESS TYPE (2)
Device Emulation Registers
0x00 0880 - 0x00 09FF
384
EALLOW protected
FLASH Registers (3)
0x00 0A80 - 0x00 0ADF
96
EALLOW protected
Code Security Module Registers
0x00 0AE0 - 0x00 0AEF
16
EALLOW protected
ADC registers (dual-mapped)
0 wait (DMA), 1 wait (CPU), read only
0x00 0B00 - 0x00 0B0F
16
Not EALLOW protected
XINTF Registers
0x00 0B20 - 0x00 0B3F
32
Not EALLOW protected
CPU–TIMER0/1/2 Registers
0x00 0C00 - 0x00 0C3F
64
Not EALLOW protected
PIE Registers
NAME
0x00 0CE0 - 0x00 0CFF
32
Not EALLOW protected
PIE Vector Table
0x00 0D00 - 0x00 0DFF
256
EALLOW protected
DMA Registers
0x00 1000 - 0x00 11FF
512
EALLOW protected
(1)
(2)
(3)
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-6. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
SIZE (×16)
ECAN-A Registers
0x00 6000 - 0x00 61FF
512
ECAN-B Registers
0x00 6200 - 0x00 63FF
512
EPWM1 + HRPWM1 registers
0x00 6800 - 0x00 683F
64
EPWM2 + HRPWM2 registers
0x00 6840 - 0x00 687F
64
EPWM3 + HRPWM3 registers
0x00 6880 - 0x00 68BF
64
EPWM4 + HRPWM4 registers
0x00 68C0 - 0x00 68FF
64
EPWM5 + HRPWM5 registers
0x00 6900 - 0x00 693F
64
EPWM6 + HRPWM6 registers
0x00 6940 - 0x00 697F
64
ECAP1 registers
0x00 6A00 - 0x00 6A1F
32
ECAP2 registers
0x00 6A20 - 0x00 6A3F
32
ECAP3 registers
0x00 6A40 - 0x00 6A5F
32
ECAP4 registers
0x00 6A60 - 0x00 6A7F
32
ECAP5 registers
0x00 6A80 - 0x00 6A9F
32
ECAP6 registers
0x00 6AA0 - 0x00 6ABF
32
EQEP1 registers
0x00 6B00 - 0x00 6B3F
64
EQEP2 registers
0x00 6B40 - 0x00 6B7F
64
GPIO registers
0x00 6F80 - 0x00 6FFF
128
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Table 3-7. Peripheral Frame 2 Registers
NAME
SIZE (×16)
System Control Registers
0x00 7010 - 0x00 702F
32
SPI-A Registers
0x00 7040 - 0x00 704F
16
SCI-A Registers
0x00 7050 - 0x00 705F
16
External Interrupt Registers
0x00 7070 - 0x00 707F
16
ADC Registers
0x00 7100 - 0x00 711F
32
SCI-B Registers
0x00 7750 - 0x00 775F
16
SCI-C Registers
0x00 7770 - 0x00 777F
16
I2C-A Registers
0x00 7900 - 0x00 793F
64
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ADDRESS RANGE
Table 3-8. Peripheral Frame 3 Registers
NAME
ADDRESS RANGE
SIZE (×16)
McBSP-A Registers (DMA)
0x5000 – 0x503F
64
McBSP-B Registers (DMA)
0x5040 - 0x507F
64
EPWM1 + HRPWM1 (DMA) (1)
0x5800 – 0x583F
64
EPWM2 + HRPWM2 (DMA)
0x5840 - 0x587F
64
EPWM3 + HRPWM3 (DMA)
0x5880 - 0x58BF
64
EPWM4 + HRPWM4 (DMA)
0x58C0 - 0x58FF
64
EPWM5 + HRPWM5 (DMA)
0x5900 - 0x593F
64
EPWM6 + HRPWM6 (DMA)
0x5940 - 0x597F
64
(1)
The ePWM/HRPWM modules can be re-mapped to Peripheral Frame 3 where they can be accessed by the DMA module. To achieve
this, bit 0 (MAPEPWM) of MAPCNF register (address 0x702E) must be set to 1. This register is EALLOW protected. When this bit is 0,
the ePWM/HRPWM modules are mapped to Peripheral Frame 1.
3.4
Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 3-9.
Table 3-9. Device Emulation Registers
NAME
DEVICECNF
PARTID
CLASSID
REVID
PROTSTART
PROTRANGE
46
ADDRESS
RANGE
SIZE (x16)
0x0880
0x0881
2
Device Configuration Register
0x380090
1
Part ID Register
0x0882
1
0x0883
1
Revision ID
Register
0x0884
1
Block Protection Start Address Register
0x0885
1
Block Protection Range Address Register
DESCRIPTION
0x00EF
0x00EF
0x0000 - Silicon Rev. 0 - TMX
0x0001 – Silicon Rev. A – TMS
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3.5
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Interrupts
Figure 3-3 shows how the various interrupt sources are multiplexed.
DMA
Peripherals
(A),
(SPI, SCI, I2C, CAN, McBSP
(A)
(A)
EPWM , ECAP, EQEP, ADC )
Clear
WDINT
Watchdog
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WAKEINT
Sync
DMA
Low Power Models
Interrupt Control
XINT1
Latch
MUX
SYSCLKOUT
XINT1CR(15:0)
XINT1CTR(15:0)
GPIOXINT1SEL(4:0)
DMA
XINT2
ADC
XINT2
XINT2SOC
Latch
Interrupt Control
MUX
PIE
C28
Core
96 Interrupts
XINT1
INT1
to
INT12
LPMINT
XINT2CR(15:0)
XINT2CTR(15:0)
GPIOXINT2SEL(4:0)
DMA
TINT0
CPU Timer 0
DMA
TINT2
CPU Timer 2
NMI
CPU Timer 1
TOUT1
Flash Wrapper
Interrupt Control
MUX
INT13
MUX
TINT1
XNMI_
XINT13
GPIO0.int
Latch
MUX
INT14
XNMICR(15:0)
1
GPIO
Mux
GPIO31.int
XNMICTR(15:0)
GPIOXNMISEL(4:0)
DMA
A.
DMA-accessible
Figure 3-3. External and PIE Interrupt Sources
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XINT3
Interrupt Control
Latch
Mux
DMA
XINT3CR(15:0)
GPIOXINT3SEL(4:0)
XINT4
Latch
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Interrupt Control
Mux
DMA
XINT4CR(15:0)
C28
Core
PIE
XINT5
Interrupt Control
Latch
Mux
INT1
to
INT12
96 Interrupts
GPIOXINT4SEL(4:0)
DMA
XINT5CR(15:0)
GPIOXINT5SEL(4:0)
XINT6
Interrupt Control
Latch
Mux
DMA
XINT6CR(15:0)
GPIOXINT6SEL(4:0)
DMA
Interrupt Control
Latch
Mux
GPIO32.int
XINT7
XINT7CR(15:0)
GPIO63.int
GPIO
Mux
GPIOXINT7SEL(4:0)
Figure 3-4. External Interrupts
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the F28335, 58 of these are used by peripherals as
shown in Table 3-10.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.
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IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
MUX
INT11
INT12
(Flag)
CPU
0
Global
Enable
(Enable)
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INTx
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
MUX
PIEACKx
(Enable/Flag)
(Enable)
(Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
From
Peripherals or
External
Interrupts
Figure 3-5. Multiplexing of Interrupts Using the PIE Block
Table 3-10. PIE Peripheral Interrupts (1)
PIE INTERRUPTS
CPU INTERRUPTS
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
(1)
INTx.8
INTx.7
INTx.6
INTx.5
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
XINT2
Reserved
Reserved
EPWM6_TZINT
(ePWM6)
EPWM5_TZINT
(ePWM5)
Reserved
Reserved
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
Reserved
Reserved
ECAP6_INT
(ECAP6)
Reserved
Reserved
Reserved
INTx.4
INTx.3
INTx.2
INTx.1
XINT1
Reserved
SEQ2INT
(ADC)
SEQ1INT
(ADC)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
ECAP5_INT
(ECAP5)
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
Reserved
Reserved
Reserved
Reserved
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
Reserved
MXINTA
(McBSP-A)
MRINTA
(McBSP-A)
MXINTB
(McBSP-B)
MRINTB
(McBSP-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
Reserved
Reserved
DINTCH6
(DMA)
DINTCH5
(DMA)
DINTCH4
(DMA)
DINTCH3
(DMA)
DINTCH2
(DMA)
DINTCH1
(DMA)
Reserved
Reserved
SCITXINTC
(SCI-C)
SCIRXINTC
(SCI-C)
Reserved
Reserved
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LUF
(FPU)
LVF
(FPU)
Reserved
XINT7
XINT6
XINT5
XINT4
XINT3
Out of the 96 possible interrupts, 58 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
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Table 3-11. PIE Configuration and Control Registers
NAME
DESCRIPTION (1)
SIZE (X16)
PIECTRL
0x0CE0
1
PIE, Control Register
PIEACK
0x0CE1
1
PIE, Acknowledge Register
PIEIER1
0x0CE2
1
PIE, INT1 Group Enable Register
PIEIFR1
0x0CE3
1
PIE, INT1 Group Flag Register
PIEIER2
0x0CE4
1
PIE, INT2 Group Enable Register
PIEIFR2
0x0CE5
1
PIE, INT2 Group Flag Register
PIEIER3
0x0CE6
1
PIE, INT3 Group Enable Register
PIEIFR3
0x0CE7
1
PIE, INT3 Group Flag Register
PIEIER4
0x0CE8
1
PIE, INT4 Group Enable Register
PIEIFR4
0x0CE9
1
PIE, INT4 Group Flag Register
PIEIER5
0x0CEA
1
PIE, INT5 Group Enable Register
PIEIFR5
0x0CEB
1
PIE, INT5 Group Flag Register
PIEIER6
0x0CEC
1
PIE, INT6 Group Enable Register
PIEIFR6
0x0CED
1
PIE, INT6 Group Flag Register
PIEIER7
0x0CEE
1
PIE, INT7 Group Enable Register
PIEIFR7
0x0CEF
1
PIE, INT7 Group Flag Register
PIEIER8
0x0CF0
1
PIE, INT8 Group Enable Register
PIEIFR8
0x0CF1
1
PIE, INT8 Group Flag Register
PIEIER9
0x0CF2
1
PIE, INT9 Group Enable Register
PIEIFR9
0x0CF3
1
PIE, INT9 Group Flag Register
PIEIER10
0x0CF4
1
PIE, INT10 Group Enable Register
PIEIFR10
0x0CF5
1
PIE, INT10 Group Flag Register
PIEIER11
0x0CF6
1
PIE, INT11 Group Enable Register
PIEIFR11
0x0CF7
1
PIE, INT11 Group Flag Register
PIEIER12
0x0CF8
1
PIE, INT12 Group Enable Register
PIEIFR12
0x0CF9
1
PIE, INT12 Group Flag Register
Reserved
0x0CFA
0x0CFF
6
Reserved
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ADDRESS
(1)
50
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
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3.5.1
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
External Interrupts
Table 3-12. External Interrupt Registers
Name
Address
Size (x16)
XINT1CR
0x00 7070
1
XINT1 configuration register
Description
XINT2CR
0x00 7071
1
XINT2 configuration register
XINT3CR
0x00 7072
1
XINT3 configuration register
XINT4CR
0x00 7073
1
XINT4 configuration register
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XINT5CR
0x00 7074
1
XINT5 configuration register
XINT6CR
0x00 7075
1
XINT6 configuration register
XINT7CR
0x00 7076
1
XINT7 configuration register
XNMICR
0x00 7077
1
XNMI configuration register
XINT1CTR
0x00 7078
1
XINT1 counter register
XINT2CTR
0x00 7079
1
XINT2 counter register
Reserved
0x707A - 0x707E
5
XNMICTR
0x00 707F
1
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge.
3.6
System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 3-6 shows the various clock and reset domains that will be discussed.
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C28x Core
CLKIN
SYSCLKOUT
I/O
SPI-A, SCI-A/B/C
LOSPCP
Bridge
Peripheral
Registers
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Memory Bus
LSPCLK
System
Control
Register
Peripheral Bus
Clock Enables
Clock Enables
I2C-A
Clock Enables
/2
Bridge
I/O
eCAN-A/B
GPIO
Mux
Peripheral
Registers
Clock Enables
I/O
EPWM1/../6, HRPWM1/../6, Peripheral
Registers
ECAP1/../6, EQEP1/2
Clock Enables
LSPCLK
I/O
McBSP-A/B
Bridge
LOSPCP
Peripheral
Registers
Clock Enables
HSPCLK
HISPCP
Bridge
12-Bit ADC
ADC
Registers
Result
Registers
DMA
Clock Enables
A.
DMA
Bus
16 Channels
CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT). See Figure 3-7 for an illustration of how CLKIN is derived.
Figure 3-6. Clock and Reset Domains
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to PCLKCR0/1/2 registers
(enables peripheral clocks) occurs to when the action is valid. This delay must be taken into
account before attempting to access the peripheral configuration registers.
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-13.
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Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
Name
Size (x16)
PLLSTS
0x00 7011
1
PLL Status Register
Reserved
0x00 7012 - 0x00 7018
7
Reserved
HISPCP
0x00 701A
1
High-Speed Peripheral Clock Pre-Scaler Register
LOSPCP
0x00 701B
1
Low-Speed Peripheral Clock Pre-Scaler Register
PCLKCR0
0x00 701C
1
Peripheral Clock Control Register 0
PCLKCR1
0x00 701D
1
Peripheral Clock Control Register 1
LPMCR0
0x00 701E
1
Low Power Mode Control Register 0
0x00 701F
1
Low Power Mode Control Register 1
0x00 7020
1
Peripheral Clock Control Register 3
0x00 7021
1
PLL Control Register
0x00 7022
1
System Control and Status Register
0x00 7023
1
Watchdog Counter Register
0x00 7024
1
Reserved
0x00 7025
1
Watchdog Reset Key Register
0x00 7026 - 0x00 7028
3
Reserved
0x00 7029
1
Watchdog Control Register
0x00 702A - 0x00 702D
6
Reserved
0x00 702E
1
ePWM/HRPWM Re-map Register
Reserved
PCLKCR3
PLLCR
SCSR
WDCNTR
Reserved
WDKEY
Reserved
WDCR
Reserved
MAPCNF
3.6.1
Description
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Address
OSC and PLL Block
Figure 3-7 shows the OSC and PLL block.
OSCCLK
XCLKIN
(3.3-V clock input
from external
oscillator)
OSCCLK
0
PLLSTS[OSCOFF]
PLL
OSCCLK or
VCOCLK
VCOCLK
n
/1
/2
CLKIN
To
CPU
/4
n≠ 0
PLLSTS[PLLOFF]
External
Crystal or
Resonator
PLLSTS[DIVSEL]
X1
On-chip
oscillator
4-bit Multiplier PLLCR[DIV]
X2
Figure 3-7. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the F28335 using the X1 and X2
pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following
configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO.
2. A 1.9-V (1.8-V for 100 MHz devices) external oscillator can be directly connected to the X1 pin. The X2
pin should be left unconnected and the XCLKIN pin tied low. The logic-high level in this case should
not exceed VDD.
The three possible input-clock configurations are shown in Figure 3-8 through Figure 3-10.
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XCLKIN
X1
X2
NC
External Clock Signal
(Toggling 0 −VDDIO)
Figure 3-8. Using a 3.3-V External Oscillator
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X2
X1
XCLKIN
External Clock Signal
(Toggling 0 −VDD)
NC
Figure 3-9. Using a 1.9-V External Oscillator
X1
XCLKIN
X2
CL2
CL1
Crystal
Figure 3-10. Using the Internal Oscillator
3.6.1.1
External Reference Oscillator Clock Option
Use of crystal/resonator not guaranteed for TC> 125°C.
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
• Fundamental mode, parallel resonant
• CL (load capacitance) = 12 pF
• CL1 = CL2 = 24 pF
• Cshunt = 6 pF
• ESR range = 25 to 40 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the DSC chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values that will
produce proper start up and stability over the entire operating range.
3.6.1.2
PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
131072 OSCCLK cycles. The input clock and PLLCR[DIV] bits should be chosen in such a way that the
output frequency of the PLL (VCOCLK) does not exceed 300 MHz.
54
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Table 3-14. PLLCR (1) Bit Descriptions
PLLCR[DIV] VALUE (2)
(2)
(3)
PLLSTS[DIVSEL] = 0 or 1
SYSCLKOUT (CLKIN)
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3
0000 (PLL bypass)
OSCCLK/4 (Default)
OSCCLK/2
OSCCLK
0001
(OSCCLK * 1)/4
(OSCCLK * 1)/2
–
0010
(OSCCLK * 2)/4
(OSCCLK * 2)/2
–
0011
(OSCCLK * 3)/4
(OSCCLK * 3)/2
–
0100
(OSCCLK * 4)/4
(OSCCLK * 4)/2
–
0101
(OSCCLK * 5)/4
(OSCCLK * 5)/2
–
0110
(OSCCLK * 6)/4
(OSCCLK * 6)/2
–
0111
(OSCCLK * 7)/4
(OSCCLK * 7)/2
–
1000
(OSCCLK * 8)/4
(OSCCLK * 8)/2
–
–
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(1)
(3)
1001
(OSCCLK * 9)/4
(OSCCLK * 9)/2
1010
(OSCCLK * 10)/4
(OSCCLK * 10)/2
–
1011 - 1111
Reserved
Reserved
Reserved
By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /2.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
This register is EALLOW protected.
Table 3-15. CLKIN Divide Options
(1)
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
/4
1
/4
2
/2
3
/1 (1)
This mode can be used only when the PLL is bypassed or off.
The PLL-based clock module provides two modes of operation:
• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
• External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-16. Possible PLL Configuration Modes
REMARKS
PLLSTS[DIVSEL]
CLKIN AND
SYSCLKOUT
PLL Off
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Enable
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0, 1
2
OSCCLK*n/4
OSCCLK*n/2
PLL MODE
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3.6.1.3
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Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
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Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog
reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops
decrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this,
the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could
be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSC will be held in reset, should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSC, should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the flash memory and the VDD3VFL rail.
3.6.2
Watchdog Block
The watchdog block on the F28335 is similar to the one used on the 240x and 281x devices. The
watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the
software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset
the watchdog counter. Figure 3-11 shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
Watchdog
Prescaler
/512
WDCLK
8-Bit
Watchdog
Counter
CLR
Clear Counter
Internal
Pullup
WDKEY(7:0)
Watchdog
55 + AA
Key Detector
WDRST
Generate
Output Pulse
WDINT
(512 OSCCLKs)
Good Key
XRS
Core-reset
WDCR (WDCHK[2:0])
WDRST(A)
A.
1
0
Bad
WDCHK
Key
SCSR (WDENINT)
1
The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-11. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
56
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In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.7, LowPower Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.
Low-Power Modes Block
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3.7
The low-power modes on the F28335 are similar to the 240x devices. Table 3-17 summarizes the various
modes.
Table 3-17. Low-Power Modes
MODE
IDLE
STANDBY
HALT
(1)
(2)
(3)
EXIT (1)
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
00
On
On
On (2)
XRS, Watchdog interrupt, any enabled
interrupt, XNMI
01
On
(watchdog still running)
Off
Off
XRS, Watchdog interrupt, GPIO Port A
signal, debugger (3), XNMI
1X
Off
(oscillator and PLL turned off,
watchdog not functional)
Off
Off
XRS, GPIO Port A signal, XNMI,
debugger (3)
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will
exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized
by the processor. The LPM block performs no tasks during this mode as
long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.
HALT Mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the
device from HALT mode. The user selects the signal in the GPIOLPMSEL
register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included). They
will be in whatever state the code left them in when the IDLE instruction was executed.
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4
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Peripherals
4.1
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The integrated peripherals of the F28335 are described in the following subsections:
• 6-channel Direct Memory Access (DMA)
• Three 32-bit CPU-Timers
• Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)
• Up to six enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, eCAP6)
• Up to two enhanced QEP modules (eQEP1, eQEP2)
• Enhanced analog-to-digital converter (ADC) module
• Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)
• Up to three serial communications interface modules (SCI-A, SCI-B, SCI-C)
• One serial peripheral interface (SPI) module (SPI-A)
• Inter-integrated circuit module (I2C)
• Up to two multichannel buffered serial port (McBSP-A, McBSP-B) modules
• Digital I/O and shared pin functions
• External Interface (XINTF)
DMA Overview
Features:
• 6 Channels with independent PIE interrupts
• Trigger Sources:
– ePWM SOCA/SOCB
– ADC Sequencer 1 and Sequencer 2
– McBSP-A and McBSP-B transmit and receive logic
– XINT1-7 and XINT13
– CPU Timers
– Software
• Data Sources/Destinations:
– L4-L7 16K × 16 SARAM
– All XINTF zones
– ADC Memory Bus mapped RESULT registers
– McBSP-A and McBSP-B transmit and receive buffers
– ePWM registers
• Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit)
• Throughput: 4 cycles/word (5 cycles/word for McBSP reads)
58
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INT7
ADC
PF2
I/F
External
interrupts
CPU
timers
PIE
L4
I/F
L4
SARAM
(4Kx16)
L5
I/F
L5
SARAM
(4Kx16)
L6
I/F
L6
SARAM
(4Kx16)
L7
I/F
L7
SARAM
(4Kx16)
McBSP A
PF3
I/F
Event
triggers
McBSP B
ePWM/
(A)
HRPWM
registers
DINT[CH1:CH6]
XINTF zones interface
ADC
CPU
ADC
PF0
ADC
control
I/F
RESULT
and
ADC registers RESULT
DMA
registers
PF0
I/F
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XINTF memory zones
CPU bus
CPU
DMA
6-ch
DMA bus
A.
The ePWM/HRPWM registers must be remapped to PF3 (through bit 0 of the MAPCNF register) before they can be
accessed by the DMA. The ePWM/HRPWM connection to DMA is not present in silicon revision 0.
Figure 4-1. DMA Functional Block Diagram
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4.2
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32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the devices (CPU-TIMER0/1/2).
Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.
These timers are different from the timers that are present in the ePWM modules.
NOTE
NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the
application.
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Reset
Timer Reload
16-Bit Timer Divide-Down
TDDRH:TDDR
32-Bit Timer Period
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Counter
TIMH:TIM
Borrow
Borrow
TINT
Figure 4-2. CPU-Timers
The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-3.
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
28x
CPU
TINT1
CPU-TIMER 1
INT13
XINT13
INT14
A.
B.
TINT2
CPU-TIMER 2
(Reserved for DSP/BIOS)
The timer registers are connected to the memory bus of the C28x processor.
The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-3. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the
value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers.
60
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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
SIZE (x16)
TIMER0TIM
0x0C00
1
CPU-Timer 0, Counter Register
TIMER0TIMH
0x0C01
1
CPU-Timer 0, Counter Register High
TIMER0PRD
0x0C02
1
CPU-Timer 0, Period Register
TIMER0PRDH
0x0C03
1
CPU-Timer 0, Period Register High
TIMER0TCR
0x0C04
1
CPU-Timer 0, Control Register
Reserved
0x0C05
1
TIMER0TPR
0x0C06
1
CPU-Timer 0, Prescale Register
TIMER0TPRH
0x0C07
1
CPU-Timer 0, Prescale Register High
TIMER1TIM
0x0C08
1
CPU-Timer 1, Counter Register
0x0C09
1
CPU-Timer 1, Counter Register High
TIMER1TIMH
TIMER1PRD
DESCRIPTION
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ADDRESS
0x0C0A
1
CPU-Timer 1, Period Register
TIMER1PRDH
0x0C0B
1
CPU-Timer 1, Period Register High
TIMER1TCR
0x0C0C
1
CPU-Timer 1, Control Register
0x0C0D
1
Reserved
TIMER1TPR
0x0C0E
1
CPU-Timer 1, Prescale Register
TIMER1TPRH
0x0C0F
1
CPU-Timer 1, Prescale Register High
TIMER2TIM
0x0C10
1
CPU-Timer 2, Counter Register
0x0C11
1
CPU-Timer 2, Counter Register High
0x0C12
1
CPU-Timer 2, Period Register
TIMER2PRDH
0x0C13
1
CPU-Timer 2, Period Register High
TIMER2TCR
0x0C14
1
CPU-Timer 2, Control Register
0x0C15
1
TIMER2TIMH
TIMER2PRD
Reserved
TIMER2TPR
0x0C16
1
CPU-Timer 2, Prescale Register
TIMER2TPRH
0x0C17
1
CPU-Timer 2, Prescale Register High
Reserved
0x0C18
0x0C3F
40
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Enhanced PWM Modules (ePWM1/2/3/4/5/6)
The F28335 contains up to six enhanced PWM Modules (ePWM). Figure 4-4 shows a block diagram of
multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM.
Table 4-2 shows the complete ePWM register set per module and Table 4-3 shows the remapped register
configuration.
EPWM1SYNCI
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EPWM1INT
EPWM1SYNCI
EPWM1A
EPWM1SOC
to eCAP1
and ePWM4
module
(sync in)
ePWM1 module
EPWM1B
TZ1 to TZ6
EPWM1SYNCO
EPWM1SYNCO
.
EPWM2SYNCI
EPWM2INT
EPWM2SOC
PIE
EPWM2A
ePWM2 module
GPIO
EPWM2B
MUX
TZ1 to TZ6
EPWM2SYNCO
EPWMxSYNCI
EPWMxINT
EPWMxSOC
EPWMxA
ePWMx module
EPWMxB
EPWMxSYNCO
TZ1 to TZ6
ADCSOCxO
ADC
A.
B.
(A)
Peripheral Bus
ADCSOCxO is sent to the DMA as well when the ePWM registers are remapped to PF3 (through bit 0 of the
MAPCNF register).
By default, ePWM/HRPWM registers are mapped to Peripheral Frame 1 (PF1). Table 4-2 shows this configuration. To
re-map the registers to Peripheral Frame 3 (PF3) to enable DMA access, bit 0 (MAPEPWM) of MAPCNF register
(address 0x702E) must be set to 1. Table 4-3 shows the remapped configuration.
Figure 4-4. Multiple PWM Modules
62
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Table 4-2. ePWM Control and Status Registers (default configuration in PF1)
EPWM1
EPWM2
EPWM3
EPWM4
EPWM5
EPWM6
SIZE (x16) /
#SHADOW
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NAME
DESCRIPTION
TBCTL
0x6800
0x6840
0x6880
0x68C0
0x6900
0x6940
1/0
Time Base Control Register
TBSTS
0x6801
0x6841
0x6881
0x68C1
0x6901
0x6941
1/0
Time Base Status Register
TBPHSHR
0x6802
0x6842
0x6882
0x68C2
0x6902
0x6942
1/0
Time Base Phase HRPWM Register
TBPHS
0x6803
0x6843
0x6883
0x68C3
0x6903
0x6943
1/0
Time Base Phase Register
TBCTR
0x6804
0x6844
0x6884
0x68C4
0x6904
0x6944
1/0
Time Base Counter Register
TBPRD
0x6805
0x6845
0x6885
0x68C5
0x6905
0x6945
1/1
Time Base Period Register Set
CMPCTL
0x6807
0x6847
0x6887
0x68C7
0x6907
0x6947
1/0
Counter Compare Control Register
CMPAHR
0x6808
0x6848
0x6888
0x68C8
0x6908
0x6948
1/1
Time Base Compare A HRPWM Register
CMPA
0x6809
0x6849
0x6889
0x68C9
0x6909
0x6949
1/1
Counter Compare A Register Set
CMPB
0x680A
0x684A
0x688A
0x68CA
0x690A
0x694A
1/1
Counter Compare B Register Set
AQCTLA
0x680B
0x684B
0x688B
0x68CB
0x690B
0x694B
1/0
Action Qualifier Control Register For Output A
AQCTLB
0x680C
0x684C
0x688C
0x68CC
0x690C
0x694C
1/0
Action Qualifier Control Register For Output B
AQSFRC
0x680D
0x684D
0x688D
0x68CD
0x690D
0x694D
1/0
Action Qualifier Software Force Register
AQCSFRC
0x680E
0x684E
0x688E
0x68CE
0x690E
0x694E
1/1
Action Qualifier Continuous S/W Force Register Set
DBCTL
0x680F
0x684F
0x688F
0x68CF
0x690F
0x694F
1/1
Dead-Band Generator Control Register
DBRED
0x6810
0x6850
0x6890
0x68D0
0x6910
0x6950
1/0
Dead-Band Generator Rising Edge Delay Count Register
DBFED
0x6811
0x6851
0x6891
0x68D1
0x6911
0x6951
1/0
Dead-Band Generator Falling Edge Delay Count Register
TZSEL
0x6812
0x6852
0x6892
0x68D2
0x6912
0x6952
1/0
Trip Zone Select Register (1)
TZCTL
0x6814
0x6854
0x6894
0x68D4
0x6914
0x6954
1/0
Trip Zone Control Register (1)
TZEINT
0x6815
0x6855
0x6895
0x68D5
0x6915
0x6955
1/0
Trip Zone Enable Interrupt Register (1)
TZFLG
0x6816
0x6856
0x6896
0x68D6
0x6916
0x6956
1/0
Trip Zone Flag Register
TZCLR
0x6817
0x6857
0x6897
0x68D7
0x6917
0x6957
1/0
Trip Zone Clear Register (1)
TZFRC
0x6818
0x6858
0x6898
0x68D8
0x6918
0x6958
1/0
Trip Zone Force Register (1)
ETSEL
0x6819
0x6859
0x6899
0x68D9
0x6919
0x6959
1/0
Event Trigger Selection Register
ETPS
0x681A
0x685A
0x689A
0x68DA
0x691A
0x695A
1/0
Event Trigger Prescale Register
ETFLG
0x681B
0x685B
0x689B
0x68DB
0x691B
0x695B
1/0
Event Trigger Flag Register
ETCLR
0x681C
0x685C
0x689C
0x68DC
0x691C
0x695C
1/0
Event Trigger Clear Register
ETFRC
0x681D
0x685D
0x689D
0x68DD
0x691D
0x695D
1/0
Event Trigger Force Register
PCCTL
0x681E
0x685E
0x689E
0x68DE
0x691E
0x695E
1/0
PWM Chopper Control Register
HRCNFG
0x6820
0x6860
0x68A0
0x68E0
0x6920
0x6960
1/0
HRPWM Configuration Register (1)
(1)
Registers that are EALLOW protected.
Peripherals
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Table 4-3. ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible)
EPWM1
EPWM2
EPWM3
EPWM4
EPWM5
EPWM6
SIZE (x16) /
#SHADOW
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NAME
DESCRIPTION
TBCTL
0x5800
0x5840
0x5880
0x58C0
0x5900
0x5940
1/0
Time Base Control Register
TBSTS
0x5801
0x5841
0x5881
0x58C1
0x5901
0x5941
1/0
Time Base Status Register
TBPHSHR
0x5802
0x5842
0x5882
0x58C2
0x5902
0x5942
1/0
Time Base Phase HRPWM Register
TBPHS
0x5803
0x5843
0x5883
0x58C3
0x5903
0x5943
1/0
Time Base Phase Register
TBCTR
0x5804
0x5844
0x5884
0x58C4
0x5904
0x5944
1/0
Time Base Counter Register
TBPRD
0x5805
0x5845
0x5885
0x58C5
0x5905
0x5945
1/1
Time Base Period Register Set
CMPCTL
0x5807
0x5847
0x5887
0x58C7
0x5907
0x5947
1/0
Counter Compare Control Register
CMPAHR
0x5808
0x5848
0x5888
0x58C8
0x5908
0x5948
1/1
Time Base Compare A HRPWM Register
CMPA
0x5809
0x5849
0x5889
0x58C9
0x5909
0x5949
1/1
Counter Compare A Register Set
CMPB
0x580A
0x584A
0x588A
0x58CA
0x590A
0x594A
1/1
Counter Compare B Register Set
AQCTLA
0x580B
0x584B
0x588B
0x58CB
0x590B
0x594B
1/0
Action Qualifier Control Register For Output A
AQCTLB
0x580C
0x584C
0x588C
0x58CC
0x590C
0x594C
1/0
Action Qualifier Control Register For Output B
AQSFRC
0x580D
0x584D
0x588D
0x58CD
0x590D
0x594D
1/0
Action Qualifier Software Force Register
AQCSFRC
0x580E
0x584E
0x588E
0x58CE
0x590E
0x594E
1/1
Action Qualifier Continuous S/W Force Register Set
DBCTL
0x580F
0x584F
0x588F
0x58CF
0x590F
0x594F
1/1
Dead-Band Generator Control Register
DBRED
0x5810
0x5850
0x5890
0x58D0
0x5910
0x5950
1/0
Dead-Band Generator Rising Edge Delay Count Register
DBFED
0x5811
0x5851
0x5891
0x58D1
0x5911
0x5951
1/0
Dead-Band Generator Falling Edge Delay Count Register
TZSEL
0x5812
0x5852
0x5892
0x58D2
0x5912
0x5952
1/0
Trip Zone Select Register (1)
TZCTL
0x5814
0x5854
0x5894
0x58D4
0x5914
0x5954
1/0
Trip Zone Control Register (1)
TZEINT
0x5815
0x5855
0x5895
0x58D5
0x5915
0x5955
1/0
Trip Zone Enable Interrupt Register (1)
TZFLG
0x5816
0x5856
0x5896
0x58D6
0x5916
0x5956
1/0
Trip Zone Flag Register
TZCLR
0x5817
0x5857
0x5897
0x58D7
0x5917
0x5957
1/0
Trip Zone Clear Register (1)
TZFRC
0x5818
0x5858
0x5898
0x58D8
0x5918
0x5958
1/0
Trip Zone Force Register (1)
ETSEL
0x5819
0x5859
0x5899
0x58D9
0x5919
0x5959
1/0
Event Trigger Selection Register
ETPS
0x581A
0x585A
0x589A
0x58DA
0x591A
0x595A
1/0
Event Trigger Prescale Register
ETFLG
0x581B
0x585B
0x589B
0x58DB
0x591B
0x595B
1/0
Event Trigger Flag Register
ETCLR
0x581C
0x585C
0x589C
0x58DC
0x591C
0x595C
1/0
Event Trigger Clear Register
ETFRC
0x581D
0x585D
0x589D
0x58DD
0x591D
0x595D
1/0
Event Trigger Force Register
PCCTL
0x581E
0x585E
0x589E
0x58DE
0x591E
0x595E
1/0
PWM Chopper Control Register
HRCNFG
0x5820
0x5860
0x58A0
058E0
0x5920
0x5960
1/0
HRPWM Configuration Register (1)
(1)
64
Registers that are EALLOW protected.
Peripherals
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Time−base (TB)
Sync
in/out
select
Mux
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CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
CTR=PRD
EPWMxSYNCO
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMxSYNCI
Counter
up/down
(16 bit)
CTR=ZERO
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
TBPHS active (24)
Phase
control
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
16
TBCTL[SWFSYNC]
(software forced sync)
Action
qualifier
(AQ)
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
8
Event
trigger
and
interrupt
(ET)
EPWMxINT
EPWMxSOCA
EPWMxSOCB
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMxAO
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
16
PWM
chopper
(PC)
EPWMB
EPWMxBO
CMPB active (16)
CMPB shadow (16)
Trip
zone
(TZ)
EPWMxTZINT
CTR = ZERO
TZ1 to TZ6
Figure 4-5. ePWM Submodules Showing Critical Internal Signal Interconnections
Peripherals
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4.4
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High-Resolution PWM (HRPWM)
4.5
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The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived
digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies greater than ~200 kHz when using a
CPU/System clock of 100 MHz.
• This capability can be utilized in both duty cycle and phase-shift control methods.
• Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase registers of the ePWM module.
• HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA output). EPWMxB output has
conventional PWM capabilities.
Enhanced CAP Modules (eCAP1/2/3/4/5/6)
The F28335 contains up to six enhanced capture (eCAP) modules. Figure 4-6 shows a functional block diagram of a module.
66
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SYNC
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SYNCIn
CTRPHS
(phase register−32 bit)
APWM mode
CTR_OVF
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SYNCOut
TSCTR
(counter−32 bit)
OVF
RST
Delta−mode
CTR [0−31]
PRD [0−31]
PWM
compare
logic
CMP [0−31]
32
CTR=PRD
CTR [0−31]
CTR=CMP
32
32
LD1
CAP1
(APRD active)
APRD
shadow
32
32
MODE SELECT
PRD [0−31]
Polarity
select
LD
32
CMP [0−31]
CAP2
(ACMP active)
32
LD
LD2
Polarity
select
Event
qualifier
ACMP
shadow
32
CAP3
(APRD shadow)
LD
32
CAP4
(ACMP shadow)
LD
eCAPx
Event
Pre-scale
Polarity
select
LD3
LD4
Polarity
select
4
Capture events
4
CEVT[1:4]
to PIE
Interrupt
Trigger
and
Flag
control
CTR_OVF
Continuous /
Oneshot
Capture Control
CTR=PRD
CTR=CMP
Figure 4-6. eCAP Functional Block Diagram
Peripherals
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The eCAP modules are clocked at the SYSCLKOUT rate.
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The clock enable bits (ECAP1/2/3/4/5/6ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power
operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, and ECAP6ENCLK are set to low,
indicating that the peripheral clock is off.
Table 4-4. eCAP Control and Status Registers
68
NAME
ECAP1
TSCTR
0x6A00
ECAP2
ECAP3
ECAP4
ECAP5
ECAP6
SIZE (x16)
0x6A20
0x6A40
0x6A60
0x6A80
0x6AA0
2
Time-Stamp Counter
CTRPHS
0x6A02
CAP1
0x6A04
CAP2
0x6A06
CAP3
0x6A08
CAP4
0x6A0A
Reserved
0x6A22
0x6A42
0x6A62
0x6A82
0x6AA2
2
Counter Phase Offset Value Register
0x6A24
0x6A44
0x6A64
0x6A84
0x6AA4
2
Capture 1 Register
0x6A26
0x6A46
0x6A66
0x6A86
0x6AA6
2
Capture 2 Register
0x6A28
0x6A48
0x6A68
0x6A88
0x6AA8
2
Capture 3 Register
0x6A2A
0x6A4A
0x6A6A
0x6A8A
0x6AAA
2
Capture 4 Register
0x6A0C0x6A12
0x6A2C-0x6A32
0x6A4C- 0x6A52
0x6A6C- 0x6A72
0x6A8C0x6A92
0x6AAC0x6AB2
8
Reserved
ECCTL1
0x6A14
0x6A34
0x6A54
0x6A74
0x6A94
0x6AB4
1
Capture Control Register 1
ECCTL2
0x6A15
0x6A35
0x6A55
0x6A75
0x6A95
0x6AB5
1
Capture Control Register 2
ECEINT
0x6A16
ECFLG
0x6A17
ECCLR
0x6A18
ECFRC
0x6A19
Reserved
0x6A1A0x6A1F
DESCRIPTION
0x6A36
0x6A56
0x6A76
0x6A96
0x6AB6
1
Capture Interrupt Enable Register
0x6A37
0x6A57
0x6A77
0x6A97
0x6AB7
1
Capture Interrupt Flag Register
0x6A38
0x6A58
0x6A78
0x6A98
0x6AB8
1
Capture Interrupt Clear Register
0x6A39
0x6A59
0x6A79
0x6A99
0x6AB9
1
Capture Interrupt Force Register
0x6A3A- 0x6A3F
0x6A5A- 0x6A5F
0x6A7A- 0x6A7F
0x6A9A0x6A9F
0x6ABA0x6ABF
6
Reserved
Peripherals
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4.6
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Enhanced QEP Modules (eQEP1/2)
The device contains up to two enhanced quadrature encoder (eQEP) modules.
System
control registers
To CPU
EQEPxENCLK
Data bus
SYSCLKOUT
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QCPRD
QCTMR
QCAPCTL
16
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
Registers
used by
multiple units
QUTMR
QWDTMR
QUPRD
QWDPRD
32
16
QEPCTL
QEPSTS
UTIME
QFLG
UTOUT
QDECCTL
QWDOG
16
WDTOUT
PIE
EQEPxINT
EQEPxAIN
QCLK
QDIR
16
QI
Position counter/
control unit
(PCCU)
QPOSLAT
QS
PHE
QPOSSLAT
EQEPxIIN
Quadrature
decoder
(QDU)
PCSOUT
QPOSILAT
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
32
32
QPOSCNT
EQEPxA/XCLK
EQEPxBIN
EQEPxB/XDIR
GPIO
MUX
EQEPxI
EQEPxS
16
QPOSCMP
QEINT
QPOSINIT
QFRC
QPOSMAX
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
Figure 4-7. eQEP Functional Block Diagram
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Table 4-5. eQEP Control and Status Registers
EQEP1
ADDRESS
EQEP2
ADDRESS
EQEP1
SIZE(x16)/
#SHADOW
QPOSCNT
0x6B00
0x6B40
2/0
eQEP Position Counter
QPOSINIT
0x6B02
0x6B42
2/0
eQEP Initialization Position Count
QPOSMAX
0x6B04
0x6B44
2/0
eQEP Maximum Position Count
QPOSCMP
0x6B06
0x6B46
2/1
eQEP Position-compare
QPOSILAT
0x6B08
0x6B48
2/0
eQEP Index Position Latch
NAME
QPOSLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
QFLG
QCLR
QFRC
QEPSTS
QCTMR
QCPRD
QCTMRLAT
QCPRDLAT
Reserved
70
0x6B0A
0x6B4A
2/0
eQEP Strobe Position Latch
0x6B0C
0x6B4C
2/0
eQEP Position Latch
0x6B0E
0x6B4E
2/0
eQEP Unit Timer
0x6B10
0x6B50
2/0
eQEP Unit Period Register
0x6B12
0x6B52
1/0
eQEP Watchdog Timer
0x6B13
0x6B53
1/0
eQEP Watchdog Period Register
0x6B14
0x6B54
1/0
eQEP Decoder Control Register
0x6B15
0x6B55
1/0
eQEP Control Register
0x6B16
0x6B56
1/0
eQEP Capture Control Register
0x6B17
0x6B57
1/0
eQEP Position-compare Control Register
0x6B18
0x6B58
1/0
eQEP Interrupt Enable Register
0x6B19
0x6B59
1/0
eQEP Interrupt Flag Register
0x6B1A
0x6B5A
1/0
eQEP Interrupt Clear Register
0x6B1B
0x6B5B
1/0
eQEP Interrupt Force Register
0x6B1C
0x6B5C
1/0
eQEP Status Register
0x6B1D
0x6B5D
1/0
eQEP Capture Timer
0x6B1E
0x6B5E
1/0
eQEP Capture Period Register
0x6B1F
0x6B5F
1/0
eQEP Capture Timer Latch
0x6B20
0x6B60
1/0
eQEP Capture Period Latch
0x6B210x6B3F
0x6B610x6B7F
31/0
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QPOSSLAT
REGISTER DESCRIPTION
Peripherals
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4.7
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Analog-to-Digital Converter (ADC) Module
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A simplified functional block diagram of the ADC module is shown in Figure 4-8. The ADC module
consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module
include:
• 12-bit ADC core with built-in S/H
• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
• Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS
• 16-channel, MUXed inputs
• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion
can be programmed to select any 1 of 16 input channels
• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state
sequencer (i.e., two cascaded 8-state sequencers)
• Sixteen result registers (individually addressable) to store conversion values
– The digital value of the input analog voltage is derived by:
when input ≤ 0 V
Digital Value + 0,
Digital Value + 4096
Input Analog Voltage * ADCLO
3
when input ≥ 3 V
Digital Value + 4095,
A.
•
•
•
•
•
when 0 V < input < 3 V
All fractional values are truncated.
Multiple triggers as sources for the start-of-conversion (SOC) sequence
– S/W - software immediate start
– ePWM start of conversion
– XINT2 ADC start of conversion
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.
Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to
synchronize conversions.
SOCA and SOCB triggers can operate independently in dual-sequencer mode.
Sample-and-hold (S/H) acquisition time window has separate prescale control.
The ADC module in the F28335 has been enhanced to provide flexible interface to ePWM peripherals.
The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at
25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel
modules. The two independent 8-channel modules can be cascaded to form a 16-channel module.
Although there are multiple input channels and two sequencers, there is only one converter in the ADC
module. Figure 4-8 shows the block diagram of the ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module
has the choice of selecting any one of the respective eight channels available through an analog MUX. In
the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,
once the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to
perform oversampling algorithms. This gives increased resolution over traditional single-sampled
conversion results.
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System
Control Block
ADCENCLK
SYSCLKOUT
High-Speed
Prescaler
HALT
DSP
HSPCLK
Analog
MUX
Result Registers
Result Reg 0
ADCINA0
70A8h
Result Reg 1
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S/H
ADCINA7
12-Bit
ADC
Module
Result Reg 7
70AFh
Result Reg 8
70B0h
Result Reg 15
70B7h
ADCINB0
S/H
ADCINB7
ADC Control Registers
S/W
EPWMSOCA
GPIO/
XINT2_ADCSOC
SOC
Sequencer 2
Sequencer 1
S/W
SOC
EPWMSOCB
Figure 4-8. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( VDD1A18,
VDD2A18 , VDDA2, VDDAIO) from the digital supply.Figure 4-9 shows the ADC pin connections for the devices.
NOTE
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:
–
–
72
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the
clock to the register will still function. This is necessary to make sure all registers and
modes go into their default reset state. The analog module, however, will be in a lowpower inactive state. As soon as reset goes high, then the clock to the registers will
be disabled. When the user sets the ADCENCLK signal high, then the clocks to the
registers will be enabled and the analog module will be enabled. There will be a
certain time delay (ms range) before the ADC is stable and can be used.
HALT: This mode only affects the analog module. It does not affect the registers. In
this mode, the ADC module goes into low-power mode. This mode also will stop the
clock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will
be turned off indirectly.
Peripherals
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Figure 4-9 shows the ADC pin-biasing for internal reference and Figure 4-10 shows the ADC pin-biasing
for external reference.
ADC 16-Channel Analog Inputs ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN
Analog input 0−3 V with respect to ADCLO
Connect to analog ground
Connect to analog ground if internal reference is used
22 k
ADC External Current Bias Resistor ADCRESEXT
ADCREFP
ADC Reference Medium Output
ADCREFM
2.2 F (A)
ADCREFP and ADCREFM should not
be loaded by external circuitry
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ADC Reference Positive Output
2.2 F (A)
VDD1A18
VDD2A18
ADC Power
VSS1AGND
VSS2AGND
ADC Analog Power Pin (1.9 V)
ADC Analog Power Pin (1.9 V)
ADC Analog Ground Pin
ADC Analog Ground Pin
VDDA2
VSSA2
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
VDDAIO
VSSAIO
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
ADC Analog and Reference I/O Power
A.
B.
C.
TAIYO YUDEN LMK212BJ225MG-T or equivalent
External decoupling capacitors are recommended on all power pins.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4-9. ADC Pin Connections With Internal Reference
ADC 16-Channel Analog Inputs
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
Connect to 1.500, 1.024, or 2.048-V precision source(D)
22 kΩ
ADC External Current Bias Resistor ADCRESEXT
ADCREFP
ADC Reference Medium Output
ADCREFM
ADC Analog Power
VDD1A18
VDD2A18
VSS1AGND
VSS2AGND
ADC Analog Power Pin (1.9 V)
ADC Analog Power Pin (1.9 V)
ADC Analog Ground Pin
ADC Analog Ground Pin
VDDA2
VSSA2
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
VDDAIO
VSSAIO
ADC Analog Power Pin (3.3 V)
ADC Analog and Reference I/O Power
A.
B.
C.
D.
(A)
2.2 µF
ADC Reference Positive Output
(A)
2.2 µF
ADCREFP and ADCREFM should not
be loaded by external circuitry
ADC Analog I/O Ground Pin
TAIYO YUDEN LMK212BJ225MG-T or equivalent
External decoupling capacitors are recommended on all power pins.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on
the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain
accuracy will be determined by accuracy of this voltage source.
Figure 4-10. ADC Pin Connections With External Reference
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NOTE
The temperature rating of any recommended component must match the rating of the end
product.
4.7.1
ADC Connections if the ADC Is Not Used
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It is recommended to keep the connections for the analog power pins, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:
• VDD1A18/VDD2A18 – Connect to VDD
• VDDA2, VDDAIO – Connect to VDDIO
• VSS1AGND/VSS2AGND, VSSA2, VSSAIO – Connect to VSS
• ADCLO – Connect to VSS
• ADCREFIN – Connect to VSS
• ADCREFP/ADCREFM – Connect a 100-nF cap to VSS
• ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS.
• ADCINAn, ADCINBn - Connect to VSS
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power
savings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (VSS1AGND/VSS2AGND)
NOTE
ADC parameters for gain error and offset error are specified only if the ADC calibration
routine is executed from the Boot ROM. See Section 4.7.3 for more information.
4.7.2
ADC Registers
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-6.
Table 4-6. ADC Registers (1)
NAME
ADDRESS (1)
ADDRESS (2)
SIZE (x16)
DESCRIPTION
ADCTRL1
0x7100
1
ADC Control Register 1
ADCTRL2
0x7101
1
ADC Control Register 2
ADCMAXCONV
0x7102
1
ADC Maximum Conversion Channels Register
ADCCHSELSEQ1
0x7103
1
ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2
0x7104
1
ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3
0x7105
1
ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4
0x7106
1
ADC Channel Select Sequencing Control Register 4
(1)
(2)
74
ADCASEQSR
0x7107
1
ADC Auto-Sequence Status Register
ADCRESULT0
0x7108
0x0B00
1
ADC Conversion Result Buffer Register 0
ADCRESULT1
0x7109
0x0B01
1
ADC Conversion Result Buffer Register 1
ADCRESULT2
0x710A
0x0B02
1
ADC Conversion Result Buffer Register 2
ADCRESULT3
0x710B
0x0B03
1
ADC Conversion Result Buffer Register 3
ADCRESULT4
0x710C
0x0B04
1
ADC Conversion Result Buffer Register 4
The registers in this column are Peripheral Frame 2 Registers.
The ADC result registers are dual mapped. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and left justified.
Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 1 wait-state for CPU accesses and 0 wait state for DMA accesses and right
justified. During high speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user
memory.
Peripherals
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Table 4-6. ADC Registers(1) (continued)
NAME
ADDRESS (1)
ADDRESS (2)
SIZE (x16)
ADCRESULT5
0x710D
0x0B05
1
ADCRESULT6
0x710E
0x0B06
1
ADC Conversion Result Buffer Register 6
ADCRESULT7
0x710F
0x0B07
1
ADC Conversion Result Buffer Register 7
ADCRESULT8
0x7110
0x0B08
1
ADC Conversion Result Buffer Register 8
DESCRIPTION
ADC Conversion Result Buffer Register 5
ADCRESULT9
0x7111
0x0B09
1
ADC Conversion Result Buffer Register 9
ADCRESULT10
0x7112
0x0B0A
1
ADC Conversion Result Buffer Register 10
ADCRESULT11
0x7113
0x0B0B
1
ADC Conversion Result Buffer Register 11
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ADCRESULT12
0x7114
0x0B0C
1
ADC Conversion Result Buffer Register 12
ADCRESULT13
0x7115
0x0B0D
1
ADC Conversion Result Buffer Register 13
ADCRESULT14
0x7116
0x0B0E
1
ADC Conversion Result Buffer Register 14
ADCRESULT15
0x7117
0x0B0F
1
ADC Conversion Result Buffer Register 15
ADCTRL3
0x7118
1
ADC Control Register 3
ADCST
0x7119
1
ADC Status Register
Reserved
0x711A
0x711B
2
ADCREFSEL
0x711C
1
ADC Reference Select Register
ADCOFFTRIM
0x711D
1
ADC Offset Trim Register
Reserved
0x711E
0x711F
2
4.7.3
ADC Calibration
The ADC_cal() routine is programmed into TI reserved OTP memory by the factory. The boot ROM
automatically calls the ADC_cal() routine to initialize the ADCREFSEL and ADCOFFTRIM registers with
device specific calibration data. During normal operation, this process occurs automatically and no action
is required by the user.
If the boot ROM is bypassed by Code Composer Studio during the development process, then
ADCREFSEL and ADCOFFTRIM must be initialized by the application. For working examples, see the
ADC initialization in the C2833x, C2823x C/C++ Header Files and Peripheral Examples (SPRC530).
NOTE
FAILURE TO INITIALIZE THESE REGISTERS WILL CAUSE THE ADC TO FUNCTION
OUT OF SPECIFICATION.
If the system is reset or the ADC module is reset using Bit 14 (RESET) from the ADC Control
Register 1, the routine must be repeated.
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Multichannel Buffered Serial Port (McBSP) Module
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The McBSP module has the following features:
• Full–duplex communication
• Double–buffered data registers that allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• A wide selection of data sizes including 8–, 12–, 16–, 20–, 24–, or 32–bits
• 8–bit data transfers with LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
• Direct interface to industry–standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
• Works with SPI–compatible devices
• The following application interfaces can be supported on the McBSP:
– T1/E1 framers
– IOM–2 compliant devices
– AC97–compliant devices (the necessary multiphase frame synchronization capability is provided.)
– IIS–compliant devices
– SPI
• McBSP clock rate,
CLKG =
CLKSRG
(1 + CLKGDV )
(1)
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O
buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit.
NOTE
See Section 6 for maximum I/O pin toggling speed.
Figure 4-11 shows the block diagram of the McBSP module.
76
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TX
Interrupt
MXINT
To CPU
Peripheral Write Bus
CPU
TX Interrupt Logic
16
McBSP Transmit
Interrupt Select Logic
16
DXR2 Transmit Buffer
LSPCLK
DXR1 Transmit Buffer
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16
16
DMA Bus
Bridge
CPU
Peripheral Bus
Compand Logic
MRINT
XSR1
MDXx
RSR2
RSR1
MDRx
16
MCLKRx
16
Expand Logic
16
16
DRR2 Receive Buffer
DRR1 Receive Buffer
RX
Interrupt
MFSRx
RBR1 Register
16
RX Interrupt Logic
MCLKXx
XSR2
RBR2 Register
McBSP Receive
Interrupt Select Logic
MFSXx
16
Peripheral Read Bus
CPU
To CPU
Figure 4-11. McBSP Module
Table 4-7 provides a summary of the McBSP registers.
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Table 4-7. McBSP Register Summary
NAME
McBSP-A
ADDRESS
McBSP-B
ADDRESS
TYPE
RESET VALUE DESCRIPTION
DATA REGISTERS, RECEIVE, TRANSMIT
DRR2
0x5000
0x5040
R
0x0000
McBSP Data Receive Register 2
DRR1
0x5001
0x5041
R
0x0000
McBSP Data Receive Register 1
DXR2
0x5002
0x5042
W
0x0000
McBSP Data Transmit Register 2
DXR1
0x5003
0x5043
W
0x0000
McBSP Data Transmit Register 1
McBSP CONTROL REGISTERS
SPCR1
RCR2
RCR1
XCR2
XCR1
SRGR2
SRGR1
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SPCR2
0x5004
0x5044
R/W
0x0000
McBSP Serial Port Control Register 2
0x5005
0x5045
R/W
0x0000
McBSP Serial Port Control Register 1
0x5006
0x5046
R/W
0x0000
McBSP Receive Control Register 2
0x5007
0x5047
R/W
0x0000
McBSP Receive Control Register 1
0x5008
0x5048
R/W
0x0000
McBSP Transmit Control Register 2
0x5009
0x5049
R/W
0x0000
McBSP Transmit Control Register 1
0x500A
0x504A
R/W
0x0000
McBSP Sample Rate Generator Register 2
0x500B
0x504B
R/W
0x0000
McBSP Sample Rate Generator Register 1
MULTICHANNEL CONTROL REGISTERS
MCR2
MCR1
RCERA
RCERB
XCERA
XCERB
PCR
RCERC
RCERD
XCERC
XCERD
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
MFFINT
78
0x500C
0x504C
R/W
0x0000
McBSP Multichannel Register 2
0x500D
0x504D
R/W
0x0000
McBSP Multichannel Register 1
0x500E
0x504E
R/W
0x0000
McBSP Receive Channel Enable Register Partition A
0x500F
0x504F
R/W
0x0000
McBSP Receive Channel Enable Register Partition B
0x5010
0x5050
R/W
0x0000
McBSP Transmit Channel Enable Register Partition A
0x5011
0x5051
R/W
0x0000
McBSP Transmit Channel Enable Register Partition B
0x5012
0x5052
R/W
0x0000
McBSP Pin Control Register
0x5013
0x5053
R/W
0x0000
McBSP Receive Channel Enable Register Partition C
0x5014
0x5054
R/W
0x0000
McBSP Receive Channel Enable Register Partition D
0x5015
0x5055
R/W
0x0000
McBSP Transmit Channel Enable Register Partition C
0x5016
0x5056
R/W
0x0000
McBSP Transmit Channel Enable Register Partition D
0x5017
0x5057
R/W
0x0000
McBSP Receive Channel Enable Register Partition E
0x5018
0x5058
R/W
0x0000
McBSP Receive Channel Enable Register Partition F
0x5019
0x5059
R/W
0x0000
McBSP Transmit Channel Enable Register Partition E
0x501A
0x505A
R/W
0x0000
McBSP Transmit Channel Enable Register Partition F
0x501B
0x505B
R/W
0x0000
McBSP Receive Channel Enable Register Partition G
0x501C
0x505C
R/W
0x0000
McBSP Receive Channel Enable Register Partition H
0x501D
0x505D
R/W
0x0000
McBSP Transmit Channel Enable Register Partition G
0x501E
0x505E
R/W
0x0000
McBSP Transmit Channel Enable Register Partition H
0x5023
0x5063
R/W
0x0000
McBSP Interrupt Enable Register
Peripherals
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4.9
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
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The CAN module has the following features:
• Fully compliant with CAN protocol, version 2.0B
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
• Low-power mode
• Programmable wake-up on bus activity
• Automatic reply to a remote request message
• Automatic retransmission of a frame in case of loss of arbitration or error
• 32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)
• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps.
For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.
The F28335 CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and
exceptions.
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eCAN0INT
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Controls Address
eCAN1INT
Data
Enhanced CAN Controller
32
Message Controller
Memory Management
Unit
Mailbox RAM
(512 Bytes)
CPU Interface,
Receive Control Unit,
Timer Management Unit
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32-Message Mailbox
of 4 × 32-Bit Words
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
32
32
32
Receive Buffer
eCAN Protocol Kernel
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4-12. eCAN Block Diagram and Interface Circuit
Table 4-8. 3.3-V eCAN Transceivers
80
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD230
3.3 V
Standby
Adjustable
Yes
–
-40°C to 85°C
SN65HVD230Q
3.3 V
Standby
Adjustable
Yes
–
-40°C to 125°C
SN65HVD231
3.3 V
Sleep
Adjustable
Yes
–
-40°C to 85°C
SN65HVD231Q
3.3 V
Sleep
Adjustable
Yes
–
-40°C to 125°C
SN65HVD232
3.3 V
None
None
None
–
-40°C to 85°C
SN65HVD232Q
3.3 V
None
None
None
–
-40°C to 125°C
SN65HVD233
3.3 V
Standby
Adjustable
None
Diagnostic
Loopback
-40°C to 125°C
SN65HVD234
3.3 V
Standby and Sleep
Adjustable
None
–
-40°C to 125°C
SN65HVD235
3.3 V
Standby
Adjustable
None
Autobaud
Loopback
-40°C to 125°C
Peripherals
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eCAN-A Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN-A Memory (512 Bytes)
6000h
Received Message Pending − CANRMP
Control and Status Registers
Received Message Lost − CANRML
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603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Remote Frame Pending − CANRFP
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Global Acceptance Mask − CANGAM
Message Object Time Stamps (MOTS)
(32 × 32-Bit RAM)
Bit-Timing Configuration − CANBTC
Message Object Time-Out (MOTO)
(32 × 32-Bit RAM)
Transmit Error Counter − CANTEC
Master Control − CANMC
Error and Status − CANES
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
eCAN-A Memory RAM (512 Bytes)
6100h−6107h
Mailbox 0
6108h−610Fh
Mailbox 1
6110h−6117h
Mailbox 2
6118h−611Fh
Mailbox 3
6120h−6127h
Mailbox 4
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
61E0h−61E7h
Mailbox 28
61E8h−61EFh
Mailbox 29
61F0h−61F7h
Mailbox 30
61F8h−61FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
61E8h−61E9h
Message Identifier − MSGID
61EAh−61EBh
Message Control − MSGCTRL
61ECh−61EDh
Message Data Low − MDL
61EEh−61EFh
Message Data High − MDH
Figure 4-13. eCAN-A Memory Map
NOTE
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO,
and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be
enabled for this.
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eCAN-B Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN-B Memory (512 Bytes)
6200h
Received Message Pending − CANRMP
Control and Status Registers
Received Message Lost − CANRML
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623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
Remote Frame Pending − CANRFP
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Global Acceptance Mask − CANGAM
Message Object Time Stamps (MOTS)
(32 × 32-Bit RAM)
Bit-Timing Configuration − CANBTC
Message Object Time-Out (MOTO)
(32 × 32-Bit RAM)
Transmit Error Counter − CANTEC
Master Control − CANMC
Error and Status − CANES
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
eCAN-B Memory RAM (512 Bytes)
6300h−6307h
Mailbox 0
6308h−630Fh
Mailbox 1
6310h−6317h
Mailbox 2
6318h−631Fh
Mailbox 3
6320h−6327h
Mailbox 4
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
63E0h−63E7h
Mailbox 28
63E8h−63EFh
Mailbox 29
63F0h−63F7h
Mailbox 30
63F8h−63FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
63E8h−63E9h
Message Identifier − MSGID
63EAh−63EBh
Message Control − MSGCTRL
63ECh−63EDh
Message Data Low − MDL
63EEh−63EFh
Message Data High − MDH
Figure 4-14. eCAN-B Memory Map
The CAN registers listed in Table 4-9 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
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Table 4-9. CAN Register Map (1)
REGISTER NAME
ECAN-A
ADDRESS
ECAN-B
ADDRESS
SIZE
(x32)
CANME
0x6000
0x6200
1
Mailbox enable
CANMD
0x6002
0x6202
1
Mailbox direction
CANTRS
0x6004
0x6204
1
Transmit request set
CANTRR
0x6006
0x6206
1
Transmit request reset
CANTA
0x6008
0x6208
1
Transmission acknowledge
CANAA
0x600A
0x620A
1
Abort acknowledge
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DESCRIPTION
CANRMP
0x600C
0x620C
1
Receive message pending
CANRML
0x600E
0x620E
1
Receive message lost
CANRFP
0x6010
0x6210
1
Remote frame pending
CANGAM
0x6012
0x6212
1
Global acceptance mask
CANMC
0x6014
0x6214
1
Master control
CANBTC
0x6016
0x6216
1
Bit-timing configuration
CANES
0x6018
0x6218
1
Error and status
CANTEC
0x601A
0x621A
1
Transmit error counter
CANREC
0x601C
0x621C
1
Receive error counter
CANGIF0
0x601E
0x621E
1
Global interrupt flag 0
CANGIM
0x6020
0x6220
1
Global interrupt mask
CANGIF1
0x6022
0x6222
1
Global interrupt flag 1
CANMIM
0x6024
0x6224
1
Mailbox interrupt mask
CANMIL
0x6026
0x6226
1
Mailbox interrupt level
CANOPC
0x6028
0x6228
1
Overwrite protection control
CANTIOC
0x602A
0x622A
1
TX I/O control
CANRIOC
0x602C
0x622C
1
RX I/O control
CANTSC
0x602E
0x622E
1
Time stamp counter (Reserved in SCC mode)
CANTOC
0x6030
0x6230
1
Time-out control (Reserved in SCC mode)
CANTOS
0x6032
0x6232
1
Time-out status (Reserved in SCC mode)
These registers are mapped to Peripheral Frame 1.
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4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
The devices include three serial communications interface (SCI) modules. The SCI modules support
digital communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the fullduplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun,
and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baudselect register.
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Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
Baud rate =
LSPCLK
(BRR ) 1) * 8
when BRR ≠ 0
Baud rate =
LSPCLK
16
when BRR = 0
NOTE
See Section 6 for maximum I/O pin toggling speed.
•
•
•
•
•
•
•
•
Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (non-return-to-zero) format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper byte
(15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 16-level transmit/receive FIFO
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The SCI port operation is configured and controlled by the registers listed in Table 4-10, Table 4-11, and
Table 4-12.
Table 4-10. SCI-A Registers (1)
NAME
ADDRESS
SIZE (x16)
SCICCRA
0x7050
1
SCI-A Communications Control Register
SCICTL1A
0x7051
1
SCI-A Control Register 1
SCIHBAUDA
0x7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x7053
1
SCI-A Baud Register, Low Bits
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SCICTL2A
0x7054
1
SCI-A Control Register 2
SCIRXSTA
0x7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
0x7059
1
SCI-A Transmit Data Buffer Register
SCIFFTXA (2)
0x705A
1
SCI-A FIFO Transmit Register
(2)
0x705B
1
SCI-A FIFO Receive Register
SCIFFCTA (2)
0x705C
1
SCI-A FIFO Control Register
SCIPRIA
0x705F
1
SCI-A Priority Control Register
SCIFFRXA
(1)
(2)
DESCRIPTION
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
Table 4-11. SCI-B Registers (1)
NAME
ADDRESS
SIZE (x16)
SCICCRB
0x7750
1
SCI-B Communications Control Register
SCICTL1B
0x7751
1
SCI-B Control Register 1
0x7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x7754
1
SCI-B Control Register 2
SCIRXSTB
0x7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
0x7759
1
SCI-B Transmit Data Buffer Register
SCIFFTXB (2)
0x775A
1
SCI-B FIFO Transmit Register
SCIFFRXB (2)
0x775B
1
SCI-B FIFO Receive Register
(2)
0x775C
1
SCI-B FIFO Control Register
0x775F
1
SCI-B Priority Control Register
SCIPRIB
(2)
DESCRIPTION
SCIHBAUDB
SCIFFCTB
(1)
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
Table 4-12. SCI-C Registers (1)
(1)
(2)
(2)
(2)
NAME
ADDRESS
SIZE (x16)
SCICCRC
0x7770
1
SCI-C Communications Control Register
DESCRIPTION
SCICTL1C
0x7771
1
SCI-C Control Register 1
SCIHBAUDC
0x7772
1
SCI-C Baud Register, High Bits
SCILBAUDC
0x7773
1
SCI-C Baud Register, Low Bits
SCICTL2C
0x7774
1
SCI-C Control Register 2
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
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Table 4-12. SCI-C Registers(1) (2) (continued)
NAME
ADDRESS
SIZE (x16)
SCIRXSTC
0x7775
1
SCI-C Receive Status Register
SCIRXEMUC
0x7776
1
SCI-C Receive Emulation Data Buffer Register
SCIRXBUFC
0x7777
1
SCI-C Receive Data Buffer Register
SCITXBUFC
0x7779
1
SCI-C Transmit Data Buffer Register
(2)
0x777A
1
SCI-C FIFO Transmit Register
SCIFFRXC (2)
0x777B
1
SCI-C FIFO Receive Register
SCIFFCTC (2)
0x777C
1
SCI-C FIFO Control Register
SCIFFTXC
DESCRIPTION
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SCIPRC
0x777F
1
SCI-C Priority Control Register
Figure 4-15 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
Parity
Even/Odd Enable
TXSHF
Register
TXENA
8
SCICCR.6 SCICCR.5
TX EMPTY
SCICTL2.6
TXRDY
TXWAKE
SCICTL1.3
1
Transmitter-Data
Buffer Register
8
TX INT ENA
SCICTL2.7
SCICTL2.0
TX FIFO
Interrupts
TX FIFO _0
TX FIFO _1
TXINT
TX Interrupt
Logic
To CPU
-----
TX FIFO _15
WUT
SCITXD
SCI TX Interrupt select logic
SCITXBUF.7-0
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCIRXD
RXSHF
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
Baud Rate
LSbyte
Register
RXENA
8
SCICTL1.0
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7-0
RXRDY
SCIRXST.6
8
BRKDT
RX FIFO _15
-----
RX FIFO_1
RX FIFO _0
RX/BK INT ENA
RX FIFO
Interrupts
SCIRXST.5
RX Interrupt
Logic
SCIRXBUF.7-0
RX FIFO registers
SCIRXST.7
SCIRXST.4 - 2
RX Error
FE OE PE
RXINT
To CPU
RXFFOVF
SCIFFRX.15
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 4-15. Serial Communications Interface (SCI) Module Block Diagram
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4.11 Serial Peripheral Interface (SPI) Module (SPI-A)
The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is
available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bittransfer rate. Normally, the SPI is used for communications between the DSC controller and external
peripherals or another processor. Typical applications include external I/O or peripheral expansion through
devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by
the master/slave operation of the SPI.
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The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO if the SPI module is not used.
• Two operational modes: master and slave
Baud rate: 125 different programmable rates.
Baud rate =
LSPCLK
(SPIBRR ) 1)
Baud rate =
LSPCLK
4
when SPIBRR = 3 to 127
when SPIBRR = 0,1, 2
NOTE
See Section 6 for maximum I/O pin toggling speed.
•
•
•
•
•
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper byte
(15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
• 16-level transmit/receive FIFO
• Delayed transmit control
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The SPI port operation is configured and controlled by the registers listed in Table 4-13.
Table 4-13. SPI-A Registers
88
ADDRESS
SIZE (X16)
SPICCR
0x7040
1
SPI-A Configuration Control Register
SPICTL
0x7041
1
SPI-A Operation Control Register
SPISTS
0x7042
1
SPI-A Status Register
SPIBRR
0x7044
1
SPI-A Baud Rate Register
SPIRXEMU
0x7046
1
SPI-A Receive Emulation Buffer Register
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(1)
DESCRIPTION (1)
NAME
SPIRXBUF
0x7047
1
SPI-A Serial Input Buffer Register
SPITXBUF
0x7048
1
SPI-A Serial Output Buffer Register
SPIDAT
0x7049
1
SPI-A Serial Data Register
SPIFFTX
0x704A
1
SPI-A FIFO Transmit Register
SPIFFRX
0x704B
1
SPI-A FIFO Receive Register
SPIFFCT
0x704C
1
SPI-A FIFO Control Register
SPIPRI
0x704F
1
SPI-A Priority Control Register
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Figure 4-16 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX Interrupt
Logic
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RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
TX FIFO _0
SPITXINT
16
SPI INT FLAG
SPITXBUF
Buffer Register
16
SPI INT
ENA
SPISTS.6
SPICTL.0
16
M
M
SPIDAT
Data Register
S
SPIDAT.15 − 0
M
S
SW1
SPISIMO
M
S
S
SW2
SPISOMI
Talk
SPICTL.1
(A)
SPISTE
State Control
Master/Slave
SPI Char
SPICCR.3 − 0
3
2
1
SW3
M
SPI Bit Rate
LSPCLK
SPIBRR.6 − 0
6
A.
5
4
3
SPICTL.2
S
0
2
1
S
Clock
Polarity
Clock
Phase
SPICCR.6
SPICTL.3
SPICLK
M
0
SPISTE is driven low by the master for a slave device.
Figure 4-16. SPI Module Block Diagram (Slave Mode)
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4.12 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module interfaces
within the device.
System Control
Block
C28X CPU
I2CAENCLK
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SYSRS
Control
Data[16]
SDAA
GPIO
MUX
Peripheral Bus
SYSCLKOUT
Data[16]
I2C−A
Addr[16]
SCLA
I2CINT1A
PIE
Block
I2CINT2A
A.
B.
The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-17. I2C Peripheral Module Interfaces
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)
• One 16-word receive FIFO and one 16-word transmit FIFO
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•
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
The registers in Table 4-14 configure and control the I2C port operation.
Table 4-14. I2C-A Registers
NAME
ADDRESS
I2COAR
0x7900
I2C own address register
DESCRIPTION
I2CIER
0x7901
I2C interrupt enable register
I2CSTR
0x7902
I2C status register
I2CCLKL
0x7903
I2C clock low-time divider register
I2CCLKH
0x7904
I2C clock high-time divider register
I2CCNT
0x7905
I2C data count register
I2CDRR
0x7906
I2C data receive register
I2CSAR
0x7907
I2C slave address register
I2CDXR
0x7908
I2C data transmit register
I2CMDR
0x7909
I2C mode register
I2CISRC
0x790A
I2C interrupt source register
I2CPSC
0x790C
I2C prescaler register
I2CFFTX
0x7920
I2C FIFO transmit register
I2CFFRX
0x7921
I2C FIFO receive register
I2CRSR
-
I2C receive shift register (not accessible to the CPU)
I2CXSR
-
I2C transmit shift register (not accessible to the CPU)
4.13 GPIO MUX
On the F28335, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in Figure 4-18. Because of the open drain capabilities of the I2C pins, the GPIO MUX block
diagram for these pins differ.
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn
registers occurs to when the action is valid.
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GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL

GPIOLMPSEL
GPIOXINT7SEL
LPMCR0
GPIOXNMISEL
External Interrupt
MUX
Low Power
Modes Block
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Asynchronous
path
PIE
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
Input
Qualification
Internal
Pullup
00
N/C
01
Peripheral 1 Input
10
Peripheral 2 Input
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
GPxDAT (latch)
01
Peripheral 1 Output
10
Peripheral 2 Output
11
Peripheral 3 Output
High Impedance
Output Control
00
0 = Input, 1 = Output
XRS
= Default at Reset
A.
B.
C.
GPxDIR (latch)
01
Peripheral 1 Output Enable
10
Peripheral 2 Output Enable
11
Peripheral 3 Output Enable
GPxMUX1/2
x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
GPxDAT latch/read are accessed at the same memory location.
This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins.
Figure 4-18. GPIO MUX Block Diagram
92
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The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame
1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO
register mapping.
Table 4-15. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPACTRL
0x6F80
2
GPIO A Control Register (GPIO0 to 31)
GPAQSEL1
0x6F82
2
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
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GPAQSEL2
0x6F84
2
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1
0x6F86
2
GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2
0x6F88
2
GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR
0x6F8A
2
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPAPUD
0x6F8C
2
Reserved
0x6F8E – 0x6F8F
2
GPBCTRL
0x6F90
2
GPIO B Control Register (GPIO32 to 63)
GPBQSEL1
0x6F92
2
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
GPBQSEL2
0x6F94
2
GPIOB Qualifier Select 2 Register (GPIO48 to 63)
GPBMUX1
0x6F96
2
GPIO B MUX 1 Register (GPIO32 to 47)
GPBMUX2
0x6F98
2
GPIO B MUX 2 Register (GPIO48 to 63)
GPBDIR
0x6F9A
2
GPIO B Direction Register (GPIO32 to 63)
GPBPUD
0x6F9C
2
GPIO B Pull Up Disable Register (GPIO32 to 63)
Reserved
0x6F9E – 0x6FA5
8
GPCMUX1
0x6FA6
2
GPIO C MUX1 Register (GPIO64 to 79)
GPCMUX2
0x6FA8
2
GPIO C MUX2 Register (GPIO80 to 87)
GPCDIR
0x6FAA
2
GPIO C Direction Register (GPIO64 to 87)
GPIO C Pull Up Disable Register (GPIO64 to 87)
GPCPUD
0x6FAC
2
Reserved
0x6FAE – 0x6FBF
18
GPADAT
0x6FC0
2
GPIO A Data Register (GPIO0 to 31)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPASET
0x6FC2
2
GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR
0x6FC4
2
GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE
0x6FC6
2
GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT
0x6FC8
2
GPIO B Data Register (GPIO32 to 63)
GPBSET
0x6FCA
2
GPIO B Data Set Register (GPIO32 to 63)
GPBCLEAR
0x6FCC
2
GPIO B Data Clear Register (GPIO32 to 63)
GPBTOGGLE
0x6FCE
2
GPIOB Data Toggle Register (GPIO32 to 63)
GPCDAT
0x6FD0
2
GPIO C Data Register (GPIO64 to 87)
GPCSET
0x6FD2
2
GPIO C Data Set Register (GPIO64 to 87)
GPCCLEAR
0x6FD4
2
GPIO C Data Clear Register (GPIO64 to 87)
GPCTOGGLE
0x6FD6
2
GPIO C Data Toggle Register (GPIO64 to 87)
Reserved
0x6FD8 0x6FDF
8
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
0x6FE0
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL
0x6FE1
1
XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXNMISEL
0x6FE2
1
XNMI GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL
0x6FE3
1
XINT3 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT4SEL
0x6FE4
1
XINT4 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT5SEL
0x6FE5
1
XINT5 GPIO Input Select Register (GPIO32 to 63)
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Table 4-15. GPIO Registers (continued)
NAME
ADDRESS
SIZE (x16)
GPIOXINT6SEL
0x6FE6
1
XINT6 GPIO Input Select Register (GPIO32 to 63)
DESCRIPTION
GPIOINT7SEL
0x6FE7
1
XINT7 GPIO Input Select Register (GPIO32 to 63)
GPIOLPMSEL
0x6FE8
2
LPM GPIO Select Register (GPIO0 to 31)
Reserved
0x6FEA – 0x6FFF
22
Table 4-16. GPIO-A Mux Peripheral Selection Matrix
GPADIR
GPADAT
GPASET
GPACLR
GPATOGGLE
QUALPRD0
QUALPRD1
GPAMUX1
GPAQSEL1
GPIOx
GPAMUX1=0,0
PER1
GPAMUX1 = 0, 1
0
1, 0
GPIO0 (I/O)
EPWM1A (O)
1
3, 2
GPIO1 (I/O)
EPWM1B (O)
2
5, 4
GPIO2 (I/O)
EPWM2A (O)
3
7, 6
GPIO3 (I/O)
EPWM2B (O)
4
9, 8
GPIO4 (I/O)
EPWM3A (O)
5
11, 10
GPIO5 (I/O)
EPWM3B (O)
MFSRA (I/O)
ECAP1 (I/O)
6
13, 12
GPIO6 (I/O)
EPWM4A (O)
EPWMSYNCI (I)
EPWMSYNCO (O)
7
15, 14
GPIO7 (I/O)
EPWM4B (O)
MCLKRA (I/O)
ECAP2 (I/O)
8
17, 16
GPIO8 (I/O)
EPWM5A (O)
CANTXB (O)
ADCSOCAO (O)
9
19, 18
GPIO9 (I/O)
EPWM5B (O)
SCITXDB (O)
ECAP3 (I/O)
QUALPRD3
94
PER2
GPAMUX1 = 1, 0
PER3
GPAMUX1 = 1, 1
ECAP6 (I/O)
MFSRB (I/O)
ECAP5 (I/O)
MCLKRB (I/O)
10
21, 20
GPIO10 (I/O)
EPWM6A (O)
CANRXB (I)
ADCSOCBO (O)
11
23, 22
GPIO11 (I/O)
EPWM6B (O)
SCIRXDB (I)
ECAP4 (I/O)
12
25, 24
GPIO12 (I/O)
TZ1 (I)
CANTXB (O)
MDXB (O)
13
27, 26
GPIO13 (I/O)
TZ2 (I)
CANRXB (I)
MDRB (I)
14
29, 28
GPIO14 (I/O)
TZ3 (I)/XHOLD (I)
SCITXDB (O)
MCLKXB (I/O)
15
QUALPRD2
PERIPHERAL SELECTION
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REGISTER BITS
31, 30
GPIO15 (I/O)
TZ4 (I)/XHOLDA (O)
SCIRXDB (I)
MFSXB (I/O)
GPAMUX2
GPAQSEL2
GPAMUX2 =0, 0
GPAMUX2 = 0, 1
GPAMUX2 = 1, 0
GPAMUX2 = 1, 1
16
1, 0
GPIO16 (I/O)
SPISIMOA (I/O)
CANTXB (O)
TZ5 (I)
17
3, 2
GPIO17 (I/O)
SPISOMIA (I/O)
CANRXB (I)
TZ6 (I)
18
5, 4
GPIO18 (I/O)
SPICLKA (I/O)
SCITXDB (O)
CANRXA (I)
19
7, 6
GPIO19 (I/O)
SPISTEA (I/O)
SCIRXDB (I)
CANTXA (O)
20
9, 8
GPIO20 (I/O)
EQEP1A (I)
MDXA (O)
CANTXB (O)
21
11, 10
GPIO21 (I/O)
EQEP1B (I)
MDRA (I)
CANRXB (I)
22
13, 12
GPIO22 (I/O)
EQEP1S (I/O)
MCLKXA (I/O)
SCITXDB (O)
23
15, 14
GPIO23 (I/O)
EQEP1I (I/O)
MFSXA (I/O)
SCIRXDB (I)
24
17, 16
GPIO24 (I/O)
ECAP1 (I/O)
EQEP2A (I)
MDXB (O)
25
19, 18
GPIO25 (I/O)
ECAP2 (I/O)
EQEP2B (I)
MDRB (I)
26
21, 20
GPIO26 (I/O)
ECAP3 (I/O)
EQEP2I (I/O)
MCLKXB (I/O)
27
23, 22
GPIO27 (I/O)
ECAP4 (I/O)
EQEP2S (I/O)
MFSXB (I/O)
28
25, 24
GPIO28 (I/O)
SCIRXDA (I)
XZCS6 (O)
29
27, 26
GPIO29 (I/O)
SCITXDA (O)
XA19 (O)
30
29, 28
GPIO30 (I/O)
CANRXA (I)
XA18 (O)
31
31, 30
GPIO31 (I/O)
CANTXA (O)
XA17 (O)
Peripherals
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Table 4-17. GPIO-B Mux Peripheral Selection Matrix
REGISTER BITS
GPBDIR
GPBDAT
GPBSET
GPBCLR
GPBTOGGLE
QUALPRD0
QUALPRD2
QUALPRD3
(1)
GPBMUX1
GPBQSEL1
GPIOx
GPBMUX1=0, 0
PER1
GPBMUX1 = 0, 1
PER2
GPBMUX1 = 1, 0
PER3
GPBMUX1 = 1, 1
0
1, 0
GPIO32 (I/O)
SDAA (I/OC) (1)
1
3, 2
EPWMSYNCI (I)
ADCSOCAO (O)
GPIO33 (I/O)
SCLA (I/OC) (1)
EPWMSYNCO (O)
2
5, 4
ADCSOCBO (O)
GPIO34 (I/O)
ECAP1 (I/O)
XREADY (I)
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QUALPRD1
PERIPHERAL SELECTION
3
7, 6
GPIO35 (I/O)
SCITXDA (O)
XR/W (O)
4
9, 8
GPIO36 (I/O)
SCIRXDA (I)
XZCS0 (O)
5
11, 10
GPIO37 (I/O)
ECAP2 (I/O)
XZCS7 (O)
6
13, 12
GPIO38 (I/O)
7
15, 14
GPIO39 (I/O)
XA16 (O)
8
17, 16
GPIO40 (I/O)
XA0/XWE1 (O)
XA1 (O)
XWE0 (O)
9
19, 18
GPIO41 (I/O)
10
21, 20
GPIO42 (I/O)
11
23, 22
GPIO43 (I/O)
12
25, 24
GPIO44 (I/O)
XA4 (O)
13
27, 26
GPIO45 (I/O)
XA5 (O)
14
29, 28
GPIO46 (I/O)
XA6 (O)
15
31, 30
GPIO47 (I/O)
XA7 (O)
GPBMUX2
GPBQSEL2
GPBMUX2 =0, 0
GPBMUX2 = 0, 1
16
1, 0
GPIO48 (I/O)
ECAP5 (I/O)
XD31 (I/O)
17
3, 2
GPIO49 (I/O)
ECAP6 (I/O)
XD30 (I/O)
18
5, 4
GPIO50 (I/O)
EQEP1A (I)
XD29 (I/O)
19
7, 6
GPIO51 (I/O)
EQEP1B (I)
XD28 (I/O)
20
9, 8
GPIO52 (I/O)
EQEP1S (I/O)
XD27 (I/O)
Reserved
XA2 (O)
XA3 (O)
GPBMUX2 = 1, 0
GPBMUX2 = 1, 1
21
11, 10
GPIO53 (I/O)
EQEP1I (I/O)
XD26 (I/O)
22
13, 12
GPIO54 (I/O)
SPISIMOA (I/O)
XD25 (I/O)
23
15, 14
GPIO55 (I/O)
SPISOMIA (I/O)
XD24 (I/O)
24
17, 16
GPIO56 (I/O)
SPICLKA (I/O)
XD23 (I/O)
25
19, 18
GPIO57 (I/O)
SPISTEA (I/O)
XD22 (I/O)
26
21, 20
GPIO58 (I/O)
MCLKRA (I/O)
XD21 (I/O)
27
23, 22
GPIO59 (I/O)
MFSRA (I/O)
XD20 (I/O)
28
25, 24
GPIO60 (I/O)
MCLKRB (I/O)
XD19 (I/O)
29
27, 26
GPIO61 (I/O)
MFSRB (I/O)
XD18 (I/O)
30
29, 28
GPIO62 (I/O)
SCIRXDC (I)
XD17 (I/O)
31
31, 30
GPIO63 (I/O)
SCITXDC (O)
XD16 (I/O)
Open drain
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Table 4-18. GPIO-C Mux Peripheral Selection Matrix
REGISTER BITS
GPCDIR
GPCDAT
GPCSET
GPCCLR
GPCTOGGLE
no qual
no qual
GPCMUX1
GPIOx or PER1
GPCMUX1 = 0, 0 or 0, 1
PER2 or PER3
GPCMUX1 = 1, 0 or 1, 1
0
1, 0
GPIO64 (I/O)
XD15 (I/O)
1
3, 2
GPIO65 (I/O)
XD14 (I/O)
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no qual
PERIPHERAL SELECTION
2
5, 4
GPIO66 (I/O)
XD13 (I/O)
3
7, 6
GPIO67 (I/O)
XD12 (I/O)
4
9, 8
GPIO68 (I/O)
XD11 (I/O)
5
11, 10
GPIO69 (I/O)
XD10 (I/O)
6
13, 12
GPIO70 (I/O)
XD9 (I/O)
7
15, 14
GPIO71 (I/O)
XD8 (I/O)
8
17, 16
GPIO72 (I/O)
XD7 (I/O)
9
19, 18
GPIO73 (I/O)
XD6 (I/O)
10
21, 20
GPIO74 (I/O)
XD5 (I/O)
11
23, 22
GPIO75 (I/O)
XD4 (I/O)
12
25, 24
GPIO76 (I/O)
XD3 (I/O)
13
27, 26
GPIO77 (I/O)
XD2 (I/O)
14
29, 28
GPIO78 (I/O)
XD1 (I/O)
15
31, 30
GPIO79 (I/O)
XD0 (I/O)
GPCMUX2
GPCMUX2 = 0, 0 or 0, 1
GPCMUX2 = 1, 0 or 1, 1
16
1, 0
GPIO80 (I/O)
XA8 (O)
17
3, 2
GPIO81 (I/O)
XA9 (O)
18
5, 4
GPIO82 (I/O)
XA10 (O)
19
7, 6
GPIO83 (I/O)
XA11 (O)
20
9, 8
GPIO84 (I/O)
XA12 (O)
21
11, 10
GPIO85 (I/O)
XA13 (O)
22
13, 12
GPIO86 (I/O)
XA14 (O)
23
15, 14
GPIO87 (I/O)
XA15 (O)
The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0, 0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2=0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.
96
Peripherals
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Time between samples
GPyCTRL Reg
GPIOx
SYNC
Qualification
Input Signal
Qualified By 3
or 6 Samples
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GPxQSEL
SYSCLKOUT
Number of Samples
Figure 4-19. Qualification Using Sampling Window
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the
input signal will default to either a 0 or 1 state, depending on the peripheral.
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4.14 External Interface (XINTF)
This section gives a top-level view of the external interface (XINTF) that is implemented on the F28335.
The XINTF is a non-multiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into
three fixed zones shown in Figure 4-20.
Data Space
Prog Space
0x0000−0000
XD(31:0)
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XA(19:0)
0x0000−4000
XINTF Zone 0
(8K x 16)
XZCS0
XINTF Zone 6
(1M x 16)
XZCS6
0x0000−5000
0x0010−0000
0x0020−0000
0x0030−0000
XZCS7
XINTF Zone 7
(1M x 16)
XA0/XWE1
XWE0
XRD
XR/W
XREADY
XHOLD
XHOLDA
XCLKOUT
A.
B.
C.
Each zone can be programmed with different wait states, setup and hold timings, and is supported by zone chip
selects that toggle when an access to a particular zone is performed. These features enable glueless connection to
many external memories and peripherals.
Zones 1 – 5 are reserved for future expansion.
Zones 0, 6, and 7 are always enabled.
Figure 4-20. External Interface Block Diagram
Figure 4-21 and Figure 4-22 show typical 16-bit and 32-bit data bus XINTF connections, illustrating how
the functionality of the XA0 and XWE1 signals change, depending on the configuration. Table 4-19 defines
XINTF configuration and control registers.
98
Peripherals
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XINTF
External
wait-state
generator
16-bits
XREADY
XCLKOUT
CS
XZCS0/6/7
A(19:1)
XA(19:1)
A(0)
XA0/XWE1
XRD
WE
XWE0
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OE
D(15:0)
XD(15:0)
Figure 4-21. Typical 16-bit Data Bus XINTF Connections
XINTF
External
wait-state
generator
Low 16-bits
XREADY
XCLKOUT
CS
A(18:0)
XA(19:1)
OE
XRD
WE
XWE0
D(15:0)
XD(15:0)
High 16-bits
A(18:0)
CS
XZCS0/6/7
OE
XA0/XWE1
(select XWE1)
WE
D(31:16)
XD(31:16)
Figure 4-22. Typical 32-bit Data Bus XINTF Connections
Table 4-19. XINTF Configuration and Control Register Mapping
NAME
ADDRESS
SIZE (x16)
0x00−0B20
2
XINTF Timing Register, Zone 0
0x00−0B2C
2
XINTF Timing Register, Zone 6
0x00−0B2E
2
XINTF Timing Register, Zone 7
0x00−0B34
2
XINTF Configuration Register
XBANK
0x00−0B38
1
XINTF Bank Control Register
XREVISION
0x00−0B3A
1
XINTF Revision Register
XRESET
0x00 083D
1
XINTF Reset Register
XTIMING0
XTIMING6
(1)
XTIMING7
XINTCNF2 (2)
(1)
(2)
DESCRIPTION
XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
XINTCNF1 is reserved and not currently used.
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Device Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSCs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of F28335-based applications:
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Software Development Tools
• Code Composer Studio™ Integrated Development Environment (IDE)
– C/C++ Compiler
– Code generation tools
– Assembler/Linker
– Cycle Accurate Simulator
• Application algorithms
• Sample applications code
Hardware Development Tools
• Development board
• Evaluation modules
• JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB
• Universal 5-V dc power supply
• Documentation and cables
6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
6.1
Absolute Maximum Ratings (1)
(2)
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.
Supply voltage range, VDDIO, VDD3VFL
with respect to VSS
– 0.3 V to 4.6 V
Supply voltage range, VDDA2, VDDAIO
with respect to VSSA
– 0.3 V to 4.6 V
Supply voltage range, VDD
with respect to VSS
– 0.3 V to 2.5 V
Supply voltage range, VDD1A18, VDD2A18
with respect to VSSA
– 0.3 V to 2.5 V
Supply voltage range, VSSA2, VSSAIO, VSS1AGND, VSS2AGND
with respect to VSS
– 0.3 V to 0.3 V
Input voltage range, VIN
– 0.3 V to 4.6 V
Output voltage range, VO
– 0.3 V to 4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VDDIO) (3)
Output clamp current, IOK (VO < 0 or VO > VDDIO)
± 20 mA
± 20 mA
Operating junction temperature, TJ
– 55°C to 215°C
Operating case temperature range, TC
– 55°C to 210°C
(1)
(2)
(3)
100
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
Continuous clamp current per pin is ± 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the
voltage to a diode drop above VDDA2 or below VSSA2.
Electrical Specifications
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45000
40000
35000
25000
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Lifetime (Hours)
30000
20000
15000
10000
5000
0
150
155
160
165
170
175
180
185
190
195
200
205
210
215
Die Junction Temperature (°C)
A.
B.
See the data sheet for absolute maximum and minimum recommended operating conditions.
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
Figure 6-1. SM320F28335 Operating Life Derating Chart
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6.2
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Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Device supply voltage, I/O, VDDIO
3.135
3.3
3.465
V
Device supply voltage CPU, VDD
1.805
1.9
1.995
V
Supply ground, VSS, VSSIO, VSSAIO, VSSA2,
VSS1AGND, VSS2AGND
0
V
3.135
3.3
3.465
V
ADC supply voltage, VDD1A18, VDD2A18
1.805
1.9
1.995
V
Flash supply voltage, VDD3VFL
3.135
3.3
3.465
V
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ADC supply voltage (3.3 V), VDDA2, VDDAIO
Device clock frequency (system clock),
fSYSCLKOUT
TC = – 55°C to 125°C
2
150
TC = 210°C
2
100
2
VDDIO
High-level input voltage, VIH
Low-level input voltage, VIL
High-level output source current, VOH = 2.4 V,
IOH
All I/Os except Group 2
–4
-8
All I/Os except Group 2
Case temperature, TC
S version
(1)
6.3
Group 2
V
0.8
Group 2 (1)
Low-level output sink current, VOL = VOL MAX,
IOL
MHz
4
(1)
8
– 55
mA
mA
210
Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, EMU1, XINTF pins, GPIO35-87, XRD.
Electrical Characteristics
Minimum and maximum parameters are characterized for operation at TC = 210°C unless otherwise noted, but may not be
production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature
performance.
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
IIL
Input current
(low level)
IIH
Input current
(high level)
MIN
IOH = IOHMAX
TYP
MAX
2.4
IOH = 50 μA
IOL = IOLMAX
0.4
VDDIO = 3.3 V, VIN = 0 V
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = 0 V
±2
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = VDDIO
±2
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = VDDIO
Output current, pullup or
pulldown disabled
CI
Input capacitance
All I/Os (including XRS)
– 80
28
– 140
V
– 190
μA
μA
50
VO = VDDIO or 0 V
Electrical Specifications
UNIT
V
VDDIO – 0.2
Pin with pullup
enabled
IOZ
102
TEST CONDITIONS
80
±2
2
μA
pF
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6.4
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Current Consumption
Table 6-1. Current Consumption by Power Supply Pins
MODE
IDLE
STANDBY
HALT (8)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
TC = -55°C to
125°C at
150-MHz
SYSCLKOUT
290
MAX
TYP
315
30
(5)
MAX
TYP
MAX
50
3
40
IDDA33 (4)
IDDA18 (3)
TYP
(5)
30
MAX
TYP (5)
MAX
35
1.5
2
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Operational
(Flash) (6)
The following peripheral
clocks are enabled:
•
ePWM1/2/3/4/5/6
•
eCAP1/2/3/4/5/6
•
eQEP1/2
•
eCAN-A
•
SCI-A/B (FIFO
mode)
•
SPI-A (FIFO
mode)
•
ADC
•
I2C
•
CPU Timer 0/1/2
All PWM pins are
toggled at 150 kHz.
All I/O pins are left
unconnected. (7)
TYP
(5)
IDD3VFL (2)
IDDIO (1)
IDD
TEST CONDITIONS
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
•
eCAN-A
•
SCI-A
•
SPI-A
•
I2C
Flash is powered down.
Peripheral clocks are
off.
Flash is powered down.
Peripheral clocks are
off.
Input clock is
disabled. (9)
mA
TC = 210°C at
100-MHz
SYSCLKOUT
300
350
30
50
35
40
35
40
1.5
2.5
TC = -55°C to
125°C at
150-MHz
SYSCLKOUT
100
120
0.060
0.120
0.002
0.010
0.005
0.060
0.015
0.020
mA
TC = 210°C at
100-MHz
SYSCLKOUT
120
160
0.110
0.300
0.002
0.010
0.130
0.060
0.015
0.020
TC = -55°C to
125°C at
150-MHz
SYSCLKOUT
8
15
0.060
0.120
0.002
0.010
0.005
0.060
0.015
0.020
TC = 210°C at
100-MHz
SYSCLKOUT
20
TC = -55°C to
125°C at
150-MHz
SYSCLKOUT
0.150
TC = 210°C at
100-MHz
SYSCLKOUT
5
60
mA
0.110
0.300
0.002
0.010
0.130
0.600
0.015
0.020
0.060
0.120
0.002
0.010
0.005
0.060
0.015
0.020
0.110
0.300
0.002
0.010
0.130
0.600
0.015
UNITS
mA
0.020
IDDIO current is dependent on the electrical loading on the I/O pins.
The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Table 6-65. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
For TJ = -55°C to 125°C, the TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and
MAX voltage (VDD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
When the identical code is run off SARAM, IDD would increase as the code operates with zero wait states.
The following is done in a loop:
• Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
• Multiplication/addition operations are performed.
• Watchdog is reset.
• ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
• 32-bit read/write of the XINTF is performed.
• GPIO19 is toggled.
HALT mode IDD currents will increase with temperature in a non-linear fashion.
If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
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NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may
share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the
same time, although such a configuration is not useful. If this is done, the current drawn by
the device will be more than the numbers specified in the current consumption tables.
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Electrical Specifications
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6.4.1
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Reducing Current Consumption
The F28335 DSC incorporates a method to reduce the device current consumption. Since each peripheral
unit has an individual clock-enable bit, reduction in current consumption can be achieved by turning off the
clock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-2
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 6-2. Typical Current Consumption by Various
Peripherals (at 150 MHz) (1) (2)
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(1)
(2)
(3)
(4)
(5)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION/MODULE (mA) (3)
ADC
8 (4)
I2C
2.5
eQEP
5
ePWM
5
eCAP
2
SCI
5
SPI
4
eCAN
8
McBSP
7
CPU - Timer
2
XINTF
10 (5)
DMA
10
FPU
15
All peripheral clocks are disabled upon reset. Writing to/reading from
peripheral registers is possible only after the peripheral clocks are
turned on.
Not production tested.
For peripherals with multiple instances, the current quoted is per
module. For example, the 5 mA number quoted for ePWM is for one
ePWM module.
This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the ADC
(IDDA18) as well.
Operating the XINTF bus has a significant effect on IDDIO current. It
will increase considerably based on the following:
• How many address/data pins toggle from one cycle to another
• How fast they toggle
• Whether 16-bit or 32-bit interface is used and
• The load on these pins.
Following are other methods to reduce power consumption further:
• The Flash module may be powered down if code is run off SARAM. This results in a current reduction
of 35 mA (typical) in the VDD3VFL rail.
• IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
• Significant savings in IDDIO may be realized by disabling the pullups on pins that assume an output
function and on XINTF pins. A savings of 35 mW (typical) can be achieved by this.
The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is
165 mA, (typical). To arrive at the IDD current for a given application, the current-drawn by the peripherals
(enabled by that application) must be added to the baseline IDD current.
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6.4.2
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Current Consumption Graphs
Current vs Frequency
350.00
300.00
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Current (mA)
250.00
200.00
150.00
100.00
50.00
0.00
10
20
30
40
50
60
70
80
90
100
110
120
130 140
150
Frequency (MHz)
IDD
IDDA18
IDD3VFL
IDDA33
IDDIO
1.9V Supply
3.3V Supply
Figure 6-2. Typical Operational Current Versus Frequency for TA = 25°C
106
Electrical Specifications
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Current vs Frequency
300.00
250.00
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Current (mA)
200.00
150.00
100.00
50.00
0.00
10
20
IDD
30
IDDIO
40
IDDA18
50
60
Frequency(MHz)
IDDA33
70
IDD3VFL
80
90
1.9V Supply
100
3.3V Supply
Figure 6-3. Typical Operational Current Versus Frequency for TA = 210°C
6.4.3
Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary.
Systems with more than 1 Watt power dissipation may require a product level thermal design. Care should
be taken to keep Tj within specified limits. In the end applications, Tcase should be measured to estimate
the operating junction temperature Tj. Tcase is normally measured at the center of the package top side
surface.
6.5
Emulator Connection Without Signal Buffering for the DSP
Figure 6-4 shows the connection between the DSP and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-4 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.
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6 inches or less
VDDIO
VDDIO
5
13
EMU0
PD
EMU0
14
EMU1
EMU1
4
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2
TRST
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
6
1
TMS
8
3
TDI
10
7
TDO
12
11
TCK
9
TCK_RET
DSP
JTAG Header
Figure 6-4. Emulator Connection Without Signal Buffering for the DSP
108
Electrical Specifications
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6.6
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Letters and symbols and their
meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
f
fall time
X
Unknown, changing, or don't care
level
h
hold time
Z
High impedance
r
rise time
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6.6.1
Lowercase subscripts and their
meanings:
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.6.2
Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
42 Ω
Data Sheet Timing Reference Point
3.5 nH
Transmission Line
Z0 = 50 Ω(Α)
Output
Under
Test
Device Pin(B)
4.0 pF
A.
B.
1.85 pF
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-5. 3.3-V Test Load Circuit
6.6.3
Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available. Table 6-3 and Table 6-5 list the cycle times of various clocks.
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Table 6-3. Clocking Nomenclature for TC = -55°C to 125°C (150-MHz Devices) (1)
MIN
On-chip oscillator
clock
Frequency
tc(SCO), Cycle time
SYSCLKOUT
LSPCLK (3)
ADC clock
(1)
(2)
(3)
(4)
Frequency
tc(XCO), Cycle time
Frequency
50
ns
35
MHz
6.67
250
ns
4
150
MHz
6.67
500
ns
2
150
MHz
6.67
2000
ns
150
MHz
150
MHz
75
MHz
25
MHz
MAX
UNIT
6.67
13.3 (4)
75 (4)
Frequency
tc(LCO), Cycle time
13.3
ns
26.7 (4)
37.5 (4)
Frequency
tc(ADCCLK), Cycle time
UNIT
20
0.5
tc(HCO), Cycle time
MAX
28.6
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HSPCLK (3)
Frequency
tc(CI), Cycle time
XCLKIN (2)
XCLKOUT
tc(OSC), Cycle time
NOM
ns
40
Frequency
ns
Not production tested.
This also applies to the X1 pin if a 1.9-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 150 MHz.
Table 6-4. Clocking Nomenclature for TC = 210°C (100-MHz Devices) (1)
MIN
On-chip oscillator
clock
XCLKIN (2)
SYSCLKOUT
XCLKOUT
HSPCLK (3)
LSPCLK (3)
ADC clock
(1)
(2)
(3)
(4)
110
tc(OSC), Cycle time
NOM
28.6
50
ns
Frequency
20
35
MHz
tc(CI), Cycle time
10
250
ns
4
100
MHz
10
500
ns
2
100
MHz
tc(XCO), Cycle time
10
2000
ns
Frequency
0.5
100
MHz
tc(HCO), Cycle time
10
Frequency
tc(SCO), Cycle time
Frequency
Frequency
20 (4)
50
tc(LCO), Cycle time
20
(4)
tc(ADCCLK), Cycle time
100
MHz
50
MHz
25
MHz
40 (4)
25 (4)
Frequency
ns
ns
40
Frequency
ns
Not production tested.
This also applies to the X1 pin if a 1.9-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 100 MHz.
Electrical Specifications
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6.7
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Clock Requirements and Characteristics
Table 6-5. Input Clock Frequency (1)
PARAMETER
MIN
Resonator (X1/X2) (2)
fx
Crystal (X1/X2) (2)
Input clock frequency
External oscillator/clock
source (XCLKIN or X1 pin)
fl
TYP
UNIT
35
20
35
150-MHz device
4
150
100-MHz device
4
100
Limp mode SYSCLKOUT frequency range (with /2 enabled)
1-5
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(1)
(2)
MAX
20
MHz
MHz
Not production tested.
Not guaranteed for TC > 125°C.
Table 6-6. XCLKIN Timing Requirements - PLL Enabled (1)
NO.
C8
tc(CI)
C9
tf(CI)
C10
tr(CI)
C11
tw(CIL)
C12
tw(CIH)
(1)
(2)
Cycle time, XCLKIN
MIN
MAX
33.3
200
ns
6
ns
6
ns
Fall time, XCLKIN (2)
Rise time, XCLKIN (2)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
(2)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
(2)
UNIT
45
55
%
45
55
%
Not production tested.
This applies to the X1 pin also.
Table 6-7. XCLKIN Timing Requirements - PLL Disabled (1)
NO.
C8
C9
tc(CI)
tf(CI)
C10
tr(CI)
C11
tw(CIL)
C12
tw(CIH)
Cycle time, XCLKIN
Fall time, XCLKIN (2)
Rise time, XCLKIN (2)
MIN
MAX
UNIT
150-MHz device
6.67
250
ns
100-MHz device
10
250
Up to 30 MHz
6
ns
30 MHz to 150 MHz
2
ns
Up to 30 MHz
6
ns
30 MHz to 150 MHz
(1)
(2)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
(2)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
(2)
2
ns
45
55
%
45
55
%
Not production tested.
This applies to the X1 pin also.
The possible configuration modes are shown in Table 3-16.
Table 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1)
NO.
C1
PARAMETER
tc(XCO)
Cycle time, XCLKOUT
6.67
100-MHz device
10
TYP
MAX
UNIT
ns
C3
tf(XCO)
Fall time, XCLKOUT
2
C4
tr(XCO)
Rise time, XCLKOUT
2
C5
tw(XCOL)
Pulse duration, XCLKOUT low
H–2
H+2
ns
C6
tw(XCOH)
Pulse duration, XCLKOUT high
H–2
H+2
ns
tp
(1)
(2)
(3)
(4)
MIN
150-MHz device
(2) (3)
PLL lock time
ns
ns
131072tc(OSCCLK)
(4)
cycles
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
Not production tested.
OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
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C10
C9
C8
XCLKIN(A)
C6
C3
C1
C4
C5
XCLKOUT(B)
B.
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
XCLKOUT configured to reflect SYSCLKOUT.
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A.
Figure 6-6. Clock Timing
6.8
Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers
of the I/O pins are powered prior to the 1.9-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or
simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins
reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see Table 610). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 μs prior to VDD reaching 1.5 V. This is to
enhance flash reliability.
Additionally it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any
pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal PN junctions in unintended ways and produce unpredictable results.
6.8.1
Power Management and Supervisory Circuit Solutions
Table 6-9 lists the power management and supervisory circuit solutions for 2833x/2823x devices. LDO
selection depends on the total power consumed in the end application. Go to www.ti.com and click on
Power Management for a complete list of TI power ICs or select the Power Management Selection Guide
link for specific power reference designs.
Table 6-9. Power Management and Supervisory Circuit Solutions
TYPE
PART
Texas Instruments
SUPPLIER
LDO
TPS767D301
DESCRIPTION
Texas Instruments
LDO
TPS70202
Dual 500/250-mA LDO with SVS
Texas Instruments
LDO
TPS766xx
250-mA LDO with PG
Texas Instruments
SVS
TPS3808
Open Drain SVS with programmable delay
Texas Instruments
SVS
TPS3803
Low-cost Open-drain SVS with 5 μS delay
Texas Instruments
LDO
TPS799xx
200-mA LDO in WCSP package
Dual 1-A low-dropout regulator (LDO) with supply voltage supervisor (SVS)
Texas Instruments
LDO
TPS736xx
400-mA LDO with 40 mV of VDO
Texas Instruments
DC/DC
TPS62110
High Vin 1.2-A dc/dc converter in 4x4 QFN package
Texas Instruments
DC/DC
TPS6230x
500-mA converter in WCSP package
112
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VDDIO, VDD3VFL
VDDA2, VDDAIO
(3.3 V)
VDD, VDD1A18,
VDD2A18
(1.9 V/1.8 V)
XCLKIN
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X1/X2
OSCCLK/16(A)
XCLKOUT
OSCCLK/8
User-Code Dependent
tOSCST
tw(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
td(EX)
th(boot-mode)(B)
Boot-Mode
Pins
User-Code Execution Phase
User-Code Dependent
GPIO Pins as Input
Peripheral/GPIO Function
Based on Boot Code
Boot-ROM Execution Starts
I/O Pins(C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A.
B.
C.
Upon power up, SYSCLKOUT is OSCCLK/4. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains
why XCLKOUT = OSCCLK/16 during this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCCLK/2.
Because the XTIMCLK register is unchanged by the boot ROM, XCLKOUT is OSCCLK/8 during this phase.
After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.
Figure 6-7. Power-on Reset
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Table 6-10. Reset (XRS) Timing Requirements (1)
MIN
(2)
tw(RSL1)
Pulse duration, stable input clock to XRS high
tw(RSL2)
Pulse duration, XRS low
tw(WDRS)
Pulse duration, reset pulse generated by
watchdog
td(EX)
Delay time, address/data valid after XRS high
tOSCST
(3)
UNIT
32tc(OSCCLK)
cycles
512tc(OSCCLK)
cycles
32tc(OSCCLK)
cycles
1
Hold time for boot-mode pins
MAX
cycles
Oscillator start-up time
th(boot-mode)
10
200tc(OSCCLK)
ms
cycles
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(1)
(2)
(3)
Warm reset
NOM
32tc(OSCCLK)
Not production tested.
In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
User-Code Dependent
OSCCLK * 5
tw(RSL2)
XRS
Address/Data/
Control
(Internal)
td(EX)
User-Code Execution
(Don’t Care)
Boot-ROM Execution Starts
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Execution Phase
GPIO Pins as Input
th(boot-mode)(A)
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A.
After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-8. Warm Reset
Figure 6-9 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
114
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OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, tp) is
131072 OSCCLK Cycles Long.)
(Changed CPU Frequency)
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OSCCLK * 2
Figure 6-9. Example of Effect of Writing Into PLLCR Register
6.9
General-Purpose Input/Output (GPIO)
6.9.1
GPIO - Output Timing
Table 6-11. General-Purpose Output Switching Characteristics (1)
PARAMETER
tr(GPO)
tf(GPO)
tfGPO
(1)
MIN
MAX
UNIT
Rise time, GPIO switching low to high
All GPIOs
8
ns
Fall time, GPIO switching high to low
All GPIOs
8
ns
25
MHz
Toggling frequency, GPO pins
Not production tested.
GPIO
tf(GPO)
tr(GPO)
Figure 6-10. General-Purpose Output Timing
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6.9.2
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GPIO - Input Timing
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
tw(SP)
0
0
1
1
1
1
1
1
1
1
1
Sampling Period determined
by GPxCTRL[QUALPRD](B)
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tw(IQSW)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A.
B.
C.
D.
This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled).
The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 6-11. Sampling Mode
Table 6-12. General-Purpose Input Timing Requirements (1)
MIN
tw(SP)
Sampling period
tw(IQSW)
Input qualifier sampling window
tw(GPI)
(1)
(2)
(3)
116
(3)
Pulse duration, GPIO low/high
MAX
UNIT
QUALPRD = 0
1tc(SCO)
cycles
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
cycles
tw(SP) * (n (2) – 1)
cycles
Synchronous mode
With input qualifier
2tc(SCO)
cycles
tw(IQSW) + tw(SP) + 1tc(SCO)
cycles
Not production tested.
"n" represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
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6.9.3
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
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Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
XCLKOUT
GPIOxn
tw(GPI)
Figure 6-12. General-Purpose Input Timing
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6.9.4
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Low-Power Mode Wakeup Timing
Table 6-13 shows the timing requirements, Table 6-14 shows the switching characteristics, and Figure 613 shows the timing diagram for IDLE mode.
Table 6-13. IDLE Mode Timing Requirements (1)
MIN
Pulse duration, external wake-up
signal
tw(WAKE-INT)
(1)
Without input qualifier
NOM
MAX
2tc(SCO)
With input qualifier
UNIT
cycles
5tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Table 6-12.
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Table 6-14. IDLE Mode Switching Characteristics (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20tc(SCO)
cycles
Delay time, external wake signal to
program execution resume (2)
td(WAKE-IDLE)
Wake-up from Flash
•
Flash module in active state
Without input qualifier
Wake-up from Flash
•
Flash module in sleep state
Without input qualifier
•
Without input qualifier
With input qualifier
20tc(SCO) + tw(IQSW)
1050tc(SCO)
With input qualifier
Wake-up from SARAM
1050tc(SCO) + tw(IQSW)
With input qualifier
(1)
(2)
cycles
20tc(SCO)
cycles
20tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Table 6-12.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
td(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE−INT)
WAKE INT(A)
A.
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-13. IDLE Entry and Exit Timing
Table 6-15. STANDBY Mode Timing Requirements
TEST CONDITIONS
tw(WAKE-INT)
(1)
118
Pulse duration, external
wake-up signal
MIN
Without input qualification
With input qualification (1)
3tc(OSCCLK)
(2 + QUALSTDBY) * tc(OSCCLK)
NOM
MAX
UNIT
cycles
QUALSTDBY is a 6-bit field in the LPMCR0 register.
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Table 6-16. STANDBY Mode Switching Characteristics (1)
PARAMETER
TEST CONDITIONS
td(IDLE-XCOL)
Delay time, IDLE instruction
executed to XCLKOUT low
td(WAKE-STBY)
Delay time, external wake
signal to program execution
resume (2)
•
MIN
TYP
32tc(SCO)
Without input qualifier
Wake up from flash
– Flash module in active
state
(1)
(2)
45tc(SCO)
cycles
100tc(SCO)
With input qualifier
100tc(SCO) + tw(WAKE-INT)
Without input qualifier
Wake up from flash
– Flash module in sleep
state
With input qualifier
Wake up from SARAM
cycles
1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)
Without input qualifier
•
UNIT
cycles
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•
MAX
With input qualifier
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
cycles
cycles
Not production tested.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
(A)
(C)
(B)
Device
Status
STANDBY
(E)
(D)
(F)
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
td(IDLE−XCOL)
A.
B.
C.
D.
E.
F.
IDLE instruction is executed to put the device into STANDBY mode.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
•
16 cycles, when DIVSEL = 00 or 01
•
32 cycles, when DIVSEL = 10
•
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is
in progress and its access time is longer than this number then it will fail.� It is recommended to enter STANDBY
mode from SARAM without an XINTF access in progress.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
The external wake-up signal is driven active.
After a latency period, the STANDBY mode is exited.
Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-14. STANDBY Entry and Exit Timing Diagram
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Table 6-17. HALT Mode Timing Requirements (1)
MIN
tw(WAKE-GPIO)
Pulse duration, GPIO wake-up signal
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
(1)
(2)
NOM
MAX
UNIT
(2)
cycles
toscst + 8tc(OSCCLK)
cycles
toscst + 2tc(OSCCLK)
Not production tested.
See Table 6-10 for an explanation of toscst.
Table 6-18. HALT Mode Switching Characteristics (1)
PARAMETER
tp
Delay time, PLL lock to program execution resume
•
Wake up from flash
– Flash module in sleep state
•
(1)
120
32tc(SCO)
PLL lock-up time
td(WAKE-HALT)
TYP
MAX
UNIT
45tc(SCO)
cycles
131072tc(OSCCLK)
cycles
1125tc(SCO)
cycles
35tc(SCO)
cycles
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td(IDLE-XCOL)
MIN
Delay time, IDLE instruction executed to XCLKOUT
low
Wake up from SARAM
Not production tested.
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(A)
(C)
(D)
Device
Status
HALT
Flushing Pipeline
(G)
(E)
(B)
(F)
HALT
PLL Lock-up Time
Wake-up Latency
Normal
Execution
GPIOn
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td(WAKE−HALT)
tw(WAKE-GPIO)
tp
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
td(IDLE−XCOL)
A.
B.
C.
D.
E.
F.
G.
IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before
oscillator is turned off and the CLKIN to the core is stopped:
•
16 cycles, when DIVSEL = 00 or 01
•
32 cycles, when DIVSEL = 10
•
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in
progress and its access time is longer than this number then it will fail.� It is recommended to enter HALT mode from
SARAM without an XINTF access in progress.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup process, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles. Note that these 131,072 clock cycles are applicable even when the PLL is disabled (i.e., code
execution will be delayed by this duration even when the PLL is disabled).
Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the
interrupt (if enabled), after a latency.
Normal operation resumes.
Figure 6-15. HALT Wake-Up Using GPIOn
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6.10 Enhanced Control Peripherals
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1-6. Table 6-19 shows the PWM timing requirements and Table 620, switching characteristics.
Table 6-19. ePWM Timing Requirements (1) (2)
TEST CONDITIONS
tw(SYCIN)
Sync input pulse width
MIN
Asynchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
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(1)
(2)
UNIT
cycles
Synchronous
With input qualifier
MAX
2tc(SCO)
For an explanation of the input qualifier parameters, see Table 6-12.
Not production tested.
Table 6-20. ePWM Switching Characteristics (1)
PARAMETER
tw(PWM)
MIN
Pulse duration, PWMx output high/low
tw(SYNCOUT)
td(PWM)tza
MAX
20
Sync output pulse width
no pin load
Delay time, trip input active to PWM Hi-Z
UNIT
ns
8tc(SCO)
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ
(1)
TEST CONDITIONS
cycles
25
ns
20
ns
Not production tested.
6.10.2 Trip-Zone Input Timing
XCLKOUT(A)
tw(TZ)
TZ
td(TZ-PWM)HZ
PWM(B)
A.
B.
TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-16. PWM Hi-Z Characteristics
Table 6-21. Trip-Zone input Timing Requirements (1) (2)
MIN
tw(TZ)
Pulse duration, TZx input low
122
UNIT
Asynchronous
1tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
With input qualifier
(1)
(2)
MAX
For an explanation of the input qualifier parameters, see Table 6-12.
Not production tested.
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Table 6-22 shows the high-resolution PWM switching characteristics.
Table 6-22. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 120 MHz) (1)
MIN
Micro Edge Positioning (MEP) step size
(1)
(2)
(2)
TYP
MAX
UNIT
150
310
ps
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Not production tested.
Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
Table 6-23 shows the eCAP timing requirement and Table 6-24 shows the eCAP switching characteristics.
Table 6-23. Enhanced Capture (eCAP) Timing Requirement (1)
(2)
TEST CONDITIONS
tw(CAP)
Capture input pulse width
MIN
Asynchronous
(1)
(2)
UNIT
cycles
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
Synchronous
With input qualifier
MAX
2tc(SCO)
For an explanation of the input qualifier parameters, see Table 6-12.
Not production tested.
Table 6-24. eCAP Switching Characteristics (1)
PARAMETER
tw(APWM)
(1)
TEST CONDITIONS
MIN
Pulse duration, APWMx output high/low
MAX
UNIT
20
ns
Not production tested.
Table 6-25 shows the eQEP timing requirement and Table 6-26 shows the eQEP switching
characteristics.
Table 6-25. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1) (2)
TEST CONDITIONS
tw(QEPP)
QEP input period
Asynchronous/synchronous
With input qualifier
tw(INDEXH)
QEP Index Input High time
QEP Index Input Low time
tw(STROBH)
QEP Strobe High time
Asynchronous/synchronous
QEP Strobe Input Low time
Asynchronous/synchronous
With input qualifier
tw(STROBL)
With input qualifier
(1)
(2)
UNIT
2tc(SCO)
cycles
cycles
2tc(SCO)
cycles
2tc(SCO) +tw(IQSW)
cycles
Asynchronous/synchronous
With input qualifier
MAX
2(1tc(SCO) + tw(IQSW))
Asynchronous/synchronous
With input qualifier
tw(INDEXL)
MIN
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
cycles
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
cycles
2tc(SCO)
cycles
2tc(SCO) +tw(IQSW)
cycles
For an explanation of the input qualifier parameters, see Table 6-12.
Not production tested.
Table 6-26. eQEP Switching Characteristics (1)
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
PARAMETER
4tc(SCO)
cycles
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync
output
6tc(SCO)
cycles
(1)
TEST CONDITIONS
MIN
Not production tested.
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Table 6-27. External ADC Start-of-Conversion Switching Characteristics (1)
PARAMETER
tw(ADCSOCAL)
(1)
MIN
Pulse duration, ADCSOCAO low
MAX
32tc(HCO )
UNIT
cycles
Not production tested.
tw(ADCSOCAL)
ADCSOCAO
or
ADCSOCBO
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Figure 6-17. ADCSOCAO or ADCSOCBO Timing
6.11 External Interrupt Timing
tw(INT)
XNMI, XINT1, XINT2
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 6-18. External Interrupt Timing
Table 6-28. External Interrupt Timing Requirements (1) (2)
TEST CONDITIONS
tw(INT)
(1)
(2)
(3)
(3)
Pulse duration, INT input low/high
MIN
MAX
UNIT
Synchronous
1tc(SCO)
cycles
With qualifier
1tc(SCO) + tw(IQSW)
cycles
For an explanation of the input qualifier parameters, see Table 6-12.
Not production tested.
This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-29. External Interrupt Switching Characteristics (1) (2)
PARAMETER
td(INT)
(1)
(2)
124
Delay time, INT low/high to interrupt-vector fetch
MIN
MAX
UNIT
tw(IQSW) + 12tc(SCO)
cycles
For an explanation of the input qualifier parameters, see Table 6-12.
Not production tested.
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
6.12 I2C Electrical Specification and Timing
Table 6-30. I2C Timing (1)
TEST CONDITIONS
MIN
UNIT
400
kHz
SCL clock frequency
vil
Low level input voltage
Vih
High level input voltage
Vhys
Input hysteresis
Vol
Low level output voltage
3-mA sink current
tLOW
Low period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
μs
tHIGH
High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
μs
lI
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
0.3 VDDIO
0.7 VDDIO
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(1)
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
MAX
fSCL
V
0.05 VDDIO
0
-10
V
V
0.4
10
V
μA
Not production tested.
6.13 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
6.13.1 Master Mode Timing
Table 6-31 lists the master mode timing (clock phase = 0) and Table 6-32 lists the timing (clock
phase = 1). Figure 6-19 and Figure 6-20 show the timing waveforms.
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Table 6-31. SPI Master Mode External Timing (Clock Phase = 0) (1)
NO.
MIN
MAX
MIN
MAX
128tc(LCO)
5tc(LCO)
127tc(LCO)
ns
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M - 0.5tc(LCO)
ns
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M - 0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO)-10
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO)- 10
0.5tc(SPC)M + 0.5tc(LCO)
td(SPCH-SIMO)M
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
10
10
td(SPCL-SIMO)M
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
10
10
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M + 0.5tc(LCO) -10
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M + 0.5tc(LCO) -10
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
35
35
ns
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
35
35
ns
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25tc(SPC)M -10
0.5tc(SPC)M- 0.5tc(LCO)- 10
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
0.25tc(SPC)M - 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
tc(SPC)M
Cycle time, SPICLK
2
tw(SPCH)M
4
5
8
9
(1)
(2)
(3)
(4)
(5)
(6)
126
UNIT
4tc(LCO)
1
3
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
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SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
(2) (3) (4) (5) (6)
ns
ns
ns
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
Not production tested.
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SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
SPISOMI
Master In Data
Must Be Valid
SPISTE(A)
A.
In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-19. SPI Master Mode External Timing (Clock Phase = 0)
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Table 6-32. SPI Master Mode External Timing (Clock Phase = 1) (1)
NO.
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
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SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0
OR 2
(2) (3) (4) (5) (6)
MIN
MAX
MIN
UNIT
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
ns
2
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc (LCO)10
0.5tc(SPC)M - 0.5tc(LCO)
ns
tw(SPCL))M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc (LCO)10
0.5tc(SPC)M - 0.5tc(LCO
ns
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) 10
0.5tc(SPC)M + 0.5tc(LCO)
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) 10
0.5tc(SPC)M + 0.5tc(LCO)
ns
tsu(SIMO-SPCH)M
Setup time, SPISIMO data valid before
SPICLK high (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 10
ns
tsu(SIMO-SPCL)M
Setup time, SPISIMO data valid before
SPICLK low (clock polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M - 10
ns
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 10
ns
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
ns
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high
(clock polarity = 0)
35
35
ns
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 1)
35
35
ns
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
0.25tc(SPC)M -10
0.5tc(SPC)M -10
ns
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
0.25tc(SPC)M -10
0.5tc(SPC)M -10
ns
3
6
7
10
11
(1)
(2)
(3)
(4)
(5)
(6)
128
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5 MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
Not production tested.
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SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
Master Out Data Is Valid
SPISIMO
Data Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
A.
In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-20. SPI Master Mode External Timing (Clock Phase = 1)
6.13.2 SPI Slave Mode Timing
Table 6-33 lists the slave mode external timing (clock phase = 0) and Table 6-34 (clock phase = 1). Figure 6-21 and Figure 6-22 show the timing
waveforms.
Table 6-33. SPI Slave Mode External Timing (Clock Phase = 0) (1)
NO.
12
(1)
(2)
(3)
(4)
(5)
(6)
tc(SPC)S
Cycle time, SPICLK
(2) (3) (4) (5) (6)
MIN
MAX
UNIT
4tc(LCO)
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
Not production tested.
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Table 6-33. SPI Slave Mode External Timing (Clock Phase = 0)(1) (2)
(3) (4) (5)(6)
(continued)
NO.
tw(SPCH)S
tw(SPCL)S
14
tw(SPCL)S
15
td(SPCH-SOMI)S
tw(SPCH)S
td(SPCL-SOMI)S
16
tv(SPCL-SOMI)S
tv(SPCH-SOMI)S
19
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
20
tv(SPCL-SIMO)S
tv(SPCH-SIMO)S
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MIN
MAX
UNIT
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
35
ns
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
35
ns
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
0.75tc(SPC)S
ns
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0.75tc(SPC)S
ns
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
35
ns
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
35
ns
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)S-10
ns
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)S-10
ns
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
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15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE(A)
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-21. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-34. SPI Slave Mode External Timing (Clock Phase = 1) (1)
NO.
(2) (3) (4) (5)
MIN
MAX
12
tc(SPC)S
Cycle time, SPICLK
13
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC) S
ns
14
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC) S
ns
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
17
tsu(SOMI-SPCH)S
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
0.125tc(SPC)S
ns
tsu(SOMI-SPCL)S
Setup time, SPISOMI before SPICLK low (clock polarity = 1
0.125tc(SPC)S
ns
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
0.75tc(SPC)S
ns
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0.75tc(SPC) S
ns
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
35
ns
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
35
ns
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S-10
ns
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)S-10
ns
18
21
22
(1)
(2)
(3)
(4)
(5)
8tc(LCO)
UNIT
ns
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
Not production tested.
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
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18
SPISOMI
Data Valid
SPISOMI Data Is Valid
21
22
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE(A)
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-22. SPI Slave Mode External Timing (Clock Phase = 1)
6.14 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 6-35 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-35. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DURATION (ns) (1)
DESCRIPTION
X2TIMING = 0
(2)
X2TIMING = 1
LR
Lead period, read access
XRDLEAD × tc(XTIM)
(XRDLEAD × 2) × tc(XTIM)
AR
Active period, read access
(XRDACTIVE + WS + 1) × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
TR
Trail period, read access
XRDTRAIL × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
LW
Lead period, write access
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
AW
Active period, write access
(XWRACTIVE + WS + 1) × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
TW
Trail period, write access
XWRTRAIL × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
(1)
(2)
tc(XTIM) − Cycle time, XTIMCLK
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No
internal device hardware is included to detect illegal settings.
6.14.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
132
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LR ≥ tc(XTIM)
Lead:
LW ≥ tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥1
≥0
≥0
≥1
≥0
≥0
0, 1
Examples of valid and invalid timing when not sampling XREADY:
Invalid (1)
(1)
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0
0
0
0
0
0
0, 1
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Valid
XRDLEAD
1
0
0
1
0
0
0, 1
No hardware to detect illegal XTIMING configurations
6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1
Lead:
LR ≥ × tc(XTIM)
LW ≥ tc(XTIM)
2
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
NOTE
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥1
≥1
≥0
≥1
≥1
≥0
0, 1
Examples of valid and invalid timing when using synchronous XREADY:
Invalid
(1)
Invalid (1)
Valid
(1)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0
0
0
0
0
0
0, 1
1
0
0
1
0
0
0, 1
1
1
0
1
1
0
0, 1
No hardware to detect illegal XTIMING configurations
6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1
Lead:
LR ≥ × tc(XTIM)
LW ≥ tc(XTIM)
2
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
3
Lead +
Active:
LR + AR ≥ 4 ×
tc(XTIM)
LW + AW ≥ 4 ×
tc(XTIM)
NOTE
Restrictions do not include external hardware wait states.
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These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥1
≥2
0
≥1
≥2
0
0, 1
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥2
≥1
0
≥2
≥1
0
0, 1
or
Examples of valid and invalid timing when using asynchronous XREADY:
XRDLEAD
Invalid
(1)
Invalid (1)
Valid
Valid
Valid
(1)
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
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Invalid (1)
X2TIMING
0
0
0
0
0
0
0, 1
1
0
0
1
0
0
0, 1
1
1
0
1
1
0
0
1
1
0
1
1
0
1
1
2
0
1
2
0
0, 1
2
1
0
2
1
0
0, 1
No hardware to detect illegal XTIMING configurations
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-36.
134
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Table 6-36. XINTF Clock Configurations
MODE
SYSCLKOUT
1
Example:
150 MHz
2
Example:
150 MHz
3
Example:
XTIMCLK
XCLKOUT
SYSCLKOUT
SYSCLKOUT
150 MHz
150 MHz
SYSCLKOUT
1/2 SYSCLKOUT
150 MHz
75 MHz
1/2 SYSCLKOUT
1/2 SYSCLKOUT
150 MHz
75 MHz
1/2 SYSCLKOUT
1/4 SYSCLKOUT
75 MHz
37.5 MHz
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4
75 MHz
Example:
150 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6-23 .
PCLKR3[XINTFENCLK]
XTIMING0
0
XTIMING6
0
1
LEAD/ACTIVE/TRAIL
XTIMING7
XBANK
C28x
CPU
SYSCLKOUT
/2
1
0
XTIMCLK
XINTCNF2 (XTIMCLK)
/2
XCLKOUT
1
0
XINTCNF2
(CLKMODE)
XINTCNF2
(CLKOFF)
Figure 6-23. Relationship Between XTIMCLK and SYSCLKOUT
6.14.4 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock
XTIMCLK. Strobes such as XRD, XWE0, XWE1, and zone chip-select (XZCS) change state in relationship
to the rising edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or
one-half the frequency of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the
rising edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change
state either on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables,
the notation XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising
edge (high) or XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of
XCLKOUT, the notation XCOH is used.
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be
aligned can be determined based on the number of XTIMCLK cycles from the start of the access to the
point at which the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with
respect to the rising edge of XCLKOUT. If this number is odd, then the signal will change with respect to
the falling edge of XCLKOUT. Examples include the following:
• Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
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Examples:
•
Zone chip-select active low
XRNWL
XR/W active low
XRDL
XRD active low
XWEL
XWE1 or XWE0 active low
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Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the
total number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If
the number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment
will be with respect to the falling edge of XCLKOUT.
Examples:
•
XZCSL
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if
the total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK
cycles is odd, then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
•
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XRDH
XRD inactive high
XWEH
XWE1 or XWE0 inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total
number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XRNWH
XR/W inactive high
6.14.5 External Interface Read Timing
Table 6-37. External Interface Read Timing Requirements (1)
MIN
ta(A)
Access time, read data from address valid
ta(XRD)
th(XD)XRD
(1)
(2)
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
UNIT
(2)
ns
AR –14
(2)
ns
Access time, read data valid from XRD active low
tsu(XD)XRD
MAX
(LR + AR) –16
14
ns
0
ns
Not production tested.
LR = Lead period, read access. AR = Active period, read access. See Table 6-35.
Table 6-38. External Interface Read Switching Characteristics (1)
PARAMETER
td(XCOH-XZCSL)
MIN
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
td(XCOHL-XRDL)
td(XCOHL-XRDH
th(XA)XZCSH
th(XA)XRD
(1)
(2)
136
–1
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
–1.5
MAX
UNIT
1
ns
0.5
ns
1.5
ns
0.5
ns
0.5
ns
Hold time, address valid after zone chip-select inactive high
(2)
ns
Hold time, address valid after XRD inactive high
(2)
ns
Not production tested.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
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(A)(B)
Trail
Active
Lead
(C)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
td(XCOH-XA)
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XA[0:19]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
(D)
XWE0, XWE1
XR/W
ta(A)
th(XD)XRD
ta(XRD)
XD[0:31], XD[0:15]
XREADY
A.
B.
C.
D.
E.
DIN
(E)
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals transition to their inactive state.
XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-24. Example Read Access
XTIMING register parameters used for this example :
XRDLEAD
≥1
(1)
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥0
≥0
0
0
N/A (1)
N/A (1)
N/A (1)
N/A (1)
N/A = Not applicable (or “Don’t care”) for this example
6.14.6 External Interface Write Timing
Table 6-39. External Interface Write Switching Characteristics (1)
PARAMETER
td(XCOH-XZCSL)
MIN
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
td(XCOHL-XWEL)
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE0, XWE1
(2)
–1
low
MAX
UNIT
1
ns
0.5
ns
1.5
ns
2
ns
ns
Delay time, XCLKOUT high/low to XWE0, XWE1 high
2
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
1
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
0.5
ns
ten(XD)XWEL
Enable time, data bus driven from XWE0, XWE1 low
td(XWEL-XD)
Delay time, data valid after XWE0, XWE1 active low
1
ns
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(1)
(2)
(3)
-1
0
ns
(3)
ns
Not production tested.
XWE1 is used in 32-bit data bus mode only. In 16-bit mode, this signal is XA0.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
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Table 6-39. External Interface Write Switching Characteristics(1) (continued)
PARAMETER
MIN
th(XD)XWE
Hold time, write data valid after XWE0, XWE1 inactive high
tdis(XD)XRNW
Maximum time for DSP to release the data bus after XR/W inactive high
(4)
TW-2
MAX
(4)
UNIT
ns
4
ns
TW = Trail period, write access. See Table 6-35.
(A) (B)
Active
Lead
(C)
Trail
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XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
td(XCOH-XA)
XA[0:19]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
(D)
XWE0, XWE1
A.
B.
C.
D.
E.
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
XD[0:31], XD[0:15]
XREADY
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
DOUT
(E)
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals transition to their inactive state.
XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-25. Example Write Access
XTIMING register parameters used for this example :
XRDLEAD
N/A (1)
(1)
138
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A (1)
N/A (1)
0
0
≥1
≥0
≥0
N/A (1)
N/A = Not applicable (or “Don’t care”) for this example
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6.14.7 External Interface Ready-on-Read Timing With One External Wait State
Table 6-40. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) (1)
PARAMETER
MIN
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive
high
MAX
-1
UNIT
1
ns
0.5
ns
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
1.5
ns
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
0.5
ns
td(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive high
0.5
ns
th(XA)XRD
(1)
(2)
- 1.5
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th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(2)
ns
Hold time, address valid after XRD inactive high
(2)
ns
Not production tested.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus, except XA0, which remains high. This
includes alignment cycles.
Table 6-41. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) (1)
MIN
ta(A)
Access time, read data from address valid
ta(XRD)
Setup time, read data valid before XRD strobe inactive high
th(XD)XRD
(1)
(2)
Hold time, read data valid after XRD inactive high
UNIT
(LR + AR) - 16
(2)
ns
AR - 14
(2)
ns
Access time, read data valid from XRD active low
tsu(XD)XRD
MAX
14
ns
0
ns
Not production tested.
LR = Lead period, read access. AR = Active period, read access. See Table 6-35.
Table 6-42. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) (1) (2)
MIN
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low
th(XRDYsynchL)
Hold time, XREADY (synchronous) low
te(XRDYsynchH)
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
(1)
(2)
UNIT
ns
6
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
th(XRDYsynchH)XZCSH
MAX
12
ns
3
ns
12
ns
0
ns
The first XREADY (synchronous) sample occurs with respect to E in Figure 6-26:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will finish. If XREADY (synchronous) is found to be
low, it is sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Not production tested.
Table 6-43. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) (1)
MIN
tsu(XRDYAsynchL)XCOHL
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
th(XRDYAsynchL)
Hold time, XREADY (asynchronous) low
te(XRDYAsynchH)
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
tsu(XRDYAsynchH)XCOHL
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
th(XRDYasynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip select high
(1)
MAX
11
UNIT
ns
6
ns
3
ns
11
ns
0
ns
Not production tested.
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WS (Synch)
(A) (B)
(C)
Active
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0 XZCS6, XZCS7
td(XCOH-XA)
XA[0:19]
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td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE0, XWE1 (D)
ta(XRD)
XR/W
ta(A)
th(XD)XRD
XD[0:31], XD[0:15]
DIN
tsu(XRDYsynchL)XCOHL
te(XRDYsynchH)
th(XRDYsynchL)
th(XRDYsynchH)XZCSH
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A.
B.
C.
D.
E.
F.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals transition to their inactive state.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
For each sample, setup time from the beginning of the access (E) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n - 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the
sample number: n = 1, 2, 3, and so forth.
Figure 6-26. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
≥1
(1)
140
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
3
≥1
1
0
N/A (1)
N/A (1)
N/A (1)
0 = XREADY
(Synch)
N/A = “Don’t care” for this example
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WS (Async)
(A) (B)
Active
Lead
Trail
(C)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
td(XCOHL-XZCSH)
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td(XCOH-XA)
XA[0:19]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE0, XWE1(D)
ta(XRD)
XR/W
ta(A)
th(XD)XRD
DIN
XD[0:31], XD[0:15]
tsu(XRDYasynchL)XCOHL
te(XRDYasynchH)
th(XRDYasynchH)XZCSH
th(XRDYasynchL)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A.
B.
C.
D.
E.
F.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
For each sample, setup time from the beginning of the access can be calculated as:
E = (XRDLEAD + XRDACTIVE -3 +n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and
so forth.
Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) tc(XTIM)
Figure 6-27. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
≥1
(1)
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
3
≥1
1
0
N/A (1)
N/A (1)
N/A (1)
1 = XREADY
(Async)
N/A = “Don’t care” for this example
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6.14.8 External Interface Ready-on-Write Timing With One External Wait State
Table 6-44. External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) (1)
PARAMETER
MIN
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
td(XCOHL-XWEL)
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE0, XWE1 high (2)
2
ns
1
ns
0.5
ns
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ten(XD)XWEL
Enable time, data bus driven from XWE0, XWE1 low (2)
(4)
Delay time, data valid after XWE0, XWE1 active low
–1
0
(2)
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high (2)
tdis(XD)XRNW
ns
ns
Delay time, XCLKOUT high/low to XR/W high
(1)
(2)
(3)
0.5
2
td(XCOHL-XRNWH)
th(XD)XWE
ns
Delay time, XCLKOUT high/low to XWE0, XWE1 low (2)
Delay time, XCLKOUT high to XR/W low
th(XA)XZCSH
–1
UNIT
1
1.5
td(XCOH-XRNWL)
td(XWEL-XD)
MAX
TW-2
ns
1
ns
(3)
ns
(4)
ns
Maximum time for DSP to release the data bus after XR/W inactive high
4
ns
Not production tested.
XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
TW = trail period, write access (see Table 6-35)
Table 6-45. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) (1) (2)
MIN
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low
th(XRDYsynchL)
Hold time, XREADY (synchronous) low
te(XRDYsynchH)
Setup time, XREADY (synchronous) high before XCLKOUT high/low
th(XRDYsynchH)XZCSH
Hold time, XREADY (synchronous) held high after zone chip select high
(2)
UNIT
ns
6
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
tsu(XRDYsynchH)XCOHL
(1)
MAX
12
ns
3
ns
12
ns
0
ns
The first XREADY (synchronous) sample occurs with respect to E in Figure 6-28:
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is high, then the access will complete. If XREADY (synchronous) is low, it is sampled
again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE +n –1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Not production tested.
Table 6-46. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) (1) (2)
MIN
tsu(XRDYasynchL)XCOHL
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
th(XRDYasynchL)
Hold time, XREADY (asynchronous) low
te(XRDYasynchH)
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
th(XRDYasynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip select high
(2)
142
UNIT
ns
6
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
tsu(XRDYasynchH)XCOHL
(1)
MAX
11
ns
3
ns
11
ns
0
ns
The first XREADY (synchronous) sample occurs with respect to E in Figure 6-28:
E = (XWRLEAD + XWRACTIVE –2) tc(XTIM). When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Not production tested.
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WS (Synch)
(A) (B)
(C)
Trail
Active
Lead 1
(D)
XCLKOUT = XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
th(XRDYsynchH)XZCSH
td(XCOH-XA)
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XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
td(XWEL-XD
th(XD)XWEH
)
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A.
B.
C.
D.
E.
F.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0
For each sample, setup time from the beginning of the access can be calculated as E = (XWRLEAD + XWRACTIVE +
n –1) tc(XTIM) – tsu(XRDYsynchL)XCOH where n is the sample number: n = 1, 2, 3, and so forth.
Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 6-28. Write With Synchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
N/A (1)
(1)
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A (1)
N/A (1)
1
0
≥1
3
≥1
0 = XREADY
(Synch)
N/A = "Don't care" for this example.
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WS (Async)
(A) (B)
(C)
Trail
Active
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
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th(XRDYasynchH)XZCSH
td(XCOH-XA)
XA[0:19]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE0,
XWE1(D)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
XR/W
tdis(XD)XRNW
td(XWEL-XD
th(XD)XWEH
)
ten(XD)XWEL
XD[31:0], XD[15:0]
DOUT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
te(XRDYasynchH)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
(D)
(E)
Legend:
= Don’t care. Signal can be high or low during this time.
A.
B.
C.
D.
E.
F.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals transition to their inactive state.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE
-3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 6-29. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A (1)
N/A (1)
N/A (1)
1
0
≥1
3
≥1
1 = XREADY
(Async)
(1)
144
N/A = “Don’t care” for this example
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6.14.9
SPRS682B – DECEMBER 2010 – REVISED MAY 2012
XHOLD and XHOLDA Timing
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the
bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active
low.
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When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still
execute code from internal memory. If an access is made to the external interface, the CPU is stalled until
the XHOLD signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[19:0]
XZCS0
XD[31:0], XD[15:0]
XZCS6
XWE0, XWE1,
XRD
XZCS7
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
Table 6-47. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
MIN
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
td(HL-HAL)
(1)
(2)
(3)
(1) (2) (3)
MAX
UNIT
Delay time, XHOLD low to Hi-Z on all address, data, and control
4tc(XTIM) + 30 ns
ns
Delay time, XHOLD low to XHOLDA low
5tc(XTIM)+ 30 ns
ns
Delay time, XHOLD high to XHOLDA high
3tc(XTIM)+ 30 ns
ns
Delay time, XHOLD high to bus valid
4tc(XTIM)+ 30 ns
ns
4tc(XTIM + 2tc(XCO) + 30 ns
ns
Delay time, XHOLD low to XHOLDA low
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
Not production tested.
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XCLKOUT
(/1 Mode)
td(HL-Hiz)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HAL)
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td(HH-BV)
XR/W
High-Impedance
XZCS0, XZCS6, XZCS7
XA[19:0]
Valid
XD[31:0], XD[15:0]
Valid
(A)
A.
B.
Valid
High-Impedance
(B)
All pending XINTF accesses are completed.
Normal XINTF operation resumes.
Figure 6-30. External Interface Hold Waveform
Table 6-48. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) (1)
MIN
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
(1)
(2)
(3)
(4)
146
(2) (3) (4)
MAX
UNIT
Delay time, XHOLD low to Hi-Z on all address, data, and
control
4tc(XTIM) + tc(XCO) + 30 ns
ns
Delay time, XHOLD low to XHOLDA low
4tc(XTIM + 2tc(XCO) + 30 ns
ns
Delay time, XHOLD high to XHOLDA high
4tc(XTIM) + 30 ns
ns
Delay time, XHOLD high to bus valid
6tc(XTIM) + 30 ns
ns
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
Not production tested.
Electrical Specifications
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XCLKOUT
(1/2 XTIMCLK)
td(HL-HAL)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HiZ)
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td(HH-BV)
XR/W,
XZCS0,
XZCS6,
XZCS7
XA[19:0]
High-Impedance
High-Impedance
Valid
XD[0:31]XD[15:0]
Valid
High-Impedance
(A)
A.
B.
Valid
(B)
All pending XINTF accesses are completed.
Normal XINTF operation resumes.
Figure 6-31. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
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6.15 On-Chip Analog-to-Digital Converter
Table 6-49. ADC Electrical Characteristics (over recommended operating conditions) (1)
PARAMETER
MIN
TYP
(2)
MAX
UNIT
25
MHz
DC SPECIFICATIONS (3)
Resolution
12
ADC clock
0.001
Bits
ACCURACY
±1.5
LSB
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INL (Integral nonlinearity)
1-12.5 MHz ADC clock (6.25 MSPS)
LSB
12.5-25 MHz ADC clock
(12.5 MSPS)
±2
DNL (Differential nonlinearity) (4)
±1
LSB
±15
LSB
±30
LSB
±30
LSB
Channel-to-channel offset variation
±4
LSB
Channel-to-channel gain variation
±4
LSB
Offset error
(5) (3)
Overall gain error with internal reference
(6) (3)
(3)
Overall gain error with external reference
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO)
ADCLO
(7)
0
–5
Input capacitance
0
V
5
mV
±5
μA
10
Input leakage current
INTERNAL VOLTAGE REFERENCE
3
pF
(6)
VADCREFP - ADCREFP output voltage at the pin based on
internal reference
1.275
V
VADCREFM - ADCREFM output voltage at the pin based on
internal reference
0.525
V
Voltage difference, ADCREFP - ADCREFM
0.75
Temperature coefficient
EXTERNAL VOLTAGE REFERENCE (6)
50
V
PPM/°C
(8)
VADCREFIN - External reference voltage input on ADCREFIN
pin 0.2% or better accurate reference recommended
ADCREFSEL[15:14] = 11b
1.024
V
ADCREFSEL[15:14] = 10b
1.500
V
ADCREFSEL[15:14] = 01b
2.048
V
67.5
dB
AC SPECIFICATIONS (9)
SINAD (100 kHz) Signal-to-noise ratio + distortion
SNR (100 kHz) Signal-to-noise ratio
THD (100 kHz) Total harmonic distortion
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
148
TC = -55°C to 120°C
TC = 210°C
65
TC = -55°C to 120°C
68
TC = 210°C
65
TC = -55°C to 120°C
–79
TC = 210°C
–79
dB
dB
Tested at 25 MHz ADCCLK.
All voltages listed in this table are with respect to VSSA2.
ADC parameters for gain error and offset error are only specified if the ADC calibration routine is executed from the Boot ROM. See
Section 4.7.3 for more information.
TI specifies that the ADC will have no missing codes.
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal reference
is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external reference option will
depend on the temperature profile of the source used.
Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference.
Not production tested.
Electrical Specifications
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Table 6-49. ADC Electrical Characteristics (over recommended operating conditions)(1) (2) (continued)
PARAMETER
MIN
TYP
MAX
UNIT
ENOB (100 kHz) Effective number of bits
TC = -55°C to 120°C
10.9
Bits
TC = 210°C
10
SFDR (100 kHz) Spurious free dynamic range
TC = -55°C to 120°C
83
TC = 210°C
83
ADC Power Up Delay
ADC Ready for Conversions
dB
6.15.1 ADC Power-Up Control Bit Timing
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PWDNBG
PWDNREF
td(BGR)
PWDNADC
td(PWD)
Request for
ADC
Conversion
Figure 6-32. ADC Power-Up Control Bit Timing
Table 6-50. ADC Power-Up Delays (1)
PARAMETER (2)
td(BGR)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
td(PWD)
Delay time for power-down control to be stable. Bit delay time for band-gap
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.
(1)
(2)
MIN
20
TYP
MAX
UNIT
5
ms
μs
50
1
Not production tested.
Timings maintain compatibility to the 281x ADC module. The 2833x/2823x ADC also supports driving all 3 bits at the same time and
waiting td(BGR) ms before first conversion.
Table 6-51. Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) (1)
ADC OPERATING MODE
CONDITIONS
VDDA3.3
UNIT
BG and REF enabled
PWD disabled
30
2
mA
•
•
•
ADC clock enabled
BG and REF enabled
PWD enabled
9
0.5
mA
•
•
•
ADC clock enabled
BG and REF disabled
PWD enabled
5
20
μA
•
•
Mode B:
Mode C:
(2)
(3)
(2) (3)
VDDA18
Mode A (Operational Mode):
(1)
ms
Test Conditions:
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO.
Not production tested.
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Table 6-51. Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)(1) (2)(3)
(continued)
ADC OPERATING MODE
Mode D:
CONDITIONS
•
•
•
ADC clock disabled
BG and REF disabled
PWD enabled
ADCIN0
Ron
1 kΩ
VDDA3.3
UNIT
5
15
μA
Switch
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Rs
VDDA18
Source
Signal
Cp
10 pF
ac
Ch
1.64 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron):
Sampling Capacitor (Ch):
Parasitic Capacitance (Cp):
Source Resistance (Rs):
1 kΩ
1.64 pF
10 pF
50 Ω
Figure 6-33. ADC Analog Input Impedance Model
6.15.2 Definitions
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at
a time. These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with
low power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:
• Sequential sampling mode (SMODE = 0)
• Simultaneous sampling mode (SMODE = 1)
150
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6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an
external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
every Sample/Hold pulse. The conversion time and latency of the Result register update are explained
below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
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Sample n+1
Analog Input on
Channel Ax or Bx
Sample n
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschx_n+1
tdschx_n
ADC Event Trigger from
ePWM or Other Sources
tSH
Figure 6-34. Sequential Sampling Mode (Single-Channel) Timing
Table 6-52. Sequential Sampling Mode Timing
SAMPLE n
td(SH)
tSH
td(schx_n)
td(schx_n+1)
Delay time from event trigger to
sampling
2.5tc(ADCCLK)
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
Delay time for first result to appear
in Result register
4tc(ADCCLK)
Delay time for successive results to
appear in Result register
SAMPLE n + 1
AT 25 MHz
ADC CLOCK,
tc(ADCCLK) = 40 ns
40 ns with Acqps = 0
REMARKS
Acqps value = 0-15
ADCTRL1[8:11]
160 ns
(2 + Acqps) *
tc(ADCCLK)
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6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or
from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold
pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC
clocks wide (maximum).
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NOTE
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
Sample n
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bx
Sample n+2
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschA0_n+1
tSH
ADC Event Trigger from
ePWM or Other Sources
tdschA0_n
tdschB0_n+1
tdschB0_n
Figure 6-35. Simultaneous Sampling Mode Timing
Table 6-53. Simultaneous Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25 MHz
ADC CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event trigger to
sampling
2.5tc(ADCCLK)
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
td(schA0_n)
Delay time for first result to
appear in Result register
4tc(ADCCLK)
160 ns
td(schB0_n )
Delay time for first result to
appear in Result register
5tc(ADCCLK)
200 ns
td(schA0_n+1)
Delay time for successive results
to appear in Result register
(3 + Acqps) * tc(ADCCLK)
120 ns
td(schB0_n+1 )
Delay time for successive results
to appear in Result register
(3 + Acqps) * tc(ADCCLK)
120 ns
152
40 ns with Acqps = 0
Electrical Specifications
REMARKS
Acqps value = 0-15
ADCTRL1[8:11]
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6.15.5 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is
defined as level one-half LSB beyond the last code transition. The deviation is measured from the center
of each particular code to the true straight line between these two points.
Differential Nonlinearity
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An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(SINAD * 1.76)
N+
6.02
it is possible to get a measure of performance expressed as N, the effective number
of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be
calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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6.16 Multichannel Buffered Serial Port (McBSP) Timing
6.16.1 McBSP Transmit and Receive Timing
Table 6-54. McBSP Timing Requirements (1)
(2) (3)
NO.
MIN
McBSP module clock (CLKG, CLKX, CLKR) range
M11
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
M12
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P–7
M13
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
M14
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
M15
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int
18
CLKR ext
2
M16
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
0
CLKR ext
6
CLKR int
18
CLKR ext
2
0
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
M18
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
CLKR ext
6
M19
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
18
CLKX ext
2
CLKX int
0
CLKX ext
6
M20
(1)
(2)
(3)
(4)
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
NO.
25 (4)
MHz
kHz
ns
1
ms
ns
ns
7
ns
7
ns
ns
ns
ns
ns
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKSRG
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = (1 ) CLKGDV) CLKSRG can be LSPCLK, CLKX,
CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
Not production tested.
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (25 MHz).
Table 6-55. McBSP Switching Characteristics (1)
M1
UNIT
40
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McBSP module cycle time (CLKG, CLKX, CLKR)
range
M17
MAX
1
PARAMETER
tc(CKRX)
Cycle time, CLKR/X
(2) (3)
MIN
CLKR/X int
2P
(4)
MAX
UNIT
ns
ns
M2
tw(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D-5
M3
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C-5 (4)
C+5 (4)
ns
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
0
4
ns
CLKR ext
3
27
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
0
4
CLKX ext
3
27
M6
(1)
(2)
(3)
(4)
154
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
D+5
(4)
CLKX int
8
CLKX ext
14
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
2P = 1/CLKG in ns.
Not production tested.
C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
Electrical Specifications
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Table 6-55. McBSP Switching Characteristics(1) (2)(3) (continued)
NO.
M7
M9
M10
ten(CKXH-DX)
MIN
Delay time, CLKX high to DX valid.
td(FXH-DXV)
ten(FXH-DX)
MAX
CLKX int
9
This applies to all bits except the first bit transmitted.
CLKX ext
28
Delay time, CLKX high to DX valid
CLKX int
8
CLKX ext
14
DXENA = 0
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
DXENA = 1
CLKX int
P+8
CLKX ext
P + 14
Enable time, CLKX high to DX driven
DXENA = 0
CLKX int
CLKX ext
6
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
DXENA = 1
CLKX int
P
CLKX ext
P+6
Delay time, FSX high to DX valid
DXENA = 0
0
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M8
PARAMETER
td(CKXH-DXV)
FSX int
8
14
P+8
DXENA = 1
FSX int
Enable time, FSX high to DX driven
DXENA = 0
FSX int
0
FSX ext
6
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode
FSX ext
DXENA = 1
FSX int
P
FSX ext
P+6
ns
ns
FSX ext
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode.
UNIT
ns
P + 14
ns
M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n−1)
(n−2)
(n−3)
M17
DR
(RDATDLY=01b)
(n−4)
M18
Bit (n−1)
(n−2)
M17
DR
(RDATDLY=10b)
Bit (n−1)
(n−3)
M18
(n−2)
Figure 6-36. McBSP Receive Timing
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M1, M11
M2, M12
M13
M3, M12
CLKX
M5
M5
FSX (int)
M19
M20
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FSX (ext)
M9
M7
M10
DX
(XDATDLY=00b)
Bit 0
Bit (n−1)
(n−2)
(n−3)
M7
M8
DX
(XDATDLY=01b)
Bit 0
Bit (n−1)
(n−2)
M7
M6
M8
DX
(XDATDLY=10b)
Bit 0
Bit (n−1)
Figure 6-37. McBSP Transmit Timing
6.16.2 McBSP as SPI Master or Slave Timing
Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
NO.
M30
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
M31
th(CKXL-DRV)
Hold time, DR valid after CLKX low
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
M33
tc(CKX)
Cycle time, CLKX
(1)
(2)
MASTER
SLAVE
MIN
MIN
MAX
30
1
2P (2)
UNIT
MAX
8P – 10
ns
8P –10
ns
8P + 10
ns
16P
ns
Not production tested.
2P = 1/CLKG
Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) (1)
NO.
PARAMETER
MASTER
SLAVE
MIN
MIN
MAX
UNIT
MAX
M24
th(CKXL-FXL)
Hold time, FSX low after CLKX low
2P (2)
M25
td(FXL-CKXH)
Delay time, FSX low to CLKX high
P
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
6
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1)
(2)
156
ns
ns
Not production tested.
2P = 1/CLKG
Electrical Specifications
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For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by
setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will
be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
M32
LSB
M33
MSB
CLKX
M25
M24
FSX
M28
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DX
M29
Bit 0
Bit(n-1)
M30
DR
Bit 0
(n-2)
(n-3)
(n-4)
M31
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-38. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
NO.
MASTER
MIN
M39
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
M40
th(CKXH-DRV)
Hold time, DR valid after CLKX high
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
M42
tc(CKX)
Cycle time, CLKX
(1)
(2)
SLAVE
MAX
30
1
2P (2)
UNIT
MIN MAX
8P – 10
ns
8P – 10
ns
16P + 10
ns
16P
ns
Not production tested.
2P = 1/CLKG
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) (1)
NO.
PARAMETER
MASTER
MIN
M34
th(CKXL-FXL)
Hold time, FSX low after CLKX low
P
(2)
SLAVE
MAX
MIN
UNIT
MAX
ns
M35
td(FXL-CKXH)
Delay time, FSX low to CLKX high
2P
M37
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX low
P+6
7P + 6
ns
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1)
(2)
ns
Not production tested.
2P = 1/CLKG
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For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 75 MHz, CLKX maximum
frequency is LSPCLK/16; that is, 4.6875 MHz and P =13.3 ns.
LSB
M42
MSB
M41
CLKX
M35
M34
FSX
M37
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DX
M38
Bit 0
Bit(n-1)
M39
DR
Bit 0
(n-2)
(n-3)
(n-4)
M40
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-39. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Table 6-60. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
NO.
MASTER
MIN
M49
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
M50
th(CKXH-DRV)
Hold time, DR valid after CLKX high
M51
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M52
(1)
(2)
tc(CKX)
Cycle time, CLKX
SLAVE
MAX
MIN
MAX
UNIT
30
8P –10
ns
1
8P –10
ns
8P + 10
ns
16P
ns
2P
(2)
Not production tested.
2P = 1/CLKG
Table 6-61. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) (1)
NO.
PARAMETER
MIN
MIN
MAX
MAX
UNIT
ns
Delay time, FSX low to CLKX low
P
ns
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
6
6P + 6
ns
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
th(CKXH-FXL)
Hold time, FSX low after CLKX high
M44
td(FXL-CKXL)
M47
M48
158
SLAVE
2P (2)
M43
(1)
(2)
MASTER
Not production tested.
2P = 1/CLKG
Electrical Specifications
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For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency
will be LSPCLK/16; that is, 4.6875 MHz and P = 13.3 ns.
M51
LSB
M52
MSB
CLKX
M43
M44
FSX
M48
M47
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DX
Bit 0
Bit(n-1)
M49
DR
Bit 0
(n-2)
(n-3)
(n-4)
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Table 6-62. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
NO.
MASTER
MIN
M58
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
M59
th(CKXL-DRV)
Hold time, DR valid after CLKX low
M60
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M61
(1)
(2)
tc(CKX)
Cycle time, CLKX
SLAVE
MAX
MIN
UNIT
MAX
30
8P – 10
ns
1
8P – 10
ns
16P + 10
ns
16P
ns
2P
(2)
Not production tested.
2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency
is LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-63. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1) (2)
NO.
PARAMETER
MASTER (3)
MIN
MAX
SLAVE
MIN
UNIT
MAX
M53
th(CKXH-FXL)
Hold time, FSX low after CLKX high
M54
td(FXL-CKXL)
Delay time, FSX low to CLKX low
2P (1)
M56
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
P+6
7P + 6
ns
M57
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1)
(2)
(3)
P
ns
ns
2P = 1/CLKG
Not production tested.
C = CLKX low pulse width = P
D = CLKX high pulse width = P
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M60
LSB
M61
MSB
CLKX
M53
M54
FSX
M56
DX
M55
M57
Bit 0
Bit(n-1)
(n-2)
M58
(n-4)
M59
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DR
(n-3)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
6.17 Flash Timing
Table 6-64. Flash Endurance (1) (2)
Nf
NOTP
(1)
(2)
Flash endurance for the array (write/erase cycles)
–40°C to 125°C (ambient)
OTP endurance for the array (write cycles)
–40°C to 125°C (ambient)
MIN
TYP
100
1000
MAX
UNIT
cycles
1
write
Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Not production tested.
Table 6-65. Flash Parameters at 150-MHz SYSCLKOUT (1)
TEST
CONDITIONS
PARAMETER
Program Time
Erase Time
MIN
IDDP
(2)
IDDIOP
(1)
(2)
(2)
(2)
MAX
UNIT
16-Bit Word
50
μs
32K Sector
1000
ms
16K Sector
500
ms
32K Sector
11
s
16K Sector
IDD3VFLP
TYP
11
s
Erase
75
mA
Program
35
mA
VDD current consumption during Erase/Program cycle
180
mA
VDDIO current consumption during Erase/Program cycle
20
mA
VDD3VFL current consumption during the Erase/Program
cycle
Not production tested.
Typical parameters as seen at room temperature including function call overhead, with all peripherals off.
Table 6-66. Flash/OTP Access Timing (1)
PARAMETER
ta(fp)
ta(fr)
ta(OTP)
(1)
160
MIN
MAX
UNIT
Paged Flash access time
37
ns
Random Flash access time
37
ns
OTP access time
60
ns
Not production tested.
Electrical Specifications
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Table 6-67. Minimum Required Flash/OTP Wait-States at Different Frequencies (1)
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
PAGE WAIT-STATE
RANDOM WAITSTATE (2)
OTP WAIT-STATE
150
6.67
5
5
8
120
8.33
4
4
7
100
10
3
3
5
75
13.33
2
2
4
50
20
1
1
2
30
33.33
1
1
1
15
4
(1)
(2)
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25
40
1
1
1
66.67
1
1
1
250
1
1
1
Not production tested.
Page and random wait-state must be ≥ 1.
Equations to compute the Flash page wait-state and random wait-state in Table 6-67 are as follows:
éæ t
ö ù
êç a (fp ) ÷ ú
÷ -1ú round up to the next highest integer), or 1 whichever is larger
Flash Page Wait State = êç
êç t
÷ ú
ç
÷
ëêè c (SCO ) ø ûú
éæ t
ö ù
êç a (fr ) ÷ ú
÷ -1ú round up to the next highest integer), or 1 whichever is larger
Flash Random Wait State = êç
êç t
÷ ú
ç
÷
êëè c (SCO ) ø úû
Equation to compute the OTP wait-state in Table 6-67 is as follows:
éæ t
ö ù
êç a (OTP ) ÷ ú
÷ -1ú round up to the next highest integer), or 1 whichever is larger
OTP Wait State = êç
êç t
÷ ú
ç
÷
ëêè c (SCO ) ø ûú
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7
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Thermal/Mechanical Data
Table 7-1 shows the thermal data. See Section 6.4.3 for more information on thermal design
considerations.
The mechanical package diagram(s) that follow the tables reflect the most current released mechanical
data available for the designated device(s).
Table 7-1. Thermal Model of 181-Pin GB
°C/W
θJC
1.13
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PARAMETER
162
Thermal/Mechanical Data
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SPRS682B – DECEMBER 2010 – REVISED MAY 2012
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June, 2011) to Revision B
•
Changed pin description for the XINTFXD pins
Page
............................................................................
30
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Thermal/Mechanical Data
163
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2012
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PACKAGING INFORMATION
Orderable Device
(1)
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
SM320F28335GBS
ACTIVE
CPGA
GB
181
21
TBD
Call TI
N / A for Pkg Type
SM320F28335KGDS1
ACTIVE
XCEPT
KGD
0
36
TBD
Call TI
N / A for Pkg Type
(3)
Samples
(Requires Login)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCPG014A – FEBRUARY 1996 – REVISED JANUARY 2002
GB (S-CPGA-P181)
CERAMIC PIN GRID ARRAY
1.590 (40,40)
SQ
1.560 (39,62)
1.400 (35,56) TYP
0.100 (2,54) TYP
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R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Bottom View
0.185 (4,70)
0.140 (3,55)
0.055 (1,40)
0.045 (1,14)
0.050 (1,27) DIA
4 Places
0.022 (0,55)
0.016 (0,41)
0.140 (3,56)
0.120 (3,05)
DIA TYP
4073426/C 11/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Index mark can appear on top or bottom, depending on package vendor.
Pins are located within 0.010 (0,25) diameter of true position relative to
each other at maximum material condition and within 0.030 (0,76) diameter
relative to the edge of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold-plated or solder-dipped.
G. Falls within MIL-STD-1835 CMGA7-PN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
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