CYPRESS CY7C148

CY7C148
CY7C149
Storage Temperature ...................................... −65°C to+150°C
Latch-Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied ................................................... −55°C to+125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 18 to Pin 9)....................................................−0.5V to+7.0V
DC Voltage Applied to Outputs
in High Z State ......................................................−0.5V to+7.0V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
−55°C to +125°C
5V ± 10%
Military
DC Input Voltage .................................................−3.0V to +7.0V
[1]
Note:
1. TA is the “instant on” case temperature.
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Electrical Characteristics Over the Operating Range[2]
7C148−25
7C149−25
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VO < VCC Output Disabled
ICC
VCC Operating
Supply Current
Max. VCC, CS < VIL,
Output Open
ISB
Automatic CS
Power-Down Current
Max. VCC, CS > VIH
7C148
Only
Com’l
IPO
Peak Power-On
Current[3]
Max. VCC, CS > VIH
7C148
Only
Com’l
IOS
Output Short
Circuit Current[4]
GND < VO < VCC
7C148−35, 45
7C149−35, 45
Max.
2.4
Min.
0.4
Com’l
Unit
V
0.4
V
2.0
6.0
2.0
6.0
V
−3.0
0.8
−3.0
0.8
V
−10
10
−10
10
µA
−50
50
−50
50
µA
80
mA
90
Mil
110
15
10
Mil
mA
10
15
10
±275
±275
Mil
Com’l
Max.
2.4
mA
10
mA
±350
Mil
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
8
pF
8
pF
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up. Otherwise current will exceed values given (CY7C148
only).
4. For test purposes, not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
2
CY7C148
CY7C149
AC Test Loads and Waveforms
R1481Ω
5V
R1481Ω
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
255Ω
30 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
3.0V
(b)
90%
90%
10%
10%
GND
< 10 ns
< 10 ns
C148–5
C148–4
THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Characteristics Over the Operating Range[2]
7C148−25
7C149−25
Parameter
Description
Min.
Max.
7C148−35
7C149−35
Min.
Max.
7C148−45
7C149−45
Min.
Max.
Unit
READ CYCLE
tRC
Address Valid to Address Do Not Care Time
(Read Cycle Time)
25
tAA
Address Valid to Data Out Valid Delay
(Address Access Time)
tACS1
tACS2
Chip Select LOW to Data Out Valid (7C148 only)
tACS
Chip Select LOW to Data Out Valid (7C149 only)
tLZ[8]
Chip Select LOW to Data Out On
tHZ[8]
Chip Select HIGH to Data Out Off
tOH
Address Unknown to Data Out Unknown Time
tPD
Chip Select HIGH to Power-Down Delay
7C148
tPU
Chip Select LOW to Power-Up Delay
7C148
35
8
7C149
5
0
ns
25
35
45
ns
25[6]
35
45
ns
30[7]
35
45
ns
20
ns
15
7C148
45
15
10
10
5
15
0
0
5
20
0
20
ns
0
20
5
30
ns
ns
30
ns
0
0
0
ns
WRITE CYCLE
tWC
Address Valid to Address Do Not Care
(Write Cycle Time)
25
35
45
ns
tWP[9]
Write Enable LOW to Write Enable HIGH
20
30
35
ns
tWR
Address Hold from Write End
5
5
5
ns
tWZ
[8]
Write Enable to Output in High Z
0
tDW
Data in Valid to Write Enable HIGH
12
20
20
ns
tDH
Data Hold Time
0
0
0
ns
tAS
Address Valid to Write Enable LOW
0
0
0
ns
tCW
[9]
8
0
8
0
8
ns
Chip Select LOW to Write Enable HIGH
20
30
40
ns
tOW[8]
Write Enable HIGH to Output in Low Z
0
0
0
ns
tAW
Address Valid to End of Write
20
30
35
ns
Notes:
6. Chip deselected greater than 25 ns prior to selection.
7. Chip deselected less than 25 ns prior to selection.
8. At any given temperature and voltage condition, tHZ is less than tLZ for all devices. Transition is measured ±500 mV from steady-state voltage with specified
loading in part (b) of AC Test Loads.
9. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
CY7C148
CY7C149
Switching Waveforms
Read Cycle No. 1 [10,11]
tRC
ADDRESS
tOH
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
C148–6
Read Cycle No. 2
[10,12]
tRC
CS
tACS
tLZ
DATA OUT
tHZ
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tPU
tPD
ICC
VCC
SUPPLY
CURRENT
50%
50%
ISB
C148–7
Write Cycle No. 1 (WE Controlled)
tWC
ADDRESS
tCW
CS
tAS
tAW
tWA
tWP
WE
tDW
DATA IN
DATA–IN VALID
tWZ
DATA OUT
tDH
tOW
HIGH IMPEDANCE
DATA UNDEFINED
C148–8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CS = VIL.
12. Address valid prior to or coincident with CS transition LOW.
4
CY7C148
CY7C149
Switching Waveforms (continued)
Write Cycle No. 2 (CSControlled) [13]
tWC
ADDRESS
tCW
CS
tWR
tAW
tWP
WE
tDH
tDW
DATA IN
DATAIN VALID
tWZ
DATA OUT
HIGH IMPEDANCE
DATA UNDEFINED
C148–9
Notes:
13. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
NORMALIZED SUPPLY CURRENT
vs.AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs.SUPPLY VOLTAGE
1.2
1.2
NORMALIZED CC
I, I SB
ICC
1.0
0.8
VIN =5.0V
TA =25°C
0.6
0.4
ICC
1.0
0.8
0.6
0.4
VCC =5.0V
VIN =5.0V
0.2
0.2
0.0
4.0
ISB
ISB
4.5
5.0
5.5
0.0
−55
6.0
NORMALIZED ACCESS TIME
vs.AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs.SUPPLY VOLTAGE
1.4
1.6
1.3
1.4
NORMALIZED t AA
NORMALIZED t AA
125
1.2
1.1
TA =25°C
1.0
1.2
1.0
VCC =5.0V
0.8
0.9
4.5
5.0
5.5
SUPPLY VOLTAGE(V)
OUTPUT SOURCE CURRENT
vs.OUTPUT VOLTAGE
120
100
80
VCC =5.0V
TA =25°C
60
40
20
0
0.0
AMBIENT TEMPERATURE(°C)
SUPPLY VOLTAGE(V)
0.8
4.0
25
6.0
0.6
−55
25
125
AMBIENT TEMPERATURE(°C)
5
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE(V)
OUTPUT SINK CURRENT (mA)
NORMALIZED CC
I ,I
SB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
OUTPUT SINK CURRENT
vs.OUTPUT VOLTAGE
140
120
100
80
60
VCC =5.0V
TA =25°C
40
20
0
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE(V)
4.0
CY7C148
CY7C149
Typical DC and AC Characteristics
TYPICAL POWER–ON CURRENT
vs.SUPPLY VOLTAGE(7C148)
TYPICAL ACCESS TIME CHANGE
vs.OUTPUT LOADING
TA =25°C
1K Ω CSPULL–UP
RESISTORTOV CC
2.0
1.5
ISB
1.0
0.0
0.0
1.4
25.0
1.3
20.0
15.0
10.0
VCC =4.5V
TA =25°C
5.0
0.5
1.0
2.0
3.0
4.0
0.0
5.0
NORMALIZED I CC vs.ACCESS TIME
30.0
SUPPLY VOLTAGE(V)
0
200
400
600
800 1000
NORMALIZED I CC
2.5
DELTA tAA (ns)
NORMALIZED I
PO
3.0
1.2
1.1
1.0
0.9
0.8
10
CAPACITANCE(pF)
20
30
Ordering Information
Speed
(ns)
Ordering Code
25
CY7C148−25PC
35
45
Speed
(ns)
Package
Name
Package Type
Operating
Range
P3
18-Lead (300-Mil) Molded DIP
Commercial
CY7C148−35PC
P3
18-Lead (300-Mil) Molded DIP
Commercial
CY7C148−35DMB
D4
18-Lead (300-Mil) CerDIP
Military
CY7C148−45PC
P3
18-Lead (300-Mil) Molded DIP
Commercial
CY7C148−45DMB
D4
18-Lead (300-Mil) CerDIP
Military
Ordering Code
Package
Name
Package Type
Operating
Range
25
CY7C149−25PC
P3
18-Lead (300-Mil) Molded DIP
Commercial
35
CY7C149−35PC
P3
18-Lead (300-Mil) Molded DIP
Commercial
CY7C149−35DMB
D4
18-Lead (300-Mil) CerDIP
Military
CY7C149−35LMB
L50
18-Pin Rectangular Leadless Chip Carrier
CY7C149−45PC
P3
18-Lead (300-Mil) Molded DIP
Commercial
CY7C149−45DMB
D4
18-Lead (300-Mil) CerDIP
Military
CY7C149−45LMB
L50
18-Pin Rectangular Leadless Chip Carrier
45
6
40
50
CYCLE FREQUENCY(MHz)
60
CY7C148
CY7C149
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameters
DC Characteristics
Subgroups
READ CYCLE
Subgroups
tRC
7, 8, 9, 10, 11
IOH
1, 2, 3
tAA
7, 8, 9, 10, 11
IOL
1, 2, 3
7, 8, 9, 10, 11
VIH
1, 2, 3
VIL Max.
1, 2, 3
tACS1[14]
tACS2[14]
tACS[15]
IIX
1, 2, 3
1, 2, 3
tOH
7, 8, 9, 10, 11
IOZ
ICC
1, 2, 3
ISB[14]
1, 2, 3
Parameters
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WRITE CYCLE
tWC
7, 8, 9, 10, 11
tWP
7, 8, 9, 10, 11
tWR
7, 8, 9, 10, 11
tDW
7, 8, 9, 10, 11
tDH
7, 8, 9, 10, 11
tAS
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
Notes:
14. 7C148 only.
15. 7C149 only.
Document #: 38−00031−D
7
CY7C148
CY7C149
18–Lead(300–Mil) CerDIP D4
MIL−STD −1835 D− 8Config.A
18–P in Rectangular Leadless Chip Carrier L50
MIL−STD −1835 C −10A
18–Lead(300–Mil) Molded DIP P3
© Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.