ONSEMI MC100EP210SMNR4G

MC100EP210S
2.5V 1:5 Dual Differential
LVDS Compatible Clock
Driver
Description
The MC100EP210S is a low skew 1−to−5 dual differential driver,
designed with LVDS clock distribution in mind. The LVDS or
LVPECL input signals are differential and the signal is fanned out to
five identical differential LVDS outputs.
The EP210S specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
Two internal 50 W resistors are provided across the inputs. For
LVDS inputs, VTA and VTB pins should be unconnected. For
LVPECL inputs, VTA and VTB pins should be connected to the VTT
(VCC − 2.0 V) supply.
Designers can take advantage of the EP210S performance to
distribute low skew LVDS clocks across the backplane or the board.
http://onsemi.com
MARKING
DIAGRAM*
MC100
EP210S
AWLYYWWG
LQFP−32
FA SUFFIX
CASE 873A
1
Features
•
•
•
•
•
•
•
•
•
20 ps Typical Output−to−Output Skew
85 ps Typical Device−to−Device Skew
550 ps Typical Propagation Delay
The 100 Series Contains Temperature Compensation
Maximum Frequency > 1 GHz Typical
Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V
Internal 50 W Input Termination Resistors
LVDS Input/Output Compatible
These are Pb−Free Devices
1
32
QFN32
MN SUFFIX
CASE 488AM
xxx
A
WL, L
YY, Y
WW, W
G
MCxxx
EP210S
ALYWG
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 10
1
Publication Order Number:
MC100EP210S/D
MC100EP210S
Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1
VCC Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 VCC
24
23
22
21
20
19
18
32
17
31
30
29
28
27
26
25
VCC
25
16
VCC
VEE
1
24 Qa3
Qa2
26
15
Qb2
VTA
2
23 Qa3
Qa2
27
14
Qb2
CLKa
3
22 Qa4
Qa1
28
13
Qb3
CLKa
4
Qa1
29
12
Qb3
VTB
5
20 Qb0
Qa0
30
11
Qb4
CLKb
6
19 Qb0
Qa0
31
10
Qb4
CLKb
7
18 Qb1
VCC
32
9
VCC
VEE
8
17 Qb1
MC100EP210S
1
2
3
4
5
6
7
8
21 Qa4
MC100EP210S
9
10
11
12
13
14
15
16
CLKb
VTB
CLKb
CLKa
VEE VTA
CLKa
VCC Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 VCC
VEE
Figure 1. 32−Lead QFN Pinout (Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 32−Lead LQFP Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLKn, CLKn
LVDS, LVPECL CLK Inputs*
Qn0:4, Qn0:4
LVDS Outputs
VTA
50 W Termination Resistors
VTB
50 W Termination Resistors
VCC
Positive Supply
VEE
Ground
EP for QFN−32,
only
The Exposed Pad (EP) on the QFN−32 package bottom is
thermally connected to the die for improved heat transfer out
of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to VEE.
*Under open or floating conditions with input pins converging to a common termination
bias voltage the device is susceptible to auto oscillation.
VTA
50 W
CLKa
CLKa
VTB
Qa0
50 W
Qa0
Qa1
Qa1
Qa2
50 W
CLKb
CLKb
Qb0
50 W
Qb0
Qb1
Qb1
Qb2
Qa2
Qb2
Qa3
Qb3
Qa3
Qb3
Qa4
Qb4
Qa4
Qb4
Figure 2. Logic Diagram
http://onsemi.com
2
MC100EP210S
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
LQFP−32
QFN−32
Flammability Rating
Pb Pkg
Pb−Free Pkg
Level 2
Level 2
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
461 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Rating
Unit
VCC
Symbol
Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
Power Supply (GND)
VCC = 2.5 V
−6
V
VI
LVDS, LVPECL Input Voltage
VEE = 0 V
6
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
32 LQFP
32 LQFP
80
55
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
32 LQFP
12 to 17
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P
QFN−32
12
°C/W
Tsol
Wave Solder
265
265
°C
Pb
Pb−Free
Condition 2
VI ≤ VCC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
http://onsemi.com
3
MC100EP210S
Table 4. DC CHARACTERISTICS VCC = 2.5 V, VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
150
200
Min
85°C
Typ
Max
150
200
Min
Typ
Max
Unit
150
200
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 3)
1250
1400
1550
1250
1400
1550
1250
1400
1550
mV
VOL
Output LOW Voltage (Note 3)
800
950
1100
800
950
1100
800
950
1100
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
1.2
2.5
1.2
2.5
1.2
2.5
V
RT
Internal Termination Resistor
43
57
43
57
43
57
W
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
150
mA
50
150
CLK
CLK
−150
−150
150
150
150
−150
−150
150
150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC.
3. All loading with 100 W across LVDS differential outputs.
4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 5. AC CHARACTERISTICS VCC = 2.375 to 2.625 V, VEE = 0 V (Note 5)
−40°C
Symbol
Characteristic
fmaxLVDS/
LVPECL
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH
tPHL
Propagation Delay
tskew
Min
Typ
25°C
Max
Min
>1
425
Typ
85°C
Max
Min
>1
525
625
Within−Device Skew (Note 6)
Device−to−Device Skew (Note 7)
Duty Cycle Skew (Note 8)
20
85
80
tJITTER
RMS Random Clock Jitter
VPP
Minimum Input Swing
tr/tf
Output Rise/Fall Time (20%−80%)
450
Typ
Max
>1
550
650
25
160
100
20
85
80
0.2
<1
150
800
1200
50
130
200
475
Unit
GHz
575
675
ps
25
160
100
20
85
80
35
160
100
ps
0.2
<1
0.2
<1
ps
150
800
1200
150
800
1200
mV
75
150
225
80
160
230
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5.
6.
7.
8.
Measured with 400 mV source, 50% duty cycle clock source. All loading with 100 W across differential outputs.
Skew is measured between outputs under identical transitions of similar paths through a device.
Device−to−Device skew for identical transitions at identical VCC levels.
Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
http://onsemi.com
4
MC100EP210S
450
Simulated
400
VOUTpp (mV)
350
300
250
200
150
100
50
0
0
200
400
600
800
1000
1200
1400
FREQUENCY (MHz)
Figure 2. Fmax
LVDS
Driver
Device
Q
Zo = 50 W
HI Z Probe
D
100 W
Q
Zo = 50 W
Oscilloscope
HI Z Probe
D
Figure 3. Typical Termination for Output Driver and Device Evaluation
http://onsemi.com
5
MC100EP210S
Figure 4. Tape and Reel Pin 1 Quadrant Orientation
ORDERING INFORMATION
Package
Shipping†
MC100EP210SFAG
LQFP−32
(Pb−Free)
250 Units / Tray
MC100EP210SFAR2G
LQFP−32
(Pb−Free)
2000 / Tape & Reel
(Pin 1 Orientation in Quadrant B, Figure 4)
MC100EP210SFATWG
LQFP−32
(Pb−Free)
2000 / Tape & Reel
(Pin 1 Orientation in Quadrant A, Figure 4)
MC100EP210SMNG
QFN−32
(Pb−Free)
72 Units / Tray
MC100EP210SMNR4G
QFN−32
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
6
MC100EP210S
4X
32
25
0.20 (0.008) AB T-U Z
BASE
METAL
1
−U−
−T−
B
B1
ÉÉ
ÉÉ
ÉÉ
P
F
DETAIL Y
17
8
N
AE
V
V1
AE
J
DETAIL Y
9
−Z−
9
0.20 (0.008) AC T-U Z
S1
8X
DETAIL AD
G
SECTION AE−AE
M_
R
C E
−AB−
H
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.450
0.750
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.018
0.030
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
http://onsemi.com
7
W
K
X
DETAIL AD
Q_
GAUGE PLANE
0.10 (0.004) AC
0.250 (0.010)
−AC−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
D
4X
S
SEATING
PLANE
M
A
0.20 (0.008)
A1
−T−, −U−, −Z−
32 LEAD LQFP
CASE 873A−02
ISSUE C
AC T-U Z
PACKAGE DIMENSIONS
MC100EP210S
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
PIN ONE
LOCATION
2X
ÉÉ
ÉÉ
0.15 C
2X
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
C
L
32 X
9
D2
SEATING
PLANE
A1
SIDE VIEW
SOLDERING FOOTPRINT*
EXPOSED PAD
16
5.30
K
32 X
17
3.20
8
32 X
E2
1
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
−−−
−−−
0.300 0.400 0.500
0.63
24
32
3.20
25
b
0.10 C A B
32 X
5.30
e
0.05 C
32 X
0.28
BOTTOM VIEW
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
8
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC100EP2105/D