IRFR9014, IRFU9014, SiHFR9014, SiHFU9014 Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Dynamic dV/dt Rating - 60 RDS(on) (Ω) VGS = - 10 V Qg (Max.) (nC) 12 Qgs (nC) 3.8 Qgd (nC) 5.1 Configuration COMPLIANT • Straight Lead (IRFU9014/SiHFU9014) • Available in Tape and Reel • P-Channel Single IPAK (TO-251) RoHS* • Surface Mount (IRFR9014/SiHFR9014) • Fast Switching S DPAK (TO-252) Available • Repetitive Avalanche Rated 0.50 • Lead (Pb)-free Available DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU/SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. G D P-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) IRFR9014PbF SiHFR9014-E3 IRFR9014 SiHFR9014 DPAK (TO-252) IRFR9014TRLPbFa SiHFR9014TL-E3a IRFR9014TRLa SiHFR9014TLa DPAK (TO-252) IRFR9014TRPbFa SiHFR9014T-E3a IRFR9014TRa SiHFR9014Ta IPAK (TO-251) IRFU9014PbF SiHFU9014-E3 IRFU9014 SiHFU9014 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Linear Derating Factor (PCB Mount)e Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Maximum Power Dissipation (PCB Mount)e Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) VGS at 5.0 V TC = 25 °C TC = 100 °C SYMBOL LIMIT VDS VGS - 60 ± 20 - 5.1 - 3.2 - 20 0.20 0.020 140 - 5.1 2.5 25 2.5 - 4.5 - 55 to + 150 ID IDM EAS IAR EAR TC = 25 °C TA = 25 °C PD dV/dt TJ, Tstg for 10 s 260d UNIT V A W/°C mJ A mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = - 25 V, starting TJ = 25 °C, L = 6.3 mH, RG = 25 Ω, IAS = - 5.1 A (see fig. 12). c. ISD ≤ - 6.7 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). www.kersemi.com 1 IRFR9014, IRFU9014, SiHFR9014, SiHFU9014 THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 5.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VDS VGS = 0 V, ID = - 250 µA - 60 - - V ΔVDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.059 - V/°C VGS(th) VDS = VGS, ID = - 250 µA - 2.0 - - 4.0 V nA IGSS IDSS RDS(on) gfs VGS = ± 20 V - - ± 100 VDS = - 60 V, VGS = 0 V - - - 100 VDS = - 48 V, VGS = 0 V, TJ = 125 °C - - - 500 ID = - 3.1 Ab VGS = - 10 V VDS = - 25 V, ID = - 3.1 Ab µA - - 0.50 Ω 1.4 - - S - 270 - - 170 - - 31 - - - 12 Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg VGS = 0 V, VDS = - 25 V, f = 1.0 MHz, see fig. 5 Gate-Source Charge Qgs - - 3.8 Gate-Drain Charge Qgd - - 5.1 Turn-On Delay Time td(on) - 11 - tr - 63 - - 9.6 - - 31 - - 4.5 - - 7.5 - - - - 5.1 - - - 20 - - - 5.5 Rise Time Turn-Off Delay Time Fall Time td(off) VGS = - 10 V ID = - 6.7 A, VDS = - 48 V, see fig. 6 and 13b VDD = - 30 V, ID = - 6.7 A, RG = 24 Ω, RD = 4.0 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contactc pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode A G S TJ = 25 °C, IS = - 5.1 A, VGS = 0 Vb TJ = 25 °C, IF = - 6.7 A, dI/dt = 100 A/µsb V - 80 160 ns - 0.096 0.19 µC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.kersemi.com 2 D IRFR9014, IRFU9014, SiHFR9014, SiHFU9014 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.kersemi.com 3 IRFR9014, IRFU9014, SiHFR9014, SiHFU9014 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.kersemi.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area IRFR9014, IRFU9014, SiHFR9014, SiHFU9014 RD VDS VGS D.U.T. RG +VDD - 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit td(on) tr td(off) tf VGS 10 % 90 % VDS Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case www.kersemi.com 5 IRFR9014, IRFU9014, SiHFR9014, SiHFU9014 L Vary tp to obtain required IAS IAS VDS VDS D.U.T. RG + V DD VDD IAS tp - 10 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit VDS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG - 10 V 12 V 0.2 µF 0.3 µF QGS - QGD D.U.T. VG + VDS VGS - 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.kersemi.com 6 Fig. 13b - Gate Charge Test Circuit IRFR9014, IRFU9014, SiHFR9014, SiHFU9014 Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG + • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test + - VDD Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % * ISD VGS = - 5 V for logic level and - 3 V drive devices Fig. 14 - For P-Channel www.kersemi.com 7