IRFR310, IRFU310, SiHFR310, SiHFU310 Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Dynamic dV/dt Rating 400 RDS(on) (Ω) VGS = 10 V 3.6 • Repetitive Avalanche Rated Qg (Max.) (nC) 12 • Surface Mount (IRFR310/SiHFR310) Qgs (nC) 1.9 • Straight Lead (IRFU310/SiHFU310) Qgd (nC) 6.5 • Available in Tape and Reel Configuration Available RoHS* COMPLIANT • Fast Switching Single • Fully Avalanche Rated D DPAK (TO-252) • Lead (Pb)-free Available IPAK (TO-251) DESCRIPTION G S N-Channel MOSFET Third generation Power MOSFETs form Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU/SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) IRFR310PbF SiHFR310-E3 IRFR310 SiHFR310 DPAK (TO-252) IRFR310TRLPbFa SiHFR310TL-E3a IRFR310TRLa SiHFR310TLa DPAK (TO-252) IRFR310TRPbFa SiHFR310T-E3a IRFR310TRa SiHFR310Ta DPAK (TO-252) IRFR310TRRPbFa SiHFR310TR-E3a - IPAK (TO-251) IRFU310PbF SiHFU310-E3 IRFU310 SiHFU310 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current SYMBOL VDS VGS VGS at 10 V TC = 25 °C TC = 100 °C ID Pulsed Drain Currenta IDM Linear Derating Factor Linear Derating Factor (PCB Mount)e Single Pulse Avalanche Energyb EAS IAR Repetitive Avalanche Currenta Repetitive Avalanche Energya EAR Maximum Power Dissipation TC = 25 °C PD Maximum Power Dissipation (PCB Mount)e TA = 25 °C c dV/dt Peak Diode Recovery dV/dt Operating Junction and Storage Temperature Range TJ, Tstg Soldering Recommendations (Peak Temperature) for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 52 mH, RG = 25 Ω, IAS = 1.7 A (see fig. 12). c. ISD ≤ 1.7 A, dI/dt ≤ 40 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1” square PCB (FR-4 or G-10 material). LIMIT 400 ± 20 1.7 1.1 6.0 0.20 0.020 86 1.7 2.5 25 2.5 4.0 - 55 to + 150 260d UNIT V A W/°C mJ A mJ W V/ns °C www.kersemi.com 1 IRFR310, IRFU310, SiHFR310, SiHFU310 THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB Mounted, steady-state)a RthJA - 50 Maximum Junction-to-Ambient RthJA - 110 Maximum Junction-to-Case RthJC - 5.0 UNIT °C/W Note a. When mounted on 1" square PCB ( FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 µA 400 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.47 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 400 V, VGS = 0 V - - 25 VDS = 320 V, VGS = 0 V, TJ = 125 °C - - 250 Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs ID = 1.0 Ab VGS = 10 V VDS = 50 V, ID = 1.0 Ab µA - - 3.6 Ω 0.97 - - S - 170 - - 34 - - 6.3 - Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5c VGS = 10 V ID = 2.0 A, VDS = 320 V, see fig. 6 and 13b, c VDD = 200 V, ID = 2.0 A, RG = 24 Ω, RD = 95 Ω, see fig. 10b, c tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact D pF - - 12 - - 1.9 - - 6.5 - 7.9 - - 9.9 - - 21 - - 11 - - 4.5 - - 7.5 - - - 1.7 - - 6.0 - - 1.6 - 240 540 ns - 0.85 1.6 µC nC ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode A G S TJ = 25 °C, IS = 1.7 A, VGS = 0 Vb TJ = 25 °C, IF = 2.0 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.kersemi.com 2 D V IRFR310, IRFU310, SiHFR310, SiHFU310 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.kersemi.com 3 IRFR310, IRFU310, SiHFR310, SiHFU310 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.kersemi.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area IRFR310, IRFU310, SiHFR310, SiHFU310 RD VDS VGS D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T. RG + - I AS V DD VDS 10 V tp 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms www.kersemi.com 5 IRFR310, IRFU310, SiHFR310, SiHFU310 Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.kersemi.com 6 Fig. 13b - Gate Charge Test Circuit IRFR310, IRFU310, SiHFR310, SiHFU310 Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - + RG + • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test Driver gate drive P.W. Period D= - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level and 3 V drive devices Fig. 14 - For N-Channel www.kersemi.com 7