NTP27N06 Power MOSFET 27 Amps, 60 Volts N−Channel TO−220 Designed for low voltage, high speed switching applications in power supplies, converters, power motor controls and bridge circuits. 27 AMPERES, 60 VOLTS RDS(on) = 46 m Features • • • • • http://onsemi.com Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Pb−Free Package is Available N−Channel D Typical Applications • • • • G Power Supplies Converters Power Motor Controls Bridge Circuits S 4 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 10 M) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tp10 ms) VGS VGS 20 30 ID ID 27 15 80 Adc PD 88.2 0.59 W W/°C Operating and Storage Temperature Range TJ, Tstg −55 to +175 °C Single Pulse Drain−to−Source Avalanche EAS 109 mJ Rating Drain Current − Continuous @ TA = 25°C − Continuous @ TA 100°C − Single Pulse (tp10 s) Total Power Dissipation @ TA = 25°C Derate above 25°C Vdc IDM Thermal Resistance, Junction−to−Case RJC 1.7 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds TL 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. January, 2005 − Rev. 3 2 3 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain Apk Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10 Vdc, L = 0.3 mH, IL(pk) = 27 A,VDS = 60 Vdc) Semiconductor Components Industries, LLC, 2005 1 TO−220AB CASE 221A STYLE 5 1 NTP27N06 AYWW 1 Gate 3 Source 2 Drain NTP27N06 A Y WW = Device Code = Assembly Location = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: NTP27N06/D NTP27N06 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 − 70 79.4 − − − − − − 1.0 10 − − ±100 2.0 − 2.8 6.9 4.0 − − 37.5 46 − − 1.05 2.12 1.5 − gFS − 13.2 − mhos Ciss − 725 1015 pF Coss − 213 300 Crss − 58 120 td(on) − 13.6 30 tr − 62.7 125 td(off) − 26.6 60 OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 1) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (Note 1) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 1) (VGS = 10 Vdc, ID = 13.5 Adc) RDS(on) Static Drain−to−Source On−Resistance (Note 1) (VGS = 10 Vdc, ID = 27 Adc) (VGS = 10 Vdc, ID = 13.5 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 1) (VDS = 7.0 Vdc, ID = 6.0 Adc) Vdc mV/°C m Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 30 Vdc, ID = 27 Adc, VGS = 10 Vdc, Vdc RG = 9.1 ) (Note 1) Fall Time Gate Charge (VDS = 48 Vdc, Vd ID = 27 Adc, Ad VGS = 10 Vdc) (Note 1) tf − 70.4 140 QT − 21.2 30 Q1 − 5.6 − Q2 − 7.3 − − − 1.05 0.93 1.25 − trr − 42 − ta − 26 − tb − 16 − QRR − 0.07 − ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 27 Adc, VGS = 0 Vdc) (Note 1) (IS = 27 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 27 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 1) Reverse Recovery Stored Charge VSD Vdc ns c 1. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature. ORDERING INFORMATION Package Shipping† NTP27N06 TO−220AB 50 Units / Rail NTP27N06G TO−220AB (Pb−Free) 50 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 NTP27N06 56 56 7.5 V 48 9V 6.5 V 8V 40 32 6V 24 5.5 V 16 5V 8 4.5 V 2 3 4 5 6 32 24 16 TJ = 25°C 8 TJ = 100°C TJ = −55°C 3.4 4.2 5 5.8 6.6 7.4 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics VGS = 10 V 0.075 0.065 TJ = 100°C 0.055 0.045 TJ = 25°C 0.035 TJ = −55°C 0.025 0.015 0 8 16 24 32 40 48 56 RDS(on), DRAIN−TO−SOURCE RESISTANCE () VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.095 0.085 40 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.095 8.2 VGS = 15 V 0.085 0.075 0.065 TJ = 100°C 0.055 0.045 TJ = 25°C 0.035 0.025 TJ = −55°C 0.015 0 8 16 24 32 40 48 56 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 2.2 10000 ID = 13.5 A VGS = 10 V VGS = 0 V 1.4 1 0.6 −50 TJ = 150°C 1000 1.8 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE () RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1 48 0 2.6 0 0 VDS 10 V 7V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = 10 V TJ = 125°C 100 TJ = 100°C 10 1 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 60 NTP27N06 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1800 C, CAPACITANCE (pF) 1600 1400 VDS = 0 V VGS = 0 V TJ = 25°C Ciss 1200 1000 Crss Ciss 800 600 400 Coss 200 0 10 Crss 0 5 VGS 10 5 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 1000 12 QT 10 8 VGS Q2 Q1 6 t, TIME (ns) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) NTP27N06 4 100 tf tr td(off) 10 td(on) 2 VDS = 30 V ID = 27 A VGS = 10 V ID = 27 A TJ = 25°C 0 1 0 10 20 30 40 50 QG, TOTAL GATE CHARGE (nC) 60 70 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE () 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS IS, SOURCE CURRENT (AMPS) 60 VGS = 0 V TJ = 25°C 50 40 30 20 10 0 0.6 0.92 0.68 0.76 0.84 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 NTP27N06 I D, DRAIN CURRENT (AMPS) 100 VGS = 20 V SINGLE PULSE TC = 25°C 10 s 100 s 10 1 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 10 ms dc 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS , SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA 200 150 125 100 Figure 11. Maximum Rated Forward Biased Safe Operating Area r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) ID = 27 A 175 75 50 25 0 25 150 50 75 100 125 175 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1 D = 0.5 0.2 0.1 0.05 0.01 SINGLE PULSE 0.1 0.0001 0.001 0.01 0.1 1 t, TIME (s) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 10 NTP27N06 PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AA B F −T− SEATING PLANE C 4 T S A Q 1 2 3 H K DIM A B C D F G H J K L N Q R S T U V Z U Z L V R G D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. J N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 STYLE 5: PIN 1. 2. 3. 4. http://onsemi.com 7 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 NTP27N06 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 For additional information, please contact your local Sales Representative. NTP27N06/D