ONSEMI NTB13N10

NTB13N10
Power MOSFET
100 V, 13 A, N−Channel
Enhancement−Mode D2PAK
Features
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• Source−to−Drain Diode Recovery Time Comparable to a Discrete
•
•
•
•
Fast Recovery Diode
Avalanche Energy Specified
IDSS and RDS(on) Specified at Elevated Temperature
Mounting Information Provided for the D2PAK Package
Pb−Free Packages are Available
V(BR)DSS
RDS(on) TYP
ID MAX
100 V
165 mW @ 10 V
13 A
N−Channel
D
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
G
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
Rating
VDSS
100
V
Drain−to−Source Voltage (RGS = 1.0 MW)
VDGR
100
V
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp v 10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Pulsed (Note 1)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 V, VGS = 10 V, IL(pk) = 13 A,
L = 1.0 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
VGS
VGSM
D2PAK
CASE 418AA
STYLE 2
4
V
"20
"30
1
2
3
A
ID
ID
IDM
13
8.0
39
PD
64.7
0.43
W
W/°C
TJ, Tstg
−55 to
+175
°C
EAS
85
mJ
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
13N10G
AYWW
°C/W
RqJC
2.32
TL
260
1
Gate
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
13N10
A
Y
WW
G
2
Drain
3
Source
= Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
1
Publication Order Number:
NTB13N10/D
NTB13N10
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
100
−
−
147
−
−
−
−
−
−
5.0
50
−
−
± 100
2.0
−
3.2
−7.6
4.0
−
−
−
0.130
0.250
0.165
0.400
−
1.82
2.34
gFS
−
6.0
−
mhos
pF
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 V, ID = 250 mA)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VGS = 0 V, VDS = 100 V, TJ = 25°C)
(VGS = 0 V, VDS = 100 V, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = $20 V, VDS = 0)
IGSS
V
mV/°C
mA
nA
ON CHARACTERISTICS
Gate Threshold Voltage
VDS = VGS, ID = 250 mA)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = 10 V, ID = 6.5 A)
(VGS = 10 V, ID = 6.5 A, TJ = 125°C)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 V, ID = 13 A)
VDS(on)
Forward Transconductance (VDS = 15 V, ID = 6.5 A)
V
mV/°C
W
V
DYNAMIC CHARACTERISTICS
(VDS = 25 V, VGS = 0 V,
f = 1.0 MHz)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Ciss
−
390
550
Coss
−
115
160
Crss
−
35
70
td(on)
−
11
20
SWITCHING CHARACTERISTICS (Notes 2 and 3)
(VDD = 80 V, ID = 13 A,
VGS = 10 V, RG = 9.1 W)
Turn−On Delay Time
Rise Time
ns
tr
−
40
80
td(off)
−
20
40
tf
−
36
70
Qtot
−
14
20
Qgs
−
3.0
−
Qgd
−
7.0
−
(IS = 13 A, VGS = 0 V)
(IS = 13 A, VGS = 0 V, TJ = 125°C)
VSD
−
−
0.98
0.88
1.3
−
V
(IS = 13 A, VGS = 0 V,
dIS/dt = 100 A/ms)
trr
−
85
−
ns
ta
−
60
−
tb
−
28
−
QRR
−
0.3
−
Turn−Off Delay Time
Fall Time
(VDS = 80 V, ID = 13 A,
VGS = 10 V)
Total Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
nC
BODY−DRAIN DIODE RATINGS (Note 2)
Diode Forward On−Voltage
Reverse Recovery Time
Reverse Recovery Stored Charge
mC
2. Indicates Pulse Test: P.W. = 300 ms max, Duty Cycle = 2%.
3. Switching characteristics are independent of operating junction temperature.
ORDERING INFORMATION
Package
Shipping †
NTB13N10
D2PAK
50 Units / Rail
NTB13N10G
D2PAK
50 Units / Rail
Device
(Pb−Free)
D2PAK
800 Units / Tape & Reel
D2PAK
(Pb−Free)
800 Units / Tape & Reel
NTB13N10T4
NTB13N10T4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
26
24
22
20
18
16
14
12
10
8
6
4
2
0
VGS = 10 V
TJ = 25°C
9V
7V
8V
7.5 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
NTB13N10
6.5 V
6V
5.5 V
5V
4.5 V
0
1
2
3
4
5
6
7
8
9
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
26
24
22
20
18
16
14
12
10
8
6
4
2
0
VDS ≥ 10 V
TJ = 25°C
TJ = 100°C
0
1
2
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS = 10 V
0.4
TJ = 100°C
TJ = 25°C
0.1
TJ = −55°C
0
0
2
4
6 8 10 12 14 16 18 20
ID, DRAIN CURRENT (AMPS)
22 24 26
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.5
0.2
0.2
TJ = 25°C
0.175
VGS = 10 V
0.15
VGS = 15 V
0.125
0.1
0
Figure 3. On−Resistance versus Drain Current
and Temperature
2
4
6 8 10 12 14 16 18 20 22 24 26
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10000
3
2.5
10
Figure 2. Transfer Characteristics
VGS = 0 V
ID = 6.5 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
0.3
TJ = −55°C
2
1.5
1
TJ = 150°C
1000
100
TJ = 100°C
0.5
0
−50 −25
10
0
25
50
75
100 125 150
TJ, JUNCTION TEMPERATURE (°C)
175
20
Figure 5. On−Resistance Variation with
Temperature
30
40
50
60
70
80
90 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTB13N10
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1000
VDS = 0 V VGS = 0 V
Ciss
800
C, CAPACITANCE (pF)
TJ = 25°C
600
Crss
Ciss
400
Coss
200
0
10
Crss
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
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4
18
90
QT
16
80
VDS
14
70
12
60
10
VGS
8
Q1
6
50
40
Q2
30
4
20
ID = 13 A
TJ = 25°C
2
0
0
2
4
6
8
10
QG, TOTAL GATE CHARGE (nC)
10
0
14
12
1000
VDD = 80 V
ID = 13 A
VGS = 10 V
100
t, TIME (ns)
100
20
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTB13N10
tr
tf
td(off)
td(on)
10
1
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (W)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
12
10
VGS = 0 V
TJ = 25°C
8
6
4
2
0
0.4
0.5
0.6
0.7
0.8
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTB13N10
ID, DRAIN CURRENT (AMPS)
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
10 ms
100 ms
1 ms
1
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
dc
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
100
ID = 13 A
80
60
40
20
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
50
75
100
125
150
175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
P(pk)
0.1
0.05
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.1
0.0001
0.001
0.01
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
0.1
1
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
10
NTB13N10
PACKAGE DIMENSIONS
D2PAK
CASE 418B−01
ISSUE J
C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
E
V
W
−B−
4
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
A
1
2
S
3
−T−
SEATING
PLANE
K
W
J
G
D 3 PL
0.13 (0.005)
VARIABLE
CONFIGURATION
ZONE
H
M
T B
M
N
R
M
STYLE 2:
PIN 1.
2.
3.
4.
P
U
L
L
M
L
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
NTB13N10
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTB13N10/D