16-Bit, 10MSPS PulSAR Differential ADC AD7626 Preliminary Technical Data FEATURES FUNCTIONAL BLOCK DIAGRAM REFIN REF VCM Throughput: 10 MSPS SAR architecture 16-bit resolution with no missing codes SNR: 92 dB Typ, 90dB Min @ 1MHz INL: ±1 LSB Typ, ±2 LSB Max DNL: ±0.3 LSB Typ, ±1 LSB Max Differential input range: ± 4.096V No latency/no pipeline delay (SAR architecture) Serial LVDS interface: Self-clocked mode Echoed-clock mode Reference: Internal 4.096 V External (1.2V) buffered to 4.096 V External 4.096 V Power dissipation 150 mW 32-Lead LFCSP package (5 mm x 5 mm) 1.2V BANDGAP LOGIC IN+ D Differential (ground sense) 16 True Bipolar Differential (anti-phase) Differential (anti-phase) 16 16 18 ≥ 2 MSPS to ≤ 3 MSPS SERIAL LVDS DCO CLK Figure 1. GENERAL DESCRIPTION The AD7626 is a 16-bit, 10MSPS, charge redistribution successive approximation register (SAR) architecture, analogto-digital converter (ADC). SAR architecture allows unmatched performance both in noise – 92dB SNR - and in linearity – 1LSB. The AD7626 contains a high speed 16-bit sampling ADC, an internal conversion clock, and an internal buffered reference. On the CNV edge, it samples the voltage difference between IN+ and IN− pins. The voltages on these pins swing in opposite phase between 0 V and REF. The 4.096V reference voltage, REF, can be generated internally or applied externally. All converted results are available on a single LVDS self-clocked or echoed-clock serial interface reducing external hardware connections. Table 1. Fast PulSAR ADC Selection ≥1 MSPS to < 2MSPS AD7653 AD7667 AD7980 AD7983 AD7671 AD7677 AD7623 AD7643 AD7982 AD7984 SAR AD7626 High dynamic range telecommunications Receivers Digital imaging systems High-speed data acquisition Spectrum analysis Test equipment Res (Bit s) CNV CAP DAC IN- APPLICATIONS Input Type VIO CLOCK 2 6 MSPS 10 MSPS AD7625 AD7626 The AD7626 is housed in a 32-lead LFCSP (5mm by 5mm) with operation specified from −40°C to +85°C. AD7985 AD7621 AD7622 AD7641 AD7986 Rev. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD7626 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................5 Applications....................................................................................... 1 ESD Caution...................................................................................5 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................6 General Description ......................................................................... 1 Terminology .......................................................................................8 Specifications..................................................................................... 3 Theory of Operation .........................................................................9 Timing Specifications .................................................................. 4 Outline Dimensions ....................................................................... 11 Absolute Maximum Ratings............................................................ 5 Rev. PrC | Page 2 of 11 Preliminary Technical Data AD7626 SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; VREF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Common Mode Input Range Analog Input CMRR Input Current THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Differential Linearity Error Transition Noise Zero Error, TMIN to TMAX Zero Error Drift Gain Error, TMIN to TMAX Gain Error Drift Power Supply Sensitivity AC ACCURACY Dynamic Range Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) −3 dB Input Bandwidth Aperture Delay Aperture jitter Transient Response INTERNAL REFERENCE Output Voltage Temperature Drift REFERENCE BUFFER REFIN Input Voltage Range REF Output Voltage range EXTERNAL REFERENCE Voltage Range VCM Output Voltage Output Impedance Conditions Min 16 VIN+ − VIN− VIN+, VIN− to AGND −VREF −0.1 VREF/2 – 0.1 fIN = 1 MHz 10 MSPS throughput Typ Max Unit Bits +VREF +VREF + 0.1 VREF/2 + 0.1 V V V dB μA 100 10 ns MSPS ±1 +2 ±0.3 0.6 ±100 1 50 1 TBD TBD +1 LSB Bits LSB LSB μV ppm/°C ppm of FS ppm/°C LSB LSB VREF/2 60 550 0.001 -2 16 -1 VDD1 = 5 V ± 5% VDD2 = 2.5 V ± 5% 90 90 Full-Scale Step 5 50 dB dB dB dB dB dB dB MHz ns ps rms ns REFIN @ 25°C −40°C to +85°C 1.2 ±7 V ppm/°C 1.2 4.096 V V 4.096 V fIN = 1 MHz fIN = 1 MHz fIN = TBD fIN = 1 MHz fIN = TBD fIN = 1 MHz REF @ 25°C 4 Rev. PrC | Page 3 of 11 92 92 110 90 -110 -90 92 100 VREF/2 5 6 VREF/2 kΩ AD7626 Parameter LVDS I/O, (ANSI-644) Data Format VOD VOCM VID VICM POWER SUPPLIES Specified Performance VDD1 VDD2 VIO Operating Currents VDD1 VDD2 VIO VIO Power Dissipation1 With Internal Reference Without Internal Reference Energy per conversion TEMPERATURE RANGE Specified Performance 1 Preliminary Technical Data Conditions Min Typ Max Unit Serial LVDS Two’s complement Differential Output Voltage, RL=100 Ω Common mode Output Voltage, RL=100Ω Differential Input Voltage Common mode Input Voltage 247 350 454 mV 1125 1250 1375 mV 650 1575 mV mV 100 800 4.75V 2.37 2.3 5 2.5 2.5 5.25V 2.63 2.7 V V V Self-clocked mode Echoed-clock mode 10 25 14 18 mA mA mA mA 10 MSPS throughput 10 MSPS throughput 10 MSPS throughput 140 120 10 mW mW nJ/sample TMIN to TMAX −40 +85 °C Power dissipation is for the AD7626 only. In self-clocked interface, 9mW is dissipated in the 100 ohm terminator. In echoed-clock interface, 18mW is dissipated in (2) 100 ohm terminators. TIMING SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.3V to 2.7 V; VREF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Time between conversion Acquisition time CNV high time CNV to D (MSB) delay CNV to last CLK (LSB) delay CLK period CLK frequency CLK to DCO delay (echoed-clock mode) DCO to D delay (echo-clock mode) CLK to D delay Symbol tCYC tACQ tCNVH tMSB tCLKL tCLK fCLK tDCO tD tCLKD Rev. PrC | Page 4 of 11 Min 100 40 10 Typ TBD 4 250 4 0 4 0 -1 0 Max 10000 40 100 64 400 7 1 7 Unit ns ns ns ns ns ns MHz ns ns ns Preliminary Technical Data AD7626 ABSOLUTE MAXIMUM RATINGS maximum rating conditions for extended periods may affect device reliability. Table 4. THERMAL RESISTANCE Parameter Analog Inputs/Outputs CAP1, REFIN IN+, IN-, REF, REF/2, CAP2 Digital Inputs/Outputs Supply Voltage VDD1 VDD2, VIO With Respect to Rating GND GND -0.3V to 2.7V -0.3V to 6V GND -0.3V to 2.7V GND GND -0.3V to 6V -0.3V to 2.7V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute Rev. PrC | Page 5 of 11 θJA θJC Unit AD7626 Preliminary Technical Data 1 2 3 4 5 6 7 8 PIN 1 INDICATOR TOP VIEW 24 23 22 21 20 19 18 17 GND IN+ INREF/2 VDD1 VDD1 VDD2 CLK+ CNV+ DD+ VIO GND DCODCO+ CLK- 9 10 11 12 13 14 15 16 VDD1 VDD2 CAP1 REFIN EN0 EN1 VDD2 CNV- 00000-000 32 31 30 29 28 27 26 25 REF GND REF REF CAP2 GND CAP2 CAP2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Table 6. Pin Function Descriptions Pin No. 1 Mnemonic VDD1 Type1 P 2 VDD2 P 3 4 CAP1 REFIN AO AI/O 5, 6 EN0, EN1 DI 7 8, 9 VDD2 CNV-, CNV+ P DI 10, 11 D-, D+ D0 12 13 14, 15 VIO GND DCO-, DCO+ P P DI/O 16, 17 CLK-, CLK+ DI Description Analog 5V Supply. Decouple with 10uF and 100nF capacitors. Analog 2.5V Supply. The system 2.5V supply should supply this pin first, decoupled with 10uF and 100nF capacitors, then starred off to other VDD2 pins. Connect to a 10nF capacitor. Pre-Buffer Reference Voltage. When using the internal reference, this pin outputs the band-gap voltage and is nominally at 1.2V. It can be overdriven with an external reference voltage like the ADR280. In either mode, a 10uF capacitor is required. If using an external 4.096V reference (connected to REF), this pin is a no connect and does not require any capacitor. Enable Pins. EN1 EN0 Operation 0 0 Power down all; ADC, internal reference and reference buffer. 0 1 Enable internal buffer, disable internal reference. An external 1.2V reference connected to REFIN pin is required. 1 0 Disable internal reference and buffer. An external reference connected to the REF pin is required. 1 1 Enable all; ADC, internal reference and reference buffer. Digital 2.5V supply. Convert Input. This input has multiple functions. On its rising edge, it samples the analog inputs and initiates a conversion cycle. CNV+ works as a CMOS input when CNV- is grounded otherwise CNV+, CNV- are LVDS inputs. LVDS Data Outputs. The conversion data is output serially on these pins. Input/Output Interface Supply. Nominally 2.5V. Ground. LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clock interface mode is selected. In this mode, the 16 bit results on D is preceded by a three bit header (010) to allow synchronization of the data by the digital host with simple logic. When DCO+ is not grounded, the echoed clock interface mode is selected. In this mode, DCO± is a copy of CLK±. The data bits are output on the falling edge of DCO+ and can be latched in the digital host on the next rising edge of DCO+. LVDS Clock Inputs. This clock shifts out the conversion results on the negative edge of CLK+. Rev. PrC | Page 6 of 11 Preliminary Technical Data Pin No. 18 19, 20 21 Mnemonic VDD2 VDD1 VCM Type1 P P AO 22 IN- AI 23 IN+ AI 24 25, 26, 28 27 GND CAP2 P AO GND P 29, 30, 32 REF AI/O 31 GND P 1 AD7626 Description Analog 2.5V Supply. Analog 5V supply. Isolate from Pin 1 with a ferrite bead. Common Mode Output. When using any reference scheme, this pin produces ½ of the voltage present on the REF pin which can be useful for driving the common mode of the input amplifiers. Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+. Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN-. Ground. Connect all three pins to a single 10uF X5R capacitor with the shortest distance. The other side of the capacitor must be placed close to pin 27 (GND). Ground. Return path for 10uF capacitor connected to pins 25, 26, and 28. Buffered Reference Voltage. When using the internal reference or 1.2V external reference (REFIN input), the 4.096V system reference is produced at this pin. When using an external reference, like the ADR434 or ADR444, the internal reference buffer must be disabled. In either case, connect all three pins to a single 10uF X5R capacitor with the shortest distance. The other side of the capacitor must be placed close to pin 31 (GND) Ground. Return path for 10uF capacitor connected to pins 29, 30, and 32. AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. Rev. PrC | Page 7 of 11 AD7626 Preliminary Technical Data TERMINOLOGY Least Significant Bit (LSB) Total Harmonic Distortion (THD) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. LSB (V ) = Signal-to-(Noise + Distortion) Ratio (SINAD) V INp-p 2 N Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive fullscale. The point used as negative full scale occurs a ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSBs beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error The difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Gain Error The first transition (from 100 ... 00 to 100 ... 01) should occur at a level ½ LSB above nominal negative full scale (−4.095938 V for the ±4.096V V range). The last transition (from 011 … 10 to 011 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.095813 V for the ±4.096V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINADdB − 1.76)/6.02] Aperture Delay Aperture delay is a measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7634 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as TCVREF ( ppm/°C ) = Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at −60 dB. The value for dynamic range is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. VREF ( Max ) – VREF ( Min ) VREF ( 25°C ) × ( TMAX – TMIN ) × 10 6 where: VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX. VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX. VREF (25°C) = VREF at 25°C. TMAX = +85°C. TMIN = –40°C. Rev. PrC | Page 8 of 11 Preliminary Technical Data AD7626 THEORY OF OPERATION Echoed-Clock Interface Mode Conversions are initiated by a CNV pulse. The CNV must be returned low ≤ tCNVH(max) for valid operation. Once a conversion has begun, it continues until completion. Additional CNV pulses are ignored during the conversion phase. After the time tMSB elapses, the host should begin to burst the CLK. Note that tMSB is the maximum time for the MSB of the new conversion result and should be used as the gating device for CLK. The echoed clock, DCO, and data, D, will be driven in phase with D being updated on the DCO+ falling edge and the host should use the DCO+ rising edge to capture D. The only requirement is that the 16 CLK pulses finish before the time tCLKL elapses of the next conversion phase or the data will be lost. From the time tCLKL to tMSB, D and DCO will be driven to 0’s. The AD7626 digital operation in “echoed-clock interface mode” is shown in Figure 3. This interface mode, requiring just a shift register on the digital host, can be used with many digital hosts (FPGA, shift register, microprocessor, etc.). It requires 3 LVDS pairs (D±, CLK±, and DCO±) between each AD7626 and the digital host. The clock DCO is a buffered copy of CLK and synchronous to the data, D, which is updated on DCO+ falling edge (tD). By keeping good propagation delay matching between D and DCO through the board and the digital host, DCO can be can be used to latch D with good timing margin for the shift register. SAMPLE N SAMPLE N+1 TCYC TCNVH CNVCNV+ TACQ ACQUISITION ACQUISITION ACQUISITION TCLKL TCLK 15 CLK- 16 1 2 15 1 16 2 3 CLK+ TDCO 15 DCODCO+ 16 1 TMSB D- D1 N-1 D0 N-1 15 1 16 2 3 D14 N+1 D13 N+1 TD TCLKD D+ 2 0 D15 N D14 N D1 N Figure 3. Echoed-Clock Interface Mode Timing Diagram Rev. PrC | Page 9 of 11 D0 N 0 D15 N+1 AD7626 Preliminary Technical Data Self Clocked Mode between the state machine clock and D including any board propagation time allowing to use the best clock signal to latch the following bits of the conversion result. The AD7626 digital operation in “self-clocked interface mode” is shown in Figure 4. This interface mode reduces the number of wires between ADCs and the digital host to 2 LVDS pairs per AD7626, CLK± and D± or a single pair if sharing a common CLK using multiple AD7626’s. This considerably eases the design of a system using multiple AD7626’s since the interface can tolerate several CLK cycles of propagation delay mismatch between the different AD7626 devices and the digital host. Conversions are initiated by a CNV pulse. The CNV must be returned low ≤ tCNVH(max) for valid operation. Once a conversion has begun, it continues until completion. Additional CNV pulses are ignored during the conversion phase. After the time tMSB elapses, the host should begin to burst the CLK. Note that tMSB is the maximum time for the first bit of the header and should be used as the gating device for CLK. CLK is also used internally on the host to begin the internal synchronization state machine. The next header bit and conversion results are output on subsequent falling edges of CLK. The only requirement is that the 18 CLK pulses finish before the time tCLKL elapses of the next conversion phase or the data will be lost. The “self-clocked interface mode” consists of preceding each ADC word results by a header of 2 bits on the data, D This header is used to synchronize D of each conversion in the digital host. Synchronization is accomplished by one simple state machine per AD7626 device. The state machine is running, for instance, at the same speed as CLK with 3 phases. The state machine measures when the first “one” of the header occurs. This provides the value of the actual propagation delay delta SAMPLE N SAMPLE N+1 TCYC TCNVH CNVCNV+ TACQ ACQUISITION ACQUISITION ACQUISITION TCLK CLK- TCLKL 17 18 1 2 4 3 17 1 18 2 3 CLK+ TMSB TCLKD D+ D- *1 D1 N-1 D0 N-1 0 1 0 D15 N D14 N D1 N D0 N 0 1 Figure 4. Self-Clocked Interface Mode Timing Diagram1 1 This timing is for silicon rev 1 or above. For silicon rev 0, there is an extra bit (a zero) in front on the bit with value 1. Therefore, silicon rev 0 needs 19 clock pulses. Rev. PrC | Page 10 of 11 0 D15 N+1 Preliminary Technical Data AD7626 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX 25 24 PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 17 16 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 5.32-Lead Lead Frame Chip Scale package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-3) ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07648-0-6/08(PrC) 3.45 3.30 SQ 3.15 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.30 0.23 0.18 1 EXPOSED PAD (BOTTOM VIEW) 0.05 MAX 0.02 NOM SEATING PLANE 32