ONSEMI NCV7729

NCV7729
8A H-Bridge Driver
The NCV7729 is an intelligent, fully protected H−Bridge Driver
designed specifically for control of DC and stepper motors in safety
critical applications under automotive/industrial environment.
Features
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Operating VS Battery Supply Voltage 5 V to 28 V
Operating VCC Supply Voltage 3.0 to 5.5 V
18 V Survivability on VCC and All Logic I/O Pins
Typical RDS(on) = 150 mW, RDS(MAX) = 300 mW (150°C)
Continuous DC Load Current 5A (TC < 100°C)
Selectable Output Current Limitation (2.5 A to 9.6 A)
Output Switching Frequency Up to 30 kHz
Monitoring of All Supply Voltages, Safe Power−up State
Loss of GND Detection
Short−Circuit Protection and Thermal Shutdown
Full Diagnosis Capability for Open Load, Short to GND/VS and
Shorted Load Conditions
SPI Interface for Configuration and Diagnosis
Undervoltage Lockout
Regulated Charge Pump for Optimized EMI Behavior
This is a Pb−Free Device
NCV Prefix for Automotive and Other Applications Requiring Site
and Change Controls
PSOP−20
CASE 525AB
MARKING DIAGRAM
20
NCV7729BG
AWLYYWWG
1
Typical Applications
• Automotive
A
WL
YY
WW
G
Electronic Throttle Control (ETC)
♦ Variable Intake Geometry
♦ Exhaust Gas Recirculation
♦ Variable Swirl
♦ Blow−off Flap
Industrial
♦
•
11
10
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NCV7729BPPR2G
PSOP−20
(Pb−Free)
750 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
April, 2010 − Rev. 0
1
Publication Order Number:
NCV7729/D
NCV7729
VCC
CHP
12
4
Core Functions
Biasing and
Supply
19
EN
13
DIS/SF
18
CSB
17
SCLK
2
SI
9
SO
8
Driver
&
Gate Control
IN2
5,16
Regulated
Chargepump
Control Logic
3
16bit
SPI−I/F
IN1
VS
Output Protection
and Diagnostics
GND Loss Detection
1
AGND
20
DGND
GND
Figure 1. Block Diagram
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2
10,11
6,7
OUT1
14,15
OUT2
NCV7729
VBAT
REVERSE
BATTERY
&
TRANSIENT
PROTECTION
REG1
VBAT
5V / 3.3V
100mF
CBUF
22 nF
100nF
REG2
VCC
5V / 3.3V
CHP
13
DIS/SF
18
CSB
17
SCLK
2
SI
9
8
SO
Ddriver
&
Gate Control
19
EN
5,16
Regulated
Chargepump
Control Logic
3
IN2
16bit
SPI−I/F
SUPERVISOR
mC
MAIN
mC
Core Functions
Biasing and
Supply
IN1
VS
4
12
Output Protection
and Diagnostics
GND Loss Detection
1
20
AGND
DGND
GND
Figure 2. ETC Application Diagram
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3
10,11
6,7
OUT1
14,15
OUT2
M
NCV7729
PACKAGE PIN DESCRIPTION
Pin#
Symbol
1
AGND
Analog Ground; Device Substrate.
2
SCLK
Serial Clock. Clock input for SPI communication (internal pullup to VCC)
3
IN1
Control Input 1 (internal pullup to VCC)
4
CHP
Charge pump in/output
5
VS
6
OUT1
Output1; must be connected to pin 7 externally
7
OUT1
Output1; must be connected to pin 6 externally
8
SO
Serial Output. 16 bit SPI communications output.
9
SI
Serial Input. 16 bit SPI communications input (internal pullup to VCC)
10
GND
Power Ground.
11
GND
Power Ground.
12
VCC
Power supply for logic
13
EN
14
OUT2
Output2; connect to pin 15 externally
15
OUT2
Output2; connect to pin 14 externally
16
VS
17
CSB
18
DIS/SF
19
IN2
20
DGND
HEAT SLUG
Description
Supply voltage; must be connected to pin 16 externally
Enable input (internal pulldown to AGND)
Supply voltage; must be connected to pin 5 externally
Chip Select Bar Input. Active low SPI port operation (internal pullup to VCC)
Disable Input / Status Flag Output (Open drain w/ internal pullup to VCC)
Control Input 2 (pullup to VCC)
Digital Ground.
Internally Connected to AGND; Device Substrate
AGND
SCLK
IN1
CHP
VS
OUT1
OUT1
SO
SI
GND
1
DGND
IN2
DIS/SF
CSB
VS
OUT2
OUT2
EN
VCC
GND
HEAT SLUG
Figure 3. Package Pinout
(Top View)
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4
NCV7729
MAXIMUM RATINGS (Voltages are with respect to device substrate.)
Rating
Value
Battery Supply and Power Outputs (VS, OUTx)
(DC)
(AC), t < 500 ms
Unit
V
−1 to 40
−2
Digital Supply (VCC),
Logic input/output pins (EN, DIS/SF, INx, CSB,SCLK, SO, SI)
V
−0.5 to 18
Charge pump Supply, relative to VS V(CHP) − V(VS)
16
V
Operating Junction Temperature
Continuous
t<1s
−40 to 150
175
Storage Temperature Range
−65 to 150
°C
260 peak
°C
Peak Reflow Soldering Temperature: Pb−Free − 60 to 150 seconds at 217°C (Note 1)
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D,
and Application Note AND8003/D.
ATTRIBUTES
Characteristic
Value
Electrostatic Discharge, Human Body Model (MIL Std 883D)
All pins
Battery / Output Pins (VS, OUTx) (Note 3)
Electrostatic Discharge, CDM
w $2
w $8
w $800
Moisture Sensitivity Level (Note 2)
MSL 1
Thermal Resistances
Junction − to − ambient (copper area, thickness)
Theta JA ( 100 mm2, 2 oz ) (Note 4)
Theta JA ( 300 mm2, 2 oz ) (Note 4)
Theta JA ( 600 mm2, 2 oz ) (Note 4)
Psi J−Board solder pad
Package Thermal Time Constant
Unit
kV
V
−
°C/W
78
47
36
1.5
1
sec
2. For additional information, see or download ON Semiconductor’s Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D, and Application Note AND8003/D.
3. VS pins (pin 5, 16) connected together; all GND pins (pin 1, 10, 11, 20) connected together.
4. Thermal estimates are based on mounting the package on a 30 x 70 x 1.5 mm FR4 substrate.
Copper areas include traces and mounting area of the device. 1 oz is equivalent to 0.035 mm thick
copper. Test/simulation is based on JEDEC JESD51.1, JESD51.2, and JESD51.3 standards still
air chamber boundary conditions steady state thermal performance.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCCop
Digital supply input voltage (VCC)
3
5.5
V
VSop
Battery supply input voltage (VS)
5
28
V
fophi
foplo
INx PWM Frequency (CBUF = 22 nF)
Charge pump in full power mode
Charge pump in reduced power mode
−
30
4
−40
150
°C
175
°C
TJ
TJac
Junction temperature
Junction temperature − transient ( t < 1s)
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5
kHz
NCV7729
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 5 V < VS < 28 V, 3 V < VCC < 5.5 V, EN = VCC, DIS/SF = GND, CBUF =
22 nF, unless otherwise specified) (Note 5)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
fpwm = 20 kHz, Iout = 0 A
−
−
30
mA
IVSop,dc
fpwm = 0, Iout = 0 A
−
−
5.5
mA
IVSdiag
DIS/SF = VCC, EN = 0,
SCLK = 0, VS = 13.2 V
Config.Enx = 1
OUT1 tied to OUT2
−
−
6.0
mA
IVSdis
DIS/SF = VCC, EN = 0,
SCLK = 0, VS = 13.2 V
Config.Enx = 0
0 v VCC v 5.5V
TA v 85°C; (Note 6)
−
−
5.0
mA
CSB = VCC,
Outputs enabled
−
−
2.0
mA
2.5
−
3.0
V
POWER SUPPLIES
VS Supply Current
VCC Supply Current
IVSop,pwm
IVCCop
VCC Undervoltage Lockout
VCCPORon
VCC POR Hysteresis
VCCPORhy
0.1
−
−
V
VCC Overvoltage Lockout
VCCOV
5.5
−
−
V
VS Undervoltage Lockout
VSPORoff
Switch−off threshold,
falling; (Note 7)
3.6
4.4
5.0
V
VSPORon
Switch−on threshold, rising
3.8
4.6
5.2
V
V
VS POR Hysteresis
Power supply lockout delay
Power−on reset, rising
VSPORhy
PORdly
Loss of Ground Lockout Threshold
GDIF
0.1
−
0.5
VCC, VS, or CHP
−
20
50
ms
|V(AGND) − V(DGND)|
−
−
300
mV
V(CHP) − V(VS)
−
10
13
V
4.5
−
6
V
100
−
400
mV
CBUF = 22 nF, fpwm = 30 kHz, CHP Full Power Mode
CHP regulation voltage
VCHP
CHP Undervoltage lockout
VCHPLV
CHP Undervoltage Hysteresis
VCHPhy
CHP output current limitation
ILIMCHP
V(CHP) = 0 V
−
−
30
mA
CHP allowable external leakage
ICHPlkg
V(CHP) − V(VS),
VS = 13.2 V,
ICHPlkg = −150 mA
8
−
−
V
tdact
V(CHP) > VCHPLV
−
−
1.0
ms
RonOUTx
VS > 5 V, IOUT = 3 A
−
150
300
mW
RonOUTxGM
VS > 5 V, IOUT = 3 A,
TJ = −30°C
−
−
135
mW
8.0
5.4
4.4
2.0
9.6
6.6
5.5
2.5
11.1
7.8
6.6
3.0
A
CHP power on delay time
VCC or VS POR release
Until OUTx active
V(CHP) − V(VS) falling
POWER OUTPUTS − DC Characteristics
Output Transistor ON Resistance
LS Current limit switch−off threshold
ILIMLSx
Config.OCx = IC4
Config.OCx = IC3 (default)
Config.OCx = IC2
Config.OCx = IC1
5. Min/Max values are valid for the temperature range −40°C vTJ v 150°C unless noted otherwise. Min/Max values are guaranteed by
test, design or statistical correlation.
6. The load must be connected between OUT1 and OUT 2 to achieve the low−quiescent current standby mode.
7. VS must first exceed the VSPORon switch−on threshold for operation down to VSPORoff.
8. The ISDLSx and ISDHSx thresholds are unaffected during temperature dependant current limit reduction.
9. No production test.
10. Latency time between overcurrent or overtemp shutdown to reactivation of output stage via ENA or DIS/SF.
11. Minimum latency between successive frames.
12. Minimum hold time after ENA H → L or DIS/SF L → H.
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NCV7729
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 5 V < VS < 28 V, 3 V < VCC < 5.5 V, EN = VCC, DIS/SF = GND, CBUF =
22 nF, unless otherwise specified) (Note 5)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
2
−
−
A
POWER OUTPUTS − DC Characteristics
LS Current limit vs. Overcurrent tracking
ItrackLS
ISDLSx − ILIMLSx
LS Overcurrent shutdown threshold
ISDLSx
(Note 8)
Config.OCx = IC4
Config.OCx = IC3 (default)
Config.OCx = IC2
Config.OCx = IC1
−
8.5
−
−
15.0
10.8
9.5
4.9
−
13.0
−
−
A
IC4 − IC3
IC3 − IC2
IC3 − IC1
3.0
0.8
4.1
4.3
1.2
5.5
5.6
1.6
6.9
A
Config.OCx = IC4
Config.OCx = IC3 (default)
Config.OCx = IC2
Config.OCx = IC1
−
−13.0
−
−
−15.0
−10.8
−9.5
−4.9
−
−8.5
−
−
A
LS Overcurrent shutdown tracking
HS Overcurrent shutdown threshold
ItrackSDLS
ISDHSx
(Note 8)
HS Overcurrent shutdown tracking
ItrackSDHS
IC4 − IC3
IC3 − IC2
IC3 − IC1
−5.6
−1.6
−6.9
−4.3
−1.2
−5.5
−3.0
−0.8
−4.1
A
OUTx leakage current
Ileak, OUTx
DIS/SF = VCC, EN = 0, SCLK
= 0, VS = 28 V
Config.Enx = 0
V(OUTx) = 0 V
−20
0
−
mA
Start of temperature dependant current limit
reduction
TLIM
(Note 9)
150
165
−
°C
Thermal Shutdown
TSD
(Note 9)
175
−
−
°C
Free−wheel diode forward voltage
VD
OUTx off, I(OUT) = 3 A
−
−
2.0
V
trr
(Note 9)
−
−
100
ns
−
−
2.0
ms
−
−
4.0
ms
POWER OUTPUTS − AC Characteristics
Free−wheel diode reverse recovery time
Disable delay time
EN or DIS/SF→OUTx
tpddis
Output ON delay − INx→OUTx
tdon
Output OFF delay − INx→OUTx
tdoff
−
−
4.0
ms
Output switching time
OUTxH→OUTxL or OUTxL→OUTxH
tr,tf
−
−
4.0
ms
LS Current limit blanking time
tb
14
20.5
27
ms
LS Current limit switch−off time
ta
16
23.5
31
ms
Switch−off to blanking tracking
RL = 5 W, VS = 15 V
VS = 13.2 V;
L = 0.75 mH, R = 0.2 W
ta/tb
1.0
−
−
−
Overcurrent fault filter time
tdfault
1.0
2.0
−
ms
Reactivation time after internal shutdown
treact
(Notes 9 and 10)
−
−
200
ms
Vth1
EN=GND or DIS/SF=VCC
Config.ENx = 1
1.25
−
2
V
1.25
−
2
V
−2000
−
−1000
mA
OPEN LOAD DIAGNOSTICS
Open Load Diagnostic Threshold
Vth2
Diagnostic Pullup current
I(OUT1)
V(VS) = 13.2 V,
V(OUT1) = 2 V
5. Min/Max values are valid for the temperature range −40°C vTJ v 150°C unless noted otherwise. Min/Max values are guaranteed by
test, design or statistical correlation.
6. The load must be connected between OUT1 and OUT 2 to achieve the low−quiescent current standby mode.
7. VS must first exceed the VSPORon switch−on threshold for operation down to VSPORoff.
8. The ISDLSx and ISDHSx thresholds are unaffected during temperature dependant current limit reduction.
9. No production test.
10. Latency time between overcurrent or overtemp shutdown to reactivation of output stage via ENA or DIS/SF.
11. Minimum latency between successive frames.
12. Minimum hold time after ENA H → L or DIS/SF L → H.
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7
NCV7729
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 5 V < VS < 28 V, 3 V < VCC < 5.5 V, EN = VCC, DIS/SF = GND, CBUF =
22 nF, unless otherwise specified) (Note 5)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
700
−
1400
mA
OPEN LOAD DIAGNOSTICS
Diagnostic Pulldown current
I(OUT2)
Diagnostic current tracking
I(OUT1) /
I(OUT2)
1.2
−
1.8
−
tddiag
40
−
110
ms
Open Load Detection Delay time
MICROCONTROLLER INTERFACE
V(VS) = 13.2 V,
V(OUT2) = 1.25 V
− DC CHARACTERISTICS
Digital Input Threshold
SI, SCLK, CSB, EN, DIS/SF, INx
VTHIN
−
30
−
70
−
%VCC
Input Hysteresis
VHYIN
2
−
10
%VCC
Input Pulldown Current EN
IPDEN
V(EN) = VCC
−
−
100
mA
Input Pullup Current
DIS/SF, INx
SI, SCLK, CSB
IPUx
V(pin) = 0 V
−200
−50
−125
−20
−
DIS/SF Output voltage
Output condition LOW
VSFL
Config.DIS/SF = 1, I(DIS/SF)
= 1 mA
−
−
0.4
V
SO − Output High
VSOH
I(SO) = −1 mA, VCC = 5.0 V
VCC −
0.5
−
−
V
SO − Output Low
VSOL
I(SO) = 1.6 mA
−
−
0.4
V
SO Tristate Leakage
ILSO
CSB = VCC
−10
−
10
mA
pF
MICROCONTROLLER INTERFACE
mA
− AC CHARACTERISTICS (VCC = 5 V)
Input Capacitance
SI, SCLK, CSB, EN, DIS/SF, INx
CINx
(Note 9)
−
−
20
SO Tristate Capacitance
CSO
(Note 9)
−
−
35
pF
−
−
5
MHz
200
−
−
ns
SCLK Frequency
SCLK Clock Period
SCLK High Time
Figure 4 #1
85
−
−
ns
SCLK Low Time
Figure 4 #2
85
−
−
ns
Figure 4 #3,4
85
−
−
ns
SI Setup Time
Figure 4 #11
50
−
−
ns
SI Hold Time
Figure 4 #12
50
−
−
ns
CSB Setup Time
Figure 4 #5,6
100
−
−
ns
CSB High Time
Figure 4 #7
200
−
−
ns
SCLK Setup Time
(Note 11)
SO Rise Time
Cload = 40 pF
−
−
25
ns
SO Fall Time
Cload = 40 pF
−
−
25
ns
5. Min/Max values are valid for the temperature range −40°C vTJ v 150°C unless noted otherwise. Min/Max values are guaranteed by
test, design or statistical correlation.
6. The load must be connected between OUT1 and OUT 2 to achieve the low−quiescent current standby mode.
7. VS must first exceed the VSPORon switch−on threshold for operation down to VSPORoff.
8. The ISDLSx and ISDHSx thresholds are unaffected during temperature dependant current limit reduction.
9. No production test.
10. Latency time between overcurrent or overtemp shutdown to reactivation of output stage via ENA or DIS/SF.
11. Minimum latency between successive frames.
12. Minimum hold time after ENA H → L or DIS/SF L → H.
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8
NCV7729
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 5 V < VS < 28 V, 3 V < VCC < 5.5 V, EN = VCC, DIS/SF = GND, CBUF =
22 nF, unless otherwise specified) (Note 5)
Characteristic
MICROCONTROLLER INTERFACE
Symbol
Conditions
Min
Typ
Max
Unit
Cload = 40 pF; (Note 9)
−
−
40
ns
Cload = 200 pF; (Note 9)
−
−
150
ns
2.0
−
−
ms
− AC CHARACTERISTICS (VCC = 5 V)
SO Valid time
Figure 4 #10
EN or DIS/SF Hold time
EN = L or DIS/SF = H
(Note 12)
5. Min/Max values are valid for the temperature range −40°C vTJ v 150°C unless noted otherwise. Min/Max values are guaranteed by
test, design or statistical correlation.
6. The load must be connected between OUT1 and OUT 2 to achieve the low−quiescent current standby mode.
7. VS must first exceed the VSPORon switch−on threshold for operation down to VSPORoff.
8. The ISDLSx and ISDHSx thresholds are unaffected during temperature dependant current limit reduction.
9. No production test.
10. Latency time between overcurrent or overtemp shutdown to reactivation of output stage via ENA or DIS/SF.
11. Minimum latency between successive frames.
12. Minimum hold time after ENA H → L or DIS/SF L → H.
4
7
CSB
5
6
SCLK
3
1
2
SI
12
SCLK
10
11
SO
Figure 4. SPI Timing Parameters
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9
NCV7729
DETAILED OPERATING DESCRIPTION
Bridge Control Inputs
(SPI command WR_Config), the functionality of DIS/SF
can be altered to operate as an open−drain status flag output.
The Config register can be accessed via the SPI port
independently of the setting at DIS/SF.
All control inputs provide internal pullup (IN1, IN2,
DIS/SF) or pulldown (EN) to ensure defined functionality in
case of open pin conditions. Bridge control logic is shown
in Figure 5 and Table 1 demonstrates all Operational
Modes.
The integrated switches can be controlled by input signals
(INx) as well as via the SPI Interface. Mode selection is
performed via the SPI configuration register. The device
provides two enable inputs: EN = active high and DIS/SF =
active low. Besides the two direct enable inputs EN and
DIS/SF, the device provides two SPI−controllable bits in the
configuration register (Config.ENx) to support a
low−quiescent current standby mode or advanced error
handling (e.g. channel deactivation).
The default setting for DIS/SF is to operate as an enable
input. By setting bit Config.SFMODE in the Config register
Table 1. H−BRIDGE OPERATIONAL MODES
DIS/SF
OUT
(Note 15)
EN
(Note 13)
DIS/SF IN
(Note 14)
IN1
(Note 16)
IN2
(Note 16)
OUT1
OUT2
Forward
H
L
H
L
H
L
H
Reverse
H
L
L
H
L
H
H
Free−wheeling low
H
L
L
L
L
L
H
Free−wheeling high
H
L
H
H
H
H
H
Disable via DIS/SF
(Note 14)
X
H
X
X
Z
Z
−
Disable via EN
L
X
X
X
Z
Z
EN disconnected
L
X
X
X
Z
Z
DIS/SF disconnected
X
H
X
X
Z
Z
IN1 disconnected
H
L
H
X
H
X
IN2 disconnected
H
L
X
H
X
H
Current limitation active
H
L
X
X
(Note 17)
(Note 17)
Under voltage (VS, CHP)
H
L
X
X
Z
Z
L
Overtemp shutdown
H
L
X
X
Z
Z
L
Overcurrent shutdown
H
L
X
X
Z
Z
L
VCC under/over voltage
X
X
X
X
Z
Z
H
SPI
see SPI diagnostic description
Operational Mode
L
L
X
H
H
H
13. EN pulled down by internal current IPDEN.
14. DIS/SF configured as enable input (Config.SFMODE = 0, default setting); pulled up by internal current IPUx.
15. DIS/SF configured as status flag output (Config.SFMODE= 1); pulled up by internal current IPUx or external resistor.
16. Device outputs enabled in Config Register (Config.EN1 = 1, Config.EN2 = 1, default setting); pulled up by internal current IPUx.
17. Affected output pulsing. See output protection description.
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NCV7729
VCC
VCC
SPI: Config.ENx
OUTxH
H = HS driver ON
DIS/SF
EN
OUTxL
INx
H = LS driver ON
RESET_DIAG
R
Q
R
VCC POR
S
OVERTEMP
OVERCURRENT
VS UNDERVOLTAGE
CHP UNDERVOLTAGE
SPI: Config.SFMODE
Figure 5. Bridge Control Logic
Bridge Outputs
If the overcurrent shutdown threshold ISD is exceeded for
t > tdfault during the blanking time tb (Figure 7), a
short−to−VS condition is detected and the device transitions
into the fault lockout state. All output transistors will be
latched off, the status flag will be set and latched
(Config.SFMODE = 1), and diagnostic register bits “Short
circuit to VS” will be latched to indicate the fault condition.
The H−Bridge output is built up by four N−channel power
DMOS devices (150 mW typ, 300 mW max @ 150°C). All
transistors are protected against overcurrent and
overtemperature conditions induced by short circuit
conditions to GND, VS, or across the load. Positive and
negative voltage transients that occur during switching
events of inductive loads are clamped by integrated
freewheeling diodes. An integrated regulated chargepump is
provided to drive the gates of the high−side DMOS
transistors.
High−side Overcurrent Shutdown
Both HS transistors are protected against shorted outputs
to GND by an individual overcurrent shutdown. The
high−side and low−side ISD overcurrent levels are designed
to track the programmed Ic level. If the overcurrent
shutdown threshold ISD is exceeded for t > tdfault
(Figure 7), a short−to−GND condition is detected and the
device transitions into the fault lockout state. All output
transistors will be latched off, the status flag will be set and
latched (Config.SFMODE = 1), and diagnostic register bits
“Short circuit to GND” will be latched to indicate the fault
condition.
Output Protection
To prevent device destruction in case of external fault
conditions (OUTx shorted to GND/VS or shorted load), all
four output stages provide overcurrent shutdown and
overtemperature shutdown functionality.
Low−side Current Limitation and Overcurrent
Shutdown
To minimize the power dissipation in case of current
limitation, a peak value control principle (Figure 6) is
integrated in each LS power stage. The current limitation
level Ic can be programmed by SPI (Config.OCx). The
high−side and low−side ISD overcurrent levels are designed
to track the programmed Ic level. When the current limit Ic
is exceeded for a time tb, the affected low side stage is
switched off, the corresponding high side stage is switched
on for a fixed time ta, and the diagnostic register bit “CLIM”
will be latched to indicate peak current limitation active. The
status flag (Config.SFMODE = 1) is not set in this case.
Shorted Load
In case of a shorted load, both active HS and LS stages
indicate an overcurrent condition. (LS: current limitation
level exceeded, HS: overcurrent shutdown threshold level
exceeded). All output transistors will be latched off, the
status flag will be set and latched (Config.SFMODE = 1),
and diagnostic register bits “Short circuit overload” will be
latched to indicate the fault condition.
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NCV7729
Iload
ISD
Ic
Overcurrent
shutdown level
(HS,LS – Tracks IC)
tb
ta
Current limitation level
(SPI programmable)
t
Output
enable
t
Figure 6. LS Peak Current Limitation
Iload
tdfault
ISD
Overcurrent shutdown
level
(HS,LS – Tracks IC)
tb
LS Current limitation level
Ic
(SPI programmable)
t
Output
enable
t
DIS/SF
(configured
as output)
t
Figure 7. Overcurrent Shutdown (HS & LS)
Overtemperature
region of operation is indicated by RD_Config register bits
“TH1”and “TH0”. THx bits are cleared by a rising edge on
EN while DIS/SF = 0 or a falling edge on DIS/SF while EN
= 1, or by reading the diagnostic register via the RD_Diag
command.
Whenever the programmed IC level is reduced in the
region between TLIM and TSD, the reduced IC level is
latched. The high−side and low−side ISD overcurrent levels
are unaffected during temperature dependant current limit
reduction. The originally programmed IC level is restored by
a rising edge on EN while DIS/SF = 0 or a falling edge on
DIS/SF while EN = 1, or by reading the diagnostic register
via the RD_Diag command.
The device is protected against excessive junction
temperatures by integrated temperature sensors. In case of
exceeding the overtemperature shutdown point TSD (175°C
min), all output transistors will be latched off, the status flag
will be set and latched (Config.SFMODE = 1), and
diagnostic register bit “OT” will be latched to indicate the
fault condition.
Temperature−Dependent Peak Current Reduction
When the junction temperature is between TLIM (165°C
typ.) and TSD, the programmed peak current is reduced as
shown in Figure 8. The diagnostic register bit “CRED” will
be latched to indicate peak current reduction active. The
status flag (Config.SFMODE = 1) is not set in this case. The
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NCV7729
TLIM
TSD
IC4
Re
st
Ar rict
ea ed
IC3
SPI programmable
preset value
Ic
(default)
IC2
IC1
TH1,TH0 = 1,1 (default)
= 1,0 = 0,1
= 0,0
Tj(°C)
Figure 8. Temperature−dependent Peak Current Reduction
Open Load Diagnostics
modes invoked via the enable inputs and the Config.ENx
register bits are detailed in Table 2.
Figure 9 shows the open load diagnostic scheme. The
diagnostic is performed by applying two different currents
to the outputs OUT1 and OUT2. The diagnostic result is
determined by a simple comparison of both pin voltages to
two separate reference voltages. The diagnostic results are
shown in Table 3.
While short to GND/VS or shorted load fault conditions
at the outputs will be detected in active mode, open load
detection is performed in off−mode. The open load
diagnostic is activated by disabling the NCV7729’s power
stages via the enable inputs EN and DIS/SF
(Config.SFMODE = 0). To allow a low−quiescent current
mode, the diagnostic function can be deactivated via the SPI
Config register (Config.ENx = 0). The device’s operating
VS
Internal Rail
SPI: Config .SFMODE
IOUT1
DIS/SF
EN
SPI: Config .EN1
Open Load
feedback signal
SPI: Config .EN2
OUT1
OUT2
Vth2
Vth1
IOUT2
GND
AGND
Figure 9. Open Load Detection
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NCV7729
Table 2. NCV7729 OPERATING MODES
EN
DIS/SF
Config.EN1
Config.EN2
Operating Mode
0
X
0
X
Standby
0
X
X
0
Standby
0
X
1
1
Open Load Diagnosis
X
1
1
1
Open Load Diagnosis
1
0
0
0
Standby
1
0
1
1
Normal Operation (Outputs active)
Table 3. OPEN LOAD DIAGNOSTICS RESULTS
Failure Mechanism
V(OUT1)
V(OUT2)
Load inserted
>Vth1
>Vth2
No fault
Open Load
>Vth1
<Vth2
Open load detected
OUT1: Short to GND AND Open Load
<Vth1
<Vth2
No Open load detected
OUT2: Short to GND AND Open Load
>Vth1
<Vth2
Open load detected
OUT1: Short to VS AND Open Load
>Vth1
<Vth2
Open load detected
OUT2: Short to VS AND Open Load
>Vth1
>Vth2
No Open load detected
Power Supplies
Diagnostic Result
and it is required to re−program the configuration register
unless default settings are used.
VS current can be reduced to a minimum in the
low−quiescent current standby mode by setting EN = L,
DIS/SF = H, and setting Config.EN[1,2] = 0,0. The load
must be connected between OUT1 and OUT2 to achieve the
low−quiescent current standby mode.
The device is powered by two supply voltages:
Battery voltage (analog and power stages supply
VS:
voltage)
VCC: Digital supply voltage
In order to provide the required gate−overdrive for the HS
power transistors, a boost supply voltage is generated by the
internal regulated chargepump. To ensure low−EMI
operation the chargepump power is regulated to the actual
drive current (deactivated in steady state operation). An
external buffering cap (CBUF in Figure 10) is used to provide
high peak currents required for fast output switching.
The chargepump output current capability is sized to
allow PWM operation up to 30 kHz. To optimize the
device’s EMI performance, the chargepump output power
can be reduced via SPI bit Config.CHPmode. In case of
low−power CHP mode, the maximum output PWM
frequency is limited to 4 kHz. Any current limitation event
automatically turns the chargepump into high power mode.
All three supply voltages (VS, VCC and CHP) are
monitored for undervoltage. In case of any undervoltage
event, the device’s output stages are turned into Hi−Z mode.
CHP and VS undervoltage events result in a non−latched
output lockout and the output stages are automatically
re−enabled after normal operating conditions are
re−established.
A VCC undervoltage event causes the device to transition
into fault lockout state (see Figure 11). VCC undervoltage is
handled as a latched lockout condition, requiring re−enable
of the device by appropriate transitions on the EN and
DIS/SF (Config.SFMODE = 0) enable inputs. Diagnostic
and status information is lost when VCC undervoltage occurs
C BUF
VS
Regulated
Chargepump
CHP
Supply for HS
output stages
Figure 10. Regulated Charge Pump
Power Supply Failure
In the event of a voltage regulator failure (e.g. Figure 2
“REG 2”), the NCV7729 is designed to allow up to 18 V at
the logic input/output pins (EN, DIS/SF, INx, CSB, SCLK,
SI, SO). However, if the voltage applied to the device’s VCC
pin (e.g. Figure 2 “REG 1”) exceeds VCCOV (VCC
overvoltage event) the output stages are turned into Hi−Z
mode and the VCC pin is internally disconnected.
A VCC overvoltage event causes the device to transition
into fault lockout state similar to VCC undervoltage. VCC
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NCV7729
All fault conditions (except VCC or loss of ground faults)
that lead to a fault lockout state are stored in the diagnostic
register in a latched manner. A fault lockout state also causes
the configuration register “LOCK” bit to be set
(RD_Config:b4 = 1). In the case of VS or CHP undervoltage
the configuration “LOCK” bit is not set and diagnostic
register data is not latched (see Note 18 on Page 20).
Diagnostic and configuration register data will persist
until the microcontroller performs an action to reset the
device or register. The device status can be read by accessing
the diagnostic register via the RD_Diag or WR_Config SPI
commands. The state of the “LOCK” bit can be accessed via
the RD_Config command.
The diagnostic register can be reset by:
• A read access to the register via SPI command
RD_Diag (reset occurs on the rising edge of CSB if
valid SPI frame)
• A rising edge on EN while DIS/SF = 0 or a falling edge
on DIS/SF while EN = 1
• VCC under/over voltage or loss of AGND or DGND
Accessing the diagnostic register via the WR_Config
command or disabling the outputs via the Config.ENx bits
does not reset the diagnostic register contents.
The configuration register “LOCK” bit can be reset by:
• A rising edge on EN while DIS/SF = 0 or a falling edge
on DIS/SF while EN = 1
• VCC under/over voltage or loss of AGND or DGND
At power−up, default diagnostic register content is b[7:0]
= 0xF0 and configuration register “LOCK” bit b4 = 1.
overvoltage is handled as a latched lockout condition,
requiring re−enable of the device by appropriate transitions
on the EN and DIS/SF (Config.SFMODE = 0) enable inputs.
Diagnostic and status information is lost when VCC
overvoltage occurs and it is required to re−program the
configuration register unless default settings are used.
Loss of Ground Failure
Loss of ground failure is detected when a difference in
potential (GDIF) between the AGND and DGND pins exists.
In the event of ground loss failure, the device transitions into
fault lockout state and the output stages are turned into Hi−Z
mode. Loss of ground is handled as a latched lockout
condition. Diagnostic and status information is lost when
loss of ground occurs.
Fault Handling
Fault handling states are shown in Figure 11. All
overcurrent and overtemperature events cause a latched
lockout of the output stages. VCC under/over voltage faults
or loss of AGND or DGND faults are handled as a latched
lockout condition, requiring re−enable of the device. The
device can be returned to normal operating mode by either
a rising edge on EN while DIS/SF = 0, or a falling edge on
DIS/SF while EN = 1. Undervoltage on VS or CHP result in
a non−latched lockout event (OUTx = Z until the supply
voltage returns into operating range).
In status flag mode (Config.SFMODE = 1), DIS/SF will
be set low when EN goes H→L and is reset when EN goes
L→H. The status flag is set and latched when a fault
condition is detected that causes transition to a latched
lockout state. In the case of VS or CHP undervoltage the
status flag is set, but is reset when the supply voltage returns
into operating range (see Table 1).
Power−up
Fault
Lockout
Device enable:
EN: L → H
DIS/SF: H → L
Output Fault Condition
(Shorted Load, Overcurrent,
Overtemp)
Normal
Operation
OUTx controlled by:
EN, DIS/SF, INx,
SPI:Config. ENx
V(VCC) < VCCPORon
OR
V(VCC) > VCCOV
OUTx = Z
DIS/SF = L
(if configured as output )
V(VCC) > VCCPORon
SPI Reset –
Default settings
VCCOV / VCCUV
Loss of AGND or
DGND
OUTx = Z
V(VS) > VSPORon
AND
V(CHP)−V(VS) > VCHPLY
VS / CHP
Undervoltage
V(VS) < VSPORoff
or
V(CHP)−V(VS) < VCHPLY
OUTx = Z
DIS/SF = L
(if configured as output )
Figure 11. Fault Handling State Diagram
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NCV7729
16−bit SPI Interface
MSB first. The device supports in−frame response to
minimize the amount of CPU overhead for communication.
The response data is transmitted within the same access
cycle immediately after decoding the ID and command bits.
Each SPI access is checked for consistency such that input
data written to internal registers (a write access is executed)
only when all of the following occur:
• Recognition of a valid chip ID
• A valid number of SCLK cycles (16)
• Recognition of a valid command
A transmission error is indicated by setting a flag bit (TF)
in the case of an invalid number of SCLK cycles or receipt
of an invalid command. The TF bit can be checked by the
microcontroller in the verification response following the
frame in which transmission error occurred. The TF bit is
reset after receipt of the next valid frame. Data stored in the
device’s configuration and diagnostic registers is unaffected
in the case of a transmission error.
The 4−wire SPI interface establishes a full duplex
synchronous serial communication link between the
NCV7729 and the application’s microcontroller. The
NCV7729 always operates in slave mode whereas the
controller provides the master function. The NCV7729 is
accessed by the SPI master by applying an active−low slave
select signal at CSB. SI is the data input, SO the data output.
The SPI master provides the clock to the NCV7729 via the
SCLK input. The data output SO is high impedance
(tri−state) when CSB is high.
The uppermost two bits of the SI data frame are used as a
chip ID to allow extended addressing. The chip ID is fixed
to 00 for the NCV7729. To avoid a bus conflict, the SO
output is held in tri−state until the ID bits have been
successfully received and decoded. If the ID does not match
the fixed NCV7729 ID, the entire frame is ignored and SO
remains tri−state. The extended addressing feature therefore
does not allow SPI daisy−chaining through the NCV7729.
SPI Frame Format
The general format of the NCV7729’s SPI frame is shown
in Figure 12. Both 16−bit input and 14−bit output data are
16−bit Write Access
CSB
SI
ID(2)
Command (6)
MSB
LSB MSB
Write Data (8)
LSB
ID=“00“
Verification (6)
Return Data (8)
MSB
LSB MSB
LSB
SO
16−bit Read Access
CSB
SI
ID(2)
Command (6)
MSB
LSB MSB
Don’t care (8)
LSB
ID=“00“
Verification (6)
Return Data (8)
MSB
LSB MSB
LSB
SO
Invalid Address Cycle
CSB
SI
ID(2)
Don’t care (n)
ID <>“00“
SO
Figure 12. General 16−bit SPI frame format.
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NCV7729
• The data received during a write access are written into
General SPI Timing
The general SPI timing shown in Figure 13 is defined as
follows for the NCV7729:
• The change at output SO is forced by the rising edge of
the SCLK signal if a valid chip ID is recognized;
otherwise SO remains tri−state
• The SI input signal is latched on the falling edge of the
SCLK signal
the internal registers at the rising edge of the CSB
signal only when all of the following occur:
♦ A valid chip ID is recognized
♦ Exactly 16 SCLK cycles were counted during CSB
= low
♦ A valid command is recognized
CSB
MSB
SCLK
SO
SI
1
LSB
2
B13
TRI−STATE
B15
4 −13
3
B14
B13
14
B12 −B3
B12 −B3
Figure 13. SPI Timing diagram
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15
B2
B2
16
B1
B1
B0
B0
NCV7729
REGISTER AND COMMAND STRUCTURE OVERVIEW
PROTOTYPE
IN
R/W
ID1
COMMAND
ID0
CD5
CD4
CD3
CD2
CD1
CD0
Data in [7:0]
Data out [7:0]
VERIFICATION
OUT
Z
Z
1
0
1
0
1
TF
BIT #
15
14
13
12
11
10
9
8
6
3
2
1
0
1
0
0
1
1
b0
EN2
OUT
Z
Z
1
0
1
0
1
TF
EN
OT
CRED
X
X
X
OC0
1
OC1
0
EN1
0
b1
CLIM
IN
RD_ID
4
Advanced Feature Control
CHP MODE
W
5
SF
MODE
WR_CONFIG
7
D21
D20
D11
D10
X
X
X
X
X
X
X
X
X
R
IN
0
0
0
0
0
0
0
0
OUT
Z
Z
1
0
1
0
1
TF
RD_REV
ID[7:0]
R
IN
0
0
0
0
0
0
1
1
OUT
Z
Z
1
0
1
0
1
TF
RD_CONFIG
X
X
X
X
SWR[3:0]
MSR[3:0]
R
0
1
0
1
0
0
0
X
X
X
X
X
X
X
X
OUT
Z
Z
1
0
1
0
1
TF
TH0
0
0
1
0
0
1
X
X
X
OUT
Z
Z
1
0
1
0
1
TF
EN
OT
X
X
X
X
X
X
X
X
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
1
0
1
TF
1
1
OUT
X
X
X
X
X
D21
D20
D11
D10
X
X
X
X
X
X
Z
Z
Z
Z
Z
X
X
X
X
X
X
1
1
1
1
1
1
R
INVALID ID
IN
OC0
0
OC1
0
LOCK
IN
RD_DIAG
TH1
CLIM
ENX
CRED
CHP MODE
0
SF
MODE
IN
−
< > “00”
Z
INVALID
CMD
Z
−
IN
0
0
OUT
Z
Z
UNDEFINED
1
0
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NCV7729
DETAILED COMMAND DESCRIPTION
WR_CONFIG
Type: W
Function: Programs the device configuration (valid SPI frame detected).
The WR_CONFIG returns the diagnostic register contents without resetting the register. The RD_DIAG command returns the
diagnostic register contents and resets all latched data in the register.
The WR_CONFIG register can only be changed when EN = 0.
Command Prototype:
0
0
1
1
0
0
1
1
EN2
EN1
OC1
OUT
Z
Z
1
0
1
0
1
TF
EN
OT
CLIM
D21
OC0
IN
CRED
Advanced Feature Control
CHP MODE
W
SF
MODE
WR_CONFIG
b1
b0
D20
D11
D10
Input Parameter Description:
Parameter
Description
b1
b0
X
X
OC1
OC0
OUTx LS Current Limit
1
1
IC4
1
0
IC3
0
1
IC2
0
0
EN1
Reserved
Future use
Default
IC1
OUT1 Control
0
Output 1 disabled
1
Output 1 enabled
EN2
0
1
CHPMODE
Default
OUT2 Control
Output 2 disabled
Output 2 enabled
Default
Charge pump Mode
0
Full power mode
1
Reduced power mode
SFMODE
Remarks
Default
DIS/SF Mode
0
DIS/SF configured as enable input
1
DIS/SF configured as status flag output
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Default
NCV7729
Output Parameter Description:
Parameter
D21
D20
Description
D11
OUT2 Status
D10
Priority encoded diagnostic data
Remarks
(Note 18)
OUT1 Status
1
1
0
0
Shorted Load
Data is latched
X
X
0
1
OUT1 short to VS
Data is latched
X
X
1
0
OUT1 short to GND
Data is latched
X
X
1
1
OUT1 Normal
0
0
1
1
Open Load
Data is latched
0
1
X
X
OUT2 Short to VS
Data is latched
1
0
X
X
OUT2 Short to GND
Data is latched
1
1
X
X
OUT2 Normal
0
0
0
0
CLIM
VCC Power−on Reset
VS or CHP Undervoltage
OUTx LS Current > ICx
1
Normal Operation
TJ > TLIM
1
Normal Operation
Data is latched
−
Data is latched
−
Overtemperature
0
TJ > TSD
1
Normal operation
EN
Data is not latched
OUTx LS Current Limit Reduction
0
OT
−
Data is latched
OUTx LS Current Limit
0
CRED
−
Enable Status
Data is latched
−
(Note 19)
0
Outputs disabled
Data is not latched
1
Outputs enabled
−
TF
Transmission Error Flag
0
Previous SPI Frame Valid
1
Transmission Error Detected
b[13:9]
Verification = “1 0 1 0 1”
−
Data is latched
Hard−coded
18. The D[21:20] and D[11:10] diagnostic data are stored according to the following priority scheme:
Priority 1 (highest): VS or CHP undervoltage
Priority 2: Shorted load
Priority 3: Short to GND or VS
Priority 4: Open load
Lower priority faults are overwritten by higher priority faults in the case of multiple faults. In the case of VS or CHP undervoltage, overwritten
fault data are restored after VS or CHP returns into normal operating range. Overwritten fault data can be retrieved via the WR_CONFIG
command. Resetting the diagnostic register via the enable inputs or the RD_DIAG command resets all latched data and overwritten fault
data cannot be retrieved. At VCC power−on reset D[21:10] = 0000.
19. The EN bit reflects the enabled/disabled state of the outputs based on the state of the EN or DIS/SF input pins or the state of the WR_CONFIG
bits EN1or EN2.
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NCV7729
RD_ID
Type: R
Function: Returns the hard−coded device identification (ID).
Command Prototype:
RD_ID
R
IN
0
0
0
0
0
0
0
0
OUT
Z
Z
1
0
1
0
1
TF
X
X
X
X
X
X
X
X
ID[7:0]
Input parameter description:
n/a
Output Parameter Description:
Parameter
ID[7:0]
TF
Description
ID = “1 0 1 0 0 0 1 0”
Hard−coded
Transmission Error Flag
0
Previous SPI Frame Valid
1
Transmission Error Detected
b[13:9]
Remarks
−
Data is latched
Verification = “1 0 1 0 1”
Hard−coded
RD_REV
Type: R
Function: Returns the hard−coded device revision counters.
Command Prototype:
RD_REV
R
IN
0
0
0
0
0
0
1
1
OUT
Z
Z
1
0
1
0
1
TF
X
X
X
X
SWR[3:0]
n/a
Output Parameter Description:
Description
Remarks
MSR[3:0]
MSR = “0 0 0 1”
Hard−coded
SWR[3:0]
SWR = “0 0 0 0”
Hard−coded
TF
0
1
b[13:9]
Transmission Error Flag
Previous SPI Frame Valid
−
Transmission Error Detected
Data is latched
Verification = “1 0 1 0 1”
Hard−coded
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X
X
MSR[3:0]
Input Parameter Description:
Parameter
X
X
NCV7729
RD_CONFIG
Type: R
Function: Returns the device configuration parameters.
Command Prototype:
IN
0
0
1
0
1
0
0
0
X
X
X
X
X
X
X
X
OUT
Z
Z
1
0
1
0
1
TF
CHP MODE
ENX
LOCK
OC1
OC0
R
SF
MODE
RD_CONFIG
TH1
TH0
Input Parameter Description:
n/a
Output Parameter Description:
Parameter
Description
TH1
TH0
1
1
TJ < TLIM
1
0
TLIM < TJ < TSD
0
1
TLIM < TJ < TSD
0
0
TJ > TSD
OC1
OC0
1
1
IC4
1
0
IC3
0
1
IC2
0
0
LOCK
State of Temperature−Dependent Current Limit
See Figure 8
OUTx LS Current Limit via WR_CONFIG OCx
Default
IC1
Fault Lockout
Data is latched
Outputs enabled
1
Output disabled
Default
Output Control via WR_CONFIG ENx
0
OUTx disabled
1
OUT1 AND OUT2 enabled
CHPMODE
Full power mode
1
Reduced power mode
DIS/SF Mode
DIS/SF configured as enable input
1
DIS/SF configured as status flag output
Default
Transmission Error Flag
0
Previous SPI Frame Valid
1
Transmission Error Detected
b[13:9]
Default
Default
0
TF
(Note 20)
Charge pump Mode
0
SFMODE
Data is latched
Default
0
ENX
Remarks
Verification = “1 0 1 0 1”
−
Data is latched
Hard−coded
20. The ENX bit reflects the enabled/disabled state of the outputs based on the state of the WR_CONFIG bits EN1or EN2.
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NCV7729
RD_DIAG
Type: R
Function: Returns the diagnostic register contents and resets the register (valid SPI frame detected).
The RD_DIAG command returns the diagnostic register contents and resets all latched data in the register. The WR_CONFIG
command can be used to return the diagnostic register contents without resetting the register.
Command Prototype:
IN
0
0
0
0
1
0
0
1
X
X
X
X
X
X
X
X
OUT
Z
Z
1
0
1
0
1
TF
EN
OT
CLIM
R
CRED
RD_DIAG
D21
D20
D11
D10
Input Parameter Description:
n/a
Output Parameter Description:
Parameter
D21
D20
Description
D11
OUT2 Status
D10
Priority encoded diagnostic data
Remarks
(Note 18)
OUT1 Status
1
1
0
0
Shorted Load
Data is latched
X
X
0
1
OUT1 short to VS
Data is latched
X
X
1
0
OUT1 short to GND
Data is latched
X
X
1
1
OUT1 Normal
0
0
1
1
Open Load
Data is latched
0
1
X
X
OUT2 Short to VS
Data is latched
1
0
X
X
OUT2 Short to GND
Data is latched
1
1
X
X
OUT2 Normal
0
CLIM
0
0
0
VCC Power−on Reset
VS or CHP Undervoltage
OUTx LS Current > ICx
1
Normal Operation
TJ > TLIM
1
Normal Operation
Data is latched
−
Data is latched
−
Overtemperature
0
TJ > TSD
1
Normal operation
EN
Data is not latched
OUTx LS Current Limit Reduction
0
OT
−
Data is latched
OUTx LS Current Limit
0
CRED
−
Enable Status
Data is latched
−
Note 18
0
Outputs disabled
Data is not latched
1
Outputs enabled
−
TF
Transmission Error Flag
0
Previous SPI Frame Valid
1
Transmission Error Detected
b[13:9]
Verification = “1 0 1 0 1”
http://onsemi.com
23
−
Data is latched
Hard−coded
NCV7729
R(t) (°C/W)
100
50% Duty Cycle
20%
10%
10
5%
2%
1%
1
0.1
Single Pulse
Max Psi BA
0.01
0.001
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
1
10
100
1000
100
1000
Figure 14. Transient Thermal Performance on 100 mm2 2 oz. Heat Spreader
100
R(t) (°C/W)
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
Single Pulse
Max Psi BA
0.01
0.001
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
1
10
Figure 15. Transient Thermal Performance on 600 mm2 2 oz. Heat Spreader
120
50 mm2
100
100 mm2
qJA (°C/W)
80
150 mm2
60
200 mm2
300 mm2
40
500 mm2
20
0
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
TIME (sec)
Figure 16. Transient Thermal Performance on Various 2 oz. Heat Spreaders
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24
100
1000
NCV7729
PACKAGE DIMENSIONS
PSOP−20
CASE 525AB−01
ISSUE A
b
(DATUM PLANE A)
2X 10 TIPS
0.20 C B
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
B
20
11
c1 c
6
SECTION A−A
4
E1
E
4X
5
C
0.10 C
PIN 1
IDENT AREA
h
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM PLANE H IS LOCATED AT THE BOTTOM
OF THE LEAD AND IS COINCIDENT WITH THE
LEAD WHERE IT EXITS THE BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15 PER
SIDE. D IS DETERMINED AT DATUM H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH PROTRUSION. INTERLEAD FLASH
PROTRUSION SHALL NOT EXCEED 0.15 PER
SIDE. E1 IS DETERMINED AT DATUM H.
6. A VISUAL IDENTIFIER IS LOCATED WITHIN THE
CROSS-HATCHED AREA.
7. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 AND
0.25mm FROM THE TIP.
8. SEATING PLANE IS DEFINED BY THE LEAD TIPS
ONLY.
9. DIMENSION D DOES NOT INCLUDE TIEBAR
PROTRUSIONS. TIEBAR PROTRUSIONS SHALL
NOT EXCEED 0.15 PER SIDE.
10. DATUMS A AND B TO BE DETERMINED AT
DATUM H.
b1
1
10
X 45 _
D2
e/2
A2
9
2X
10
A3
0.10 C
7
A1
DETAIL B
D
A
3
8
9
E2
DETAIL B
H
A
e
b
0.25
DETAIL A
2X
SEATING
PLANE
7
20X
M
C A B
L1
D1
GAUGE
PLANE
A
A
L
q
DETAIL A
E4
E3
MOUNTING FOOTPRINT*
14.66
20X
2.90
1.33
BOTTOM VIEW
DIM
A
A1
A2
A3
b
b1
c
c1
D
D1
D2
e
E
E1
E2
E3
E4
h
L
L1
q
1
12.60
20X
1.27
PITCH
0.62
16.06
7.20
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
25
MILLIMETERS
MIN
MAX
3.00
3.40
0.10
0.30
2.90
3.10
0.00
0.10
0.40
0.52
0.40
0.49
0.23
0.32
0.23
0.28
15.90 BSC
11.70
12.60
0.90
1.10
1.27 BSC
13.95
14.45
11.00 BSC
2.50
2.70
6.40
7.20
2.70
2.90
--1.10
0.84
1.10
0.35 BSC
0_
8_
NCV7729
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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26
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NCV7729/D