TI SN761646RHBR

SN761646
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SLES251 – NOVEMBER 2009
DIGITAL TV TUNER IC
Check for Samples: SN761646
FEATURES
1
VHI RFIN
UHF RFIN2
UHF RFIN1
GPP2
VHI OSC B
24
RF GND
UHF OSC B2
2
23
MIXOUT2
OSC GND
3
22
MIXOUT1
CP
4
21
IF IN
VTU
5
20
RFAGC OUT
IF GND
6
19
SDA
IF OUT
7
18
SCL
VCC
8
17
GPP1
XTAL2
XTAL1
IFGCA CTRL
10 11 12 13 14 15 16
IFGCA OUT1
9
IFGCA OUT2
Digital TVs
Digital CATVs
Set-Top Boxes
1
IFGCA GND
•
•
•
UHF OSC C2
IFGCA IN2
APPLICATIONS
32 31 30 29 28 27 26 25
IFGCA IN1
•
•
•
•
VHI OSC C
•
RHB PACKAGE
(TOP VIEW)
UHF OSC B1
•
Integrated Mixer/Oscillator/PLL and IF GCA
VHF-H, UHF 2-Band Local Oscillator
I2C Bus Protocol (Fixed Address)
30-V Tuning Voltage Output
Two General Purpose Ports
Selectable Wide/Narrow Band RF AGC
Detector
Crystal Oscillator 4 MHz/8 MHz/16 MHz
Support
Programmable Reference Divider Ratio
(24/28/48/56/64/96/128)
IF GCA Enable/Disable Control
Standby Mode
5-V Power Supply
32-Pin Quad Flatpack No Lead (QFN) Package
UHF OSC C1
•
•
•
•
•
•
DESCRIPTION
The SN761646 is a low-phase-noise synthesized tuner IC designed for digital TV tuning systems. The circuit
consists of a PLL synthesizer, two-band local oscillator and mixer, RF AGC detector circuit and IF gain controlled
amplifier, and is available in a small outline package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN761646
SLES251 – NOVEMBER 2009
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FUNCTIONAL BLOCK DIAGRAM
IF IN
MIX OUT1
MIX OUT2
UHF OSC B2
UHF OSC C2
UHF OSC C1
UHF OSC B1
VHI OSC C
VHI OSC B
OSC GND
IF AMP
VHF-H
OSC
UHF
OSC
IF OUT
IF GND
VHF-H
MIXER
VHI RF IN
UHF
MIXER
RF AGC OUT
RF AGC
DETECT
UHF RF IN1
UHF RF IN2
RF GND
PROGRAMMABLE
DIVIDER
CP
VTU
XTAL1
XTAL2
4MHz/8MHz
XTALOSC
24/28/48/56/
64/96/128DIV
PHASE
DETECTOR
CHARGE
PUMP
OP
AMP
VCC
SCL
SDA
I2C BUS
INTERFACE
GENERAL PURPOSE
PORT
IF GCAOUT1
IF
GCA
50k
IF GCAOUT2
IF GCA GND
50k
100k
IF GCA CTRL
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IF GCA IN2
IF GCA IN1
GPP1
GPP2
2
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TERMINAL FUNCTIONS
Table 1.
TERMINAL
NAME
DESCRIPTION
NO.
SCHEMATIC
CP
4
Charge-pump output
Figure 1
GPP1
17
General purpose port output 1 (open collector type)
Figure 2
GPP2
28
General purpose port output 2 (emitter follower type)
Figure 3
IFGCA CTRL
14
IF GCA control voltage input
Figure 4
IFGCA GND
11
IF GCA ground
IFGCA IN1
9
IF GCA input
Figure 5
IFGCA IN2
10
IF GCA input
Figure 5
IFGCA OUT1
13
IF GCA output
Figure 6
IFGCA OUT2
12
IF GCA output
Figure 6
IF GND
6
IF ground
IF IN
21
IF amplifier input
Figure 7
IF OUT
7
IF amplifier output
Figure 8
MIXOUT1
22
Mixer output 1
Figure 9
MIXOUT2
23
Mixer output 2
Figure 9
OSC GND
3
Oscillator ground
RF AGC OUT
20
RF AGC output
RF GND
24
Mixer ground
SCL
18
Serial clock input
Figure 11
SDA
19
Serial data input/output
Figure 12
UHF OSC B1
31
UHF oscillator base 1
Figure 13
UHF OSC B2
2
UHF oscillator base 2
Figure 13
UHF OSC C1
32
UHF oscillator collector 1
Figure 13
UHF OSC C2
1
UHF oscillator collector 2
Figure 13
UHF RF IN1
27
UHF RF input 1
Figure 14
UHF RF IN2
26
UHF RF input 2
Figure 14
VCC
8
Supply voltage
VHI OSC B
29
VHF-H oscillator base
Figure 15
VHI OSC C
30
VHF-H oscillator collector
Figure 15
VHI RF IN
25
VHF-H RF input
Figure 16
VTU
5
Tuning voltage amplifier output
Figure 17
XTAL1
15
Crystal oscillator
Figure 18
XTAL2
16
Crystal oscillator
Figure 18
Figure 10
50k
10
25
17
4
25
Figure 1. CP
Figure 2. GPP1
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1k
14
100k
10
28
50k
Figure 3. GPP2
Figure 4. IF GCA CTRL
Vbais
1k
1k
9
10
15
13
12
Figure 5. . IF GCA IN1 and IF GCA IN2
Figure 6. IF GCA OUT1 and IF GCA OUT2
2k
10
A
7
25
1k
25
1k
21
1k
Figure 7. IF IN
25
Figure 8. IF OUT
23
25
22
A
20
Figure 9. MIXOUT1 and MIXOUT2
Figure 10. RF AGC OUT
25
1k
19
1k
18
Figure 11. SCL
4
Figure 12. SDA
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26
1
27
32
3k
20
3k
20
2
31
8k
8k
Figure 13. UHF OSC B1, UHF OSC B2, UHF OSC
C1, and UHF OSC C2
Figure 14. UHF RF IN1 and UHF RF IN2
30
25
40
3k
29
3k
8k
8k
Figure 15. VHI OSC B and VHI OSC C
Figure 16. VHI RF IN
5
16
15
10
20
50k
Figure 17. VTU
Figure 18. XTAL1 and XTAL2
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ABSOLUTE MAXIMUM RATINGS (1)
(2)
over recommended operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VCC
Supply voltage range
(3)
VCC
–0.4 to 6.5
V
VGND
Input voltage range 1
(3)
RF GND, OSC GND
–0.4 to 0.4
V
VVTU
Input voltage range 2
(3)
VTU
–0.4 to 35
V
VIN
Input voltage range 3
(3)
Other pins
–0.4 to 6.5
V
TA
Operating free-air temperature range
–20 to 85
°C
θJA
Package thermal impedance (4)
32.4
°C/W
Tstg
Storage temperature range
–65 to 150
°C
TJ
Maximum junction temperature
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Overshoot or undershoot of input voltage beyond absolute maximum rating may induce failure. Latch up performance exceeds
+/-100mA per JESD78, except for GPP1 (pin 17).
Voltage values are with respect to the IF GND of the circuit.
The package thermal impedance is calculated in accordance with JESD 51-5 (High-K).
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
4.5
5
5.5
V
30
33
V
GPP1
–5
mA
GPP2
10
mA
85
°C
VCC
Supply voltage
VCC
VVTU
Tuning supply voltage
VTU
IGPP1
Output current of general purpose port 1
IGPP2
Output current of general purpose port 2
TA
Operating free-air temperature
–20
UNIT
xxx
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures
can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated
circuits may be more susceptible to damage because very small parametric changes could cause the device not
to meet its published specifications.
IF IN, MIXOUT1, and MIXOUT2 (pins 21–23) withstand 1.5 kV; all other pins withstand 2 kV, according to the
Human-Body Model (1.5 kΩ, 100 pF).
6
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ELECTRICAL CHARACTERISTICS
Total Device and Serial Interface
VCC = 4.5 V to 5.5 V, TA = –20°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
Supply current 1
BS[2:1] = 10, IGPP1,2 = 0 mA, IFGCA
disabled
80
mA
ICC2
Supply current 2
BS[2:1] = 10, IGPP1,2 = 0 mA, IFGCA
enabled
110
mA
ICC-STBY
Standby supply current
BS[2:1] = 11
VIH
High-level input voltage (SCL, SDA)
VIL
Low-level input voltage (SCL, SDA)
IIH
High-level input current (SCL, SDA)
IIL
Low-level input current (SCL, SDA)
–10
VPOR
Power-on-reset supply voltage (threshold of supply
voltage between reset and operation mode)
2.1
8
14
2.3
mA
V
1.05
V
10
μA
μA
2.8
3.5
V
I2C Interface
VOL
Low-level output voltage (SDA)
VCC = 5 V, IOL = 3 mA
0.4
V
lSDAH
High-level output leakage current (SDA)
VSDA = 5.5 V
10
μA
fSCL
Clock frequency (SCL)
400
kHz
tHD-DAT
Data hold time
0.9
μs
tBUF
Bus free time
1.3
μs
tHD-STA
Start hold time
0.6
μs
tLOW
SCL-low hold time
1.3
μs
tHIGH
SCL-high hold time
0.6
μs
tSU-STA
Start setup time
0.6
μs
tSU-DAT
Data setup time
0.1
tr
Rise time (SCL, SDA )
0.3
μs
tf
Fall time (SCL, SDA)
0.3
μs
tSU-STO
Stop setup time
100
See Figure 19
0
μs
0.6
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PLL and General Purpose Port
VCC = 4.5 V to 5.5 V, TA = –20°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
N
Divider ratio
15-bit frequency word
fXTAL
Crystal oscillator frequency
See Figure 21
ZXTAL
Crystal oscillator input impedance
8 MHz, VCC = 5 V, TA = 25°C
VVTUL
Tuning amplifier low-level output voltage
RL = 22 kΩ, VTU = 30 V
IVTUOFF
Tuning amplifier leakage current
Tuning amplifier = off, VTU = 30 V
ICP11
ICP10
ICP01
Charge-pump current
ICP00
ICP100
MIN
MAX
4
16
1.5
0.2
0.45
0.6
V
10
μA
600
750
CP[2:0] = 010
250
350
450
CP[2:0] = 001
100
140
200
CP[2:0] = 000
35
70
95
900
1200
CP[2:0] = 100, Mode = 1
PLL locked
ICPOFF
Charge-pump leakage current
VCP = 2 V, TA = 25°C
IGPP1
General purpose port 1 (GPP1) output
current
VGPP1ON
General purpose port 1 (GPP1) output ON
voltage
IGPP2
General purpose port 2 (GPP2) output
current
650
1.95
–15
IGPP1 = –2 mA, VCC = 5 V, TA = 25°C
IGPP2 = 10 mA
2.9
IGPP2 = 10 mA, VCC = 5 V, TA = 25°C
3.4
VGPP22
General purpose port 2 (GPP2) output
voltage
IGPP2OFF
General purpose port 2 (GPP2) OFF leakage
VGPP2 = 0 V
current
MHz
kΩ
450
Charge-pump output voltage
UNIT
32767
CP[2:0] = 011
VCP
VGPP21
TYP
512
μA
V
15
nA
–5
mA
0.6
V
10
mA
V
3.6
8
μA
RF AGC
VCC = 5 V, TA = 25°C, measured in Figure 20 reference measurement circuit at 50-Ω system, IF = 44 MHz,
IF filter characteristics: fpeak = 44 MHz (unless otherwise noted)
PARAMETER
IOAGC0
TEST CONDITIONS
RF AGC output source current
IOAGC1
MIN
TYP
300
nA
ATC = 1
9
μA
RF AGC peak sink current
ATC = 0
VOAGCH
RFAGCOUT output high voltage (max level)
ATC = 1
VOAGCL
RFAGCOUT output low voltage (min level)
4.0
ATC = 1
0.3
ATP[2:0] = 000, ATC=0, AISL=0
114
VAGCSP01
ATP[2:0] = 001, ATC=0, AISL=0
112
ATP[2:0] = 010, ATC=0, AISL=0
110
ATP[2:0] = 011, ATC=0, AISL=0
108
VAGCSP04
ATP[2:0] = 100, ATC=0, AISL=0
106
VAGCSP05
ATP[2:0] = 101, ATC=0, AISL=0
104
VAGCSP06
ATP[2:0] = 110, ATC=0, AISL=0
102
8
Start-point IF output level
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μA
100
3.5
VAGCSP00
VAGCSP03
UNIT
ATC = 0
IOAGCSINK
VAGCSP02
MAX
4.5
V
V
dBμV
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Mixer, Oscillator, IF Amplifier (DIF OUT)
VCC = 5 V, TA = 25°C, measured in Figure 20 reference measurement circuit at 50-Ω system, IF = 44 MHz,
IF filter characteristics: fpeak = 44 MHz (unless otherwise noted)
PARAMETER
GC4D
GC6D
GC7D
GC9D
NF4D
NF6D
NF7D
NF9D
CM4D
CM6D
CM7D
CM9D
VIFO4D
VIFO6D
VIFO7D
VIFO9D
ΦPLVL4D
ΦPLVL6D
ΦPLVL7D
ΦPLVL9D
(1)
(2)
(3)
(4)
TEST CONDITIONS
Conversion gain (mixer-IF amplifier), VHF-HIGH
Conversion gain (mixer-IF amplifier), UHF
Noise figure, VHF-HIGH
Noise figure, UHF
Input voltage causing 1% cross-modulation distortion,
VHF-HIGH
Input voltage causing 1% cross-modulation distortion, UHF
IF output voltage, VHF-HIGH
IF output voltage, UHF
Phase noise, VHF-HIGH
Phase noise, UHF
TYP
(1)
29
fin = 467 MHz (1)
29
fin = 473 MHz (1)
29
fin = 864 MHz (1)
29
fin = 177 MHz
fin = 177 MHz
9
fin = 467 MHz
10
fin = 473 MHz
10
fin = 864 MHz
12
fin = 177 MHz (2)
79
fin = 467 MHz (2)
79
fin = 473 MHz (2)
77
fin = 864 MHz (2)
77
fin = 177 MHz
117
fin = 467 MHz
117
fin = 473 MHz
117
fin = 864 MHz
117
fin = 177 MHz (3)
–85
(4)
–77
fin = 473 MHz (3)
–80
fin = 864 MHz (4)
–77
fin = 467 MHz
UNIT
dB
dB
dB
dB
dBμV
dBμV
dBμV
dBμV
dBc/Hz
dBc/Hz
IF = 44 MHz, RF input level = 70 dBμV
fundes = fdes ±6 MHz, Pin = 70 dBμV, AM 1 kHz, 30%, DES/CM = S/I = 46 dB
Offset = 1 kHz, CP current = 350 μA, reference divider = 128, crystal = 8 MHz
Offset = 1 kHz, CP current = 900 μA, reference divider = 128, crystal = 8 MHz
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IF Gain Controlled Amplifier
VCC = 5 V, TA = 25°C, measured in Figure 20 reference measurement circuit at 50-Ω system, IF = 45.75 MHz,
IF filter characteristics: fpeak = 44 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
IIFGCA
Input current (IF GCA CTRL)
VIFGCA = 3 V
60
µA
VIFGCAMAX
Maximum gain control voltage
Gain Maximum
3
VCC
V
VIFGCAMIN
Minimum gain control voltage
Gain Minimum
0
0.2
GIFGCAMAX
Maximum gain
VIFGCA = 3 V
65
dB
GIFGCAMIN
Minimum gain
VIFGCA = 0 V
–1
dB
GCRIFGCA
Gain control range
VIFGCA = 0 V to 3 V
66
dB
VIFGCAOUT
Output voltage
Single-ended output, VIFGCA = 3
V
2.1
Vp-p
NFIFGCA
Noise figure
VIFGCA=3V
11
dB
Third order intermodulation distortion
fIFGCAIN1 = 43 MHz,
fIFGCAIIN2 = 44 MHz,
VIFGCAOUT = –2 dBm,
VIFGCA = 3 V
–50
dBc
IIP3IFGCA
Input intercept point
VIFGCA = 0 V
11
dBm
RIFGCAIN
Input resistance (IF GCA IN1, IF GCA
IN2)
1
kΩ
RIFGCAOUT
Output resistance (IF GCA OUT1, IF
GCA OUT2)
25
Ω
IM3IFGCA
10
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30
MAX
V
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FUNCTIONAL DESCRIPTION
I2C Bus Mode
I2C Write Mode (R/W = 0)
Table 2. Write Data Format
MSB
LSB
Address byte (ADB)
1
1
0
0
0
0
0
R/W = 0
A (1)
Divider byte 1 (DB1)
0
N14
N13
N12
N11
N10
N9
N8
A (1)
Divider byte 2 (DB2)
N7
N6
N5
N4
N3
N2
N1
N0
A (1)
Control byte 1 (CB1)
1
0
ATP2
ATP1
ATP0
RS2
RS1
RS0
A (1)
CP1
CP0
AISL
0
GPP2
GPP1
BS2
BS1
A (1)
1
1
ATC
MODE
T3/DISGCA
T2
T1/CP2
T0
A (1)
Band switch byte (BB)
Control byte 2 (CB2)
(1)
A : acknowledge
Table 3. Write Data Symbol Description
SYMBOL
ADB
DESCRIPTION
DEFAULT
Address byte (Write mode)
ADB[7:0]=11000000
N[14:0]
Programmable counter set bits
N14 = N13 = N12 = ... = N0 = 0
N = N14 × 214 + N13 × 213 + ... + N1 × 2 + N0
ATP[2:0]
RF AGC start-point control bits (see Table 4)
ATP[2:0] = 000
RS[2:0]
Reference divider ratio-selection bits (see Table 5)
RS[2:0] = 000
CP[1:0]
Charge-pump current-set bit (see Table 6)
CP[1:0] = 00
AISL
RF AGC detector input selection bit
AISL = 0
AISL = 0: IF amplifier
AISL = 1: Mixer output
GPP[2:1]
General purpose port output control bit
GPP[2:1]=00
GPPn = 0: Output transistor = OFF
GPPn = 1: Output transistor = ON
BS[4:1]
ATC
Band selection bits
BS2
BS1
0
1
0
1
1
0
0
1
BS[2:1]=00
Not allowed
VHF-HI
UHF
Standby mode/stop MOP function
RF AGC current-set bit
ATC = 0
ATC = 0: Current = 300 nA
ATC = 1: Current = 9 μA
Mode
T3/DISGCA
T2
T1/CP2
T0
Mode = 0:
IF GCA enabled
T3/DISGCA, T2, T1/CP2, T0 are test bits (see Table 7)
Mode = 1:
T3/DISGCA =0 : IF GCA enabled
T3/DISGCA =1 : IF GCA disabled
T1/CP2 : Icp control bit, See Table 6
MODE = 0
T[3:0] = 0000
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Table 4. RF AGC Start Point
ATP2
ATP1
ATP0
IFOUT LEVEL (dBμV)
0
0
0
114
0
0
1
112
0
1
0
110
0
1
1
108
1
0
0
106
1
0
1
104
1
1
0
102
1
1
1
Disabled (Hi-Z)
Table 5. Reference Divider Ratio
RS2
RS1
RS0
REFERENCE DIVIDER RATIO
0
0
0
24
0
0
1
28
0
1
0
48
0
1
1
56
1
0
0
64
1
0
1
96
1
1
0
128
1
1
1
Reserved
Table 6. Charge-Pump Current
CP2
CP1
CP0
X
0
0
0
70
X
0
0
1
140
X
0
1
0
350
X
0
1
1
600
1
1
0
0
900
Table 7. Test Bits
(1)
CHARGE PUMP CURRENT
(μA)
MODE
(1)
MODE
T3/DISGCA
T2
T1/CP2
T0
DEVICE OPERATION
0
0
0
0
X
Normal operation
1
X
X
X
X
Normal operation
0
X
1
X
X
Test mode
0
1
X
X
X
Test mode
RFAGC is not available in test mode.
I2C Read Mode (R/W = 1)
Table 8. Read Data Format
MSB
Address byte (ADB)
Status byte (SB)
(1)
12
LSB
1
1
0
0
0
0
0
R/W = 1
A (1)
POR
FL
1
1
1
1
1
1
–
A : acknowledge
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Table 9. Read Data Symbol Description
SYMBOL
DESCRIPTION
ADB
Address byte (Read mode)
POR
Power-on-reset flag
DEFAULT
ADB[7:0] = 11000001
POR = 1
POR set: power on
POR reset: end-of-data transmission procedure
FL (1)
In-lock flag
PLL locked (FL = 1), unlocked (FL = 0)
(1)
Lock detector works by using phase error pulse at the phase detector. Lock flag (FL) is set or reset according to this pulse width
disciminator. Hence unstableness of PLL may cause the lock detect circuit to malfunction. In order to stable PLL, it is required to
evaluate application circuit in various condition of loop-gain (loo-p filter, CP current), and to verify with whole conditions of actual
application
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Example I2C Data Write Sequences
Telegram examples:
Start - ADB - DB1
Start - ADB - DB1
Start - ADB - CB1
Start - ADB - CB1
Start - ADB - CB2
-
DB2 - CB1 – BB - CB2 - Stop
DB2 - Stop
BB - CB2 - Stop
BB - Stop
Stop
Abbreviations:
ADB: Address byte
BB: Bandswitch byte
CB1: Control byte 1
CB2: Control byte 2
DB1: Divider byte 1
DB2: Divider byte 2
Start: Start condition
Stop: Stop condition
t HD-STA
t SU-STA
t HIGH
tF
SCL
t SU-DAT
t LOW
t SU-STO
tR
SDA
t HD-DAT
t BUF
Figure 19. I2C Timing Chart
14
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APPLICATION INFORMATION
R4
VC2
C10
VC1
C1
R1
GPP2
R5
C33
L1
C2
C3
C31
C7
R7
UHF OSC C2
27
26
25
VHI RF IN
C13
1
28
UHF RF IN2
C6
C8
29
UHF RF IN1
L3
30
GPP2
C9
R6
31
VHI OSC B
32
C5
VHI OCS C
R2
UHF OSC B1
VC3
UHF OSC C1
C4
L2
UHF IN1
R27
C32
VHI IN
R26
Vcc
RF GND
R25
24
L6
R3
R9
2 UHF OSC B2
MIX OUT2 23
3 OSC GND
MIX OUT1 22
R24
(See Note A)
R8
C14
L7
L10
C30
L8
C11
R10
L9
C29
4 CP
IF IN 21
C28
C12
5 VTU
VTU
RF AGC OUT 20
C26
C27
RFAGCOUT
R28
C15
6 IF GND
SDA 19
7 IF OUT
SCL
R11
C16
C17
IF GCA OUT2
IF GCA OUT1
IF GCA CTRL
XTAL1
XTAL2
R15
IFGCA IN1
IF GCA GND
8 VCC
IF GCA IN2
Vcc
9
10
11
12
13
14
15
16
18
SCL
C35
GPP1 17
C19
SDA
C34
R29
IF GCA IN1
IF OUT
R31
Vcc
GPP1
X1
R13
C25
IFGCA IN2
C24
C20
R17
IFGCA OUT2
C21
R18
R20
IFGCA OUT1
R19
IFGCA CTRL
C23
C22
R21
R23
R22
A.
To prevent abnormal oscillation, connect C14, which does not affect a PLL.
B.
This application information is advisory and performance-check is required at actual application circuits. TI assumes
no responsibility for the consequences of use of this circuit, such as an infringement of intellectual property rights or
other rights, including patents, of third parties.
Figure 20. Reference Measurement Circuit
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Table 10. Component Values for Measurement Circuit (1)
PARTS NAME
VALUE
PARTS NAME
VALUE
C1 (VHI OSC B)
7 pF
L6 (MIXOUT)
680 nH (LK1608R68K-T)
C2 (VHI OSC C)
5 pF
L7 (MIX OUT)
680 nH (LK1608R68K-T)
C3 (VHI OSC)
0.5 pF
L8 (IF IN)
Short
C4 (UHF OSCB1)
1.5 pF
L9 (MIX OUT)
Short
C5 (UHF OSCC1)
1 pF
L10 (MIXOUT)
Short
C6 (UHF OSCC2)
1 pF
R1 (VHI OSC B)
4.7 Ω
C7 (UHF OSCB2)
1.5 pF
R2 (UHF OSC B1)
7.5 Ω
C8 (UHF OSC)
10 pF
R3 (UHF OSC B2)
7.5 Ω
C9 (UHF OSC)
100 pF
R4 (VHI OSC)
3.3 kΩ
C10 (VHI OSC)
51 pF
R5 (VHI OSC)
3.3 kΩ
C11 (CP)
0.01 µF/50 V
R6 (UHF OSC)
1kΩ
C12 (CP)
22 pF/50 V
R7 (UHF OSC)
2.2 kΩ
C13 (VTU)
2.2 nF
R8 (CP)
47 kΩ
C14 (VTU)
150 pF
R9 (VTU)
3kΩ
C15 (VTU)
2.2 nF/50 V
R10 (VTU)
22 kΩ
C16 (IF OUT)
2.2 nF
R11 (IF OUT)
200 Ω
C17 (VCC)
0.1 µF
R13 (IFGCA IN1)
50 Ω
C19 (IFGCA IN1)
2.2 nF
R15 (IF GCA IN)
0Ω
C20 (IFGCA IN2)
2.2 nF
R17 (IFGCA IN2)
0Ω
C21 (IFGCA OUT2)
2.2 nF
R18 (IFGCA OUT2)
200 Ω
C22 (IFGCA OUT1)
2.2 nF
R19 (IFGCA OUT2)
Open
C23 (IFGCA CTRL)
0.1 µF
R20 (IFGCA OUT2)
Open
C24 (XTAL)
15 pF
R21 (IFGCA OUT1)
Open
C25 (XTAL)
15 pF
R22 (IFGCA OUT1)
200 Ω
C26 (RFAGC OUT)
0.1 µF
R23 (IFGCA OUT1)
50 Ω
C27 (RFAGC OUT)
0.047 µF
R24 (MIXOUT)
Open
C28 (IF IN)
Open
R25 (MIXOUT)
0Ω
C29 (MIXOUT)
6 pF
R26 (VHI IN)
50 Ω
C30 (MIXOUT)
2.2 nF
R27 (UHF RFIN1)
50 Ω
C31 (VHI RF IN)
2.2 nF
R28 (SDA)
330 Ω
C32 (UHF RFIN2)
2.2 nF
R29 (SCL)
330 Ω
C33 (UHF RFIN1)
2.2 nF
R31 (GPP1)
Open
C34 (SDA)
Open
VC1 (VHI OSC)
MA2S372
C35 (SCL)
Open
VC2 (VHI OSC)
MA2S374
L1 (VHI OSC)
φ2.0 mm, 3T, wire 0.4 mm, L
VC3 (UHF OSC)
MA2S372
L2 (UHF OSC)
φ1.8 mm, 3T, wire 0.4 mm, R
X1
8 MHz crystal
L3 (UHF OSC)
φ1.8 mm, 3T, wire 0.4 mm, R
(1)
16
If frequency = 44 MHz,
local frequency range:
VHF-HIGH: 221–511 MHz
UHF: 517–908 MHz
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APPLICATION INFORMATION (CONTINUED)
XTAL1
XTAL2
Reference Crystal Oscillation Circuit
15
16
CRYSTAL X1
FREQUENCY
X1
CAPACITORS
C24
C25
4 MHz
HC49SFNB04000H0 (Kyocera)
27 pF
27 pF
8 MHz
CX5032GB08000H0 (Kyocera)
15 pF
15 pF
16 MHz
CX3225GB16000D0 (Kyocera)
14 pF
14 pF
TYPE
C24
Figure 21. Reference Crystal Oscillation Circuit
Test Circuits
DUT
SG
Spectrum
Analyzer
200 W
VHI RFIN
50 W
50 W
IFOUT
Gv = 20log(VOUT/VIN) + 14.0
VIN
VOUT
50 W
Figure 22. Conversion Gain Measurement Circuit
DUT
SG
Spectrum
Analyzer
200 W
UHFRF IN1
50 W
50 W
VIN
IFOUT
Gv = 20log(VOUT/VIN) + 14.0
VOUT
UHFRF IN2
50 W
Figure 23. UHF Conversion Gain Measurement Circuit
DUT
SG
IFGCAIN1
50 W
50 W
VIN
IFGCAIN2
Vout difft
200 W
Spectrum
Analyzer
IFGCAOUT1
VOUT
IFGCAOUT2
IFGCACTRL
50 W
Gv = 20log(VOUTDIFF/VIN)
= 20log(VOUT/VIN) + 6 + 14.0
250 W
DC Power Source
Figure 24. IF GCA Gain Measurement Circuit
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NF
Meter
Noise
Source
DUT
Figure 25. Noise Figure Measurement Circuit
Signal
Generator
fdes: P = 70 dBmV
Signal
Generator
Mix
Pad
fdes ±6 MHz
AM 30%, 1 kHz
Modulation
Analyzer
DUT
Figure 26. 1% Cross-Modulation Distortion Measurement Circuit
TYPICAL CHARACTERISTICS
General Purpose Port 2 (GPP2) Output Voltage
5.0
4.5
Vcc=5.5V
4.0
Vcc=5.0V
Output Voltage [V]
3.5
Vcc=4.5V
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
2
4
6
8
10
12
14
16
18
20
Output Current [mA]
Figure 27. GPP2 Output Current vs Output Voltage
18
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TYPICAL CHARACTERISTICS (continued)
IF GCA Gain vs Control Voltage
70
60
50
Vcc=5.5V
Gain [dB]
40
Vcc=5.0V
Vcc=4.5V
30
20
10
0
-10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IF GCA CTRL voltage [V]
Figure 28. IF GCA Gain vs Control Voltage
S-Parameter
40MHz
500MHz
Figure 29. VHI RFIN
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TYPICAL CHARACTERISTICS (continued)
900MHz
350MHz
Figure 30. UHF RFIN
60MHz
30MHz
Figure 31. IFOUT
20
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TYPICAL CHARACTERISTICS (continued)
20MHz
70MHz
Figure 32. IF GCA IN
70MHz
20MHz
Figure 33. IF GCA OUT
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PACKAGE OPTION ADDENDUM
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31-Mar-2012
PACKAGING INFORMATION
Orderable Device
SN761646RHBR
Status
(1)
NRND
Package Type Package
Drawing
QFN
RHB
Pins
Package Qty
32
3000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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Addendum-Page 1
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