TI SN74AUP1G74DCUR

SN74AUP1G74
www.ti.com
SCES644C – MARCH 2006 – REVISED MARCH 2010
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
Check for Samples: SN74AUP1G74
FEATURES
1
•
•
•
•
•
•
•
Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption:
ICC = 0.9 mA Max
Low Dynamic-Power Consumption:
Cpd = 5.5 pF Typ at 3.3 V
Low Input Capacitance: Ci = 1.5 pF Typ
Low Noise – Overshoot and Undershoot
<10% of VCC
Ioff Supports Partial-Power-Down Mode
Operation
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(Vhys = 250 mV Typ at 3.3 V)
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
Q
3
6
CLK
D
Q
PRE
GND
CLR
GND
4
5
Q
CLK
D
1
2
8
7
VCC
1
8
2
7
3
6
4
5
•
•
•
•
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 5 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
RSE PACKAGE
(TOP VIEW)
DQE PACKAGE
(TOP VIEW)
8 V
CLK 1
CC
VCC
D
PRE
Q
CLR GND
Q
2
7
3
6
4
5
YFP OR YZP PACKAGE
(TOP VIEW)
VCC
PRE
CLR PRE
Q
1
CLR
2
Q
3
8
4
CLK
D
7
CLK
6
D
5
Q
Q
GND
A1
18
A2
B1
2 7
B2
C1
3 6
C2
D1
4 5
D2
VCC
PRE
CLR
Q
GND
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2010, Texas Instruments Incorporated
SN74AUP1G74
SCES644C – MARCH 2006 – REVISED MARCH 2010
www.ti.com
Static-Power Consumption
Dynamic-Power Consumption
(µA)
(pF)
Switching Characteristics
at 25 MHz†
100%
100%
3.5
80%
80%
2.5
60%
60%
3.3-V
Logic†
40%
Voltage − V
3
3.3-V
LVC
Logic†
40%
AUP
0%
†
Output
0.5
20%
20%
Input
2
1.5
1
0
−0.5
AUP
0%
0
Single, dual, and triple gates
†
Figure 1. AUP – The Lowest-Power Family
5
10
15
20 25 30
Time − ns
35
40
45
AUP1G08 data at CL = 15 pF
Figure 2. Excellent Signal Integrity
This single positive-edge-triggered D-type flip-flop is designed for 0.8-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 85°C
(1)
(2)
(3)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (3)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP
Reel of 3000
SN74AUP1G74YFPR
_ _ _HS_
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUP1G74YZPR
_ _ _HS_
SSOP – DCT
Reel of 3000
SN74AUP1G74DCTR
H74_ _ _
VSSOP – DCU
Reel of 3000
SN74AUP1G74DCUR
H74_
uQFN – DQE
Reel of 5000
SN74AUP1G74DQER
HS
QFN – RSE
Reel of 5000
SN74AUP1G74RSER
HS
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DCT: The actual top-side marking has three additional characters that designate the year, month, and wafer fab/assembly site.
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
2
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
X
L
X
X
L
H
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
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SCES644C – MARCH 2006 – REVISED MARCH 2010
LOGIC DIAGRAM (POSITIVE LOGIC)
CLR
CLK
6
1
C
C
C
3
Q
TG
C
C
5
C
Q
C
D
PRE
2
TG
TG
TG
C
C
C
7
Pin numbers shown are for the DCT, DCU, and DQE packages
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
–0.5
4.6
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off state
VO
Output voltage range in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
qJA
Package thermal impedance (3)
DCT package
220
DCU package
227
DQE package
261
RSE package
253
YFP/YZP package
Tstg
(1)
(2)
(3)
Storage temperature range
V
°C/W
102
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SCES644C – MARCH 2006 – REVISED MARCH 2010
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RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
MIN
MAX
0.8
3.6
UNIT
V
VCC
0.65 × VCC
V
1.6
2
VCC = 0.8 V
0
VCC = 1.1 V to 1.95 V
0.35 × VCC
VIL
Low-level input voltage
VI
Input voltage
0
3.6
VO
Output voltage
0
VCC
V
VCC = 0.8 V
–20
mA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65
–1.9
VCC = 2.3 V
–3.1
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
IOH
High-level output current
IOL
Low-level output current
0.9
VCC = 3 V
–4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
V
V
mA
mA
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES644C – MARCH 2006 – REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC
MIN
0.8 V to 3.6 V
VCC – 0.1
VCC – 0.1
1.1 V
0.75 × VCC
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.11
1.03
IOH = –1.9 mA
1.65 V
1.32
1.3
2.05
1.97
2.3 V
IOH = –2.7 mA
3V
IOH = –4 mA
1.9
1.85
2.72
2.67
2.6
2.55
MAX
0.8 V to 3.6 V
0.1
0.1
IOL = 1.1 mA
1.1 V
0.3 × VCC
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
0.37
IOL = 1.9 mA
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
2.3 V
IOL = 3.1 mA
IOL = 2.7 mA
3V
IOL = 4 mA
0.44
0.45
0 V to 3.6 V
0.1
V
0.5
mA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
0.6
mA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
mA
ICC
VI = GND or (VCC to 3.6 V),
IO = 0
0.8 V to 3.6 V
0.5
0.9
mA
ΔICC
VI = VCC – 0.6 V (1), IO = 0
3.3 V
40
50
mA
Ci
VI = VCC or GND
Co
VO = GND
(1)
VI = GND to 3.6 V
UNIT
V
IOL = 20 mA
IOL = 2.3 mA
A or B input
TA = –40°C to 85°C
MAX
IOH = –1.1 mA
IOH = –3.1 mA
II
TYP
IOH = –20 mA
IOH = –2.3 mA
VOL
TA = 25°C
MIN
0V
1.5
3.6 V
1.5
0V
pF
3
pF
One input at VCC – 0.6 V, other input at VCC or GND
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TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
VCC
TA = 25°C
TYP
0.8 V
fclock
Clock frequency
TA = –40°C to
85°C
MIN
21
1.2 V ± 0.1 V
40
1.5 V ± 0.1 V
50
1.8 V ± 0.15 V
60
2.5 V ± 0.2 V
90
3.3 V ± 0.3 V
0.8 V
CLK high or low
tw
PRE or CLR low
2
1.5 V ± 0.1 V
2
1.8 V ± 0.15 V
2
2.5 V ± 0.2 V
2
Data high
2
1.5 V ± 0.1 V
2
1.8 V ± 0.15 V
2
2.5 V ± 0.2 V
2
3.3 V ± 0.3 V
2
Data low
1.3
1.5 V ± 0.1 V
1
1.8 V ± 0.15 V
1
2.5 V ± 0.2 V
0.5
3.3 V ± 0.3 V
0.5
1
1.2 V ± 0.1 V
1.2
1.5 V ± 0.1 V
1
1.8 V ± 0.15 V
1
2.5 V ± 0.2 V
1
3.3 V ± 0.3 V
0.8 V
PRE or CLR inactive
1
0.5
1.5 V ± 0.1 V
0.5
1.8 V ± 0.15 V
0.5
2.5 V ± 0.2 V
0.5
3.3 V ± 0.3 V
th
6
Hold time, data after CLK↑
0.5
0
1.2 V ± 0.1 V
0
1.5 V ± 0.1 V
0
1.8 V ± 0.15 V
0
2.5 V ± 0.2 V
0
3.3 V ± 0.3 V
0
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ns
1
1.2 V ± 0.1 V
0.8 V
ns
3
1.2 V ± 0.1 V
0.8 V
Setup time before CLK↑
2
4.5
1.2 V ± 0.1 V
0.8 V
tsu
90
1.2 V ± 0.1 V
0.8 V
MHz
3.5
3.3 V ± 0.3 V
Pulse duration
UNIT
MAX
ns
Copyright © 2006–2010, Texas Instruments Incorporated
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SCES644C – MARCH 2006 – REVISED MARCH 2010
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
fmax
Q
CLK
tpd
Q or Q
MAX
MIN
1.2 V ± 0.1 V
80
1.5 V ± 0.1 V
125
90
1.8 V ± 0.15 V
150
120
2.5 V ± 0.2 V
180
160
3.3 V ± 0.3 V
190
180
0.8 V
31
UNIT
MAX
60
MHz
1.2 V ± 0.1 V
2
10
20
2.7
20.4
1.5 V ± 0.1 V
2
6
12
1.9
12.4
1.8 V ± 0.15 V
2
5
9
1.4
9.5
2.5 V ± 0.2 V
2
3
6
1.1
6.2
3.3 V ± 0.3 V
2
3
4
1
4.7
28
1.2 V ± 0.1 V
2
9
19
2.4
19
1.5 V ± 0.1 V
2
6
11
1.6
11.8
1.8 V ± 0.15 V
2
5
9
1.3
9
2.5 V ± 0.2 V
2
3
6
1.1
6
3.3 V ± 0.3 V
2
3
4
1
4.6
0.8 V
PRE or CLR
TYP
60
0.8 V
Q
TA = –40°C to
85°C
TA = 25°C
VCC
26
1.2 V ± 0.1 V
2
9
20
2
20
1.5 V ± 0.1 V
2
6
12
1.5
13
1.8 V ± 0.15 V
2
5
9
1.3
10
2.5 V ± 0.2 V
2
3
6
1
7
3.3 V ± 0.3 V
2
3
5
1
5
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7
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SCES644C – MARCH 2006 – REVISED MARCH 2010
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
Q
CLK
tpd
MIN
8
Q or Q
MAX
MIN
46
1.2 V ± 0.1 V
65
50
1.5 V ± 0.1 V
95
55
1.8 V ± 0.15 V
110
60
2.5 V ± 0.2 V
170
130
3.3 V ± 0.3 V
180
160
0.8 V
33
UNIT
MAX
MHz
1.2 V ± 0.1 V
2
10
22
3.4
21.8
1.5 V ± 0.1 V
2
7
13
2.4
13.5
1.8 V ± 0.15 V
2
6
10
1.9
10.4
2.5 V ± 0.2 V
2
4
6
1.5
7
3.3 V ± 0.3 V
2
3
5
1.2
5.3
30
1.2 V ± 0.1 V
2
10
20
3
20.3
1.5 V ± 0.1 V
2
7
12
2.2
12.8
1.8 V ± 0.15 V
2
5
9
1.8
9.9
2.5 V ± 0.2 V
2
4
6
1.3
6.7
3.3 V ± 0.3 V
2
3
5
1.1
5.2
0.8 V
PRE or CLR
TYP
0.8 V
0.8 V
Q
TA = –40°C to
85°C
TA = 25°C
VCC
29
1.2 V ± 0.1 V
2
10
21
2
21.4
1.5 V ± 0.1 V
2
7
13
2
13.8
1.8 V ± 0.15 V
2
5
10
2
10.8
2.5 V ± 0.2 V
2
4
7
1.5
7.4
3.3 V ± 0.3 V
2
3
5
1.5
5.8
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SCES644C – MARCH 2006 – REVISED MARCH 2010
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
Q
CLK
tpd
MIN
Q or Q
MAX
MIN
41
1.2 V ± 0.1 V
75
50
1.5 V ± 0.1 V
95
55
1.8 V ± 0.15 V
100
60
2.5 V ± 0.2 V
150
130
3.3 V ± 0.3 V
200
160
0.8 V
35
MHz
2
12
23.1
4.1
23.2
1.5 V ± 0.1 V
2
8
14.1
2.9
14.6
1.8 V ± 0.15 V
2
6
10.7
2.4
11.3
2.5 V ± 0.2 V
2
4
7
1.9
7.6
3.3 V ± 0.3 V
2
4
5.4
1.6
5.9
21.8
32
1.2 V ± 0.1 V
2
11
21.8
3.7
1.5 V ± 0.1 V
2
7
13.5
2.6
14
1.8 V ± 0.15 V
2
6
10.4
2.2
10.9
2.5 V ± 0.2 V
2
4
7.1
1.7
7.5
3.3 V ± 0.3 V
2
3
5.4
1.4
5.8
2
11
23
2
22.9
1.5 V ± 0.1 V
2
7
14
2
14.9
1.8 V ± 0.15 V
2
6
11
2
11.7
2.5 V ± 0.2 V
2
4
7
2
8.1
3.3 V ± 0.3 V
2
4
6
1.5
6.4
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31
1.2 V ± 0.1 V
Copyright © 2006–2010, Texas Instruments Incorporated
UNIT
MAX
1.2 V ± 0.1 V
0.8 V
PRE or CLR
TYP
0.8 V
0.8 V
Q
TA = –40°C to
85°C
TA = 25°C
VCC
9
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SCES644C – MARCH 2006 – REVISED MARCH 2010
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
Q
CLK
MIN
TYP
Q
Q or Q
MIN
21
1.2 V ± 0.1 V
50
40
1.5 V ± 0.1 V
60
50
1.8 V ± 0.15 V
75
70
2.5 V ± 0.2 V
100
90
3.3 V ± 0.3 V
100
90
0.8 V
32
UNIT
MAX
MHz
1.2 V ± 0.1 V
3
14
27
5.9
27
1.5 V ± 0.1 V
3
10
17
4.4
17.2
1.8 V ± 0.15 V
3
8
13
3.6
13.4
2.5 V ± 0.2 V
3
6
9
3
9.2
3.3 V ± 0.3 V
3
5
7
2.6
7.2
40
1.2 V ± 0.1 V
3
13
26
5.5
25.9
1.5 V ± 0.1 V
3
9
16
4.1
16.8
1.8 V ± 0.15 V
3
7
13
3.5
13.2
2.5 V ± 0.2 V
3
5
9
2.7
9.2
3.3 V ± 0.3 V
3
5
7
2.4
7.2
0.8 V
PRE or CLR
MAX
0.8 V
0.8 V
tpd
TA = –40°C to
85°C
TA = 25°C
VCC
ns
38
1.2 V ± 0.1 V
3
13
26
3
27
1.5 V ± 0.1 V
3
9
17
3
17.4
1.8 V ± 0.15 V
3
8
13
3
14
2.5 V ± 0.2 V
3
6
9
3
10
3.3 V ± 0.3 V
3
5
7
2.5
8
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
10
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
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VCC
TYP
0.8 V
5.5
1.2 V ± 0.1 V
5.5
1.5 V ± 0.1 V
5.5
1.8 V ± 0.15 V
5.5
2.5 V ± 0.2 V
5.5
3.3 V ± 0.3 V
5.5
UNIT
pF
Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G74
SN74AUP1G74
www.ti.com
SCES644C – MARCH 2006 – REVISED MARCH 2010
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
VCC/2
0V
tPLH
tsu
VOH
VM
Output
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
th
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G74
11
SN74AUP1G74
SCES644C – MARCH 2006 – REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × VCC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
tPZL
VCC
VCC/2
VOL + V∆
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
12
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Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G74
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUP1G74DCUR
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G74DCURG4
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G74DQER
ACTIVE
X2SON
DQE
8
5000 Green (RoHS &
no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
SN74AUP1G74RSER
ACTIVE
UQFN
RSE
8
5000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G74YFPR
ACTIVE
DSBGA
YFP
8
3000
SN74AUP1G74YZPR
ACTIVE
DSBGA
YZP
8
3000 Green (RoHS &
no Sb/Br)
TBD
Lead/Ball Finish
Call TI
SNAGCU
MSL Peak Temp (3)
Call TI
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AUP1G74DCUR
US8
DCU
8
3000
180.0
9.2
2.25
3.35
1.05
4.0
8.0
Q3
SN74AUP1G74DQER
X2SON
DQE
8
5000
180.0
8.4
1.17
1.67
0.73
4.0
8.0
Q1
SN74AUP1G74RSER
UQFN
RSE
8
5000
180.0
8.4
1.6
1.6
0.66
4.0
8.0
Q2
SN74AUP1G74YFPR
DSBGA
YFP
8
3000
178.0
9.2
0.9
1.75
0.6
4.0
8.0
Q1
SN74AUP1G74YZPR
DSBGA
YZP
8
3000
180.0
8.4
1.02
2.02
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1G74DCUR
US8
DCU
8
3000
202.0
201.0
28.0
SN74AUP1G74DQER
X2SON
DQE
8
5000
202.0
201.0
28.0
SN74AUP1G74RSER
UQFN
RSE
8
5000
202.0
201.0
28.0
SN74AUP1G74YFPR
DSBGA
YFP
8
3000
220.0
220.0
35.0
SN74AUP1G74YZPR
DSBGA
YZP
8
3000
220.0
220.0
34.0
Pack Materials-Page 2
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