TS3DV520 www.ti.com SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 5-CHANNEL DIFFERENTIAL 10:20 MULTIPLEXER SWITCH FOR DVI/HDMI APPLICATIONS Check for Samples: TS3DV520 FEATURES 1 49 GND 50 VCC 51 NC 52 NC 53 GND 54 NC 55 GND 56 VCC 2 47 1B1 A1 3 46 0B2 VCC 4 45 1B2 NC 5 44 GND GND 6 43 2B1 A2 7 42 3B1 A3 8 41 2B2 GND 9 40 3B2 39 GND VCC 10 A4 11 38 VCC A5 12 37 4B1 GND 13 36 5B1 A6 14 35 4B2 A7 15 34 5B2 33 GND GND 16 32 6B1 VCC 18 31 7B1 A8 19 30 6B2 A9 20 29 7B2 GND 28 SEL 17 9B2 26 • A0 VCC 27 • 48 0B1 8B2 25 • • 1 9B1 23 • GND GND 24 • TQFN PACKAGE (TOP VIEW) 8B1 22 • • • Compatible With HDMI v1.2a (Type A) DVI 1.0 High-Speed Digital Interface – Wide Bandwidth of Over 1.65 Gbps (Bandwidth 2.4 Gbps Typ) – 165-MHz Speed Operation – Serial Data Stream at 10× Pixel Clock Rate – Supports All Video Formats up to 1080p and SXGA (1280 × 1024 at 75 Hz) – Total Raw Capacity 4.95 Gbps (Single Link) – HDCP Compatible Low Crosstalk (XTALK = –41 dB Typ) Low Bit-to-Bit Skew (tsk(o) = 0.1 ns Max) Low and Flat ON-State Resistance (ron = 6 Ω Max, ron(flat) = 0.5 Ω Typ) Low Input/Output Capacitance (CON = 7.8 pF Typ) Rail-to-Rail Switching on Data I/O Ports (0 to 5 V) VCC Operating Range From 3 V to 3.6 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) GND 21 • NC – No internal connection APPLICATIONS • • • • DVI/HDMI Signal Switching Differential DVI, HDMI Signal Multiplexing for Audio/Video Receivers and High-Definition Televisions (HDTVs) 10/100/1000 Base-T Signal Switching Hub and Router Signal Switching DESCRIPTION/ORDERING INFORMATION The TS3DV520 is a 20-bit to 10-bit multiplexer/demultiplexer digital video switch with a single select (SEL) input. SEL controls the data path of the multiplexer/demultiplexer. The device provides five differential channels for digital video signal switching. This device can also be used to replace mechanical relays in LAN applications and allows for signals to be routed from a 10/100/1000 Base-T transceiver to the RJ-45 connectors in laptops or docking stations. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2009, Texas Instruments Incorporated TS3DV520 SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com This device provides low and flat ON-state resistance (ron) and excellent ON-state resistance match. Low input/output capacitance, high bandwidth, low skew, and low crosstalk among channels make this device suitable for various digital video applications, such as DVI and HDMI. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. DVD Player Digital TV TS3DV520 STB HDMI Receiver Table 1. ORDERING INFORMATION (1) TA PACKAGE –40°C to 85°C (1) (2) TQFN (2) ORDERABLE PART NUMBER Tape and reel TS3DV520RHUR TOP-SIDE MARKING SD520 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE INPUT SEL INPUT/OUTPUT An L nB1 An = nB1 nB2 high-impedance mode H nB2 An = nB2 nB1 high-impedance mode FUNCTION PIN DESCRIPTION 2 NAME DESCRIPTION An Data I/O nBm Data I/O SEL Select input Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 TS3DV520 www.ti.com SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 LOGIC DIAGRAM (POSITIVE LOGIC) 2 48 3 47 0B1 A0 1B1 A1 46 0B2 45 1B2 7 43 2B1 A2 8 42 3B1 A3 41 2B2 40 3B2 11 37 4B1 A4 12 36 5B1 A5 35 4B2 34 5B2 14 32 15 31 6B1 A6 7B1 A7 30 6B2 29 7B2 19 22 8B1 A8 20 23 9B1 A9 25 8B2 26 9B2 SEL 17 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 3 TS3DV520 SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX –0.5 4.6 UNIT V –0.5 7 V –0.5 7 VIN Control input voltage range (2) (3) VI/O Switch I/O voltage range (2) (3) (4) IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA ±128 mA II/O ON-state switch current (5) V Continuous current through VCC or GND ±100 mA θJA Package thermal impedance (6) 31.8 °C/W Tstg Storage temperature range 150 °C (1) (2) (3) (4) (5) (6) –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) MIN MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level control input voltage (SEL) 2 5.5 V VIL Low-level control input voltage (SEL) 0 0.8 V VI/O Input/output voltage 0 5.5 V TA Operating free-air temperature –40 85 °C (1) 4 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 TS3DV520 www.ti.com SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 Electrical Characteristics (1) for high-frequency switching over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIK SEL VCC = 3.6 V, IIN = –18 mA IIH SEL VCC = 3.6 V, VIN = VCC IIL SEL MIN VCC = 3.6 V, VIN = GND Ioff VCC = 0, VO = 0 to 3.6 V, VI = 0 ICC VCC = 3.6 V, II/O = 0, Switch ON or OFF CIN SEL f = 1 MHz, VIN = 0 COFF B port (2) MAX –0.7 –1.2 V ±1 μA ±1 μA 1 μA 250 500 μA 2 2.5 pF TYP UNIT VI = 0, f = 1 MHz, Outputs open, Switch OFF 2.5 3 pF CON VI = 0, f = 1 MHz, Outputs open, Switch ON 7.8 8.5 pF ron VCC = 3 V, 1.5 V ≤ VI ≤ VCC, IO = –40 mA 3.5 6 Ω VCC = 3 V, VI = 1.5 V and VCC, IO = –40 mA 0.5 VCC = 3 V, 1.5 V ≤ VI ≤ VCC, IO = –40 mA 0.4 1 (1) MAX ron(flat) Δron (1) (2) (3) (4) (3) (4) Ω Ω VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ron(flat) is the difference of ron in a given channel at specified voltages. Δron is the difference of ron from center (A4, A5) ports to any other port. Switching Characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, RL = 200 Ω, CL = 10 pF (unless otherwise noted) (see Figure 4 and Figure 5) FROM (INPUT) TO (OUTPUT) A or B B or A tPZH, tPZL SEL A or B 0.5 15 ns tPHZ, tPLZ SEL A or B 0.5 9 ns A or B B or A 0.05 0.1 ns 0.05 0.1 ns PARAMETER tpd (1) (2) (3) (4) (2) tsk(o) (3) tsk(p) (4) MIN TYP 0.25 UNIT ns All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). Output skew between center port (A4 to A5) to any other port Skew between opposite transitions of the same output in a given device |tPHL – tPLH| Dynamic Characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER (1) TEST CONDITIONS TYP (1) UNIT XTALK RL = 100 Ω, f = 250 MHz, See Figure 7 –41 OIRR RL = 100 Ω, f = 250 MHz, See Figure 8 –39 dB BW RL = 100 Ω, See Figure 6 1.2 GHz dB All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 5 TS3DV520 SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com OPERATING CHARACTERISTICS 0 0 −2 Attenuation (dB) −20 Gain (dB) −4 −6 −8 −40 −60 −80 −10 −12 0.1 1 10 100 1000 10,000 −100 0.1 1 Frequency (MHz) Figure 1. Gain/Phase vs Frequency Figure 2. OFF Isolation vs Frequency 6 0 5 4 −40 ron (W) Attenuation (dB) −20 3 −60 2 −80 −100 0.1 1 0 1 10 100 Frequency (MHz) 1000 10,000 0 1 2 3 4 5 6 VCOM (V) Figure 3. Crosstalk vs Frequency 6 10,000 1000 10 100 Frequency (MHz) Figure 4. ron and V0 vs V1 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 TS3DV520 www.ti.com SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 APPLICATION INFORMATION Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 7 TS3DV520 SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator S1 RL VO VI Open GND 50 Ω CL (see Note A) 50 Ω VG2 RL TEST VCC S1 RL VI CL V∆ tPLZ/tPZL 3.3 V ± 0.3 V 2 × VCC 200 Ω GND 10 pF 0.3 V tPHZ/tPZH 3.3 V ± 0.3 V GND 200 Ω VCC 10 pF 0.3 V 2.5 V Output Control (VIN) 1.25 V 1.25 V 0V Output Waveform 1 S1 at 2 y VCC (see Note B) tPZL tPLZ VOH VCC/2 VOL +0.3 V tPZH Output Waveform 2 S1 at GND (see Note B) VOL tPHZ VCC/2 VOH −0.3 V VOH VOL VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. Figure 5. Test Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 TS3DV520 www.ti.com SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 PARAMETER MEASUREMENT INFORMATION (Skew) VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator S1 RL VO VI Open GND 50 Ω CL (see Note A) 50 Ω VG2 RL TEST VCC S1 RL VI CL tsk(o) 3.3 V ± 0.3 V Open 200 Ω VCC or GND 10 pF tsk(p) 3.3 V ± 0.3 V Open 200 Ω VCC or GND 10 pF V∆ 3.5 V 2.5 V 1.5 V Data In at Ax or Ay tPLHx tPHLx VOH (VOH + VOL)/2 VOL Data Out at XB1 or XB2 tsk(o) 2.5 V 1.5 V tsk(o) VOH (VOH + VOL)/2 VOL Data Out at YB1 or YB2 tPLHy 3.5 V Input tPHLy tPLH tPHL VOH (VOH + VOL)/2 VOL Output tsk(p) = |tPLH − tPLH| tsk(o) = |tPLHy − tPLHx| or |tPHLy − tPHLx| VOLTAGE WAVEFORMS OUTPUT SKEW (tsk(o)) VOLTAGE WAVEFORMS PULSE SKEW (tsk(p)) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 6. Test Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 9 TS3DV520 SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VCC 0B1 A0 SEL DUT CL = 10 pF (see Note A) VSEL NOTE A: CL includes probe and jig capacitance. Figure 7. Test Circuit for Frequency Response (BW) Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and A0 is the input, the output is measured at 0B1. All unused analog I/O ports are left open. HP8753ES setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM 10 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 TS3DV520 www.ti.com SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VCC A0 0B1 RL = 100 Ω A1 1B1 0B2 DUT A2 1B2 2B1 RL = 100 Ω A3 3B1 2B2 3B2 SEL VSEL NOTES: A. CL includes probe and jig capacitance. B. A 50-Ω termination resistor is needed to match the loading of the network analyzer. Figure 8. Test Circuit for Crosstalk (XTALK) Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VSEL = 0 and A0 is the input, the output is measured at 1B1. All unused analog input (A) ports are connected to GND, and output (B) ports are connected to GND through 50-Ω pulldown resistors. HP8753ES setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 11 TS3DV520 SCDS197D – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VCC A0 0B1 RL = 100 Ω A1 1B1 DUT 0B2 1B2 SEL VSEL NOTES: A. CL includes probe and jig capacitance. B. A 50-Ω termination resistor is needed to match the loading of the network analyzer. Figure 9. Test Circuit for OFF Isolation (OIRR) OFF isolation is measured at the output of the OFF channel. For example, when VSEL = VCC and A0 is the input, the output is measured at 0B2. All unused analog input (A) ports are left open, and output (B) ports are connected to GND through 50-Ω pulldown resistors. HP8753ES setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 P1 = 0 dBM 12 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TS3DV520 PACKAGE OPTION ADDENDUM www.ti.com 29-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TS3DV520ERHUR ACTIVE WQFN RHU 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SD520E TS3DV520RHUR ACTIVE WQFN RHU 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SD520 TS3DV520RHURG4 ACTIVE WQFN RHU 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SD520 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-May-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TS3DV520ERHUR WQFN RHU 56 2000 330.0 24.4 5.3 11.3 1.0 12.0 24.0 Q1 TS3DV520RHUR WQFN RHU 56 2000 330.0 24.4 5.3 11.3 1.0 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS3DV520ERHUR WQFN RHU 56 2000 346.0 346.0 35.0 TS3DV520RHUR WQFN RHU 56 2000 346.0 346.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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