TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 • • • • • • • • JT OR NT PACKAGE (TOP VIEW) 58-MHz Max Clock Rate Ideal for Waveform Generation and High-Performance State Machine Applications CLK I0 I1 I2 I3 I4 I5 Q0 Q1 Q2 Q3 GND 6-Bit Internal Binary Counter 8-Bit Internal State Register Programmable Clock Polarity Outputs Programmable for Registered or Combinational Operation 6-Bit Counter Simplifies Logic Equation Development in State Machine Designs 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC I6 I7 I8 I9 I10 I11 I12/OE Q7 Q6 Q5 Q4 Programmable Output Enable FK OR FN PACKAGE (TOP VIEW) The TIBPSG507AC contains 80 product (AND) terms, a 6-bit binary counter with control logic, eight S/R state holding registers, and eight outputs. The eight outputs can be individually programmed for either registered or combinational operation. The clock input is fuse programmable for either positive- or negativeedge operation. I2 I3 I4 NC I5 Q0 Q1 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 I8 I9 I10 NC I11 I12/OE Q7 Q2 Q3 GND NC Q4 Q5 Q6 The TIBPSG507AC is a 13 × 80 × 8 Programmable Sequence Generator (PSG) that offers the system designer unprecedented flexibility in a high-performance field-programmable logic device. Applications such as waveform generators, state machines, dividers, timers, and simple logic reduction are all possible with the PSG. By utilizing the built-in binary counter, the PSG is capable of generating complex timing controllers. The binary counter also simplifies logic equation development in state machine and waveform generator applications. I1 I0 CLK NC VCC I6 I7 description NC – No internal connection The 6-bit binary counter is controlled by a synchronous-clear and a count/hold function. Each control function has a nonregistered and registered option. When either SCLR0 or SCLR1 is taken high, the counter resets to zero on the next active clock edge. When either CNT/HLD0 or CNT/HLD1 is taken high, the counter is held at the present count and is not allowed to advance on the active clock edge. The SCLR function overrides the CNT/HLD feature when both lines are simultaneously high. Clock polarity is programmable through the clock polarity fuse. Leaving this fuse intact selects positive-edge triggering. Negative-edge triggering is selected by blowing this fuse. Pin 17 functions as an input and/or an output enable. When the output enable fuse is intact, all outputs are always enabled allowing pin 17 to be used strictly as an input. Blowing the output enable fuse lets pin 17 function as an output enable and an input. In this mode, the outputs are enabled when pin 17 is low and are in a high-impedance state when pin 17 is high. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 description (continued) The eight outputs can be individually programmed for combinational operation by blowing the output multiplexer fuse. After power up, the device must be initialized to the desired state. When the output multiplexer fuse is left intact, registered operation is selected. The TIBPSG507AC is characterized for operation from 0°C to 75°C. 6-BIT COUNTER CONTROL FUNCTION TABLE (see Note 1) CNT/HLD1 CNT/HLD0 SCLR1 SCLR0 L L L L counter active OPERATION X X X H synchronous clear X X H X synchronous clear X H L L hold counter H X L L hold counter NOTE 1: When all fuses are blown on a product line (AND), its output will be high. When all fuses are blown on a sum line (OR), its output will be low. All product and sum terms are low on devices with fuses intact. S/R FUNCTION TABLE (see Note 2) CLK POLARITY FUSE CLK S R INTACT ↑ L L Q0 INTACT ↑ L H L INTACT ↑ H L H INTACT ↑ H H INDET† BLOWN ↓ L L Q0 BLOWN ↓ L H L BLOWN ↓ H L H BLOWN ↓ H H INDET† STATE REGISTER † Output state is indeterminate NOTE 2: After power up, the device must be initialized to its desired state. Q0 is the state of the S/R register before the active clock edge. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 functional block diagram (positive logic) CLK 8 6 State Registers ≥1 80 x 38 C1 Binary Counter CTR 6 G2 1S 1R 1S 6x 6 & 54 x 80 1CT = 0 1R C1/2,3+ 6 6 C0 – C5 G3 6 1CT = 0 8x 8 8 8 C1 80 8 I0 – I11 I12/OE 12 13 x 1 13 8 8x 8 1S 1R Output Cell 13 8 1 C1 8 8 8x 8 1 8 Q0 – Q7 1S 1R G1 EN denotes fused inputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 7268 6532 5796 5050 4324 3588 2852 2115 Binary Counter Functional Logic Symbol 5 10 15 20 ”AND” Term Numbers 0 CTR 6 G2 CNT/HLD1 1CT = 0 SCLR1 C1/2,3+ CLK CNT/HLD0 SCLR0 25 26 7361 • DALLAS, TEXAS 75265 ”AND” Term Numbers POST OFFICE BOX 655303 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 PRE/OE 2 3 4 5 6 7 23 22 21 20 19 18 17 1380 0 7360 644 1 P0 P1 P2 P3 P4 P5 P6 P7 41 CTR C0 C1 C2 C3 C4 C5 53 SCLR0 54 1S C1 1R 58 1S C1 1R 1S C1 1R 62 1S C1 1R 1S C1 1R 66 1S C1 1R SCLR1 CNT/HLD0 CNT/HLD1 C0 C1 C2 C3 G3 C4 1CT = 0 C5 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR CLK SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 4 logic diagram (positive logic) 1S C1 1R 70 1S C1 1R 1S C1 1R 1S C1 1R 1 MUX 1S C1 1R 1 1 MUX 78 1S C1 1R Q5 15 Q6 16 Q7 7367 1 G1 7369 5 SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 7368 1 All inputs to AND gates, exclusive-OR gates, and multiplexers with a blown link assume the logic-1 state. All OR gate inputs with a blown link assume the logic-0 state. 14 7366 1 91 Q4 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR 1 90 13 7365 G1 1 MUX 1S C1 1R Q3 G1 1 MUX 1S C1 1R 11 7364 1 • DALLAS, TEXAS 75265 1S C1 1R Q2 G1 1 MUX 86 10 G1 1 MUX 1S C1 1R Q1 7363 1 POST OFFICE BOX 655303 1S C1 1R 9 7362 G1 1 MUX 82 Q0 G1 1 MUX 1S C1 1R 8 G1 1 ”OR” Term Numbers 74 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C NOTE 3: These ratings apply except for programming pins during a programming cycle or during the diagnostic mode. recommended operating conditions MIN NOM MAX UNIT 4.75 5 5.25 V 5.5 V VCC VIH Supply voltage VIL IOH Low-level input voltage High-level output current – 3.2 mA IOL Low-level output current 16 mA tw Pulse duration tsu th High-level input voltage 2 0.8 Setup time before CLK active transition† Hold time after CLK active transition† Clock high 6 Clock low 6 Input or feedback to S/R↑ inputs 12 Input or feedback to S/R↓ inputs‡ 19 Input or feedback to SCLR0 20 Input or feedback to CNT/HLD0 25 Input or feedback at S/R inputs 0 Input or feedback at SCLR0 0 Input or feedback at CNT/HLD0 0 V ns ns ns TA Operating free-air temperature 0 25 75 °C † Internal setup and hold times, tsu feedback to SCLR1, feedback to CNT/HLD1; th feedback at SCLR1 and feedback at CNT/HLD1, are guaranteed by fmax specifications. The active transition of CLK is determined by the programmed state of the CLK polarity fuse. ‡ See the OR term loading section and Figure 3. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT – 1.2 V VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = – 18 mA IOH = – 3.2 mA VOL IOZH VCC = 4.75 V, VCC = 5.25 V, IOL = 16 mA VO = 2.7 V IOZL II VCC = 5.25 V, VCC = 5.25 V, VO = 0.4 V VI = 5.5 V IIH IIL IO‡ VCC = 5.25 V, VCC = 5.25 V, VI = 2.7 V VI = 0.4 V VCC = 5.25 V, VCC = 5.25 V, VO = 0.5 V See Note 4, f = 1 MHz, 7 pF 11 pF 14 pF ICC Ci Co f = 1 MHz, VI = 2 V VO = 2 V Cclk f = 1 MHz, VCLK = 2 V 2.4 3.2 0.25 – 30 Outputs open 156 V 0.5 V 20 µA –20 µA 0.1 mA 20 µA – 0.25 mA –130 mA 210 mA switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fmax§ FROM (INPUT) TO (OUTPUT) MIN TYP† 6-Bit counter with SCLR1 or CNT/HLD1 58 65 6-Bit counter with SCLR0 40 55 6-Bit counter with CNT/HLD0 33 50 60 TEST CONDITION ten tdis CLK UNIT MHz R1 = 300 Ω, 45 Q (nonregistered)# R2 = 390 Ω, 6 25 Q (registered) See Figure 6 3 10 20 ns With external feedback (see Figure 1) tpd¶ MAX ns I or Feedback Q (nonregistered) 6 OE↓ Q 1 6 10 ns OE↑ Q 1 6 10 ns † All typical values are at VCC = 5 V, TA = 25°C. ‡ This parameter approximates IOS. The condition VO = 0.5 V takes tester noise into account. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. § See the fmax calculations section. ¶ The active edge of CLK is determined by the programmed state of the CLK polarity fuse. # tpd CLK to Q (nonregistered) is the same for data clocked from the counter or state registered. NOTE 4: When the clock is programmed for negitive edge, then VI = 4.5 V. When the clock is programmed for positive edge, then VI = 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 fmax calculations The following are the different speeds that can be achieved when using the TIBPSG507AC as a state machine. The way the 6-bit counter is controlled will largely determine the operating frequency of the state machine. fmax for a 6-bit counter using SCLR1 or CNT/HLD1 = ) 1 where setup time tsu for input CLK to Q pd or feedback to the S/R inputs = 12 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5 ns (difference in tpd from CLK and feedback, 25 to 20). Thus: fmax for this condition + 1 (12 + 5) ns + t su + 1 17 ns fmax for a 6-bit counter using SCLR0 for reset = ) t 58 MHz. 1 where setup time tsu for input or CLK to Q pd feedback to the SCLR0 inputs = 20 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5 ns (difference in tpd from CLK and feedback, 25 to 20) Thus: fmax for this condition + 1 (20 + 5) ns + t su 1 25 ns fmax for a 6-bit counter using CNT/HLD0 for reset = t + ) 40 MHz. 1 where setup time tsu for input or CLK to Q pd feedback to CNT/HLD0 = 25 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5 ns (difference in tpd from CLK and feedback, 25 to 20). Thus: fmax for this condition + 1 (25 + 5) ns + t su 1 30 ns + t 33 MHz. programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers that are capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 tmin(1) Min Clock Period Using This Path tmin(2) Min Clock Period using This Path tmin(3) Min Clock Period Using This Path Dedicated Inputs Counter or Internal SRs tsu(3) tmin(2) tsu(2) I to Internal S or R CLK SCLR0 or CNT/HLD0 Feedback Lines SR SR SR CLK Internal Output SRs CLK tmin(1) tsu(1) I to Output S or R SR SR tpd(3) CLK Internal to Output Response tpd(2) CLK to Q Pin tpd(1) I to Output Pin Dedicated Inputs Output Pin Figure 1. Timing Model POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 glossary — timing model tpd(1) — Maximum time interval from the time a signal edge is received at any input pin to the time any logically affected combinational output pin delivers a response. tpd(2) — Maximum time interval from a positive edge on the clock input pin to data delivery on the output pin corresponding to any output SR register. tpd(3) — Maximum time interval from the positive edge on the clock input pin to the response on any logically affected combinational configured output (at the pin), where data origin is any internal SR register or counter bit. tsu(1) — Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin when data affects the S or R line of any output SR register. tsu(2) — Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin when data affects the S or R line of any internal SR register. tsu(3) — Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin only when entering data on the CNT/HLD0 line. tsu(4) — Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin only when entering data on the SCLR0 line. tmin(1) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register or counter bit to feed the S or R line of any output SR register. tmin(2) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register to feed the S or R line of any internal SR register. tmin(3) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register or counter bit to feed SCLR0 or CNT/HLD0. PARAMETER VALUES FOR TIMING MODEL tpd(1) = 20 ns tpd(2) = 10 ns tsu(1) = 12 ns† tsu(2) = 12 ns† tmin(1) = 17 ns tmin(2) = 17 ns tpd(3) = 25 ns tsu(3) = 25 ns tmin(3) = 25 ns tsu(4) = 20 ns INTERNAL NODE NUMBERS SCLR0 SCLR1 25 CNTHLD0 SET 26 CNTHLD1 RESET 27 28 SET 31-38 Q0-Q7 RESET 47-54 SET 29 RESET 30 C0-C5 P0-P7 RESET 39-46 55-60 † Use tsu = 19 ns for applications where the setup time for S/R↓ inputs are required. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 diagnostics A diagnostic mode is provided that allows the user to inspect the contents of the state registers. The following are step-by-step procedures required for the diagnostics. Step 1. Step 2. Step 3. Disable all outputs by taking pin 17 (OE) high (see Note 5). Take pin 8 (Q0) to VIHH to enable the diagnostics test sequence. Apply appropriate levels of voltage to pins 11 (Q3), 13 (Q4), and 14 (Q5) to select the desired state register (see Table 1). The voltage level monitored on pin 9 will indicate the state of the selected state register. NOTE 5: If pin 17 is being used as an input to the array, then pin 7 (I5) must be taken to VIHH before pin 17 is taken high. VIHH† I5 Pin 7 OE Pin 17 VIH 100 ns VOHH VOH Q0 Pin 8 VOL VOHH 100 ns VOH Q3, Q4, Q5 Pins 11, 13, 14 100 ns VOL VOH Q1 Pin 9 VOL † VIHH = 10.25 V min, 10.5 V nom, 10.75 V max Figure 2. Diagnostics Waveforms Table 1. Addressing State Registers During Diagnostics REGISTER BINARY ADDRESS BURIED REGISTER PIN 11 PIN13 PIN 14 L L L SCLR0 L L H SCLR1 L L HH CNT/HLD0 L H L CNT/HLD1 L H H P0 L H HH P1 L HH L P2 L HH H P3 L HH HH P4 H L L P5 H L H P6 H L HH P7 H H L C0 H H H C1 H H HH C2 H HH L C3 H HH H C4 H HH HH C5 POST OFFICE BOX 655303 SELECTED • DALLAS, TEXAS 75265 11 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 PRINCIPLES OF OPERATION PSG design theory Most state machine and waveform generator designs can be simplified with the PSG by referencing all or part of each sequence to a binary count. The internal state registers can then be used to keep track of which binary count sequence is in operation, to store input data and keep track of internally generated status bits, or as output registers when connected to a nonregistered output cell. State registers can also be used to expand the binary counter when a larger counter is needed. Through the use of the binary counter, the number of product lines and state registers required for a design is usually reduced. In addition, the designer does not have to be concerned about generating wait states where the outputs are unaffected because these can be timed from the binary counter. For detailed information and examples using this design concept, see A Designer’s Guide to the TIBPSG507 applications report. OR term loading As shown in Figure 3 and by the fmax calculation, fmax is affected by the number of terms connected to each OR array line. Theoretically, fmax is calculated as: 1 fmax = t su t CLK to Q pd Since the setup time (input or feedback to S/R↓) varies with the number of terms connected to each OR array line, (due to capacitance loading) fmax will also vary. Figure 3 illustrates the relationship between the number of terms connected per OR line and the setup time. ) Use Figure 3 to determine the worst-case setup time for a particular application. Identify the OR array line with the maximum number of terms connected. Count the number of terms and use the graph to determine the setup time. WORST-CASE SETUP TIME (input or feedback to SR↓) vs ”OR” TERM LOAD 20 VCC = 4.75 V TA = 75°C 19 t su – Setup Time – ns 18 17 16 15 14 13 12 11 10 0 20 40 60 Maximum Number of OR Terms Connected Figure 3 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 80 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 fmax with external feedback The configuration shown is a typical state-machine design with feedback signals sent off-chip. This external feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining the clock period is the sum of the clock-to-output delay time and the setup time for the input or feedback signals (tsu + tpd CLK to Q). Thus: fmax with external feedback = CLK t su ) 1 t pd CLK to Q Internal SR Registers Logic Array Input Output SR Registers Next Device tpd CLK to Q tsu Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 APPLICATION INFORMATION The TIBPSG507AC is used in this application to generate the required memory timing control signals (RAS, CAS, etc.) for the memory timing controller. RFC Dynamic RAM Refresh Timer Dynamic Memory Controller SN74ALS6301 REFEQ REFREQ Memory Timing Controller TIBPSG507A OSC Clock Generator RFC CLK Q0-Q8 VCC LE RESET RAASI CAASI MSEL MC1 WAIT R/W A22 ALE AS A0-A8 RAS0 CAS0 W A0-A8 Bank1 1 Meg x 32 Bit TMS4C1027 RAS1 CAS1 W A0-A8 OE CS Bank0 1 Meg x 32 Bit TMS4C1027 Bank2 1 Meg x 32 Bit TMS4C1027 RAS2 CAS2 W Microprocessor SN74ALS6301 A0-A8 Address 2 SEL0,1 Memory Bank Signals Data For detailed information, please see the Systems Solution for Static Column Decode Application Report. Figure 5 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RAS3 CAS3 W Bank3 1 Meg x 32 Bit TMS4C1027 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 1.5 V 1.5 V tw th 3.5 V Data Input 1.5 V 3.5 V 0.3 V In-Phase Output VOH 1.5 V VOL tpd tpd 1.5 V VOH 1.5 V VOL 3.5 V 1.5 V Waveform 1 S1 Closed (see Note B) tdis 1.5 V ≈ 3.3 V VOL +0.5 V VOL tdis ten Waveform 2 S1 Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 0.3 V ten tpd 1.5 V 1.5 V 0.3 V Output Control (low–level enabling) 1.5 V tpd 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 3.5 V Low-Level Pulse 1.5 V 0.3 V Input 1.5 V 0.3 V 0.3 V tsu Out-of-Phase Output (see Note D) 3.5 V High-Level Pulse 3.5 V Timing Input VOH 1.5 V VOH –0.5 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf ≤ 2 ns, duty cycle = 50%. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 6. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE 200 I CC – Supply Current – mA 175 150 125 VCC = 5.25 V VCC = 5 V 100 VCC = 4.75 V 75 50 25 0 0 25 75 50 TA – Free-Air Temperature – °C Figure 7 POWER DISSIPATION vs FREQUENCY 1000 Power Dissipation – mW 950 900 850 TA = 0°C 800 TA = 25°C 750 TA = 50°C 700 1 2 4 7 10 20 40 f – Frequency – MHz Figure 8 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 70 100 TIBPSG507AC 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs SUPPLY VOLTAGE PROPAGATION DELAY TIME vs LOAD CAPACITANCE 30 20 VCC = 5 V R1 = 300 Ω R2 = 390 Ω TA = 25°C tPHL (I or Feedback to Q) 16 25 Propagation Delay Time – ns Propagation Delay Time – ns 18 14 tPLH (I or Feedback to Q) 12 10 tPLH (CLK to Q) 8 6 tPHL (CLK to Q) R1 = 300 Ω R2 = 390 Ω CL = 50 pF TA = 25°C 4 2 20 15 tPHL (I or Feedback to Q) tPLH (I or Feedback to Q) tPLH (CLK to Q) tPHL (CLK to Q) 10 5 0 0 4.75 0 5.25 5 100 VCC – Supply Voltage – V 300 400 500 200 CL – Load Capacitance – pF Figure 10 Figure 9 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING 20 20 18 18 tPHL (I or Feedback to Q) tPHL (I or Feedback to Q) 16 14 Propagation Delay Time – ns Propagation Delay Time – ns 600 tPLH (I or Feedback to Q) 12 10 8 tPLH (CLK to Q) 6 tPHL (CLK to Q) 4 VCC = 5 V R1 = 300 Ω R2 = 390 Ω CL = 50 pF 2 0 0 16 14 tPLH (I or Feedback to Q) 12 10 tPLH (CLK to Q) 8 6 4 2 0 25 0 75 50 tPHL (CLK to Q) VCC = 5 V R1 = 300 Ω R2 = 390 Ω CL = 50 pF TA = 25°C 0 TA – Free-Air Temperature – °C 1 2 3 4 5 6 7 8 Number of Outputs Switching Figure 11 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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