TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 • • • • • • • • JT OR NT PACKAGE (TOP VIEW) 58-MHz Max Clock Rate Two Transition Complement Array Terms CLK I0 I1 I2 I3 I4 I5 Q0 Q1 Q2 Q3 GND 16-Bit Internal State Registers 8-Bit Output Registers Outputs Programmable for Registered or Combinational Operation Ideal for Waveform Generation and High-Performance State Machine Applications Programmable Output Enable Programmable Clock Polarity 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC I6 I7 I8 I9 I10 I11 I12/OE Q7 Q6 Q5 Q4 FK OR FN PACKAGE (TOP VIEW) The outputs of the internal state registers (P0– P15) are fed back and combined with the 13 inputs (I0 – I12) to form the AND array. In addition, two sum terms are complemented and fed back to the AND array, which allows any product term to be summed, complemented, and used as input to the AND array. The eight output cells can be individually programmed for registered or combinational operation. Nonregistered operation is selected by blowing the output multiplexer fuse. Registered output operation is selected by leaving the output multiplexer fuse intact. I2 I3 I4 NC I5 Q0 Q1 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 I8 I9 I10 NC I11 I12/OE Q7 Q2 Q3 GND NC Q4 Q5 Q6 The TIBPLS506AC is a TTL field-programmable state machine of the Mealy type. This state machine (logic sequencer) contains 97 product terms (AND terms) and 48 sum terms (OR terms). The product and sum terms are used to control the 16-bit internal state registers and the 8-bit output registers. I1 I0 CLK NC VCC I6 I7 description NC – No internal connection Pin 17 can be programmed to function as an input and/or an output enable. Blowing the output enable fuse lets pin 17 function as an output enable but does not disconnect pin 17 from the input array. When the output enable fuse is intact, pin 17 functions only as an input with the outputs being permanently enabled. The state and output registers are synchronously clocked by the fuse programmable clock input. The clock polarity fuse selects either postive- or negative-edge triggering. Negative-edge triggering is selected by blowing the clock polarity fuse. Leaving this fuse intact selects positive-edge triggering. After power-up, the device must be initialized to the desired state. When the output multiplexer fuse is left intact, registered operation is selected. The TIBPLS506AC is characterized for operation from 0°C to 75°C. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 2 3 4 5 6 7 23 22 21 20 19 18 17 10450 10560 9570 9680 8690 8800 7810 7920 6930 7040 6050 6160 5170 5280 4290 4400 3410 3520 2530 2640 DETAIL: 1S 0 C1 5 10 15 20 ”AND” Term Numbers 1R Each S-R Flip-Flop MUX 1 1 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 PRE/OE 1650 1760 0 10670 770 880 1 G1 Each Multiplexer 25 30 • DALLAS, TEXAS 75265 ”AND” Term Numbers POST OFFICE BOX 655303 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 C0 P15 26 10671 36 41 46 51 59 C1 60 P15 1S C1 1R 64 68 72 1S C1 1R P14 1S C1 1R P0 1S C1 1R P1 1S C1 1R P2 1S C1 1R P3 1S C1 1R P4 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER CLK SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 2 logic diagram (positive logic) 76 ”OR” Term Numbers 80 84 88 1S C1 1R P6 1S C1 1R P7 1S C1 1R P8 1S C1 1R P9 1S C1 1R P10 1S C1 1R P11 1S C1 1R P12 1S C1 1R P13 1 MUX 1 MUX 96 1 Q5 15 Q6 16 Q7 10677 1 10678 1 3 All inputs to AND gates, exclusive-OR gates, and multiplexers with a blown link assume the logic-1 state. All OR gate inputs with a blown link assume the logic-0 state. 14 10676 1 109 1S C1 1R Q4 G1 1 MUX 108 13 G1 1 MUX 1S C1 1R Q3 10675 1 1S C1 1R 11 G1 1 MUX 104 Q2 G1 1 MUX 1S C1 1R 10 10674 1 1S C1 1R Q1 10673 G1 1 MUX 100 9 10672 G1 1 MUX 1S C1 1R Q0 G1 10679 SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 1S C1 1R 8 G1 1 • DALLAS, TEXAS 75265 1S C1 1R TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER P5 1 POST OFFICE BOX 655303 92 1S C1 1R TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 S-R FUNCTION TABLE (see Note 1) CLK POLARITY FUSE CLK S R STATE REGISTER INTACT ↑ INTACT ↑ L L Q0 L H INTACT L ↑ H L H INTACT ↑ H H INDETERMINATE BLOWN ↓ L L Q0 BLOWN ↓ L H L BLOWN ↓ H L H BLOWN ↓ H H INDETERMINATE NOTE 1: Q0 is the state of the S-R registers before the active clock edge. functional block diagram (positive logic) CLK 16 2 ≥1 97 x 50 C1 & 60 x 97 16 16 2 2x 2 16 x 16 16 x 1R I0 – I11 I12/OE 13 x 1 13 8 8x 8 8 1 1S 1R 13 G1 EN denotes fused inputs 4 1 C1 97 8 12 8 x MUX 8 16 16 16 1S POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 – Q7 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C NOTE 2: These ratings apply except when programming pins during a programming cycle or during diagnostic testing. recommended operating conditions MIN NOM MAX UNIT 4.75 5 5.25 V 5.5 V VCC VIH Supply voltage VIL IOH Low-level input voltage, VCC = 4.75 V High-level output current – 3.2 mA IOL Low-level output current 16 mA tw Pulse duration tsu Setup time before CLK active transition† High-level input voltage, VCC = 5.25 V 2 0.8 Clock high 6 Clock low 6 Input or feedback to S/R↑ inputs Input or feedback to S/R↓ inputs‡ Input or feedback to S/R inputs th TA Hold time after CLK Without C-array ns 12 20 With C-array Input or feedback to S/R inputs ns 25 0 Operating free-air temperature V 0 ns 25 75 °C † The active edge of CLK is determined by the programmed state of CLK polarity fuse. ‡ See the OR term loading section and Figure 3. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = – 18 mA IOH = – 3.2 mA VOL IOZH VCC = 4.75 V, VCC = 5.25 V, IOL = 16 mA VO = 2.7 V IOZL II VCC = 5.25 V, VCC = 5.25 V, IIH IIL IO¶ ICC Ci MIN 2.4 TYP§ MAX UNIT – 1.2 V 3 0.37 V 0.5 V 20 µA VO = 0.4 V VI = 5.5 V –20 µA 0.1 mA VCC = 5.25 V, VCC = 5.25 V, VI = 2.7 V VI = 0.4 V 20 µA – 0.25 mA VCC = 5.25 V, VCC = 5.25 V, VO = 0.5 V See Note 3, –130 mA 210 mA f = 1 MHz, – 30 Outputs open 156 pF f = 1 MHz, VI = 2 V VO = 2 V 7 Co 11 pF Cclk f = 1 MHz, VCLK = 2 V 14 pF § All typical values are at VCC = 5 V, TA = 25°C. ¶ This parameter approximates IOS. The condition VO = 0.5 V takes tester noise into account. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. NOTE 3: When the clock is programmed for negitive edge, then VI = 4.75 V. When the clock is programmed for positive edge, then VI = 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fmax‡ FROM (INPUT) TO (OUTPUT) MIN TYP† Without C-array 58 65 With C-array 33 45 External feedback without C-array 45 60 40 TEST CONDITION R1 = 300 Ω, 28.5 R2 = 390 Ω, 6 25 Q (registered) See Figure 5 3 10 ten tdis CLK UNIT MHz Q (nonregistered) External feedback with C-array tpd MAX ns I or Feedback Q (nonregistered) 6 20 ns OE↓ Q 1 6 10 ns OE↑ Q 1 6 10 ns † All typical values are at VCC = 5 V, TA = 25°C. ‡ See the fmax calculations section. fmax calculations The following is a brief description of how the different operating frequencies can be achieved when using the TIBPLS506A. t su ) 1 (12 + 5) ns + fmax without C-(complementary) array = 1 where setup time tsu before CLK at the S/R CLK to Q pd register inputs = 12 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5ns (difference in tpd from CLK and feedback, 25 to 20). Thus: fmax for this condition fmax with the C-array = + ) t + 1 17 ns 58 MHz. 1 where tsu setup time before CLK at the S/R register CLK to Q pd inputs = 25 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5 ns (difference in tpd from CLK and feedback, 25 to 20) t su Thus: fmax for this condition + t + 1 (25 + 5) ns fmax external feedback without the C-array = + 1 30 ns ) 33 MHz. 1 where setup time tsu before CLK at the CLK to Q pd S/R register inputs = 12 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 10 ns Thus: fmax for this condition + t su 1 (12 + 10) ns fmax external feedback with the C-array = + ) t 1 22 ns + 45 MHz. 1 where setup time tsu before CLK at the S/R CLK to Q pd register inputs = 25 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 10 ns. Thus: fmax for this condition 6 + t su 1 (25 + 10) ns t + POST OFFICE BOX 655303 1 35 ns + 28.5 MHz. • DALLAS, TEXAS 75265 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 Dedicated Inputs tmin(2) Min Clock Period for This Path c a, b C Array a Internal SRs b, c SR tsu(a) I to Internal S or R, Data Through C Array CLK SR Feedback Lines SR tmin(3) Min Clock Period for This Path SR tsu(2) I to Internal S or R CLK Internal Output SRs tmin(1) Min Clock Period for This Path CLK SR tpd(3) CLK Internal to Output Response SR tsu(b) or tmin(c) tpd(b) or tpd(c) SR tpd(2) CLK to Q Pin tsu(1) I to Output S or R tpd(1) I to Output Pin Dedicated Inputs Output Pin Figure 1. Timing Model POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 glossary — timing model tpd(1) — Maximum time interval from the time a signal edge is received at any input pin to the time any logically affected combinational output pin delivers a response. tpd(2) — Maximum time interval from a positive edge on the clock input pin to data delivery on the output pin corresponding to any output SR register. tpd(3) — Maximum time interval from the positive edge on the clock input pin to the response on any logically affected combinational configured output (at the pin), where data origin is any internal SR register. tpd(b) — Maximum time interval from the time a signal edge is received at any input pin to the time any logically affected combinational output pin delivers a response, where data passes through a C-array once before reaching the affected output. tpd(c) — Maximum time interval from the positive edge on the clock input pin to the response on any logically affected combinational configured output (at the pin), where data origin is any internal SR register and data passes once through a C-array before reaching an affected output. tsu(1) — Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin when data affects the S or R line of any output SR register. tsu(2) — Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin when data affects the S or R line of any internal SR register. tsu(a) — Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin when data passes once through a C-array before reaching an affected S or R line on any internal SR register. tsu(b) — Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin when data passes once through a C-array before reaching an affected S or R line on any output SR register. tmin(1) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register or counter bit to feed the S or R line of any output SR register. tmin(2) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register to feed the S or R line of any internal SR register. tmin(3) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register to feed the S or R line of any internal SR register and data passes once through a C-array before reaching an affected S or R line on any internal SR register. tmin(c) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register to feed the S or R line of any output SR register and data passes once through a C-array before reaching an affected S or R line on any output SR register. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 PARAMETER VALUES FOR TIMING MODEL tpd(1) = 20 ns tpd(2) = 10 ns tsu(1) = 12 ns† tsu(2) = 12 ns† tmin(1) = 20 ns tmin(2) = 20 ns tpd(3) = 25 ns tsu(a) = 25 ns tmin(3) = 25 ns tsu(b) = 25 ns tmin(c) = 25 ns INTERNAL NODE NUMBERS Q0-Q7 RESET 25-32 C0 65 C1 66 P0-P15 SET 33-48 RESET 49-64 † Use tsu = 20 ns for applications where the setup time for S/R↓ inputs are required. diagnostics A diagnostic mode is provided with these devices that allows the user to inspect the contents of the state registers. The step-by-step procedures required to use the diagnostics follow. Step 1. Step 2. Step 3. Disable all outputs by taking pin 17 (OE) high (see Note 4). Take pin 8 (Q0) to VIHH to enable the diagnostics test sequence. Apply appropriate levels of voltage to pins 11 (Q3), 13 (Q4), and 14 (Q5) to select the desired state register (see Table 1). The voltage level monitored on pin 9 will indicate the state of the selected state register. NOTE 4: If pin 17 is being used as an input to the array, then pin 7 (I5) must be taken to VIHH before pin 17 is taken high. VIHH† I5 Pin 7 VIH OE Pin 17 100 ns VOHH VOH Q0 Pin 8 VOL 100 ns VOHH VOH Q3, Q4, Q5 Pins 11, 13, 14 VOL 100 ns Q1 Pin 9 VOH VOL † VIHH = 10.25 V min, 10.5 V nom, 10.75 V max Figure 2. Diagnostics Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 Table 1. Addressing State Registers During Diagnostics† REGISTER BINARY ADDRESS BURIED REGISTER PIN 11 PIN13 PIN 14 L L L SELECTED C1 L L H P15 L L HH C0 L H L P14 L H H P0 L H HH P1 L HH L P2 L HH H P3 L HH HH P4 H L L P5 H L H P6 H L HH P7 H H L P8 H H H P9 H H HH P10 H HH L P11 H HH H P12 H HH HH P13 † VIHH = 10.25 V min, 10.5 V nom, 10.75 V max programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers that are capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 OR term loading As shown in Figure 3 and by the fmax calculations, fmax is affected by the number of terms connected to each OR array line. Theoretically, fmax is calculated as: fmax = t su ) 1 t pd CLK to Q Since the setup time (input or feedback to S/R↓) varies with the number of terms connected to each OR array line, (due to capacitance loading) fmaxwill also vary. Figure 3 illustrates the relationship between the number of terms connected per OR line and the setup time. Use Figure 3 to determine the worst-case setup time for a particular application. Identify the OR array line with the maximum number of terms connected. Count the number of terms and use the graph to determine the setup time. WORST-CASE SETUP TIME (input or feedback to SR↓) vs ”OR” TERM LOAD 20 VCC = 4.75 V TA = 75°C 19 t su – Setup Time – ns 18 17 16 15 14 13 12 11 10 0 20 40 60 80 100 Maximum Number of OR Terms Connected Figure 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 fmax with external feedback The configuration shown is a typical state-machine design with feedback signals sent off-chip. This external feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining the clock period is the sum of the clock-to-output delay time and the setup time for the input or feedback signals (tsu + tpd CLK to Q). Thus: fmax with external feedback = CLK t su ) 1 t pd CLK to Q Internal SR Registers Logic Array Input Output SR Registers tpd CLK to Q tsu Figure 4 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Next Device TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 1.5 V 1.5 V tw th 3.5 V Data Input 1.5 V 3.5 V 0.3 V In-Phase Output VOH 1.5 V VOL tpd tpd 1.5 V VOH 1.5 V VOL 3.5 V 1.5 V Waveform 1 S1 Closed (see Note B) tdis 1.5 V ≈ 3.3 V VOL +0.5 V VOL tdis ten Waveform 2 S1 Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 0.3 V ten tpd 1.5 V 1.5 V 0.3 V Output Control (low–level enabling) 1.5 V tpd 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 3.5 V Low-Level Pulse 1.5 V 0.3 V Input 1.5 V 0.3 V 0.3 V tsu Out-of-Phase Output (see Note D) 3.5 V High-Level Pulse 3.5 V Timing Input VOH 1.5 V VOH –0.5 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf ≤ 2 ns, duty cycle = 50%. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 5. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE 200 I CC – Supply Current – mA 175 150 125 VCC = 5.25 V VCC = 5 V 100 VCC = 4.75 V 75 50 25 0 0 25 75 50 TA – Free-Air Temperature – °C Figure 6 POWER DISSIPATION vs FREQUENCY 1000 Power Dissipation – mW 950 900 850 TA = 0°C 800 TA = 25°C 750 TA = 50°C 700 1 2 4 7 10 20 40 f – Frequency – MHz Figure 7 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 70 100 TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs SUPPLY VOLTAGE PROPAGATION DELAY TIME vs LOAD CAPACITANCE 30 20 VCC = 5 V R1 = 300 Ω R2 = 390 Ω TA = 25°C 25 tPHL (I or Feedback to Q) 16 Propagation Delay Time – ns Propagation Delay Time – ns 18 14 tPLH (I or Feedback to Q) 12 10 8 tPLH (CLK to Q) 6 tPHL (CLK to Q) R1 = 300 Ω R2 = 390 Ω CL = 50 pF TA = 25°C 4 2 20 15 tPHL (I or Feedback to Q) tPLH (I or Feedback to Q) tPLH (CLK to Q) tPHL (CLK to Q) 10 5 0 0 4.75 0 5.25 5 100 VCC – Supply Voltage – V 300 400 500 200 CL – Load Capacitance – pF Figure 9 Figure 8 PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING 20 20 18 18 tPHL (I or Feedback to Q) 14 Propagation Delay Time – ns Propagation Delay Time – ns PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 16 tPLH (I or Feedback to Q) 12 10 8 tPLH (CLK to Q) 6 tPHL (CLK to Q) 4 VCC = 5 V R1 = 300 Ω R2 = 390 Ω CL = 50 pF 2 0 0 tPHL (I or Feedback to Q) 16 14 tPLH (I or Feedback to Q) 12 10 tPLH (CLK to Q) 8 6 4 0 50 75 tPHL (CLK to Q) VCC = 5 V R1 = 300 Ω R2 = 390 Ω CL = 50 pF TA = 25°C 2 25 600 0 TA – Free-Air Temperature – °C 1 2 3 4 5 6 7 8 Number of Outputs Switching Figure 10 Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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