MC74LCX74 Low-Voltage CMOS Dual D-Type Flip-Flop With 5 V−Tolerant Inputs The MC74LCX74 is a high performance, dual D−type flip−flop with asynchronous clear and set inputs and complementary (O, O) outputs. It operates from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX74 inputs to be safely driven from 5.0 V devices. The MC74LCX74 consists of 2 edge−triggered flip−flops with individual D−type inputs. The flip−flop will store the state of individual D inputs, that meet the setup and hold time requirements, on the LOW−to−HIGH Clock (CP) transition. Designed for 2.3 V to 3.6 V VCC Operation 5.0 V Tolerant Inputs − Interface Capability With 5.0 V TTL Logic LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA • • ESD Performance: • Human Body Model >2000 V Machine Model >200 V These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2012 July, 2012 − Rev. 7 MARKING DIAGRAMS 14 SOIC−14 D SUFFIX CASE 751A 14 1 LCX74G AWLYWW 1 14 Features • • • • • • http://onsemi.com 1 14 1 TSSOP−14 DT SUFFIX CASE 948G 1 A L, WL Y, YY W, WW G or G LCX 74 ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. Publication Order Number: MC74LCX74/D MC74LCX74 SD1 14 13 D2 12 CP2 SD2 O2 11 10 CP1 O2 9 2 D1 3 CP1 4 5 SD1 O1 Q CP Q 6 7 O1 GND CP2 CD2 SD 11 D Q CP Q 13 Figure 2. Logic Diagram PIN NAMES Function Clock Pulse Inputs D1−D2 Data Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs On−On Outputs TRUTH TABLE Inputs Outputs SDn CDn CPn Dn On On Operating Mode L H X X H L Asynchronous Set H L X X L H Asynchronous Clear Undetermined H h L l NC X ↑ ↑ O1 10 CD CP1, CP2 6 O1 1 12 D2 Figure 1. Pinout: 14−Lead (Top View) Pins 5 CD SD2 1 3 D 8 CD1 CD1 SD 2 D1 VCC CD2 4 L L X X H H H H ↑ h H L H H ↑ l L H H H ↑ X NC NC Load and Read Register Hold = High Voltage Level = High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition = Low Voltage Level = Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition = No Change = High or Low Voltage Level and Transitions are Acceptable = Low−to−High Transition = Not a Low−to−High Transition For ICC reasons, DO NOT FLOAT Inputs http://onsemi.com 2 9 8 O2 O2 MC74LCX74 MAXIMUM RATINGS Symbol VCC Parameter Value DC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current Condition Units −0.5 to +7.0 V −0.5 ≤ VI ≤ +7.0 V −0.5 ≤ VO ≤ VCC + 0.5 Output in HIGH or LOW State (Note 1) V −50 VI < GND mA −50 VO < GND mA +50 VO > VCC mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 °C MSL Moisture Sensitivity Level 1 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Operating Data Retention Only Min Type Max 2.0 1.5 2.5, 3.3 2.5, 3.3 3.6 3.6 Units V VI Input Voltage 0 5.5 V VO Output Voltage (HIGH or LOW State) 0 VCC V IOH HIGH Level Output Current VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V −24 −12 −8 IOL LOW Level Output Current VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V +24 +12 +8 TA Operating Free−Air Temperature Dt/DV Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V mA mA −40 +85 °C 0 10 ns/V ORDERING INFORMATION Package Shipping† MC74LCX74DG SOIC−14 (Pb−Free) 55 Units / Rail MC74LCX74DR2G SOIC−14 (Pb−Free) 2500 Tape & Reel MC74LCX74DTG TSSOP−14 (Pb−Free) 96 Units / Rail MC74LCX74DTR2G TSSOP−14 (Pb−Free) 2500 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 MC74LCX74 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol VIH VIL VOH VOL IOFF Characteristic HIGH Level Input Voltage (Note 2) LOW Level Input Voltage (Note 2) HIGH Level Output Voltage LOW Level Output Voltage Condition Min 2.3 V ≤ VCC ≤ 2.7 V 1.7 2.7 V ≤ VCC ≤ 3.6 V 2.0 Max V 2.3 V ≤ VCC ≤ 2.7 V 0.7 2.7 V ≤ VCC ≤ 3.6 V 0.8 VCC − 0.2 2.3 V ≤ VCC ≤ 3.6 V; IOH = −100 mA VCC = 2.3 V; IOH = −8 mA 1.8 VCC = 2.7 V; IOH = −12 mA 2.2 VCC = 3.0 V; IOH = −18 mA 2.4 VCC = 3.0 V; IOH = −24 mA 2.2 Units V V 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA 0.2 VCC = 2.3 V; IOL = 8 mA 0.6 VCC = 2.7 V; IOL = 12 mA 0.4 VCC = 3.0 V; IOL = 16 mA 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 V Power Off Leakage Current VCC = 0, VIN = 3.6 V or VOUT = 3.6 V 10 mA IIN Input Leakage Current VCC = 0 to 3.6 V, VIN = 3.6 V or GND ±5 mA ICC Quiescent Supply Current VCC = 3.6 V, VIN = 3.6 V or VOUT = 3.6 V 10 mA Increase in ICC per Input 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 mA DICC 2. These values of VI are used to test DC electrical characteristics only. AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 W Limits TA = −40°C to +85°C Symbol Parameter VCC = 3.3 V + 0.3 V VCC = 2.7 V VCC = 2.5 V + 0.2 V CL = 50 pF CL = 50 pF CL = 30 pF Waveform Min Max Min Max Max Clock Pulse Frequency 1 150 tPLH tPHL Propagation Delay CPn to On or On 1 1.5 1.5 7.0 7.0 1.5 1.5 8.0 8.0 1.5 1.5 8.4 8.4 ns tPLH tPHL Propagation Delay SDn or CDn to On or On 2 1.5 1.5 7.0 7.0 1.5 1.5 8.0 8.0 1.5 1.5 8.4 8.4 ns ts Setup Time, HIGH or LOW Dn to CPn 1 2.5 2.5 4.0 ns th Hold Time, HIGH or LOW Dn to CPn 1 1.5 1.5 2.0 ns tw CPn Pulse Width, HIGH or LOW SDn or CDn Pulse Width, LOW 4 3.3 3.3 3.3 3.6 4.0 4.0 ns trec Recovery Time SDn or CDn to CPn 3 2.5 3.0 4.5 ns Output−to−Output Skew (Note 3) 1.0 1.0 150 Units fmax tOSHL tOSLH 150 Min MHz ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 4 MC74LCX74 DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Condition Min Typ Max Units VOLP Dynamic LOW Peak Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V 0.8 0.6 V V VOLV Dynamic LOW Valley Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V −0.8 −0.6 V V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol CIN Parameter Condition Typical Units Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 7 pF COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF Vcc Dn Vmi 0V th ts Vcc tw CPn Vmi 0V fmax tPLH, tPHL VOH On, On Vmo VOL WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Vcc SDn 0V Vcc CDn 1.5 V 0V tPLH On tPHL Vmo Vmo VOL VOH tPLH On tPHL Vmo Vmo WAVEFORM 2 − PROPAGATION DELAYS tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 3. AC Waveforms http://onsemi.com 5 MC74LCX74 Vcc tw SDn, CDn Vmi 0V trec Vcc Vmi CPn 0V WAVEFORM 3 − RECOVERY TIME tR = tF = 2.5 ns from 10% to 90%; f = 1 MHz; tw = 500 ns Vcc CPn Vmi Vmi tw 0V Vcc tw SDn, CDn, CPn Vmi Vmi 0V WAVEFORM 4 − PULSE WIDTH tR = tF = 2.5 ns (or fast as required) from 10% to 90%; Output requirements: VOL ≤ 0.8 V, VOH ≥ 2.0 V Vcc Symbol 3.3 V + 0.3 V 2.7 V 2.5 V + 0.2 V Vmi 1.5 V 1.5 V Vcc/2 Vmo 1.5 V 1.5 V Vcc/2 Figure 3. AC Waveforms (Continued) VCC PULSE GENERATOR DUT RT CL = CL = RL = RT = CL RL 50 pF at VCC = 3.3 ± 0.3 V or equivalent (includes jig and probe capacitance) 30 pF at VCC = 2.5 ± 0.2 V or equivalent (includes jig and probe capacitance) R1 = 500 W or equivalent ZOUT of pulse generator (typically 50 W) Figure 4. Test Circuit http://onsemi.com 6 MC74LCX74 PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 7 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74LCX74 PACKAGE DIMENSIONS D SOIC−14 NB CASE 751A−03 ISSUE K A B 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 M C A S B S e DETAIL A h A X 45 _ M A1 C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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