MC74LCX574 Low-Voltage CMOS Octal D-Type Flip-Flop Flow Through Pinout With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The MC74LCX574 is a high performance, non−inverting octal D−type flip−flop operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX574 inputs to be safely driven from 5.0 V devices. The MC74LCX574 consists of 8 edge−triggered flip−flops with individual D−type inputs and 3−state true outputs. The buffered clock and buffered Output Enable (OE) are common to all flip−flops. The eight flip−flops will store the state of individual D inputs that meet the setup and hold time requirements on the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the contents of the eight flip−flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. The OE input level does not affect the operation of the flip−flops. The LCX574 flow through design facilitates easy PC board layout. Features • • • • • • • • • • • Designed for 2.3 to 3.6 V VCC Operation 5 V Tolerant − Interface Capability With 5 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: ♦ Human Body Model >2000 V ♦ Machine Model >200 V These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2012 July, 2012 − Rev. 7 1 http://onsemi.com MARKING DIAGRAMS 20 LCX574 AWLYYWWG SOIC−20 WB DW SUFFIX CASE 751D 1 LCX 574 ALYWG G TSSOP−20 DT SUFFIX CASE 948E A L, WL Y, YY W, WW G or G = = = = = Assembly Location Wafer Lot Year Work Week Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. Publication Order Number: MC74LCX574/D MC74LCX574 OE CP 1 11 2 D0 VCC O0 O1 O2 O3 O4 O5 O6 O7 CP 20 19 18 17 16 15 14 13 12 11 3 D1 4 5 6 7 8 9 10 OE D0 D1 D2 D3 D4 D5 D6 D7 GND D3 D4 D5 Pins Function OE Output Enable Input CP Clock Pulse Input D0−D7 Data Inputs O0−O7 3−State Outputs 16 nCP O3 Q 15 nCP O4 Q 14 nCP O5 Q D 8 D6 13 nCP O6 Q D 9 D7 O2 Q D 7 PIN NAMES 17 nCP D 6 Figure 1. Pinout: 20−Lead (Top View) O1 Q D 5 3 18 nCP D D2 2 O0 Q D 4 1 19 nCP 12 nCP Q D Figure 2. Logic Diagram TRUTH TABLE INPUTS H h L l NC X Z ↑ ↑ INTERNAL LATCHES OUTPUTS OE CP Dn Q On OPERATING MODE L L ↑ ↑ l h L H L H Load and Read Register L ↑ X NC NC Hold and Read Register H ↑ X NC Z Hold and Disable Outputs H H ↑ ↑ l h L H Z Z Load Internal Register and Disable Outputs = = = = = = = = = High Voltage Level High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition Low Voltage Level Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition No Change High or Low Voltage Level and Transitions are Acceptable High Impedance State Low−to−High Transition Not a Low−to−High Transition; For ICC Reasons, DO NOT FLOAT Inputs http://onsemi.com 2 O7 MC74LCX574 MAXIMUM RATINGS Symbol VCC Parameter Value DC Supply Voltage Condition Units −0.5 to +7.0 V V VI DC Input Voltage −0.5 ≤ VI ≤ +7.0 VO DC Output Voltage −0.5 ≤ VO ≤ +7.0 Output in 3−State V −0.5 ≤ VO ≤ VCC + 0.5 (Note 1) V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA +50 VO > VCC mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA ±100 mA −65 to +150 °C IGND DC Ground Current Per Ground Pin TSTG Storage Temperature Range MSL Moisture Sensitivity Level 1 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Output in HIGH or LOW State. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Operating Data Retention Only Min Typ Max 2.0 1.5 3.3 3.3 3.6 3.6 Units V VI Input Voltage 0 5.5 VO Output Voltage (HIGH or LOW State) (3−State) 0 0 VCC 5.5 IOH HIGH Level Output Current, VCC = 3.0 V − 3.6 V −24 mA IOL LOW Level Output Current, VCC = 3.0 V − 3.6 V 24 mA IOH HIGH Level Output Current, VCC = 2.7 V − 3.0 V −12 mA IOL LOW Level Output Current, VCC = 2.7 V − 3.0 V TA Operating Free−Air Temperature Dt/DV Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V V V 12 mA −40 +85 °C 0 10 ns/V ORDERING INFORMATION Package Shipping† MC74LCX574DWR2G SOIC−20 (Pb−Free) 1000 Tape & Reel MC74LCX574DWR2G SOIC−20 (Pb−Free) 1000 Tape & Reel MC74LCX574DTR2G SOEIAJ−20 (Pb−Free) 2000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 MC74LCX574 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol Characteristic Condition Min 2.0 VIH HIGH Level Input Voltage (Note 2) 2.7 V ≤ VCC ≤ 3.6 V VIL LOW Level Input Voltage (Note 2) 2.7 V ≤ VCC ≤ 3.6 V VOH HIGH Level Output Voltage VOL LOW Level Output Voltage IOZ 3−State Output Current IOFF Power Off Leakage Current IIN Input Leakage Current ICC Quiescent Supply Current DICC Increase in ICC per Input Max V 0.8 2.7 V ≤ VCC ≤ 3.6 V; IOH = −100 mA VCC − 0.2 VCC = 2.7 V; IOH = −12 mA 2.2 VCC = 3.0 V; IOH = −18 mA 2.4 VCC = 3.0 V; IOH = −24 mA 2.2 Units V V 2.7 V ≤ VCC ≤ 3.6 V; IOL = 100 mA 0.2 V VCC = 2.7 V; IOL = 12 mA 0.4 VCC = 3.0 V; IOL = 16 mA 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 VCC = 3.6 V, VIN = VIH or VIL, VOUT = 0 to 3.6 V ±5 mA VCC = 0, VIN = 3.6 V or VOUT = 3.6 V 10 mA VCC = 0 to 3.6 V, VIN = 3.6 V or GND ±5 mA VCC = 3.6 V, VIN = 3.6 V or VOUT = 3.6 V ±10 mA 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 mA 2. These values of VI are used to test DC electrical characteristics only. AC CHARACTERISTICS (tR = tF = 2.5 ns; CL = 50 pF; RL = 500 W) Limits TA = −40°C to +85°C VCC = 3.0 V to 3.6 V Symbol Waveform Min fmax Clock Pulse Frequency 1 150 tPLH tPHL Propagation Delay CP to On 1 1.5 1.5 8.5 8.5 1.5 1.5 9.5 9.5 ns tPZH tPZL Output Enable Time to HIGH and LOW Levels 2 1.5 1.5 8.5 8.5 1.5 1.5 9.5 9.5 ns tPHZ tPLZ Output Disable Time from HIGH and LOW Levels 2 1.5 1.5 6.5 6.5 1.5 1.5 7.0 7.0 ns ts Setup TIme, HIGH or LOW Dn to CP 1 2.5 2.5 ns th Hold TIme, HIGH or LOW Dn to CP 1 1.5 1.5 ns tw CP Pulse Width, HIGH or LOW 3 3.3 3.3 ns tOSHL tOSLH Parameter Output−to−Output Skew (Note 3) Max VCC = 2.7 V Min Max Units MHz 1.0 1.0 ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 4 MC74LCX574 DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Condition Min Typ Max Units VOLP Dynamic LOW Peak Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V 0.8 V VOLV Dynamic LOW Valley Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V 0.8 V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol Condition Typical Units Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 7 pF COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF CIN Parameter 2.7 V 2.7 V 1.5 V 1.5 V OE Dn 1.5 V 0V 0V tPZH th ts tPHZ 2.7 V CP VOH - 0.3 V 1.5 V On 1.5 V VCC ≈0V 0V fmax tPLH, tPHL tPZL ≈ 3.0 V VOH On tPLZ 1.5 V On VOL + 0.3 V 1.5 V GND VOL WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns WAVEFORM 1 - PROPAGATION DELAYS, SETUP AND HOLD TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns 2.7 V CP 1.5 V 1.5 V tw 0V 2.7 V tw CP 1.5 V 1.5 V 0V WAVEFORM 3 - PULSE WIDTH tR = tF = 2.5 ns (or fast as required) from 10% to 90%; Output requirements: VOL ≤ 0.8 V, VOH ≥ 2.0 V Figure 3. AC Waveforms http://onsemi.com 5 MC74LCX574 VCC R1 PULSE GENERATOR DUT RT CL Test Switch tPLH, tPHL Open tPZL, tPLZ 6V Open Collector/Drain tPLH and tPHL 6V tPZH, tPHZ GND RL CL = 50 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 500 W or equivalent RT = ZOUT of pulse generator (typically 50 W) Figure 4. Test Circuit http://onsemi.com 6 6V OPEN GND MC74LCX574 PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE G A 20 q X 45 _ E h 1 10 20X B B 0.25 M T A S B S A L H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 7 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74LCX574 PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D 0.100 (0.004) −T− SEATING H DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* PLANE 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74LCX574 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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