SQ9945BEY www.vishay.com Vishay Siliconix Automotive Dual N-Channel 60 V (D-S) 175 °C MOSFET FEATURES PRODUCT SUMMARY VDS (V) • TrenchFET® Power MOSFET 60 RDS(on) () at VGS = 10 V 0.064 RDS(on) () at VGS = 4.5 V 0.082 ID (A) per leg 6 Configuration Dual SO-8 D1 S1 1 8 D1 G1 2 7 D1 S2 3 6 D2 G2 4 5 D2 G1 • 100 % Rg and UIS Tested • AEC-Q101 Qualified • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 D2 G2 S1 S2 N-Channel MOSFET N-Channel MOSFET Top View ORDERING INFORMATION Package SO-8 Lead (Pb)-free and Halogen-free SQ9945BEY-T1-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 60 Gate-Source Voltage VGS ± 20 TC = 25 °C Continuous Drain Current Continuous Source Current (Diode TC = 125 °C Conduction)a Pulsed Drain Currentb Single Pulse Avalanche Current Single Pulse Avalanche Energy Maximum Power Dissipationb L = 0.1 mH TC = 25 °C TC = 125 °C Operating Junction and Storage Temperature Range ID V 5.4 3.1 IS 3.6 IDM 21.5 IAS 8.5 EAS 3.6 PD UNIT 4 1.3 A mJ W TJ, Tstg - 55 to + 175 °C SYMBOL LIMIT UNIT RthJA 112 RthJF 38 THERMAL RESISTANCE RATINGS PARAMETER Junction-to-Ambient Junction-to-Foot (Drain) PCB Mountc °C/W Notes a. Package limited. b. Pulse test; pulse width 300 μs, duty cycle 2 %. c. When mounted on 1" square PCB (FR-4 material). S12-1522-Rev. C, 25-Jun-12 Document Number: 71504 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SQ9945BEY www.vishay.com Vishay Siliconix SPECIFICATIONS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage Gate-Source Threshold Voltage Gate-Source Leakage VDS VGS = 0 V, ID = 250 μA 60 - - VGS(th) VDS = VGS, ID = 250 μA 1.5 2 2.5 VDS = 0 V, VGS = ± 20 V IGSS - - ± 100 VGS = 0 V VDS = 60 V - - 1 - - 50 Zero Gate Voltage Drain Current IDSS VGS = 0 V VDS = 60 V, TJ = 125 °C VGS = 0 V VDS = 60 V, TJ = 175 °C - - 150 On-State Drain Currenta ID(on) VGS = 10 V VDS5 V 20 - - VGS = 10 V ID = 3.4 A - 0.045 0.064 VGS = 10 V ID = 3.4 A, TJ = 125 °C - - 0.110 VGS = 10 V ID = 3.4 A, TJ = 175 °C - - 0.137 VGS = 4.5 V ID = 3.7 A - 0.060 0.082 - 12 - - 375 470 - 70 88 36 Drain-Source On-State Resistancea Forward Transconductancef RDS(on) gfs VDS = 15 V, ID = 3.7 A V nA μA A S Dynamicb Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss - 30 Total Gate Chargec Qg - 8 12 Gate-Source Chargec Qgs - 1.2 1.5 Gate-Drain Chargec Gate Resistance Turn-On Delay Timec Rise Timec Turn-Off Delay Timec Fall Timec VGS = 0 V VDS = 25 V, f = 1 MHz VGS = 10 V VDS = 30 V, ID = 4.3 A Qgd pF nC - 1.7 2.6 f = 1 MHz 2.22 - 6.66 td(on) - 6 9 tr VDD = 30 V, RL = 8.8 ID 3.4 A, VGEN = 10 V, Rg = 1 - 2.8 4.2 - 17 26 - 1.7 3 - - 21.5 A - 0.75 1.1 V Rg td(off) tf ns Source-Drain Diode Ratings and Characteristicsb Pulsed Currenta ISM Forward Voltage VSD IF = 2 A, VGS = 0 V Notes a. Pulse test; pulse width 300 μs, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S12-1522-Rev. C, 25-Jun-12 Document Number: 71504 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SQ9945BEY www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted) 20 20 V GS = 10 V thru 5 V 16 V GS = 4 V ID - Drain Current (A) ID - Drain Current (A) 16 12 8 12 8 4 4 T C = 25 °C V GS = 3 V T C = 125 °C T C = - 55 °C 0 0 0 1 2 3 4 0 5 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) Transfer Characteristics Output Characteristics 600 0.25 C - Capacitance (pF) RDS(on) - On-Resistance (Ω) 500 0.20 0.15 0.10 V GS = 4.5 V Ciss 400 300 200 Coss 100 0.05 V GS = 10 V Crss 0 0 0 4 8 12 16 0 20 10 20 40 50 60 VDS - Drain-to-Source Voltage (V) ID - Drain Current (A) Capacitance On-Resistance vs. Drain Current 2.5 10 ID = 4.3 A ID = 4.3 A 2.1 V DS = 30 V 6 4 V GS = 10 V (Normalized) 8 RDS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) 30 1.7 V GS = 4.5 V 1.3 0.9 2 0 0 2 4 6 Qg - Total Gate Charge (nC) Gate Charge S12-1522-Rev. C, 25-Jun-12 8 10 0.5 - 50 - 25 0 25 50 75 100 125 150 175 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature Document Number: 71504 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SQ9945BEY www.vishay.com Vishay Siliconix 100 0.25 10 0.20 RDS(on) - On-Resistance (Ω) IS - Source Current (A) TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted) T J = 150 °C 1 T J = 25 °C 0.1 0.15 T J = 150 °C 0.10 T J = 25 °C 0.05 0.01 0 0.001 0 0.2 0.4 0.6 0.8 1.0 0 1.2 2 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 75 0.6 ID = 1 mA VDS - Drain-to-Source Voltage (V) VGS(th) Variance (V) 0.3 0 - 0.3 ID = 5 mA - 0.6 ID = 250 μA - 0.9 - 1.2 - 50 - 25 0 25 50 75 100 125 150 72 69 66 63 60 - 50 175 - 25 0 TJ - Temperature (°C) 25 50 75 100 125 150 175 TJ - Junction Temperature (°C) Threshold Voltage Drain Source Breakdown vs. Junction Temperature IDM Limited Limited by RDS(on)* 10 ID - Drain Current (A) 100 µs 1 1 ms 10 ms 100 ms 1s 10 s, DC 0.1 TC = 25 °C Single Pulse 0.01 0.01 0.1 BVDSS Limited 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area S12-1522-Rev. C, 25-Jun-12 Document Number: 71504 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SQ9945BEY www.vishay.com Vishay Siliconix THERMAL RATINGS (TA = 25 °C, unless otherwise noted) 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 2. Per Unit Base = R thJA = 112 °C/W 3. T JM - TA = PDMZthJA(t) Single Pulse 0.01 t1 t2 10- 3 10- 4 4. Surface Mounted 10- 2 10- 1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10- 4 10- 3 10- 2 10- 1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Note • The characteristics shown in the two graphs - Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C) - Normalized Transient Thermal Impedance Junction-to-Foot (25 °C) are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities can widely vary depending on actual application parameters and operating conditions. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71504. S12-1522-Rev. C, 25-Jun-12 Document Number: 71504 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SOIC (NARROW): 8-LEAD JEDEC Part Number: MS-012 8 6 7 5 E 1 3 2 H 4 S h x 45 D C 0.25 mm (Gage Plane) A e B All Leads q A1 L 0.004" MILLIMETERS INCHES DIM Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.20 0.004 0.008 B 0.35 0.51 0.014 0.020 C 0.19 0.25 0.0075 0.010 D 4.80 5.00 0.189 0.196 E 3.80 4.00 0.150 e 0.101 mm 1.27 BSC 0.157 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.50 0.93 0.020 0.037 q 0° 8° 0° 8° S 0.44 0.64 0.018 0.026 ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498 Document Number: 71192 11-Sep-06 www.vishay.com 1 VISHAY SILICONIX TrenchFET® Power MOSFETs Application Note 808 Mounting LITTLE FOOT®, SO-8 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. 0.288 7.3 0.050 1.27 0.196 5.0 0.027 0.69 0.078 1.98 0.2 5.07 Figure 1. Single MOSFET SO-8 Pad Pattern With Copper Spreading Document Number: 70740 Revision: 18-Jun-07 0.050 1.27 0.088 2.25 0.088 2.25 0.027 0.69 0.078 1.98 0.2 5.07 Figure 2. Dual MOSFET SO-8 Pad Pattern With Copper Spreading The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose. Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. www.vishay.com 1 APPLICATION NOTE In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. 0.288 7.3 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SO-8 0.172 (4.369) 0.028 0.022 0.050 (0.559) (1.270) 0.152 (3.861) 0.047 (1.194) 0.246 (6.248) (0.711) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 22 Document Number: 72606 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Material Category Policy Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Revision: 12-Mar-12 1 Document Number: 91000