TCP-3068H Advance Information 6.8 pF Passive Tunable Integrated Circuits (PTIC) Introduction ON Semiconductor’s PTICs have excellent RF performance and power consumption, making them suitable for any mobile handset or radio application. The fundamental building block of our PTIC product line is a tunable material called ParaScant, based on Barium Strontium Titanate (BST). PTICs have the ability to change their capacitance from a supplied bias voltage generated by the Control IC. The 6.8 pF PTICs are available as wafer-level chip scale packages (WLCSP) and in QFN packages for easy mounting directly on printed circuit boards. http://onsemi.com WLCSP 12 pillar CASE TBD QFN 6 pin CASE TBD Key Features • • • • • • • • • High Tuning Range and Operation up to 20 V Usable Frequency Range: from 700 MHz to 2.7 GHz High Quality Factor (Q) for Low Loss High Power Handling Capability Compatible with PTIC Control IC TCC-103 WLCSP Package: 0.722 x 1.179 x 0.611 mm (12 pillar) QFN Package: 1.200 x 1.600 x 0.950 mm QFN: MSL−2 Moisture Sensitivity Level (per J−STD−020) Pb−Free and RoHS Compliant Typical Applications • • • • Multi-band, Multi-standard, Advanced and Simple Mobile Phones Tunable Antenna Matching Networks Tunable RF Filters Active Antennas QFN MARKING DIAGRAM X.XH X.X = 6.8 H = High Tuning FUNCTIONAL BLOCK DIAGRAM PTIC RF1 RF2 Bias Figure 1. PTIC Functional Block Diagram ORDERING INFORMATION Device This document contains information on a new product. Specifications and information herein are subject to change without notice. © Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. P1 1 Package Shipping TCP−3068H−DT WLCSP (Pb−Free) 4000 Units / 7” Reel TCP−3068H−QT QFN (Pb−Free) 8000 Units / 13” Reel For detailed ordering information, including part number definition and capacitance (pF) see the package dimensions section on page 7 of this datasheet. Publication Order Number: TCP−3068H/D TCP−3068H TYPICAL SPECIFICATIONS Representative Performance Data at 255C Table 1. PERFORMANCE DATA Parameter Min Typ Units 20 V Operating Bias Voltage 2.0 Capacitance (Vbias = 2 V) 6.12 6.80 7.48 pF Capacitance (Vbias = 20 V) 1.70 1.79 1.88 pF Tuning Range (2 V - 20 V) 3.40 3.80 4.20 Tuning Range (20 V - 2 V) 3.60 Leakage Current (WLCSP) Operating Frequency 700 2.0 mA 2700 MHz Quality Factor @ 700 MHz, 10 V 100 Quality Factor @ 2.4 GHz, 10 V 75 IP3 (Vbias = 2 V) [1,3] 70 dBm 85 dBm -70 dBm -80 dBm -40 dBm IP3 (Vbias = 20 V) [1,3] 2nd Harmonic (Vbias = 2 V) [2,3] 2nd Harmonic (Vbias = 20 V) 3rd Harmonic (Vbias = 2 V) [2,3] [2,3] 3rd Harmonic (Vbias = 20 V) 1. 2. 3. 4. Max [2,3] -70 dBm Transition Time (Cmin ³ Cmax) [4] 80 ms Transition Time (Cmax ³ Cmin) [4] 70 ms f1 = 850 MHz, f2 = 860 MHz, Pin 25 dBm/Tone 850 MHz, Pin +34 dBm IP3 and Harmonics are measured in the shunt configuration in a 50 W environment RFIN and RFOUT are both connected to DC ground http://onsemi.com 2 TCP−3068H Representative performance data at 255C for 6.8 pF WLCSP Package Figure 2. Capacitance Figure 3. Harmonic Power* Figure 4. IP3* Figure 5. Q* *The data shown is based on the TCP−3068N device performance, for reference only. The TCP−3068H performance data will be available in the Production Datasheet. Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Input Power +40 dBm Bias Voltage +25 (Note 5) V Operating Temperature Range −30 to +85 °C Storage Temperature Range −55 to +125 °C ESD − Human Body Model Class 1A JEDEC HBM Standard (Note 6) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 5. WLCSP: Recommended Bias Voltage not to exceed 20 V 6. Class 1A defined as passing 250 V, but may fail after exposure to 500 V ESD pulse http://onsemi.com 3 TCP−3068H PACKAGE INFORMATION QFN Package Layout and Dimensional Information PIN #1 ID 0.100 X 45° Chamfer 0.950 mm ±0.050 mm 1.200 mm ±0.050 mm 3X 0.700 mm 3X 0.250 mm 2X 0.300 mm X.XH 1.600 mm ±0.050 mm 4X 0.500 mm N/C RF2 RF1 RF2 RF1 6X 0.350 mm ±0.030 mm 6X 0.075 mm SIDE VIEW TOP VIEW (Seen Through Package) Metal Pads Far Side 4X 0.575 mm 4X 0.475 mm 3X 0.200 mm 6X 0.575 mm 6X 0.300 mm 0.475 mm 4X 0.100 mm Bias N/C RF2 RF1 RF2 RF1 6X 0.250 mm ±0.030 mm 4X 0.175 mm 0.000 mm / 0.050 mm TOP VIEW (Note: X.X reflects the PTIC value e.g.: 6.8 indicates 6.8 pF) Bias 2X 0.100 mm 6X 0.400 mm 2X 0.900 mm 6X PCB Top Solder Mask Opening 4X PCB Top Metal 4X PCB Top Metal 6X PCB Top Solder Mask Opening Recommended PCB Pad Layout For 6 Pin Package (Metal Defined Pads) 2X 0.400 mm Bias N/C RF2 RF1 RF2 RF1 6X 0.300 mm 2X 0.200 mm Recommended PCB Pad Layout For 6 Pin Package (Solder Mask Defined Pads) Note: 2X means 2 sites with the specific value 3X means 3 sites with the specific value 4X means 4 sites with the specific value 0.9 mm pad layout is standard for all products. Shorter pad layouts can be considered for smaller products. Figure 6. QFN Pin Markers and Dimensions http://onsemi.com 4 TCP−3068H Wafer Level Chip Scale Package (WLCSP) Layout and Dimensional Information D3 D2 (Copper Pillar Height) D1 A2 C1 C2 C3 2X 0.104 mm (Typ) (Copper Pillar) N/C Bias 2X 0.069 mm (Typ) (Copper Pillar) B3 RF1 RF2 A1 B2 B2 Top View (Pillars Down) B4 Side View Note: 2X means 2 sites with the specific value 3X means 3 sites with the specific value 4X means 4 sites with the specific value RF1 RF2 RF1 RF2 RF1 RF2 RF1 RF2 RF Pillars 0.104 mm (Typ) B1 Bottom View (Pillars Up) RF Pillars 0.069 mm (Typ) Figure 7. WLCSP Pin Markers and Dimensions Table 3. PACKAGE DIMENSIONS (All dimensions are in milimeters) WLCSP * DIM Nominal Max Device 8P A1 0.879 1.2, 2.7 pF 10P A1 1.029 3.3, 3.9 pF 12P A1 1.179 4.7, 5.6, 6.8, 8.2 pF 14P A1 1.329 ALL A2 0.722 ALL B1 0.460 ALL B2 0.150 ALL B3 0.300 ALL B4 0.130 ALL C1 0.148 ALL C2 0.425 Note: 0.9 mm pad layout is standard for all products. Shorter pad layouts can be considered for smaller products. ALL C3 0.130 Figure 8. Recommended Pad Layout ALL D1 0.530 ALL D2 0.081 *Total number of pillars http://onsemi.com 5 TCP−3068H ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE Molding The following assembly considerations should be observed: The PTIC die is compatible for over-molding or under-fill. Cleanliness These chips should be handled in a clean environment. Electro-static Sensitivity ON Semiconductor’s PTICs are ESD Class 1A sensitive. The proper ESD handling procedures should be used. Mounting The WLCSP PTIC is fabricated for Flip Chip solder mounting. Connectivity to the RF and Bias terminations on the PTIC die is established through copper pillar posts (53 mm nominal height) topped with lead-free SAC351 solder caps (28 mm nominal height). The PTIC die is RoHS-compliant and compatible with lead-free soldering profile. Post-reflow Cleaning Use of ultrasonic cleaning is not recommended for pillared devices as it may lead to premature fatigue failure of the pillars. Figure 9. Reflow Profile ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES RF When configuring the PTIC in your specific circuit design, at least one of the RF terminals must be connected to DC ground. If minimum transition times are required, DC ground on both RF terminals is recommended. To minimize losses, the PTIC should be oriented such that RF2 is at the lower RF impedance of the two RF nodes. A shunt PTIC, for example, should have RF2 connected to RF ground. ANT RF1 (PTIC Pad) RF2 (PTIC Pad) Bias Figure 10. PTIC Orientation Functional Block Diagram http://onsemi.com 6 TCP−3068H PART NUMBER DEFINITION Example: TCP−3068H−DT TCP - 30 68 H - D T Product Family Process Status Process Generation Capacitor Value Tuning Package / Format Packing TCP “blank” = Production X = Pilot Production 10= Gen 1.0 30= Gen 3.0 12 = 1.2pF 27 = 2.7pF 33 = 3.3pF 39 = 3.9pF 47 = 4.7pF 56 = 5.6pF 68 = 6.8pF 82 = 8.2pF N = Normal H = High D = WLCSP Q = QFN T = T&R - S= Special/Custom P = Prototype - Table 4. PART NUMBERS Capacitance 2V 20 V Package* TCP−3068H-DT 6.80 1.79 12-Pillar WLCSP TCP−3068H-QT 6.80 1.79 6-Pin QFN Part Number *See PTIC package dimensions on page 5 http://onsemi.com 7 TCP−3068H TAPE & REEL DIMENSIONS 4.00 ± 0.10 2.00 ± 0.05 4.00 ± 0.10 ∅ 1.50 + 0.10 1.75 ± 0.10 3.50 ± 0.05 8.00 + 0.30 − 0.10 0.20 0.20 ± 0.02 45° 0° 0.82 ± 0.05 Ao 45° 0° 0.76 ± 0.05 Ko 1.28 ± 0.05 Bo Note: The reel size is 7” Pocket may have a hole 0.2 mm to 0.4 mm ± 0.05 mm Figure 11. 12 Pillar WLCSP Carrier Tape Drawing http://onsemi.com 8 TCP−3068H TAPE & REEL DIMENSIONS (Cont’d) 4.00 ± 0.10 2.00 ± 0.05 4.00 ± 0.10 ∅ 1.50 + 0.10 1.75 ± 0.10 3.50 ± 0.05 8.00 + 0.30 − 0.10 ∅ 0.60 ± 0.05 Pin 1 (Upper Left) 0.25 ± 0.02 5° MAX 1.32 ± 0.05 5° MAX 1.82 ± 0.05 1.10 ± 0.05 Ao Ko Bo Figure 12. QFN Carrier Tape Drawing POCKET DIMENSION Pocket Dimension (mm) Unit Dimension (mm) Spec Max Min Spec Max Min Ao 1.32 ± 0.05 1.37 1.27 A 1.2 ± 0.05 1.25 1.15 Bo 1.82 ± 0.05 1.87 1.77 B 1.6 ± 0.05 1.65 1.55 Ko 1.1 ± 0.05 1.15 1.05 K 0.95 ± 0.05 1.00 0.90 NOTE: The reel size is 13” ParaScan is a trademark of Paratek Microwave, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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