dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, ADC and Comparators Operating Conditions Advanced Analog Features (Continued) • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS • ADC module: - 10-bit resolution with Successive Approximation Register (SAR) converter (2 Msps) and three Sample-and-Hold (S&H) circuits - Up to 8 input channels grouped into four conversion pairs, plus two inputs for monitoring voltage references - Flexible and independent ADC trigger sources - Dedicated Result register for each analog channel Core: 16-Bit dsPIC33F CPU • • • • • Code Efficient (C and Assembly) Architecture Two 40-Bit Wide Accumulators Single-Cycle (MAC/MPY) with Dual Data Fetch Single-Cycle Mixed-Sign MUL plus Hardware Divide 32-Bit Multiply Support Clock Management Timers/Output Compare/Input Capture • • • • • • • • • ±2% Internal Oscillator Programmable PLLs and Oscillator Clock Sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer (WDT) Fast Wake-up and Start-up Power Management • • • • Low-Power Management modes (Sleep, Idle, Doze) Integrated Power-on Reset and Brown-out Reset 2.0 mA/MHz Dynamic Current (typical) 135 µA IPD Current (typical) High-Speed PWM • Up to Three PWM Pairs with Independent Timing • Dead Time for Rising and Falling Edges • 1.04 ns PWM Resolution for Dead Time, Duty Cycle, Phase and Frequency • PWM Support for: - DC/DC, AC/DC, Inverters, PFC and Lighting • Programmable Fault Inputs • Flexible Trigger Configurations for ADC Conversions Advanced Analog Features • Two High-Speed Comparators with Direct Connection to the PWM module: - Buffered/amplified output drive - Independent 10-bit DAC for each comparator - Rail-to-rail comparator operation - DACOUT amplifier (1x, 1.8x) - Selectable hysteresis - Programmable output polarity - Interrupt generation capability 2011-2012 Microchip Technology Inc. Two 16-Bit General Purpose Timers/Counters Input Capture module Output Compare module Peripheral Pin Select (PPS) to allow Function Remap Communication Interfaces • UART module (10 Mbps): - With support for LIN/J2602 protocols and IrDA® • 4-Wire SPI module • I2C™ module (up to 1 Mbaud) with SMBus Support • PPS to allow Function Remap Input/Output • Constant Current Source: - Constant current generator (10 µA nominal) • Sink/Source 18 mA on 8 Pins and 6 mA on 13 Pins • 5V Tolerant Pins • Selectable Open-Drain and Pull-ups • External Interrupts on 16 I/O Pins Qualification and Class B Support • AEC-Q100 REVG (Grade 1, -40ºC to +125ºC) Planned • Class B Safety Library, IEC 60730 Debugger Development Support • • • • In-Circuit and In-Application Programming Two Breakpoints IEEE 1149.2 Compatible (JTAG) Boundary Scan Trace and Run-Time Watch DS75018C-page 1 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table 1. The following pages show their pinout diagrams. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES Input Capture Output Compare UART SPI PWM(2) Analog Comparator External Interrupts(1) DAC Output Constant Current Source Reference Clock I2C™ SARs Sample-and-Hold (S&H) Circuit Analog-to-Digital Inputs 256 8 2 0 0 0 0 2x2 2 3 0 0 0 1 1 2 6 PDIP, 13 SOIC SSOP 6 256 8 2 0 1 1 1 2x2 0 3 0 0 1 1 1 3 6 PDIP, 13 SOIC SSOP 20 dsPIC33FJ06GS101A 18 20 dsPIC33FJ06GS102A 28 6 256 16 2 0 1 1 1 2x2 0 3 0 0 1 1 1 3 6 36 dsPIC33FJ06GS202A 28 28 6 1K 16 2 1 1 1 1 2x2 2 3 1 0 1 1 1 3 6 9 1K 16 2 1 1 1 1 3x2 2 3 1 1 1 1 1 3 8 SPDIP, SOIC, 21 SSOP, QFN-S VTLA 1: INT0 is not remappable. 2: The PWM4 pair is remappable and only available on dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices. DS75018C-page 2 SPDIP, SOIC, 21 SSOP, QFN-S VTLA 36 Note SPDIP, SOIC, 21 SSOP, QFN-S VTLA 36 dsPIC33FJ09GS302 Packages 16-Bit Timer 6 I/O Pins Remappable Pins 18 ADC RAM (Bytes) dsPIC33FJ06GS001 Remappable Peripherals Program Flash Memory (Kbytes) Device Pins TABLE 1: 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams = Pins are up to 5V tolerant 18-Pin SOIC, PDIP 1 18 2 17 VSS AN1/CMP1B/RA1 3 16 PWM1L/RA3 15 PWM1H/RA4 14 VCAP 13 VSS 12 11 PGEC1/SDA1/RP7(1)/CN7/RB7 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 dsPIC33FJ06GS001 MCLR AN0/CMP1A/RA0 AN2/CMP1C/CMP2A/RA2 4 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 5 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 6 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 PGED2/TCK/INT0/RP3(1)/CN3/RB3 7 8 PGEC2/TMS/EXTREF/RP4(1)/CN4/RB4 9 10 VDD 1 18 VDD 2 17 VSS AN1/RA1 3 16 PWM1L/RA3 AN2/RA2 4 15 PWM1H/RA4 AN3/RP0(1)/CN0/RB0 5 14 VCAP OSC1/CLKI/AN6/RP1(1)/CN1/RB1 6 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 PGED2/TCK/INT0/RP3(1)/CN3/RB3 7 8 PGEC2/TMS/RP4(1)/CN4/RB4 9 dsPIC33FJ06GS101A MCLR AN0/RA0 13 VSS 12 11 PGEC1/SDA1/RP7(1)/CN7/RB7 10 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 = Pins are up to 5V tolerant 20-Pin SSOP 20 AVDD 2 19 AVSS AN1/CMP1B/RA1 3 18 PWM1L/RA3 AN2/CMP1C/CMP2A/RA2 4 PWM1H/RA4 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 5 17 16 VSS 6 15 VCAP OSCI/CLKI/AN6/RP1(1)/CN1/RB1 OSCO/CLKO/AN7/RP2(1)/CN2/RB2 7 8 14 13 VSS PGEC1/SDA1/RP7(1)/CN7/RB7 MCLR PGED2/TCK/INT0/RP3(1)/CN3/RB3 (1) PGEC2/TMS/EXTREF/RP4 /CN4/RB4 VDD 12 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 10 11 TDO/RP5(1)/CN5/RB5 9 1 20 AVDD 2 19 AVSS AN1/RA1 3 18 PWM1L/RA3 AN2/RA2 4 PWM1H/RA4 AN3/RP0(1)/CN0/RB0 5 17 16 VSS 6 15 VCAP OSCI/CLKI/AN6/RP1(1)/CN1/RB1 OSCO/CLKO/AN7/RP2(1)/CN2/RB2 7 8 14 13 VSS PGEC1/SDA1/RP7(1)/CN7/RB7 PGED2/TCK/INT0/RP3(1)/CN3/RB3 9 12 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 11 TDO/RP5(1)/CN5/RB5 PGEC2/TMS/RP4 /CN4/RB4 10 dsPIC33FJ06GS101A MCLR AN0/RA0 (1) Note 1: dsPIC33FJ06GS001 1 AN0/CMP1A/RA0 VDD The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2011-2012 Microchip Technology Inc. DS75018C-page 3 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) = Pins are up to 5V tolerant 28-Pin SOIC, SPDIP, SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC33FJ06GS102A MCLR AN0/RA0 AN1/RA1 AN2/RA2 (1) AN3/RP0 /CN0/RB0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKI/RP1(1)/CN1/RB1 (1) OSC2/CLKO/RP2 /CN2/RB2 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 = Pins are up to 5V tolerant 28-Pin SPDIP, SOIC, SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC33FJ06GS202A MCLR AN0/CMP1A/RA0 AN1/CMP1B/RA1 AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN4/CMP2C/RP9(1)/CN9/RB9 AN5/CMP2D/RP10(1)/CN10/RB10 VSS OSC1/CLKI/RP1(1)/CN1/RB1 OSC2/CLKO/RP2(1)/CN2/RB2 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/EXTREF/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-Pin SPDIP, SOIC, SSOP Note 1: AVDD AVSS PWM1L/RA3 PWM1H/RA4 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA1/RP7(1)/CN7/RB7 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC33FJ09GS302 MCLR AN0/CMP1A/RA0 AN1/CMP1B1/RA1 AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN4/ISRC4/CMP2C/RP9(1)/CN9/RB9 AN5/ISRC3/CMP2D/RP10(1)/CN10/RB10 VSS OSC1/CLKI/AN6/ISRC2/RP1(1)/CN1/RB1 OSC2/CLKO/AN7/ISRC1/RP2(1)/CN2/RB2 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/EXTREF/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 AVDD AVSS PWM1L/RA3 PWM1H/RA4 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA1/RP7(1)/CN7/RB7 PGED1/TDI/1SCL1/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS PWM1L/RA3 PWM1H/RA4 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA1/RP7(1)/CN7/RB7 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15/CN15/RB15 The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. DS75018C-page 4 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) = Pins are up to 5V tolerant AN1/RA1 AN0/RA0 MCLR AVDD AVSS PWM1L/RA3 PWM1H/RA4 28-Pin QFN-S(2) 28 27 26 25 24 23 22 AN2/RA2 AN3/RP0(1)/CN0/RB0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKI/RP1(1)/CN1/RB1 OSC2/CLKO/RP2(1)/CN2/RB2 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA1/RP7(1)/CN7/RB7 PWM1L/RA3 PWM1H/RA4 AVDD AVSS = Pins are up to 5V tolerant MCLR AN1/CMP1B/RA1 28-Pin QFN-S(2) AN0/CMP1A/RA0 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 1 21 2 20 3 19 4 dsPIC33FJ06GS102A 18 5 17 6 16 7 15 8 9 10 11 12 13 14 28 27 26 25 24 23 22 AN2/CMP1C/CMP2A/RA2 1 21 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 2 20 AN4/CMP2C/RP9(1)/CN9/RB9 3 AN5/CMP2D/RP10(1)/CN10/RB10 VSS 4 OSC1/CLKI/RP1(1)/CN1/RB1 OSC2/CLKO/RP2(1)/CN2/RB2 7 19 TCK/RP12(1)/CN12/RB12 18 TMS/RP11(1)/CN11/RB11 5 17 6 16 VCAP VSS 15 PGEC1/SDA1/RP7(1)/CN7/RB7 dsPIC33FJ06GS202A TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 9 10 11 12 13 14 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/EXTREF/RP4(1)/CN4/RB4 VDD 8 Note 1: 2: PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2011-2012 Microchip Technology Inc. DS75018C-page 5 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) 28-Pin QFN-S(2) AN1/CMP1B/RA1 AN0/CMP1A/RA0 MCLR AVDD AVSS PWM1L/RA3 PWM1H/RA4 = Pins are up to 5V tolerant 28 27 26 25 24 23 22 1 2 3 4 dsPIC33FJ09GS302 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA1/RP7(1)/CN7/RB7 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/EXTREF/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 AN2/CMP1C/CMP2A/RA2 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN4/ISRC4/CMP2C/RP9(1)/CN9/RB9 AN5/ISRC3/CMP2D/RP10(1)/CN10/RB10 VSS OSC1/CLKI/AN6/ISRC2/RP1(1)/CN1/RB1 OSC2/CLKO/AN7/ISRC1//RP2(1)/CN2/RB2 Note 1: 2: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS75018C-page 6 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) 36-Pin VTLA AVDD AVSS PWM1L/RA3 RMW1H/RA4 34 AN0/RA0 AN1/RA1 35 MCLR AN2/RA2 36 33 32 31 30 29 28 27 PWM2L/RP14(1)/CN14/RB14 AN4/RP9(1)/CN9/RB9 1 26 PWM2H/RP13(1)/CN13/RB13 AN5/RP10(1)/CN10/RB10 2 25 TCK/RP12(1)/CN12/RB12 NC 3 24 TMS/RP11(1)/CN11/RB11 NC 4 23 VDD VDD 5 22 VCAP VSS 6 21 VSS OSCI/CLKI/RP1(1)/CN1/RB1 7 20 N/C OSCO/CLKO/RP2 /CN2/RB2 8 19 PGEC1/SDA1/RP7(1)/CN7/RB7 NC 9 12 13 14 15 16 17 18 VSS VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 11 VDD 10 PGEC2/RP4(1)/CN4/RB4 dsPIC33FJ06GS102A PGED2/INT0/RP3(1)/CN3/RB3 (1) Note AN3/RP0(1)/CN0/RB0 = Pins are up to 5V tolerant 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2011-2012 Microchip Technology Inc. DS75018C-page 7 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) 36-Pin VTLA Note 1: 2: RMW1H/RA4 33 PWM1L/RA3 AN0/CMP1A/RA0 34 AVSS AN1/CMP1B/RA1 35 MCLR AN2/CMP1C/CMP2A/RA2 36 AVDD AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 = Pins are up to 5V tolerant 32 31 30 29 28 27 PWM2L/RP14(1)/CN14/RB14 AN4/CMP2C/RP9(1)/CN9/RB9 1 26 PWM2H/RP13(1)/CN13/RB13 AN5/CMP2D/RP10(1)/CN10/RB10 2 25 TCK/RP12(1)/CN12/RB12 NC 3 24 TMS/RP11(1)/CN11/RB11 NC 4 23 VDD VDD 5 22 VCAP VSS 6 21 VSS OSCI/CLKI/RP1(1)/CN1/RB1 7 20 N/C OSCO/CLKO/RP2(1)/CN2/RB2 8 19 PGEC1/SDA1/RP7(1)/CN7/RB7 NC 9 VSS VDD 15 16 17 18 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 PGEC2/EXTREF/RP4(1)/CN4/RB4 14 TDO/RP5(1)/CN5/RB5 13 PGEC3/RP15(1)/CN15/RB15 12 VDD 11 PGED3/RP8(1)/CN8/RB8 10 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 dsPIC33FJ06GS202A The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS75018C-page 8 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) 36-Pin VTLA AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN2/CMP1C/CMP2A/RA2 AN1/CMP1B/RA1 AN0/CMP1A/RA0 MCLR AVDD AVSS PWM1L/RA3 RMW1H/RA4 = Pins are up to 5V tolerant 36 35 34 33 32 31 30 29 28 27 PWM2L/RP14(1)/CN14/RB14 1 26 PWM2H/RP13(1)/CN13/RB13 AN5/ISRC3/CMP2D/RP10(1)/CN10/RB10 2 25 TCK/RP12(1)/CN12/RB12 NC 3 24 TMS/RP11(1)/CN11/RB11 NC 4 23 VDD VDD 5 22 VCAP VSS 6 21 VSS OSCI/CLKI/AN6/ISRC2/RP1(1)/CN1/RB1 7 20 N/C OSCO/CLKO/AN7/ISRC1/RP2 /CN2/RB2 8 19 PGEC1/SDA1/RP7(1)/CN7/RB7 NC 9 Note 1: 2: 11 12 13 14 15 16 17 18 VSS VDD VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 (1) PGED1/TDI/SCL1/RP6 /CN6/RB6 10 PGEC2/EXTREF/RP4(1)/CN4/RB4 (1) dsPIC33FJ09GS302 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 AN4/ISRC4/CMP2C/RP9(1)/CN9/RB9 The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2011-2012 Microchip Technology Inc. DS75018C-page 9 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers .......................................................................................... 17 3.0 CPU............................................................................................................................................................................................ 25 4.0 Memory Organization ................................................................................................................................................................. 37 5.0 Flash Program Memory .............................................................................................................................................................. 75 6.0 Resets ....................................................................................................................................................................................... 79 7.0 Interrupt Controller ..................................................................................................................................................................... 87 8.0 Oscillator Configuration ......................................................................................................................................................... 123 9.0 Power-Saving Features............................................................................................................................................................ 137 10.0 I/O Ports ................................................................................................................................................................................... 145 11.0 Timer1 ...................................................................................................................................................................................... 173 12.0 Timer2 Features ....................................................................................................................................................................... 175 13.0 Input Capture............................................................................................................................................................................ 177 14.0 Output Compare....................................................................................................................................................................... 179 15.0 High-Speed PWM..................................................................................................................................................................... 183 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 205 17.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 211 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 219 19.0 High-Speed 10-Bit Analog-to-Digital Converter (ADC)............................................................................................................. 225 20.0 High-Speed Analog Comparator .............................................................................................................................................. 243 21.0 Constant Current Source.......................................................................................................................................................... 249 22.0 Special Features ...................................................................................................................................................................... 251 23.0 Instruction Set Summary .......................................................................................................................................................... 259 24.0 Development Support............................................................................................................................................................... 267 25.0 Electrical Characteristics .......................................................................................................................................................... 271 26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 315 27.0 Packaging Information.............................................................................................................................................................. 319 Appendix A: Revision History............................................................................................................................................................. 339 Index ................................................................................................................................................................................................. 341 DS75018C-page 10 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2011-2012 Microchip Technology Inc. DS75018C-page 11 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered the primary reference for the operation of a particular module or device feature. Note: • • • • • • • • • • • • • • • • • • • • • To access the documents listed below, visit the Microchip web site (www.microchip.com). Section 1. “Introduction” (DS70197) Section 2. “CPU” (DS70204) Section 3. “Data Memory” (DS70202) Section 4. “Program Memory” (DS70203) Section 5. “Flash Programming” (DS70191) Section 8. “Reset” (DS70192) Section 9. “Watchdog Timer (WDT) and Power-Saving Modes” (DS70196) Section 10. “I/O Ports” (DS70193) Section 11. “Timers” (DS70205) Section 12. “Input Capture” (DS70198) Section 13. “Output Compare” (DS70209) Section 17. “UART” (DS70188) Section 18. “Serial Peripheral Interface (SPI)” (DS70206) Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) Section 24. “Programming and Diagnostics” (DS70207) Section 25. “Device Configuration” (DS70194) Section 41. “Interrupts (Part IV)” (DS70300) Section 42. “Oscillator (Part IV)” (DS70307) Section 43. “High-Speed PWM” (DS70323) Section 44. “High-Speed 10-Bit ADC” (DS70321) Section 45. “High-Speed Analog Comparator” (DS70296) DS75018C-page 12 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections. The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. This document contains device-specific information for the following dsPIC33F Digital Signal Controller (DSC) devices: • • • • • dsPIC33FJ06GS001 dsPIC33FJ06GS101A dsPIC33FJ06GS102A dsPIC33FJ06GS202A dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. DS75018C-page 13 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 1-1: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 PORTB 16 23 16 16 Remappable Pins Address Generator Units Address Latch Program Memory EA MUX Data Latch ROM Latch 24 Control Signals to Various Blocks Power-up Timer Instruction Reg Literal Data Instruction Decode and Control Timing OSC2/CLKO OSC1/CLKI Generation 16 16 16 DSP Engine Divide Support 16 x 16 W Register Array 16 Oscillator Start-up Timer Power-on Reset FRC/LPRC Oscillators 16-Bit ALU Watchdog Timer Voltage Regulator VCAP Note: 16 Brown-out Reset VDD, VSS MCLR Timer1,2 Constant Current Source UART1 ADC1 OC1 PWM 3x2 Analog Comparator 1, 2 Reference Clock IC1 CNx I2C1 SPI1 Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS75018C-page 14 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type PPS Capable AN0-AN7 I Analog No Analog input channels. CLKI I ST/CMOS No CLKO O — No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I ST/CMOS No OSC2 I/O — No CN0-CN15 I ST No Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. IC1 I ST Yes Capture Input 1. OCFA OC1 I O ST — Yes Yes Compare Fault A input (for Compare Channel 1). Compare Output 1. INT0 INT1 INT2 I I I ST ST ST No Yes Yes External Interrupt 0. External Interrupt 1. External Interrupt 2. RA0-RA4 I/O ST No PORTA is a bidirectional I/O port. RB0-RB15(1) I/O ST No PORTB is a bidirectional I/O port. RP0-RP15(1) Pin Name Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. I/O ST No Remappable I/O pins. T1CK T2CK I I ST ST Yes Yes Timer1 external clock input. Timer2 external clock input. U1CTS U1RTS U1RX U1TX I O I O ST — ST — Yes Yes Yes Yes UART1 Clear-to-Send. UART1 Ready-to-Send. UART1 receive. UART1 transmit. SCK1 SDI1 SDO1 SS1 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. SCL1 SDA1 I/O I/O ST ST No No Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. TMS TCK TDI TDO I I I O TTL TTL TTL — No No No No JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select — = Does not apply Note 1: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for availability. 2: This pin is available on dsPIC33FJ09GS302 devices only. 2011-2012 Microchip Technology Inc. DS75018C-page 15 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS Capable CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D I I I I I I I I Analog Analog Analog Analog Analog Analog Analog Analog No No No No No No No No Comparator 1 Channel A. Comparator 1 Channel B. Comparator 1 Channel C. Comparator 1 Channel D. Comparator 2 Channel A. Comparator 2 Channel B. Comparator 2 Channel C. Comparator 2 Channel D. DACOUT O — No DAC output voltage. ACMP1-ACMP2 O — Yes DAC trigger to PWM module. ISRC1(2) ISRC2(2) ISRC3(2) ISRC4(2) O O O O — — — — No No No No Constant Current Source Output 1. Constant Current Source Output 2. Constant Current Source Output 3. Constant Current Source Output 4. EXTREF I Analog No External voltage reference input for the reference DACs. REFCLKO O — Yes REFCLKO output signal is a postscaled derivative of the system clock. Pin Name Description FLT1-FLT8 I ST Yes Fault inputs to PWM module. SYNCI1-SYNCI2 SYNCO1 PWM1L PWM1H PWM2L PWM2H PWM4L PWM4H I O O O O O O O ST — — — — — — — Yes Yes No No No No Yes Yes External synchronization signal to PWM master time base. PWM master time base for external device synchronization. PWM1 low output. PWM1 high output. PWM2 low output. PWM2 high output. PWM4 low output. PWM4 high output. PGED1 PGEC1 I/O I ST ST No No PGED2 PGEC2 I/O I ST ST No No PGED3(1) PGEC3(1) I/O I ST ST No No Data I/O pin for programming/debugging Communication Channel 1. Clock input pin for programming/debugging Communication Channel 1. Data I/O pin for programming/debugging Communication Channel 2. Clock input pin for programming/debugging Communication Channel 2. Data I/O pin for programming/debugging Communication Channel 3. Clock input pin for programming/debugging Communication Channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD P P No Positive supply for analog modules. This pin must be connected at all times. AVDD is connected to VDD on 18 and 28-pin devices. AVSS P P No Ground reference for analog modules. AVSS is connected to VSS on 18 and 28-pin devices. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP P — No CPU logic filter capacitor connection. VSS P — No Ground reference for logic and I/O pins. Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select — = Does not apply Note 1: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for availability. 2: This pin is available on dsPIC33FJ09GS302 devices only. DS75018C-page 16 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the dsPIC33FJ06GS001/101A/ 102A/202A and dsPIC33FJ09GS302 family of 16-bit Digital Signal Controllers (DSCs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins, regardless if ADC module is not used (see Section 2.2 “Decoupling Capacitors”) • VCAP (see Section 2.3 “Capacitor on Internal Voltage Regulator (VCAP)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP™ Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”) 2011-2012 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high-frequency noise: If the board is experiencing high-frequency noise, upward of tens of MHz, add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible; for example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB track inductance. DS75018C-page 17 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic R R1 VSS VCAP VDD 10 µF Tantalum VDD MCLR C VDD 0.1 µF Ceramic VSS VSS AVSS VDD AVDD 0.1 µF Ceramic VDD 0.1 µF Ceramic 0.1 µF Ceramic 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1 and the inductor capacity greater than 10 mA. Where: CNV ------------f = F 2 1 f = --------------------- 2 LC (i.e., ADC conversion rate/2) 2 1 L = ---------------------- 2f C 2.2.1 A low-ESR (<0.5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a capacitor between 4.7 µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 25.0 “Electrical Characteristics” for additional information. 2.4 Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: • Device Reset • Device Programming and Debugging L1(1) Note Capacitor on Internal Voltage Regulator (VCAP) The placement of this capacitor should be close to the VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 22.2 “On-Chip Voltage Regulator” for details. dsPIC33F VSS 2.3 TANK CAPACITORS During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as shown in Figure 2-2, it is recommended that the capacitor, C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device; typical values range from 4.7 µF to 47 µF. VDD R(1) JP R1(2) MCLR dsPIC33F C Note 1: 2: DS75018C-page 18 EXAMPLE OF MCLR PIN CONNECTIONS R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R1 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2.5 ICSP™ Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins, are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and Input Voltage High (VIH) and Input Voltage Low (VIL) pin requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins), programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™. For more information on MPLAB ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site (www.microchip.com): • “Using MPLAB® ICD 3” (poster) (DS51765) • “Multi-Tool Design Advisory” (DS51764) • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” (DS51616) • “Using MPLAB® REAL ICE™” (poster) (DS51749) 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Main Oscillator 13 Guard Ring 14 15 Guard Trace Secondary Oscillator 16 17 18 19 20 2011-2012 Microchip Technology Inc. DS75018C-page 19 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside of this range, the application must start up in the FRC mode first. The default PLL settings after a POR, with an oscillator frequency outside of this range, will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration Word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the Analog-to-Digital input pins (ANx) as “digital” pins, by setting all bits in the ADPCFG register. If your application needs to use certain Analog-to-Digital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of these registers is only done during debugger operation. Failure to correctly configure the register(s) will result in all Analog-to-Digital pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1k to 10k resistor between VSS and unused pins, and drive the output to logic low. 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-4 through Figure 2-8. The bits in the registers that correspond to the Analog-to-Digital pins that are initialized by MPLAB ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. DS75018C-page 20 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 2-4: DIGITAL PFC IPFC VHV_BUS |VAC| k1 k3 VAC k2 ADC Channel FET Driver ADC Channel PWM Output ADC Channel dsPIC33FJ06GS001 FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION IPFC VINPUT VOUTPUT k1 k3 ADC Channel k2 FET Driver ADC Channel PWM Output ADC Channel dsPIC33FJ06GS001 2011-2012 Microchip Technology Inc. DS75018C-page 21 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output k7 ADC Channel FET Driver k1 k2 PWM PWM I5V Analog Comp. ADC Channel dsPIC33FJ06GS202A FIGURE 2-7: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k3 k1 k2 VOUTFET Driver ADC Channel ADC Channel DS75018C-page 22 PWM FET Driver ADC Channel PWM ADC Channel ADC Channel dsPIC33FJ06GS202A 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 2-8: PHASE-SHIFTED FULL-BRIDGE CONVERTER VIN+ Gate 6 Gate 3 Gate 1 VOUT+ S1 S3 VOUT- Gate 2 Gate 4 Gate 5 Gate 6 Gate 5 VIN- FET Driver k2 PWM ADC Channel k1 Analog Ground Gate 1 S1 FET Driver PWM Gate 3 S3 FET Driver ADC Channel dsPIC33FJ09GS302 PWM Gate 2 Gate 4 2011-2012 Microchip Technology Inc. DS75018C-page 23 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 24 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.0 CPU 3.1 Data Addressing Overview Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU Circular Addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. The CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies from device to device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point. The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a Data, Address or Address Offset register. The sixteenth working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. There are two classes of instruction: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the devices are capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program-to-data space mapping feature lets any instruction access program space as if it were data space. 3.2 DSP Engine Overview The DSP engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 16 bits, right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal realtime performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model is shown in Figure 3-2. 2011-2012 Microchip Technology Inc. DS75018C-page 25 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.3 Special MCU Features The 16/16 and 32/16 divide operations are supported, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A 17-bit by 17-bit single-cycle multiplier is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 3-1: A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 8 16 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 16 16 16 Address Generator Units Address Latch Program Memory EA MUX Data Latch ROM Latch 24 Instruction Reg 16 Literal Data Instruction Decode and Control 16 16 Control Signals to Various Blocks DSP Engine Divide Support 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules DS75018C-page 26 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 3-2: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand Registers W5 W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer Stack Pointer Limit Register SPLIM AD39 AD15 AD31 AD0 ACCA DSP Accumulators ACCB PC22 PC0 Program Counter 0 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address DOEND DO Loop End Address 22 15 0 Core Configuration Register CORCON OA OB SA SB OAB SAB DA SRH 2011-2012 Microchip Technology Inc. DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRL DS75018C-page 27 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.4 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA(1) SB(1) OAB SAB(1,4) DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) IPL<2:0>(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Settable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1,4) 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred Note 1: 2: 3: 4: This bit can be read or cleared (not set). The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when IPL3 = 1. The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). Clearing this bit will clear SA and SB. DS75018C-page 28 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: 2: 3: 4: This bit can be read or cleared (not set). The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when IPL3 = 1. The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). Clearing this bit will clear SA and SB. 2011-2012 Microchip Technology Inc. DS75018C-page 29 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 3-2: U-0 — bit 15 U-0 — R/W-0 SATB Legend: R = Readable bit 0’ = Bit is cleared bit 11 bit 10-8 U-0 — R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATA bit 7 bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER R/W-1 SATDW R/W-0 ACCSAT C = Clearable bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented: Read as ‘0’ US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops active • • • bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 001 = 1 DO loop active 000 = 0 DO loops active SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation is enabled 0 = Accumulator A saturation is disabled SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation is enabled 0 = Accumulator B saturation is disabled SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation is enabled 0 = Data space write saturation is disabled ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space is visible in data space 0 = Program space is not visible in data space RND: Rounding Mode Select bit 1 = Biased (conventional) rounding is enabled 0 = Unbiased (convergent) rounding is enabled IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops This bit will always read as ‘0’. The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS75018C-page 30 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.5 Arithmetic Logic Unit (ALU) The ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the “16-Bit MCU and DSC Programmer’s Reference Manual” (DS70157) for information on the SR bits affected by each instruction. The CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. 3.5.1 MULTIPLIER Using the high-speed, 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes: • • • • • • • 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned 3.5.2 DIVIDER 3.6 DSP Engine The DSP engine consists of a high-speed, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic). The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 devices feature a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (for example, ED, EDAC). The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG. The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below: • • • • • • Fractional or Integer DSP Multiply (IF) Signed or Unsigned DSP Multiply (US) Conventional or Convergent Rounding (RND) Automatic Saturation On/Off for ACCA (SATA) Automatic Saturation On/Off for ACCB (SATB) Automatic Saturation On/Off for Writes to Data Memory (SATDW) • Accumulator Saturation mode Selection (ACCSAT) A block diagram of the DSP engine is shown in Figure 3-3. TABLE 3-1: Instruction DSP INSTRUCTIONS SUMMARY Algebraic Operation CLR A=0 ED A = (x – y)2 ACC Write Back Yes No y)2 No The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: EDAC A = A + (x – MAC A = A + (x * y) MAC A = A + x2 No • • • • MOVSAC No change in A Yes MPY A=x*y No MPY A = x2 No MPY.N A=–x*y No MSC A=A–x*y Yes 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 2011-2012 Microchip Technology Inc. Yes DS75018C-page 31 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM S a 40 Round t 16 u Logic r a t e 40-Bit Accumulator A 40-Bit Accumulator B 40 Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 Zero Backfill 16 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array DS75018C-page 32 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.6.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. Integer data is inherently represented as a signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range of an N-bit 2’s complement integer is -2N-1 to 2N-1 – 1. • For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0 • For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF) When the multiplier is configured for fractional multiplication, the data is represented as a 2’s complement fraction, where the MSb is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit 2’s complement fraction with this implied radix point is -1.0 to (1 – 21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0 and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10-10. The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed-sign multiply operations. The MUL instruction can be directed to use byte or word-sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array. 3.6.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. 3.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: • Overflow from bit 39: This is a catastrophic overflow in which the sign of the accumulator is destroyed • Overflow into guard bits, 32 through 39: This is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other. The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously and the SAT<A:B> (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate. Six STATUS register bits support saturation and overflow: • OA: ACCA overflowed into guard bits • OB: ACCB overflowed into guard bits • SA: ACCA saturated (bit 31 overflow and saturation) or ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation) • SB: ACCB saturated (bit 31 overflow and saturation) or ACCB overflowed into guard bits and saturated (bit 39 overflow and saturation) • OAB: Logical OR of OA and OB • SAB: Logical OR of SA and SB The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overflow Trap Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section 7.0 “Interrupt Controller”). This allows the user application to take immediate action, for example, to correct system gain. The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled. • In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented) • In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented 2011-2012 Microchip Technology Inc. DS75018C-page 33 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programmers can check one bit in the STATUS Register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both accumulators. The device supports three Saturation and Overflow modes: • Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations). • Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set. • Bit 39 Catastrophic Overflow: Bit 39 Overflow Status bit, from the adder, is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. 3.6.3 ACCUMULATOR ‘WRITE BACK’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: 3.6.3.1 Round Logic The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word is simply discarded. Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through 31 of the accumulator). • If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented • If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged A consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined: • If it is ‘1’, ACCxH is incremented • If it is ‘0’, ACCxH is not modified Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 3.6.3.2 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator writeback operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding.‘ • W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. • [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). DS75018C-page 34 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.6.3.2 Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: • For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF • For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000 3.6.4 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data). The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 15 for left shifts. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. 2011-2012 Microchip Technology Inc. DS75018C-page 35 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 36 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 MEMORY ORGANIZATION Note: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Program Memory” (DS70203) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). The device architecture features separate program and data memory spaces and buses. This architecture also allows the direct access to program memory from the data space during code execution. User Memory Space FIGURE 4-1: 4.1 Program Address Space The device program address memory space is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.7 “Interfacing Program and Data Memory Spaces”. User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the constant current source trim value and Device ID sections of the configuration memory space. The device memory maps are shown in Figure 4-1. PROGRAM MEMORY MAPS FOR dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DEVICES dsPIC33FJ06GS001/101A/102A/202A 0x000000 GOTO Instruction 0x000002 Reset Address 0x000004 Interrupt Vector Table 0x0000FE 0x000100 Reserved 0x000104 Alternate Vector Table 0x0001FE 0x000200 User Program Flash Memory (1784 instructions) 0x000FEE 0x000FF0 Configuration 0x000FFE 0x001000 dsPIC33FJ09GS302 GOTO Instruction Reset Address Interrupt Vector Table Reserved User Memory Space 4.0 Alternate Vector Table User Program Flash Memory (2808 instructions) Configuration 0x7FFFFE 0x800000 Configuration Memory Space Configuration Memory Space 2011-2012 Microchip Technology Inc. Constant Current Source Trim Value 0x800840 Reserved Reserved 0x0017EE 0x0017F0 0x0017FE 0x001800 (Read ‘0’s) 0x7FFFFE 0x800000 DEVID (2) 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 Unimplemented Unimplemented (Read ‘0’s) Constant Current Source Trim Value 0x000000 0x000002 0x000004 0xFEFFFE 0xFF0000 0xFF0002 0xFFFFFE 0x800840 Reserved DEVID (2) Reserved 0xFEFFFE 0xFF0000 0xFF0002 0xFFFFFE DS75018C-page 37 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (see Figure 4-2). The devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during the code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. FIGURE 4-2: msw Address PROGRAM MEMORY ORGANIZATION 16 8 PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) DS75018C-page 38 least significant word most significant word 23 0x000001 0x000003 0x000005 0x000007 INTERRUPT AND TRAP VECTORS Instruction Width 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.2 Data Address Space The CPU has a separate, 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps are shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section 4.7.3 “Reading Data from Program Memory Using Program Space Visibility”). All devices implement up to 1 Kbyte of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. 4.2.1 DATA SPACE WIDTH The data memory space is organized in byteaddressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes Post-Modified Register Indirect Addressing mode [Ws++], which results in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. 2011-2012 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A Sign-Extend (SE) instruction is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. 4.2.3 SFR SPACE The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. Note: 4.2.4 The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information. NEAR DATA SPACE The 8-Kbyte area between 0x0000 and 0x1FFF is referred to as the Near Data Space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an Address Pointer. DS75018C-page 39 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ06GS001/101A/102A DEVICES WITH 256 BYTES OF RAM MSB Address MSb 2-Kbyte SFR Space 256-Byte SRAM Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x087F 0x0881 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x087E 0x0880 0x08FF 0x0901 0x08FE 0x0900 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS75018C-page 40 LSB Address 16 bits 0xFFFE 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 4-4: DATA MEMORY MAP FOR THE dsPIC33FJ09GS302 DEVICE WITH 1 KB RAM MSB Address MSb 2-Kbyte SFR Space 1-Kbyte SRAM Space LSB Address 16 bits LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x09FF 0x0A01 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x09FE 0x0A00 0x0BFF 0x0C01 0x0BFE 0x0C00 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 2011-2012 Microchip Technology Inc. 0xFFFE DS75018C-page 41 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.2.5 X AND Y DATA SPACES The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms, such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT). Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class). All Effective Addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. DS75018C-page 42 All data memory writes, included in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable. 2011-2012 Microchip Technology Inc. Special Function Register Maps TABLE 4-1: SFR Name SFR Addr CPU CORE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 WREG11 0016 Working Register 11 0000 WREG12 0018 Working Register 12 0000 WREG13 001A Working Register 13 0000 WREG14 001C Working Register 14 0000 0800 WREG15 001E Working Register 15 SPLIM 0020 Stack Pointer Limit Register xxxx ACCAL 0022 ACCAL xxxx ACCAH 0024 ACCAU 0026 ACCAH ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> xxxx ACCA<39> ACCA<39> ACCAU xxxx ACCBL 0028 ACCBL ACCBH 002A ACCBH ACCBU 002C PCL 002E PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 RCOUNT 0036 Repeat Loop Counter Register xxxx DCOUNT 0038 DCOUNT<15:0> xxxx ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> xxxx xxxx ACCB<39> ACCB<39> xxxx Program Counter Low Word Register DS75018C-page 43 DOSTARTL 003A DOSTARTH 003C DOENDL 003E DOENDH 0040 — — — — — — — — SR 0042 OA OB SA SB OAB SAB DA DC Legend: ACCBU 0000 DOSTARTL<15:1> — — — — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — IPL<2:0> xxxx 0 xxxx 00xx DOENDL<15:1> — 0 DOSTARTH<5:0> DOENDH RA N OV 00xx Z C 0000 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. 4.3 SFR Name SFR Addr CPU CORE REGISTER MAP (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 EDT CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — — Bit 10 Bit 9 Bit 8 DL<2:0> Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF BWM<3:0> YWM<3:0> XWM<3:0> All Resets 0020 0000 XMODSRT 0048 XS<15:1> 0 xxxx XMODEND 004A XE<15:1> 1 xxxx YMODSRT 004C YS<15:1> 0 xxxx YMODEND 004E YE<15:1> 1 xxxx XBREV 0050 BREN DISICNT 0052 — Legend: XB<14:0> — Disable Interrupts Counter Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. xxxx xxxx 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 44 TABLE 4-1: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS001 AND dsPIC33FJ06GS101A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 CNEN1 0060 — — — — — — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CNPU1 0068 — — — — — — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE File Name Legend: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 All Resets CN1IE CN0IE 0000 CN1PUE CN0PUE 0000 Bit 1 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: File Name SFR Addr CNEN1 0060 CNPU1 0068 Legend: Bit 7 CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A, AND dsPIC33FJ09GS302 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 DS75018C-page 45 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-2: File Name SFR Addr. INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS001 DEVICES ONLY Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI Bit 13 Bit 12 Bit 11 Bit 10 OVBERR COVAERR COVBERR OVATE Bit 9 OVBTE Bit 8 Bit 7 Bit 6 Bit 5 COVTE SFTACERR DIV0ERR — — — — — — — — — — Bit 4 Bit 3 MATHERR ADDRERR — — Bit 0 All Reset s Bit 2 Bit 1 STKERR OSCFAIL — 0000 INT2EP INT1EP INT0EP 0000 2011-2012 Microchip Technology Inc. IFS0 0084 — — ADIF — — — — — T2IF — — — T1IF — — INT0IF 0000 IFS1 0086 — — INT2IF — — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 IFS4 008C — — — — — — — — — — — — — — — — 0000 IFS5 008E — PWM1IF — — — — — — — — — — — — — JTAGIF 0000 IFS6 0090 ADCP1IF ADCP0IF — — — — — — AC2IF — — — — — PWM4IF — 0000 IFS7 0092 — — — — — — — — — — — ADCP6IF — — ADCP3IF — 0000 IEC0 0094 — — ADIE — — — — — T2IE — — — T1IE — — INT0IE 0000 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 IEC4 009C — — — — — — — — — — — — — — — — 0000 IEC5 009E — PWM1IE — — — — — — — — — — — — — JTAGIE 0000 IEC6 00A0 ADCP1IE ADCP0IE — — — — — — AC2IE — — — — — PWM4IE — 0000 IEC7 00A2 — — — — — — — — — — ADCP6IE — — ADCP3IE — IPC0 00A4 — — — — — — — — — — IPC1 00A6 — — — — — — — — — — — — — IPC3 00AA — — — — — -— ADIP<2:0> — — — — IPC4 00AC — — MI2C1IP<2:0> — IPC5 00AE — — — — — — — — — IPC7 00B2 — — — — — — — — — INT2IP<2:0> — — — — IPC14 00C0 — — — — — — — — — PSEMIP<2:0> — — — — IPC20 00CC — — — — — — — — — — IPC23 00D2 — — — — — — — IPC24 00D4 — — — — — — — — — IPC25 00D6 — AC2IP<2:0> — — — — — — — IPC27 00DA — ADCP1IP<2:0> — — — — IPC28 00DC — — — — — — — — — IPC29 00DE — — — — — — — — — INTTREG 00E0 — — — — Legend: — T1IP<2:0> T2IP<2:0> — — — CNIP<2:0> — AC1IP<2:0> PWM1IP<2:0> ADCP0IP<2:0> ILR<3:0> — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — — SI2C1IP<2:0> — 0000 4004 4000 0040 4444 INT1IP<2:0> 0004 0040 — — — — — — — — 0400 — — — — 0040 — — — — — 4400 — — — — — 4000 — — — — ADCP3IP<2:0> — — — VECNUM<6:0> JTAGIP<2:0> 0040 — PWM4IP<2:0> — INT0IP<2:0> ADCP6IP<2:0> 0004 0040 0004 0000 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 46 TABLE 4-4: File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS101A DEVICES ONLY SFR Addr. Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 OVBERR COVAERR COVBERR OVATE OVBTE Bit 8 Bit 7 Bit 6 Bit 5 COVTE SFTACERR DIV0ERR — — — — — — — — — — Bit 4 Bit 3 MATHERR ADDRERR — Bit 2 Bit 1 Bit 0 All Resets STKERR OSCFAIL — 0000 — INT2EP INT1EP INT0EP 0000 0000 IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF — T2IF — — — T1IF OC1IF — INT0IF IFS1 0086 — — INT2IF — — — — — — — — INT1IF CNIF — MI2C1IF SI2C1IF 0000 IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 IFS5 008E — PWM1IF — — — — — — — — — — — — — JTAGIF 0000 IFS6 0090 ADCP1IF ADCP0IF — — — — — — — — — — — — PWM4IF — 0000 IFS7 0092 — — — — — — — — — — — — — — ADCP3IF — 0000 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE — T2IE — — — T1IE OC1IE — INT0IE 0000 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000 IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 IEC5 009E — PWM1IE — — — — — — — — — — — — — JTAGIE 0000 IEC6 00A0 ADCP1IE ADCP0IE — — — — — — — — — — — — PWM4IE — 0000 IEC7 00A2 — — — — — — — — — — — — — ADCP3IE — IPC0 00A4 — — — — — — IPC1 00A6 — — — — IPC2 00A8 IPC3 00AA — IPC4 00AC — IPC5 00AE — — — — IPC7 00B2 — — — IPC14 00C0 — — IPC16 00C4 — IPC20 00CC IPC23 IPC24 — T1IP<2:0> — — T2IP<2:0> — — U1RXIP<2:0> — — — — — — SPI1IP<2:0> INT0IP<2:0> 0000 4404 — — — — — SPI1EIP<2:0> — — — — ADIP<2:0> — U1TXIP<2:0> 0044 — SI2C1IP<2:0> 4044 — INT1IP<2:0> 4000 4440 DS75018C-page 47 — — — — -— — — — — — — — — — — — — — — — — INT2IP<2:0> — — — — 0040 — — — — — — — PSEMIP<2:0> — — — — 0040 — — — — — — — — U1EIP<2:0> — — — — — — — — — — — — — — 00D2 — — — — — — — 00D4 — — — — — IPC27 00DA — IPC28 00DC — — — — INTTREG 00E0 — — — — Legend: — OC1IP<2:0> CNIP<2:0> ADCP1IP<2:0> PWM1IP<2:0> — — — — — ADCP0IP<2:0> — ILR<3:0> — — — — MI2C1IP<2:0> — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — — — — — — — — — 0400 — — — — 0040 — — — — 4400 — — — — 0040 — ADCP3IP<2:0> — VECNUM<6:0> JTAGIP<2:0> 0040 — PWM4IP<2:0> — 0004 0004 0000 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-5: File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS102A DEVICES ONLY SFR Addr. Bit 15 Bit 14 Bit 13 INTCON1 0080 NSTDIS OVAERR OVBERR INTCON2 0082 ALTIVT DISI — — — IFS0 0084 — — ADIF U1TXIF Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 OVATE OVBTE COVTE — — — — — — — — U1RXIF SPI1IF SPI1EIF — T2IF — — — COVAERR COVBERR Bit 7 Bit 6 Bit 5 SFTACERR DIV0ERR — Bit 4 Bit 3 Bit 0 All Resets OSCFAIL — 0000 INT1EP INT0EP 0000 OC1IF — INT0IF 0000 Bit 2 Bit 1 STKERR INT2EP T1IF MATHERR ADDRERR 2011-2012 Microchip Technology Inc. IFS1 0086 — — INT2IF — — — — — — — — INT1IF CNIF — MI2C1IF SI2C1IF 0000 IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — JTAGIF 0000 IFS6 0090 ADCP1IF ADCP0IF — — — — — — — — — — — — — — 0000 IFS7 0092 — — — — — — — — — — — — — — — ADCP2IF 0000 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE — T2IE — — — T1IE OC1IE — INT0IE 0000 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000 IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — JTAGIE 0000 IEC6 00A0 ADCP1IE ADCP0IE — — — — — — — — — — — — — — 0000 IEC7 00A2 — — — — — — — — — — — — — — ADCP2IE 0000 IPC0 00A4 — T1IP<2:0> — IPC1 00A6 — T2IP<2:0> — — — 4000 IPC2 00A8 — — — 4440 IPC3 00AA — IPC4 00AC — IPC5 00AE — — — IPC7 00B2 — — IPC14 00C0 — IPC16 00C4 — IPC20 00CC — IPC23 00D2 — IPC27 00DA — IPC28 00DC — — — — INTTREG 00E0 — — — — Legend: — U1RXIP<2:0> OC1IP<2:0> — — — — — — — — — — — — — — 4404 — SPI1EIP<2:0> — — — — -— ADIP<2:0> — U1TXIP<2:0> 0044 — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4044 — — — — — — — INT1IP<2:0> — — — — — — — INT2IP<2:0> — — — — 0040 — — — — — — — — PSEMIP<2:0> — — — — 0040 — — — — — — — — U1EIP<2:0> — — — — 0040 — — — — — — — — — — — — — — — — — — — — 4400 — — — — — — — — 4400 — — — — — — — CNIP<2:0> PWM2IP<2:0> SPI1IP<2:0> INT0IP<2:0> — — — — — ADCP1IP<2:0> PWM1IP<2:0> — — ADCP0IP<2:0> — — — ILR<3:0> x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — — — VECNUM<6:0> 0004 JTAGIP<2:0> ADCP2IP<2:0> 0004 0004 0000 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 48 TABLE 4-6: File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS202A DEVICES ONLY SFR Addr. Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 OVBERR COVAERR COVBERR OVATE OVBTE — — — — Bit 8 Bit 7 Bit 6 COVTE SFTACERR DIV0ERR — Bit 5 — — — — — Bit 4 Bit 3 MATHERR ADDRERR — Bit 2 Bit 1 Bit 0 All Resets STKERR OSCFAIL — 0000 — INT2EP INT1EP INT0EP 0000 0000 IFS0 0084 — — ADIF U1TXIF U1RXIF — T2IF — — — T1IF OC1IF IC1IF INT0IF IFS1 0086 — — INT2IF — — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — JTAGIF 0000 IFS6 0090 ADCP1IF ADCP0IF — — — — — — AC2IF — — — — — — — 0000 IFS7 0092 — — — — — — — — — — — ADCP6IF — — — ADCP2IF 0000 0000 SPI1IF SPI1EIF DS75018C-page 49 IEC0 0094 — — ADIE U1TXIE U1RXIE — T2IE — — — T1IE OC1IE IC1IE INT0IE IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — JTAGIE 0000 IEC6 00A0 ADCP1IE ADCP0IE — — — — — — AC2IE — — — — — — — 0000 IEC7 00A2 — — — — — — — — — — ADCP6IE — — — ADCP2IE 0000 IPC0 00A4 — T1IP<2:0> — IPC1 00A6 — T2IP<2:0> — IPC2 00A8 — U1RXIP<2:0> — IPC3 00AA — IPC4 00AC — IPC5 00AE — — — — — — — — — IPC7 00B2 — — — — — — — — — INT2IP<2:0> — — — — 0040 IPC14 00C0 — — — — — — — — — PSEMIP<2:0> — — — — 0040 IPC16 00C4 — — — — — — — — — U1EIP<2:0> — — — — IPC20 00CC — — — — — — — — — — — — — IPC23 00D2 — PWM2IP<2:0> — — — — — — — — — 4400 IPC25 00D6 — AC2IP<2:0> — — — — — — — — — 4000 IPC27 00DA — ADCP1IP<2:0> — — — — — — — — — IPC28 00DC — — — — — — — — — — — — — ADCP2IP<2:0> 0004 IPC29 00DE — — — — — — — — — — — — — ADCP6IP<2:0> 0004 INTTREG 00E0 — — — — Legend: — — — — CNIP<2:0> — SPI1IE SPI1EIE OC1IP<2:0> — — — — SPI1IP<2:0> — — — — AC1IP<2:0> — — ADCP0IP<2:0> ILR<3:0> IC1IP<2:0> — — — — INT0IP<2:0> 4444 — — — — — — — 4000 — SPI1EIP<2:0> — -— ADIP<2:0> — U1TXIP<2:0> 0044 — SI2C1IP<2:0> 4444 — INT1IP<2:0> — PWM1IP<2:0> — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. MI2C1IP<2:0> — — — VECNUM<6:0> 4440 0004 JTAGIP<2:0> 0040 0004 4400 0000 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-7: File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ09GS302 DEVICES ONLY SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 3 Bit 1 Bit 0 All Resets INTCON1 0080 NSTDIS OVAERR STKERR OSCFAIL — 0000 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF — T2IF — — — T1IF OC1IF IC1IF INT0IF 0000 IFS1 0086 — — INT2IF — — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 OVBTE COVTE SFTACERR DIV0ERR MATHERR ADDRERR Bit 2 INTCON2 OVBERR COVAERR COVBERR OVATE — Bit 4 IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — JTAGIF 0000 IFS6 0090 ADCP1IF ADCP0IF — — — — — — AC2IF — — — — — PWM4IF — 0000 IFS7 0092 — — — — — — — — — — — ADCP6IF — — ADCP3IF ADCP2IF 0000 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE — T2IE — — — T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 2011-2012 Microchip Technology Inc. IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — JTAGIE 0000 IEC6 00A0 ADCP1IE ADCP0IE — — — — — — AC2IE — — — — — PWM4IE — 0000 IEC7 00A2 — — — — — — — — — — ADCP6IE — — ADCP3IE ADCP2IE 0000 IPC0 00A4 — T1IP<2:0> — IPC1 00A6 — T2IP<2:0> — — — 4000 IPC2 00A8 — — — 4440 IPC3 00AA — IPC4 00AC — IPC5 00AE — — — — — — — — — IPC7 00B2 — — — — — — — — — INT2IP<2:0> — — — — 0040 IPC14 00C0 — — — — — — — — — PSEMIP<2:0> — — — — 0040 IPC16 00C4 — — — — — — — — — U1EIP<2:0> — — — — 0040 IPC20 00CC — — — — — — — — — — — — — IPC23 00D2 — — — — — — — — — 4400 IPC24 00D4 — — — — — — — — — — 0040 IPC25 00D6 — AC2IP<2:0> — — — — — — — — — 4000 IPC27 00DA — ADCP1IP<2:0> — — — — 4400 IPC28 00DC — — — — — — — IPC29 00DE — — — — — — — INTTREG 00E0 — — — — Legend: — U1RXIP<2:0> — — — CNIP<2:0> PWM2IP<2:0> — — OC1IP<2:0> — — — IC1IP<2:0> — — — — INT0IP<2:0> -— — — 4444 — SPI1IP<2:0> — SPI1EIP<2:0> — -— — -— ADIP<2:0> — U1TXIP<2:0> 0044 — AC1IP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 — INT1IP<2:0> — — — — PWM1IP<2:0> ADCP0IP<2:0> ILR<3:0> — — — PWM4IP<2:0> — — — 0004 JTAGIP<2:0> 0004 -— — — — — ADCP3IP<2:0> — ADCP2IP<2:0> 0044 — — — ADCP6IP<2:0> 0004 — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — — VECNUM<6:0> 0000 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 50 TABLE 4-8: SFR Name SFR Addr TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TON — TSIDL — — — — — — TMR2 0106 Timer2 Register PR2 010C Period Register 2 T2CON 0110 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-10: SFR Name SFR Addr TON — TSIDL — — — — — — Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — Bit 8 Bit 7 IC1BUF 0140 0142 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. SFR Name SFR Addr Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 FFFF TGATE TCKPS<1:0> — TSYNC TCS — 0000 0000 FFFF TGATE TCKPS<1:0> — — TCS — 0000 Bit 1 Bit 0 All Resets INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 IC1CON TABLE 4-11: Bit 6 Bit 6 Bit 5 Bit 4 Bit 3 ICOV ICBNE Bit 2 Input Capture 1 Register — — xxxx ICI<1:0> ICM<2:0> 0000 OUTPUT COMPARE REGISTER MAP FOR dsPIC33FJ06GS101A, dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets OC1RS 0180 Output Compare 1 Secondary Register xxxx OC1R 0182 Output Compare 1 Register xxxx OC1CON 0184 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — OCSIDL — — — — — — — — OCFLT — OCM<2:0> 0000 DS75018C-page 51 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-9: HIGH-SPEED PWM REGISTER MAP Addr Offset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 PTCON 0400 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN — PTCON2 0402 — — — — — — — — — — PTPER 0404 SEVTCMP 0406 File Name Bit 3 Bit 2 SYNCSRC<1:0> — Bit 1 Bit 0 SEVTPS<3:0> — — 040A 041A 0000 FFF8 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — — — — — MDC<15:0> CHPCLKEN — — — — All Resets 0000 PCLKDIV<2:0> SEVTCMP<15:3> CHOP 0000 0000 — CHOPCLK<6:0> 0000 HIGH-SPEED PWM GENERATOR 1 REGISTER MAP Addr Offset Bit 15 PWMCON1 0420 FLTSTAT IOCON1 0422 PENH FCLCON1 0424 IFLTMOD PDC1 0426 File Name Bit 4 PTPER<15:0> MDC TABLE 4-13: Bit 5 Bit 14 Bit 13 CLSTAT TRGSTAT PENL POLH Bit 12 Bit 11 Bit 10 FLTIEN CLIEN TRGIEN POLL PMOD<1:0> CLSRC<4:0> Bit 9 Bit 8 ITB Bit 7 MDCS OVRENH CLPOL Bit 6 DTC<1:0> OVRENL OVRDAT<1:0> CLMOD Bit 5 Bit 4 — — FLTDAT<1:0> Bit 0 All Resets XPRES IUE 0000 SWAP OSYNC 0000 Bit 3 Bit 2 Bit 1 — CAM CLDAT<1:0> FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000 PDC1<15:0> 0000 PHASE1<15:0> 0000 PHASE1 0428 DTR1 042A — — DTR1<13:0> 0000 ALTDTR1 042C — — ALTDTR1<13:0> 0000 2011-2012 Microchip Technology Inc. SDC1 042E SDC1<15:0> SPHASE1 0430 SPHASE1<15:0> TRIG1 0432 TRGCON1 0434 STRIG1 0436 STRGCMP<15:3> — — — 0000 PWMCAP1 0438 PWMCAP1<15:3> — — — 0000 LEBCON1 043A PHR PHF PLR PLF — — — AUXCON1 043E HRPDIS HRDDIS — — Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0000 0000 TRGCMP<15:3> TRGDIV<3:0> — — — — — FLTLEBEN CLLEBEN — — DTM — — — — — TRGSTRT<5:0> LEB<6:0> — — CHOPSEL<3:0> 0000 0000 CHOPHEN CHOPLEN 0000 0000 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 52 TABLE 4-12: HIGH-SPEED PWM GENERATOR 2 REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 Addr Offset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN IOCON2 0442 PENH PENL POLH POLL FCLCON2 0444 IFLTMOD PDC2 0446 File Name PMOD<1:0> CLSRC<4:0> Bit 9 Bit 8 ITB MDCS Bit 7 DTC<1:0> OVRENH OVRENL CLPOL Bit 6 OVRDAT<1:0> CLMOD Bit 5 Bit 4 — — FLTDAT<1:0> Bit 2 Bit 1 — CAM XPRES IUE 0000 CLDAT<1:0> SWAP OSYNC 0000 FLTSRC<4:0> FLTPOL Bit 0 All Resets Bit 3 FLTMOD<1:0> 0000 PDC2<15:0> 0000 PHASE2<15:0> 0000 PHASE2 0448 DTR2 044A — — DTR2<13:0> ALTDTR2 044C — — ALTDTR2<13:0> SDC2 044E SPHASE2 0450 TRIG2 0452 TRGCON2 0454 STRIG2 0456 STRGCMP<15:3> — — — 0000 PWMCAP2 0458 PWMCAP2<15:3> — — — 0000 LEBCON2 045A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — AUXCON2 045E HRPDIS HRDDIS — — — — Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0000 0000 SDC2<15:0> 0000 SPHASE2<15:0> 0000 TRGCMP<15:3> TRGDIV<3:0> — — — — — DTM — — — — — TRGSTRT<5:0> LEB<6:0> — — CHOPSEL<3:0> 0000 0000 CHOPHEN CHOPLEN 0000 0000 DS75018C-page 53 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-14: HIGH-SPEED PWM GENERATOR 4 REGISTER MAP FOR dsPIC33FJ06GS001, dsPIC33FJ06GS101A AND dsPIC33FJ09GS302 Addr Offset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 PWMCON4 0480 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN IOCON4 0482 PENH PENL POLH POLL FCLCON4 0484 IFLTMOD PDC4 0486 File Name PMOD<1:0> CLSRC<4:0> Bit 9 Bit 8 ITB MDCS Bit 7 DTC<1:0> OVRENH OVRENL CLPOL Bit 6 OVRDAT<1:0> CLMOD Bit 5 Bit 4 — — FLTDAT<1:0> Bit 2 Bit 1 — CAM XPRES IUE 0000 SWAP OSYNC 0000 CLDAT<1:0> FLTSRC<4:0> FLTPOL Bit 0 All Resets Bit 3 FLTMOD<1:0> 0000 PDC4<15:0> 0000 PHASE4<15:0> 0000 PHASE4 0488 DTR4 048A — — DTR4<13:0> 0000 ALTDTR4 048C — — ALTDTR4<13:0> 0000 SDC4 048E SDC4<15:0> SPHASE4 0490 SPHASE4<15:0> TRIG4 0492 TRGCON4 0494 STRIG4 0496 0000 0000 TRGCMP<15:3> TRGDIV<3:0> — — — — — DTM — 0498 LEBCON4 049A PHR PHF PLR PLF PWMCAP4<15:3> AUXCON4 049E HRPDIS HRDDIS — — Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. FLTLEBEN CLLEBEN — — LEB<6:0> — — — — — 0000 — — — 0000 — — — 0000 — — — 0000 TRGSTRT<5:0> STRGCMP<15:3> PWMCAP4 — CHOPSEL<3:0> 0000 CHOPHEN CHOPLEN 0000 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 54 TABLE 4-15: I2C1 REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 — — — — — — — — Receive Register I2C1TRN 0202 — — — — — — — — Transmit Register 00FF I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000 I2CEN — I2C1CON 0206 I2C1STAT 0208 I2C1ADD 020A — I2C1MSK 020C — Legend: Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 All Resets 0000 IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 — — — — — Address Register 0000 — — — — — AMSK<9:0> 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-17: SFR Name SFR Addr U1MODE 0220 U1STA 0222 UART1 REGISTER MAP FOR dsPIC33FJ06GS101A, dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 Bit 15 Bit 14 Bit 13 Bit 12 UARTEN — USIDL IREN UTXISEL1 UTXINV UTXISEL0 — Bit 11 Bit 10 RTSMD — UTXBRK UTXEN Bit 9 Bit 8 Bit 7 Bit 6 UEN1 UEN0 WAKE LPBACK UTXBF TRMT URXISEL<1:0> Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR U1TXREG 0224 — — — — — — — UART Transmit Register U1RXREG 0226 — — — — — — — UART Receive Register U1BRG 0228 Legend: Bit 2 — ACKSTAT TRSTAT I2CSIDL SCLREL Bit 7 Bit 2 Bit 1 PDSEL<1:0> FERR OERR Bit 0 All Resets STSEL 0000 URXDA 0110 xxxx 0000 Baud Rate Generator Prescaler 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-18: SPI1 REGISTER MAP FOR dsPIC33FJ06GS101A, dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 SFR Name SFR Addr Bit 15 Bit 14 Bit 13 SPI1STAT 0240 SPIEN — SPISIDL SPI1CON1 0242 — — — SPI1CON2 0244 FRMEN SPIFSD FRMPOL Bit 12 Bit 11 — — DISSCK DISSDO — — Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — — — — — SPIROV — MODE16 SMP CKE SSEN CKP MSTEN — — — — — — SPI1BUF 0248 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. SPI1 Transmit and Receive Buffer Register Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — SPITBF SPIRBF 0000 SPRE<2:0> — — PPRE<1:0> — FRMDLY — 0000 0000 0000 DS75018C-page 55 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-16: File Name ISRCCON Legend: CONSTANT CURRENT SOURCE REGISTER MAP ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 0500 ISRCEN — — — — Bit 10 Bit 9 Bit 8 Bit 6 — — OUTSEL<2:0> Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISRCCAL<5:0> All Resets 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-20: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS001 AND dsPIC33FJ06GS101A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — ADPCFG 0302 — — — — — — — ADSTAT 0306 — — — — — — — ADBASE 0308 SFR Name Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 FORM EIE ORDER — PCFG7 PCFG6 — — PCFG3 PCFG2 PCFG1 PCFG0 — — P6RDY — — P3RDY — P1RDY P0RDY SEQSAMP ASYNCSAMP Bit 3 Bit 2 — Bit 1 ADCS<2:0> ADBASE<15:1> ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC3<4:0> — — — ADCPC3 0310 — — IRQEN6 PEND6 SWTRG6 ADCBUF0 0320 — — — — — — Bit 0 0003 — — TRGSRC6<4:0> 0000 0000 — 0000 — 0000 TRGSRC0<4:0> — All Resets 0000 — 0000 ADC Data Buffer 0 xxxx xxxx ADCBUF1 0322 ADC Data Buffer 1 ADCBUF2 0324 ADC Data Buffer 2 xxxx ADCBUF3 0326 ADC Data Buffer 3 xxxx ADCBUF6 032C ADC Data Buffer 6 xxxx ADCBUF7 032E ADC Data Buffer 7 xxxx ADCBUF12 0338 ADC Data Buffer 12 xxxx ADCBUF13 033A ADC Data Buffer 13 xxxx Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 56 TABLE 4-19: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS102A AND dsPIC33FJ06GS202A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER ADPCFG 0302 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 ADSTAT 0306 — — — — — — — — — P6RDY — — — P2RDY P1RDY P0RDY ADBASE 0308 SFR Name Bit 5 Bit 4 SEQSAMP ASYNCSAMP Bit 3 — Bit 2 Bit 1 ADCS<2:0> ADBASE<15:1> ADCPC0 030A IRQEN1 PEND1 SWTRG1 ADCPC1 030C — — — — — TRGSRC1<4:0> — — ADCPC3 0310 — — — — — — — ADCBUF0 0320 Bit 0 All Resets 0003 — 0000 0000 0000 IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> 0000 — IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> 0000 — IRQEN6 PEND6 SWTRG6 TRGSRC6<4:0> 0000 ADC Data Buffer 0 xxxx xxxx ADCBUF1 0322 ADC Data Buffer 1 ADCBUF2 0324 ADC Data Buffer 2 xxxx ADCBUF3 0326 ADC Data Buffer 3 xxxx ADCBUF4 0328 ADC Data Buffer 4 xxxx ADCBUF5 032A ADC Data Buffer 5 xxxx ADCBUF12 0338 ADC Data Buffer 12 xxxx ADCBUF13 033A ADC Data Buffer 13 xxxx Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS75018C-page 57 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-21: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ09GS302 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — ADPCFG 0302 — — — — — — — ADSTAT 0306 — — — — — — — ADBASE 0308 SFR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FORM EIE ORDER — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 — — P6RDY — — P3RDY P2RDY P1RDY P0RDY SEQSAMP ASYNCSAMP Bit 2 — Bit 1 Bit 0 ADCS<2:0> ADBASE<15:1> All Resets 0003 — 0000 0000 0000 ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC3<4:0> IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> 0000 ADCPC3 0310 — — IRQEN6 PEND6 SWTRG6 TRGSRC6<4:0> 0000 — — — — — — 0000 ADCBUF0 0320 ADC Data Buffer 0 xxxx ADCBUF1 0322 ADC Data Buffer 1 xxxx ADCBUF2 0324 ADC Data Buffer 2 xxxx ADCBUF3 0326 ADC Data Buffer 3 xxxx ADCBUF4 0328 ADC Data Buffer 4 xxxx ADCBUF5 032A ADC Data Buffer 5 xxxx xxxx ADCBUF6 032C ADC Data Buffer 6 ADCBUF7 032E ADC Data Buffer 7 xxxx ADCBUF12 0338 ADC Data Buffer 12 xxxx ADCBUF13 033A ADC Data Buffer 13 xxxx Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-23: File Name ANALOG COMPARATOR CONTROL REGISTER MAP FOR dsPIC33FJ06GS001, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. ADR Bit 15 Bit 14 Bit 13 CMPCON1 0540 CMPON — CMPSIDL CMPDAC1 0542 — — — CMPCON2 0544 CMPON — CMPSIDL CMPDAC2 0546 — — — Legend: Note 1: Bit 12 Bit 11 HYSSEL<1:0> — — HYSSEL<1:0> — — Bit 10 Bit 9 Bit 8 Bit 7 FLTREN FCLKSEL DACOE(1) Bit 6 INSEL<1:0> — FLTREN FCLKSEL DACOE(1) — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This bit is not available in the dsPIC33FJ06GS001 device. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXTREF HYSPOL CMPSTAT HGAIN CMPPOL RANGE CMREF<9:0> INSEL<1:0> EXTREF HYSPOL CMREF<9:0> All Resets 0000 0000 CMPSTAT HGAIN CMPPOL RANGE 0000 0000 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 58 TABLE 4-22: SFR Name PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33FJ06GS001 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 — — Bit 11 Bit 10 Bit 9 Bit 8 — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — — — — — 3F00 — — — — — — 3F00 — — 3F00 RPINR0 0680 — — RPINR1 0682 — — RPINR2 0684 — — RPINR3 0686 — — — — RPINR29 06BA — — FLT1R<5:0> — — RPINR30 06BC — — FLT3R<5:0> — — FLT2R<5:0> 3F3F RPINR31 06BE — — FLT5R<5:0> — — FLT4R<5:0> 3F3F RPINR32 06C0 — — FLT7R<5:0> — — FLT6R<5:0> 3F3F RPINR33 06C2 — — SYNCI1R<5:0> — — FLT8R<5:0> 3F3F RPINR34 06C4 — — — — SYNCI2R<5:0> 003F Legend: — — T1CKR<5:0> — — — — — — — — — — — — INT2R<5:0> — — — — — — — 003F T2CKR<5:0> — 003F x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-25: SFR Name INT1R<5:0> Bit 7 PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33FJ06GS101A AND dsPIC33FJ06GS102A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 — — Bit 11 Bit 10 Bit 9 Bit 8 — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — — — — — 3F00 — — — — — — 3F00 RPINR0 0680 — — RPINR1 0682 — — RPINR2 0684 — — RPINR3 0686 — — — — — — — — — — T2CKR<5:0> 003F RPINR11 0696 — — — — — — — — — — OCFAR<5:0> 003F RPINR18 06A4 — — U1CTSR<5:0> — U1RXR<5:0> 3F3F RPINR20 06A8 — — SCK1R<5:0> — SDI1R<5:0> 3F3F RPINR21 06AA — — — — SS1R<5:0> RPINR29 06BA — — FLT1R<5:0> — — RPINR30 06BC — — FLT3R<5:0> — — FLT2R<5:0> 3F3F RPINR31 06BE — — FLT5R<5:0> — — FLT4R<5:0> 3F3F RPINR32 06C0 — — FLT7R<5:0> — — FLT6R<5:0> 3F3F RPINR33 06C2 — — SYNCI1R<5:0> — — FLT8R<5:0> 3F3F RPINR34 06C4 — — — — SYNCI2R<5:0> 003F DS75018C-page 59 Legend: INT1R<5:0> Bit 7 — — T1CKR<5:0> — — — — — — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. INT2R<5:0> — — — — — — — — 003F 003F — — 3F00 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-24: SFR Name PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 — — Bit 11 Bit 10 Bit 9 Bit 8 — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — — — — — 3F00 — — — — — — 3F00 RPINR0 0680 — — RPINR1 0682 — — RPINR2 0684 — — RPINR3 0686 — — — — — — — — — — T2CKR<5:0> 003F RPINR7 068E — — — — — — — — — — IC1R<5:0> 003F RPINR11 0696 — — — — — — — — — — OCFAR<5:0> 003F RPINR18 06A4 — — U1CTSR<5:0> — — U1RXR<5:0> 3F3F RPINR20 06A8 — — SCK1R<5:0> — — SDI1R<5:0> 3F3F RPINR21 06AA — — — — SS1R<5:0> RPINR29 06BA — — FLT1R<5:0> — — RPINR30 06BC — — FLT3R<5:0> — — FLT2R<5:0> 3F3F RPINR31 06BE — — FLT5R<5:0> — — FLT4R<5:0> 3F3F RPINR32 06C0 — — FLT7R<5:0> — — FLT6R<5:0> 3F3F RPINR33 06C2 — — SYNCI1R<5:0> — — FLT8R<5:0> 3F3F RPINR34 06C4 — — — — SYNCI2R<5:0> 003F Legend: — T1CKR<5:0> — — — — — — — — — — — — INT2R<5:0> — — — — — 003F — — 003F — — — 3F00 PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS001 AND dsPIC33FJ06GS101A 2011-2012 Microchip Technology Inc. Addr Bit 15 Bit 14 RPOR0 06D0 — — RPOR1 06D2 — — RPOR2 06D4 — RPOR3 06D6 — RPOR16 06F0 RPOR17 06F2 Legend: — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-27: File Name INT1R<5:0> Bit 7 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 6 RP1R<5:0> — — RP0R<5:0> 0000 RP3R<5:0> — — RP2R<5:0> 0000 — RP5R<5:0> — — RP4R<5:0> 0000 — RP7R<5:0> — — RP6R<5:0> 0000 — — RP33R<5:0> — — RP32R<5:0> 0000 — — RP35R<5:0> — — RP34R<5:0> 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Bit 7 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 60 TABLE 4-26: File Name PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RPOR0 06D0 — — RP1R<5:0> — — RP0R<5:0> 0000 RPOR1 06D2 — — RP3R<5:0> — — RP2R<5:0> 0000 RPOR2 06D4 — — RP5R<5:0> — — RP4R<5:0> 0000 RPOR3 06D6 — — RP7R<5:0> — — RP6R<5:0> 0000 RPOR4 06D8 — — RP9R<5:0> — — RP8R<5:0> 0000 RPOR5 06DA — — RP11R<5:0> — — RP10R<5:0> 0000 RPOR6 06DC — — RP13R<5:0> — — RP12R<5:0> 0000 RPOR7 06DE — — RP15R<5:0> — — RP14R<5:0> 0000 RPOR16 06F0 — — RP33<5:0> — — RP32<5:0> 0000 RPOR17 06F2 — — RP35<5:0> — — RP34<5:0> 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS75018C-page 61 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-28: PORTA REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 0000 ODCA 02C6 — — — — — — — — — — — ODCA4 ODCA3 — — — 0000 SFR Name Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-30: SFR Name PORTB REGISTER MAP FOR dsPIC33FJ06GS001 AND dsPIC33FJ06GS101A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISB 02C8 — — — — — — — — TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 00FF PORTB 02CA — — — — — — — — RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CC — — — — — — — — LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 ODCB 02CE — — — — — — — — ODCB7 ODCB6 — — — — — — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-31: SFR Name PORTB REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 — — ODCB8 ODCB7 ODCB6 — — — — — — 0000 Legend: 2011-2012 Microchip Technology Inc. x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 62 TABLE 4-29: SYSTEM CONTROL REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) OSCCON 0742 — CLKLOCK IOLOCK LOCK — CF — — OSWEN 0300(2) CLKDIV 0744 ROI PLLFBD 0746 — — — — — — — — — — — — — COSC<2:0> — DOZE<2:0> DOZEN OSCTUN 0748 — LFSR 074C — REFOCON 074E ROON — ROSSLP ROSEL 0750 ENAPLL APLLCK SELACLK — ACLKCON Legend: Note 1: 2: FRCDIV<2:0> PLLPOST<1:0> — — 3040 — 0030 — TUN<5:0> 0000 LFSR<14:0> RODIV<3:0> — APSTSCLR<2:0> 0000 — — — — — — — — 0000 ASRCSEL FRCSEL — — — — — — 0000 Bit 4 Bit 3 Bit 2 Bit 1 NVM REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 NVMCON 0760 WR WREN WRERR — — — — — — ERASE — NVMKEY 0766 — — — — — — — — Legend: Note 1: PLLPRE<4:0> PLLDIV<8:0> x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. The RCON register Reset values are dependent on the type of Reset. The OSCCON register Reset values are dependent on the FOSCx Configuration bits and on type of Reset. TABLE 4-33: File Name NOSC<2:0> — NVMKEY<7:0> x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. NVMOP<3:0> Bit 0 All Resets 0000(1) 0000 DS75018C-page 63 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-32: SFR Name PMD REGISTER MAP FOR dsPIC33FJ06GS001 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 PMD1 0770 — — — T2MD PMD3 0774 — — — — PMD4 0776 — — — PMD6 077A — — — PMD7 077C — — — Legend: Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1MD — PWMMD — I2C1MD — — — — — — ADCMD 0000 — CMPMD — — — — — — — — — — 0000 — — — — — — — — — REFOMD — — — 0000 — PWM4MD — — PWM1MD — — — — — — — — 0000 — — — CMPMD2 CMPMD1 — — — — — — — — 0000 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-35: SFR Name All Resets Bit 10 PMD REGISTER MAP FOR dsPIC33FJ06GS101A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 PMD1 0770 — — — T2MD T1MD — PWMMD — I2C1MD — U1MD — — — ADCMD PMD2 0772 — — — — — — — — — — — — — — — OC1MD 0000 PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 PMD6 077A — — — — PWM4MD — — PWM1MD — — — — — — — — 0000 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-36: SFR Name SPI1MD PMD REGISTER MAP FOR dsPIC33FJ06GS102A 2011-2012 Microchip Technology Inc. SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 PMD1 0770 — — — T2MD T1MD — PWMMD — I2C1MD — U1MD — — — ADCMD PMD2 0772 — — — — — — — — — — — — — — — OC1MD 0000 PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 PMD6 077A — — — — — — PWM2MD PWM1MD — — — — — — — — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. SPI1MD dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 64 TABLE 4-34: SFR Name PMD REGISTER MAP FOR dsPIC33FJ06GS202A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 PMD1 0770 — — — T2MD T1MD — PMD2 0772 — — — — — — PMD3 0774 — — — — — CMPMD PMD4 0776 — — — — — — PMD6 077A — — — — — — PMD7 077C — — — — — — CMP2MD Legend: Bit 1 Bit 0 All Resets — — ADCMD 0000 — — OC1MD 0000 — — — — 0000 — REFOMD — — — 0000 — — — — — 0000 — — — — — — 0000 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PWMMD — I2C1MD — U1MD — — IC1MD — — — — — — — — — — — — — — — — PWM2MD PWM1MD — — — CMP1MD — — Bit 8 Bit 7 SPI1MD x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-38: SFR Name Bit 2 Bit 8 PMD REGISTER MAP FOR dsPIC33FJ09GS302 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 PMD1 0770 — — — T2MD T1MD — PWMMD — I2C1MD — U1MD — — — ADCMD 0000 PMD2 0772 — — — — — — — IC1MD — — — — — — — OC1MD 0000 PMD3 0774 — — — — — CMPMD — — — — — — — — — — 0000 PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 PMD6 077A — — — — PWM4MD — PWM2MD PWM1MD — — — — — — — — 0000 PMD7 077C — — — — — — CMP2MD CMP1MD — — — — — — — — 0000 PMD8 077E — — — — — — — — — — — — — — CCSMD — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. SPI1MD DS75018C-page 65 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. TABLE 4-37: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.3.1 4.4 SOFTWARE STACK In addition to its use as a working register, the W15 register in the devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and postincrements for stack pushes, as shown in Figure 4-5. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the push, ensuring that the MSb is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSb of the PC prior to the push. The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x1000 in RAM, initialize the SPLIM with the value 0x0FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 4-5: Stack Grows Toward Higher Address 0x0000 15 CALL STACK FRAME 0 PC<15:0> 000000000 PC<22:16> <Free Word> Instruction Addressing Modes The addressing modes shown in Table 4-39 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 4.4.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near Data Space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 4.4.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 <function> Operand 2 where Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: • • • • • Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-Bit or 10-Bit Literal Note: Not all instructions support all of the addressing modes shown above. Individual instructions can support different subsets of these addressing modes. W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] DS75018C-page 66 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 4-39: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Description The address of the File register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset 4.4.3 The sum of Wn and a literal forms the EA. MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (register offset) field is shared by both source and destination (but typically only used by one). In summary, the following addressing modes are supported by move and accumulator instructions: • • • • • • • • Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-Bit Literal 16-Bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. 2011-2012 Microchip Technology Inc. 4.4.4 MAC INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. The two-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU, and W10 and W11 are always directed to the Y AGU. The Effective Addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11. Note: Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). In summary, the following addressing modes are supported by the MAC class of instructions: • • • • • Register Indirect Register Indirect Post-modified by 2 Register Indirect Post-modified by 4 Register Indirect Post-modified by 6 Register Indirect with Register Offset (Indexed) 4.4.5 OTHER INSTRUCTIONS Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. DS75018C-page 67 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.5 Modulo Addressing 4.5.1 Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can be configured to operate in only one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer. The only exception to the usage restrictions is for buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries). START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 4-1). Note: Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). 4.5.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select the registers that will operate with Modulo Addressing: • If XWM = 15, X RAGU and X WAGU Modulo Addressing is disabled • If YWM = 15, Y AGU Modulo Addressing is disabled The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table 4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than ‘15’ and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>. FIGURE 4-6: MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 MOV MOV MOV MOV MOV MOV #0x1100, W0 W0, XMODSRT #0x1163, W0 W0, MODEND #0x8001, W0 W0, MODCON MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 MOV W0, [W1++] AGAIN: INC W0, W0 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;fill the 50 buffer locations ;fill the next location ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 32 words DS75018C-page 68 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.5.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: XB<14:0> is the Bit-Reversed Address modifier, or ‘pivot point,’ which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Note: • Upper boundary addresses for incrementing buffers • Lower boundary addresses for decrementing buffers It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes can, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.6 The modulo corrected Effective Address is written back to the register only when PreModify or Post-Modify Addressing mode is used to compute the Effective Address. When an address offset (such as [W7 + W2]) is used, Modulo Addressing correction is performed but the contents of the register remain unchanged. Bit-Reversed Addressing Bit-Reversed Addressing mode is intended to simplify data re-ordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. 4.6.1 All bit-reversed EA calculations assume word-sized data (LSb of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses. When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It will not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB), and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored (and always clear). Note: Modulo Addressing and Bit-Reversed Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing will assume priority when active for the X WAGU and X WAGU; Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU. If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer. BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled when all of these conditions are met: • BWMx bits (W register selection) in the MODCON register are any value other than ‘15’ (the stack cannot be accessed using Bit-Reversed Addressing) • BREN bit is set in the XBREV register • Addressing mode used is Register Indirect with Pre-increment or Post-increment If the length of a bit-reversed buffer is M = 2N bytes, the last ‘N’ bits of the data buffer start address must be zeros. 2011-2012 Microchip Technology Inc. DS75018C-page 69 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 4-7: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-40: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address A3 A2 A1 A0 Bit-Reversed Address Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 DS75018C-page 70 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.7 Interfacing Program and Data Memory Spaces 4.7.1 Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The device architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). Aside from normal execution, the device architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) For remapping operations, the 8-bit Program Space Visibility Register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-41: ADDRESSING PROGRAM SPACE Table 4-41 and Figure 4-8 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, and D<15:0> refers to a data space word. PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Program Space Address <23> <22:16> <15> <14:1> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 <0> 0 0xx xxxx xxxx xxxx xxxx xxx0 0xxx xxxx User Data EA<15:0> xxxx xxxx xxxx xxxx 0 PSVPAG<7:0> 0 xxxx xxxx Data EA<14:0>(1) xxx xxxx xxxx xxxx Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. 2011-2012 Microchip Technology Inc. DS75018C-page 71 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 4-8: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space Visibility(1) (Remapping) 0 1 EA 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS75018C-page 72 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.7.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. • TBLRDL (Table Read Low): - In Word mode, this instruction maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>) FIGURE 4-9: - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’. • TBLRDH (Table Read High): - In Word mode, this instruction maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. - In Byte mode, this instruction maps the upper or lower byte of the program word to D<7:0> of the data address, in the TBLRDL instruction. The data is always ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1). Similarly, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 0x020000 0x030000 00000000 00000000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W 0x800000 2011-2012 Microchip Technology Inc. The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. DS75018C-page 73 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.7.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL or TBLRDH). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 0x8000 and higher maps directly into a corresponding program memory address (see Figure 4-10), only the lower 16 bits of the 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction using PSV to access data, to execute in a single cycle. FIGURE 4-10: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space PSVPAG 02 23 15 Data Space 0 0x000000 0x0000 Data EA<14:0> 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... 0x8000 PSV Area 0x800000 DS75018C-page 74 ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 5.0 FLASH PROGRAM MEMORY pin pairs: PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/ 102A/202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Programming” (DS70191) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write a single program memory word at a time, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time. 5.1 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. These devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits<7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming FIGURE 5-1: Table Instructions and Flash Programming The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter Program Counter 0 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits User/Configuration Space Select 2011-2012 Microchip Technology Inc. 16 bits 24-bit EA Byte Select DS75018C-page 75 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 5.2 RTSP Operation The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 25-12 shows typical erase and programming times. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. 5.3 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished. The programming time depends on the FRC accuracy (see Table 25-19) and the value of the FRC Oscillator Tuning register (see Register 8-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time and Word Write Cycle Time parameters (see Table 25-12). EQUATION 5-1: For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 8-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. EQUATION 5-2: MINIMUM PAGE ERASE TIME 168517 Cycles T RW = ---------------------------------------------------------------------------------------------- = 21.85ms 7.37 MHz 1 + 0.05 1 – 0.00375 The maximum row write time is equal to Equation 5-3. EQUATION 5-3: MAXIMUM PAGE ERASE TIME 168517 Cycles T RW = ---------------------------------------------------------------------------------------------- = 24.16ms 7.37 MHz 1 – 0.05 1 – 0.00375 Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 5.4 Control Registers Two SFRs are used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. PROGRAMMING TIME T ------------------------------------------------------------------------------------------------------------------------7.37 MHz FRC Accuracy % FRC Tuning % DS75018C-page 76 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 5.5 Flash Memory Control Registers REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 WR(1) WREN(1) WRERR(1) — — — — — bit 15 bit 8 U-0 R/W-0 U-0 U-0 — ERASE(1) — — R/W-0 R/W-0 R/W-0 R/W-0 NVMOP<3:0>(1,2) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. This bit can only be set (not cleared) in software. 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit(1) 1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command 0 = Performs the program operation specified by NVMOP<3:0> on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,2) If ERASE = 1: 1111 = No operation 1101 = Erase general segment 0011 = No operation 0010 = Memory page erase operation 0001 = Reserved 0000 = Reserved If ERASE = 0: 1111 = No operation 1101 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Reserved 0000 = Reserved Note 1: 2: These bits can only be reset on a Power-on Reset (POR). All other combinations of NVMOP<3:0> are unimplemented. 2011-2012 Microchip Technology Inc. DS75018C-page 77 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only) DS75018C-page 78 x = Bit is unknown 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure 6-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: • • • • • • • • POR: Power-on Reset BOR: Brown-out Reset MCLR: Master Clear Pin Reset SWR: Software RESET Instruction WDTO: Watchdog Timer Reset CM: Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset FIGURE 6-1: Any active source of Reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state, and some are unaffected. Note: Refer to the specific peripheral section or Section 3.0 “CPU” of this data sheet for register Reset states. All types of device Reset sets a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A POR clears all the bits (except for the POR (RCON<0> bit) that are set. The user application can set or clear any bit, at any time, during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset is meaningful. RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD BOR Internal Regulator SYSRST VDD Rise Detect POR Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch 2011-2012 Microchip Technology Inc. DS75018C-page 79 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.1 Reset Control Register RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — — — CM VREGS bit 15 bit 8 R/W-0 EXTR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has occurred 0 = A Configuration Mismatch Reset has NOT occurred bit 8 VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep bit 7 EXTR: External Reset Pin (MCLR) bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset Flag (Instruction) bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode Note 1: 2: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS75018C-page 80 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: 2: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 2011-2012 Microchip Technology Inc. DS75018C-page 81 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.2 System Reset A warm Reset is the result of all the other Reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source, as indicated by the Current Oscillator Selection bits (COSC<2:0>) in the Oscillator Control register (OSCCON<14:12>). There are two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR). On a cold Reset, the FNOSC Configuration bits in the FOSC Configuration register select the device clock source. TABLE 6-1: The device is kept in a Reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. The sequence in which this occurs is provided in Figure 6-2. OSCILLATOR DELAY Oscillator Mode Oscillator Start-up Delay Oscillator Start-up Timer PLL Lock Time Total Delay FRC, FRCDIV16, FRCDIVN TOSCD(1) — — TOSCD(1) FRCPLL TOSCD(1) — TLOCK(3) TOSCD + TLOCK(1,3) XT TOSCD(1) TOST(2) — TOSCD + TOST(1,2) HS TOSCD(1) TOST(2) — TOSCD + TOST(1,2) EC — — — — XTPLL TOSCD(1) TOST(2) TLOCK(3) TOSCD + TOST + TLOCK(1,2,3) HSPLL TOSCD(1) TOST(2) TLOCK(3) TOSCD + TOST + TLOCK(1,2,3) TLOCK(3) TOSCD(1) ECPLL — — TLOCK(3) LPRC TOSCD(1) — — Note 1: 2: 3: TOSCD = Oscillator start-up delay (1.1 s max. for FRC, 70 s max. for LPRC). Crystal oscillator start-up times vary with crystal characteristics, load capacitance, etc. TOST = Oscillator Start-up Timer (OST) delay (1024 oscillator clock period). For example, TOST = 102.4 s for a 10 MHz crystal and TOST = 32 ms for a 32 kHz crystal. TLOCK = PLL lock time (1.5 ms nominal) if PLL is enabled. DS75018C-page 82 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR POR 1 TBOR 2 BOR 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Reset Device Status Run Time Note 1: 2: 3: 4: 5: 6: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. PWRT Timer: The programmable Power-up Timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay, TPWRT has elapsed and the SYSRST becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles. Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table 6-1. Refer to Section 8.0 “Oscillator Configuration” for more information. When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is ready and the delay, TFSCM, has elapsed. TABLE 6-2: Symbol OSCILLATOR PARAMETERS Parameter Value VPOR POR threshold 1.8V nominal TPOR POR extension time 30 s maximum VBOR BOR threshold 2.65V nominal 100 s maximum TBOR BOR extension time TPWRT Programmable 0-128 ms nominal Power-up Time delay TFSCM Fail-Safe Clock Mon- 900 s maximum itor delay 2011-2012 Microchip Technology Inc. Note: When the device exits the Reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device may not function correctly. The user application must ensure that the delay between the time power is first applied, and the time SYSRST becomes inactive, is long enough to get all operating parameters within the specification. DS75018C-page 83 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.3 Power-on Reset (POR) A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. The delay, TPOR, ensures the internal device bias circuits become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 25.0 “Electrical Characteristics” for details. The POR status (POR) bit in the Reset Control (RCON<0>) register is set to indicate the Power-on Reset. 6.4 Brown-out Reset (BOR) and Power-up Timer (PWRT) The on-chip regulator has a Brown-out Reset (BOR) circuit that resets the device when the VDD is too low (VDD < VBOR) for proper device operation. The BOR circuit keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. The BOR status bit in the Reset Control (RCON<1>) register is set to indicate the Brown-out Reset. The device will not run at full speed after a BOR, as the VDD should rise to acceptable levels for full-speed operation. The PWRT provides a Power-up Time Delay (TPWRT) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the SYSRST is released. Figure 6-3 shows the typical brown-out scenarios. The Reset delay (TBOR + TPWRT) is initiated each time VDD rises above the VBOR trip point. FIGURE 6-3: BROWN-OUT SITUATIONS VDD VBOR TBOR + TPWRT SYSRST VDD VBOR TBOR + TPWRT SYSRST VDD Dips Before PWRT Expires VDD VBOR TBOR + TPWRT SYSRST DS75018C-page 84 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.5 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 25.0 “Electrical Characteristics” for minimum pulse width specifications. The external Reset (MCLR) pin (EXTR) bit in the Reset Control (RCON) register is set to indicate the MCLR Reset. 6.5.1 EXTERNAL SUPERVISORY CIRCUIT Many systems have external supervisory circuits that generate Reset signals to reset multiple devices in the system. This external Reset signal can be directly connected to the MCLR pin to reset the device when the rest of the system is reset. 6.5.2 INTERNAL SUPERVISORY CIRCUIT When using the internal power supervisory circuit to reset the device, the external Reset pin (MCLR) should be tied directly or resistively to VDD. In this case, the MCLR pin will not be used to generate a Reset. The external Reset pin (MCLR) does not have an internal pull-up and must not be left unconnected. 6.6 Software RESET Instruction (SWR) Whenever the RESET instruction is executed, the device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will still remain. SYSRST is released at the next instruction cycle and the Reset vector fetch will commence. The Software Reset (SWR) flag (instruction) in the Reset Control register (RCON<6>) is set to indicate the software Reset. 6.7 Watchdog Time-out Reset (WDTO) Whenever a Watchdog Timer time-out occurs, the device will asynchronously assert SYSRST. The clock source will remain unchanged. A WDT time-out during Sleep or Idle mode will wake-up the processor, but will not reset the processor. 6.8 Trap Conflict Reset If a lower priority hard trap occurs, while a higher priority trap is being processed, a hard Trap Conflict Reset occurs. The hard traps include exceptions of Priority Level 13 through Level 15, inclusive. The address error (Level 13) and oscillator error (Level 14) traps fall into this category. The Trap Reset (TRAPR) flag in the Reset Control register (RCON<15>) is set to indicate the Trap Conflict Reset. Refer to Section 7.0 “Interrupt Controller” for more information on Trap Conflict Resets. 6.9 Illegal Condition Device Reset An illegal condition device Reset occurs due to the following sources: • Illegal Opcode Reset • Uninitialized W Register Reset • Security Reset The illegal opcode or Uninitialized W Access Reset (IOPUWR) flag in the Reset Control register (RCON<14>) is set to indicate the illegal condition device Reset. 6.9.1 ILLEGAL OPCODE RESET A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory. The Illegal Opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the Illegal Opcode Reset, use only the lower 16 bits of each program memory section to store the data values. The upper 8 bits should be programmed with 0x3F, which is an illegal opcode value. 6.9.2 UNINITIALIZED W REGISTER RESET Any attempt to use the uninitialized W register as an Address Pointer will Reset the device. The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. The Watchdog Timer Time-out (WDTO) flag in the Reset Control (RCON<4>) register is set to indicate the Watchdog Timer Reset. Refer to Section 22.4 “Watchdog Timer (WDT)” for more information on Watchdog Reset. 2011-2012 Microchip Technology Inc. DS75018C-page 85 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.10 Using the RCON Status Bits The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the Reset. Note: Table 6-3 provides a summary of the Reset flag bit operation. The status bits in the RCON register should be cleared after they are read so that the next RCON register value, after a device Reset, will be meaningful. TABLE 6-3: RESET FLAG BIT OPERATION Flag Bit Set by: Cleared by: TRAPR (RCON<15>) Trap conflict event POR, BOR IOPWR (RCON<14>) Illegal opcode or uninitialized W register access or Security Reset POR, BOR CM (RCON<9>) Configuration Mismatch POR, BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR, BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, CLRWDT instruction, POR, BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits can be set or cleared by user software. DS75018C-page 86 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 41. “Interrupts (Part IV)” (DS70300) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU. The controller has the following features: • Up to eight processor exceptions and software traps • Seven user-selectable priority levels • Interrupt Vector Table (IVT) with up to 118 vectors • A unique vector for each interrupt or exception source • Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug support • Fixed interrupt entry and return latencies 7.1 Interrupt Vector Table The Interrupt Vector Table (IVT) is shown in Figure 7-1. The IVT resides in program memory, starting at location, 000004h. The IVT contains 126 vectors, consisting of eight non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). 2011-2012 Microchip Technology Inc. Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with Vector 0 will take priority over interrupts at any other vector address. The devices implement up to 28 unique interrupts and four non-maskable traps. These are summarized in Table 7-1. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 7.2 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. A device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location, 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. DS75018C-page 87 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Decreasing Natural Order Priority FIGURE 7-1: Note 1: DS75018C-page 88 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Start of Code 0x000000 0x000002 0x000004 0x000014 0x00007C 0x00007E 0x000080 Interrupt Vector Table (IVT)(1) 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 Alternate Interrupt Vector Table (AIVT)(1) 0x00017C 0x00017E 0x000180 0x0001FE 0x000200 See Table 7-1 for the list of implemented interrupt vectors. 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 7-1: INTERRUPT VECTORS Vector Number Interrupt Request (IQR) IVT Address 8 0 0x000014 AIVT Address Interrupt Source Highest Natural Order Priority 0x000114 INT0 – External Interrupt 0 9 1 0x000016 0x000116 IC1 – Input Capture 1 10 2 0x000018 0x000118 OC1 – Output Compare 1 11 3 0x00001A 0x00011A T1 – Timer1 12-14 4-6 0x00001C-0x000020 15 7 0x000022 0x000122 T2 – Timer2 0x00011C-0x000120 Reserved 16 8 0x000024 0x000124 Reserved 17 9 0x000026 0x000126 SPI1E – SPI1 Error 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC – ADC Group Convert Done 22 14 0x000030 0x000130 Reserved Reserved 23 15 0x000032 0x000132 24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Event 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Event 26 18 0x000038 0x000138 CMP1 – Analog Comparator 1 Interrupt 27 19 0x00003A 0x00013A CN – Input Change Notification Interrupt 28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29-36 21-28 0x00003E-0x0004C 37 29 0x00004E 0x00014E 38-64 30-56 0x000050-0x000084 0x000150-0x000184 65 57 0x000086 0x000186 66-72 58-64 0x000088-0x000094 0x000188-0x000194 73 65 0x000096 74-87 66-79 0x000098-0x0000B2 88 80 0x0000B4 89-101 81-93 102 94 0x00013E-0x00014C Reserved 0x000196 INT2 – External Interrupt 2 Reserved PSEM – PWM Special Event Match Interrupt Reserved U1E – UART1 Error Interrupt 0x000198-0x0001B2 Reserved 0x0001B4 JTAG – Data Ready 0x0000B6-0x0000CE 0x0001B6-0x0001CE Reserved 0x0000D0 0x0001D0 PWM1 – PWM1 Interrupt 103 95 0x0000D2 0x0001D2 PWM2 – PWM2 Interrupt 104 96 0x0000D4 0x0001D4 Reserved 105 97 0x0000D6 0x0001D6 PWM4 – PWM4 Interrupt 106-110 98-102 0x0000D8-0x0000E0 111 103 0x0000E2 112-117 104-109 0x0000E4-0x0000EE 118 110 0x0000F0 0x0001F0 ADC Pair 0 Convert Done 119 111 0x0000F2 0x0001F2 ADC Pair 1 Convert Done 120 112 0x0000F4 0x0001F4 ADC Pair 2 Convert Done 121 113 0x0000F6 0x0001F6 ADC Pair 3 Convert Done 122 114 0x0000F8 0x0001F8 Reserved 123 115 0x0000FA 0x0001FA Reserved 124 116 0x0000FC 0x0001FC ADC Pair 6 Convert Done 125 117 0x0000FE 0x0001FE Reserved 0x0001D8-0x0001E0 Reserved 0x00001E2 CMP2 – Analog Comparator 2 Interrupt 0x0001E4-0x0001EE Reserved Lowest Natural Order Priority 2011-2012 Microchip Technology Inc. DS75018C-page 89 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 7.3 Interrupt Control and Status Registers The following registers are implemented for the interrupt controller: • • • • • • INTCON1 INTCON2 IFSx IECx IPCx INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. 7.3.2 IFSx The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.3.3 IECx The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. 7.3.4 IPCx 7.3.5 INTTREG The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt Priority Level, which are latched into the Vector Number (VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit fields in the INTTREG register. The new Interrupt Priority Level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 7-1. For example, the INT0 (External Interrupt 0) is shown as having Vector Number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit is found in IEC0<0> and the INT0IP bits are found in the first position of IPC0 (IPC0<2:0>). 7.3.6 STATUS/CONTROL REGISTERS Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. • The CPU STATUS Register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU Interrupt Priority Level. The user can change the current CPU priority level by writing to the IPL bits. • The CORCON register contains the IPL3 bit, which together with IPL<2:0>, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register 7-1 through Register 7-35. The IPCx registers are used to set the Interrupt Priority Level (IPL) for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. DS75018C-page 90 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) IPL<2:0>(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 7-5 Note 1: 2: 3: For complete register details, see Register 3-1. The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when IPL3 = 1. The IPL<2:0> status bits are read-only when NSTDIS (INTCON1<15>) = 1. REGISTER 7-2: U-0 — bit 15 U-0 — R/W-0 SATB Legend: R = Readable bit 0’ = Bit is cleared Note 1: 2: U-0 — R/W-0 US R/W-0 EDT R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATA bit 7 bit 3 CORCON: CORE CONTROL REGISTER(1) R/W-1 SATDW R/W-0 ACCSAT C = Clearable bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less For complete register details, see Register 3-2. The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. 2011-2012 Microchip Technology Inc. DS75018C-page 91 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap is disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap is disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B is enabled 0 = Trap is disabled bit 7 SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Divide-by-Zero Error Trap Status bit 1 = Math error trap was caused by a divide-by-zero 0 = Math error trap was not caused by a divide-by-zero bit 5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Math Error Trap Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred DS75018C-page 92 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. DS75018C-page 93 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Uses alternate vector table 0 = Uses standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS75018C-page 94 x = Bit is unknown 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-5: U-0 IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 — — R/W-0 ADIF R/W-0 (1) U1TXIF R/W-0 (1) U1RXIF R/W-0 SPI1IF (1) R/W-0 U-0 (1) SPI1EIF — bit 15 bit 8 R/W-0 U-0 T2IF U-0 — — U-0 R/W-0 — T1IF R/W-0 (1) OC1IF R/W-0 IC1IF R/W-0 (2) INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 ADIF: ADC Group Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPI1EIF: SPI1 Error Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 Unimplemented: Read as ‘0’ bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6-4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit(2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: 2: x = Bit is unknown This bit is not implemented in the dsPIC33FJ06GS001 device. This bit is not implemented in dsPIC33FJ06GS001/101A/102A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 95 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IF — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF AC1IF(1 MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 AC1IF: Analog Comparator 1 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS101A/102A devices. DS75018C-page 96 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIF: PWM Special Event Match Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ REGISTER 7-8: x = Bit is unknown IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — U1EIF(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown This bit is not implemented in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 97 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-9: IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IF(1) PWM1IF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — JTAGIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM2IF: PWM2 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-1 Unimplemented: Read as ‘0’ bit 0 JTAGIF: JTAG Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS001/101A devices. DS75018C-page 98 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-10: IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ADCP1IF ADCP0IF — — — — — — bit 15 bit 8 R/W-0 AC2IF U-0 (1) U-0 — — U-0 — U-0 — U-0 — R/W-0 U-0 (2) PWM4IF bit 7 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-8 Unimplemented: Read as ‘0’ bit 7 AC2IF: Analog Comparator 2 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6-2 Unimplemented: Read as ‘0’ bit 1 PWM4IF: PWM4 Interrupt Flag Status bit(2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: 2: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS101A/102A devices. This bit is not implemented in dsPIC33FJ06GS102A/202A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 99 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-11: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — — ADCP6IF — — ADCP3IF(1) ADCP2IF(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IF: ADC Pair 6 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3-2 Unimplemented: Read as ‘0’ bit 1 ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit(2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: 2: This bit is not implemented in dsPIC33FJ06GS102A/202A devices. This bit is not implemented in dsPIC33FJ06GS001/101A devices. DS75018C-page 100 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-12: U-0 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 — — R/W-0 ADIE R/W-0 (1) U1TXIE R/W-0 (1) U1RXIE R/W-0 (1) SPI1IE R/W-0 U-0 (1) SPI1EIE — bit 15 bit 8 R/W-0 U-0 T2IE U-0 — — U-0 — R/W-0 T1IE R/W-0 (1) OC1IE R/W-0 (2) IC1IE R/W-0 INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 ADIE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 SPI1IE: SPI1 Event Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 Unimplemented: Read as ‘0’ bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit(2) 1 = Interrupt request is enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: 2: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS001/101A/102A devices. This bit is not implemented in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 101 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IE — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — R/W-0 INT1IE R/W-0 CNIE R/W-0 (1) AC1IE R/W-0 R/W-0 MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 AC1IE: Analog Comparator 1 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS101A/102A devices. DS75018C-page 102 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIE: PWM Special Event Match Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8-0 Unimplemented: Read as ‘0’ REGISTER 7-15: x = Bit is unknown IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — U-0 — U-0 R/W-0 U-0 — U1EIE(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown This bit is not implemented in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 103 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IE(1) PWM1IE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — JTAGIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM2IE: PWM2 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 PWM1IE: PWM1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-1 Unimplemented: Read as ‘0’ bit 0 JTAGIE: JTAG Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS001/101A devices. DS75018C-page 104 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-17: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ADCP1IE ADCP0IE — — — — — — bit 15 bit 8 R/W-0 U-0 AC2IE(1) U-0 — — U-0 — U-0 — U-0 — R/W-0 U-0 (2) PWM4IE bit 7 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 ADCP0IE: ADC Pair 0 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-8 Unimplemented: Read as ‘0 bit 7 AC2IE: Analog Comparator 2 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6-2 Unimplemented: Read as ‘0’ bit 1 PWM4IE: PWM4 Interrupt Enable bit(2) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: 2: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS101A/102A devices. This bit is not implemented in dsPIC33FJ06GS102A/202A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 105 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-18: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — R/W-0 ADCP6IE U-0 U-0 — — R/W-0 ADCP3IE R/W-0 (1) ADCP2IE(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3-2 Unimplemented: Read as ‘0’ bit 1 ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit(2) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: 2: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS102A/202A devices. This bit is not implemented in dsPIC33FJ06GS001/101A devices. DS75018C-page 106 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-19: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 OC1IP<2:0> R/W-0 (1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 (2) — IC1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits(2) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Note 1: 2: x = Bit is unknown These bits are not implemented in the dsPIC33FJ06GS001 device. These bits are not implemented in dsPIC33FJ06GS001/101A/102A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 107 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-20: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ DS75018C-page 108 x = Bit is unknown 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-21: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 R/W-0 R/W-0 U1RXIP<2:0>(1) — U-0 R/W-1 R/W-0 R/W-0 SPI1IP<2:0>(1) — bit 15 bit 8 U-0 R/W-1 R/W-0 SPI1EIP<2:0>(1) — R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown These bits are not implemented in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 109 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 ADIP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADIP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Note 1: x = Bit is unknown These bits are not implemented in the dsPIC33FJ06GS001 device. DS75018C-page 110 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-23: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 — R/W-0 R/W-0 CNIP<2:0> U-0 R/W-1 R/W-0 R/W-0 AC1IP<2:0>(1) — bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Note 1: x = Bit is unknown These bits are not implemented in dsPIC33FJ06GS101A/102A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 111 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 7-25: x = Bit is unknown IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-1 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 INT2IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS75018C-page 112 x = Bit is unknown 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 R/W-0 PSEMIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PSEMIP<2:0>: PWM Special Event Match Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ REGISTER 7-27: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 U1EIP<2:0>(1) — R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown These bits are not implemented in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 113 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-28: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 JTAGIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 JTAGIP<2:0>: JTAG Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS75018C-page 114 x = Bit is unknown 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-29: U-0 IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 R/W-1 R/W-0 R/W-0 U-0 PWM2IP(1) — R/W-1 — R/W-0 R/W-0 PWM1IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM2IP<2:0>: PWM2 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown These bits are not implemented in dsPIC33FJ06GS001/101A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 115 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-30: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 (1) — PWM4IP U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PWM4IP<2:0>: PWM4 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown These bits are not implemented in dsPIC33FJ06GS102A/202A devices. DS75018C-page 116 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-31: U-0 IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 R/W-1 R/W-0 R/W-0 AC2IP<2:0>(1) — U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown These bits are not implemented in dsPIC33FJ06GS101A/102A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 117 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-32: U-0 IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 R/W-1 — R/W-0 R/W-0 ADCP1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 ADCP0IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS75018C-page 118 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-33: IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 (1) — ADCP3IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 (2) ADCP2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits(2) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Note 1: 2: x = Bit is unknown These bits are not implemented in dsPIC33FJ06GS102A/202A devices. These bits are not implemented in dsPIC33FJ06GS001/101A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 119 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-34: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 ADCP6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 ADCP6IP<2:0>: ADC Pair 6 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS75018C-page 120 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is Number 135 • • • 0000001 = Interrupt vector pending is Number 9 0000000 = Interrupt vector pending is Number 8 2011-2012 Microchip Technology Inc. x = Bit is unknown DS75018C-page 121 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 7.4 Interrupt Setup Procedures 7.4.1 7.4.3 INITIALIZATION Complete the following steps to configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources can be programmed to the same non-zero value. Note: 3. 4. At a device Reset, the IPCx registers are initialized such that all user interrupt sources are assigned to Priority Level 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. 7.4.2 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 7.4.4 INTERRUPT DISABLE The following steps outline the procedure to disable all user interrupts: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to Priority Level 7 by inclusive ORing the value, 0xE0 with SRL. To enable user interrupts, the POP instruction can be used to restore the previous SR value. Note: Only user interrupts with a priority level of 7 or lower can be disabled. Trap sources (Level 8-Level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of Priority Levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. INTERRUPT SERVICE ROUTINE The method used to declare an ISR and initialize IVT with the correct vector address depends on programming language (C or assembler) and language development toolsuite used to develop application. the the the the In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles; otherwise, the program will re-enter the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and the old CPU priority level. DS75018C-page 122 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 OSCILLATOR CONFIGURATION The oscillator system provides: • External and internal oscillator options as clock sources • An on-chip Phase Lock Loop (PLL) to scale the internal operating frequency to the required system clock frequency • An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware • Clock switching between various clock sources • Programmable clock postscaler for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures • An Oscillator Control register (OSCCON) • Nonvolatile Configuration bits for main oscillator selection • An auxiliary PLL for ADC and PWM A simplified diagram of the oscillator system is shown in Figure 8-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 42. “Oscillator (Part IV)” (DS70307) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 8-1: OSCILLATOR SYSTEM DIAGRAM OSC1 DOZE<2:0> Primary Oscillator POSCCLK R(2) XT, HS, EC S3 PLL(1) S1 OSC2 XTPLL, HSPLL, ECPLL, FRCPLL FVCO(1) S2 FCY(3) DOZE 8.0 S1/S3 POSCMD<1:0> FRCDIV FRC Oscillator FP(3) FRCCLK FRCDIVN FOSC FRCDIV<2:0> TUN<5:0> ÷2 S7 FRCDIV16 ÷ 16 FRC S0 LPRC LPRC Oscillator S6 S5 Reference Clock Generation POSCCLK ÷N FOSC RPx ROSEL Clock Fail Clock Switch Reset S7 NOSC<2:0> FNOSC<2:0> REFCLKO WDT, PWRT, FSCM RODIV<3:0> Auxiliary Clock Generation POSCCLK FRCCLK ASRCSEL Note 1: 2: 3: FVCO(1) APLL(1) x16 FRCSEL ÷N ENAPLL SELACLK ACLK, FADC To PWM/ADC(1) To LFSR APSTSCLR<2:0> See Section 8.1.3 “PLL Configuration” and Section 8.2 “Auxiliary Clock Generation” for configuration restrictions. If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected. The term, FP, refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this document, FP and FCY are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used in any ratio other than 1:1, which is the default. 2011-2012 Microchip Technology Inc. DS75018C-page 123 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.1 CPU Clocking System output frequencies for device operation. PLL configuration is described in Section 8.1.3 “PLL Configuration”. The devices provide six system clock options: • • • • • • Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Low-Power RC (LPRC) Oscillator FRC Oscillator with Postscaler 8.1.1 The FRC frequency depends on the FRC accuracy (see Table 25-20) and the value of the FRC Oscillator Tuning register (see Register 8-4). 8.1.2 SYSTEM CLOCK SOURCES The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz. User software can tune the FRC frequency. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the FRC clock frequency is divided. This factor is selected using the FRCDIV<2:0> (CLKDIV<10:8>) bits. The primary oscillator can use one of the following as its clock source: SYSTEM CLOCK SELECTION The oscillator source used at a device Power-on Reset event is selected using Configuration bit settings. The Oscillator Configuration bit settings are located in the Configuration registers in the program memory. (Refer to Section 22.1 “Configuration Bits” for further details.) The initial Oscillator Selection Configuration bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0> (FOSC<1:0>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator is the default (unprogrammed) selection. • XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins. • HS (High-Speed Crystal): Crystals in the range of 10 MHz to 32 MHz. The crystal is connected to the OSC1 and OSC2 pins. • EC (External Clock): The external clock signal is directly applied to the OSC1 pin. The Configuration bits allow users to choose among 12 different clock modes, shown in Table 8-1. The LPRC internal oscIllator runs at a nominal frequency of 32.768 kHz. It is also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). Instruction execution speed or device operating frequency, FCY, is given by Equation 8-1. The output of the oscillator (or the output of the PLL if a PLL mode has been selected), FOSC, is divided by 2 to generate the device instruction clock (FCY) and the peripheral clock time base (FP). FCY defines the operating speed of the device and speeds up to 40 MHz are supported by the device architecture. EQUATION 8-1: The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase Lock Loop (PLL) to provide a wide range of TABLE 8-1: DEVICE OPERATING FREQUENCY FCY = FOSC/2 CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> See Note Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2 Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal xx 101 1 Reserved xx 100 — Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 — Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011 — Reserved Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1 Primary Oscillator (HS) Primary 10 010 — Primary Oscillator (XT) Primary 01 010 — Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1 Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: 2: OSC2 pin function is determined by the OSCIOFNC Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. DS75018C-page 124 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.1.3 PLL CONFIGURATION • If PLLPOST<1:0> = 00, then N2 = 2. This provides a FOSC of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS. The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 8-2. EQUATION 8-3: FCY = FOSC = XT WITH PLL MODE EXAMPLE 1 * 32 ( 10000000 ) = 40 MIPS 2*2 The output of the primary oscillator or FRC, denoted as ‘FIN’, is divided down by a prescale factor (N1) of 2, 3, ... or 33 before being provided to the PLL’s Voltage Controlled Oscillator (VCO). The input to the VCO must be selected in the range of 0.8 MHz to 8 MHz. The prescale factor, ‘N1’, is selected using the PLLPRE<4:0> bits (CLKDIV<4:0>). 8.2 The PLL Feedback Divisor, selected using the PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’, by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output frequency is in the range of 100 MHz to 200 MHz. The primary oscillator and internal FRC oscillator sources can be used with an auxiliary PLL to obtain the auxiliary clock. The auxiliary PLL has a fixed 16x multiplication factor. • For proper PWM operation, auxiliary clock generation must be configured for 120 MHz (see Parameter OS56 in Table 25-18 in Section 25.0 “Electrical Characteristics”). If a slower frequency is desired, the PWM Input Clock Prescaler (Divider) Select bits (PCLKDIV<2:0>) should be used. • To achieve 1.04 ns PWM resolution, the auxiliary clock must use the 16x auxiliary PLL (APLL). All other clock sources will have a minimum PWM resolution of 8 ns. • If the primary PLL is used as a source for the auxiliary clock, the primary PLL should be configured up to a maximum operation of 30 MIPS or less FOSC CALCULATION (N1 M* N2) For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL (see Equation 8-3). 8.3 • If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz. • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged needed. FIGURE 8-2: Auxiliary Clock Generation The auxiliary clock has the following configuration restrictions: For a primary oscillator or FRC oscillator, output ‘FIN’, the PLL output ‘FOSC’, is given by Equation 8-2. FOSC = FIN * Reference Clock Generation The reference clock output logic provides the user with the ability to output a clock signal based on the system clock or the crystal oscillator on a device pin. The user application can specify a wide range of clock scaling prior to outputting the reference clock. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PLL BLOCK DIAGRAM FVCO 100-200 MHz Here(1) 0.8-8.0 MHz Here(1) Source (Crystal, External Clock or Internal RC) PLLPRE VCO X PLLDIV N1 Divide by 2-33 Note 1: 2 The auxiliary clock generation is used for a peripherals that need to operate at a frequency unrelated to the system clock, such as a PWM or ADC. The VCO output is further divided by a postscale factor, ‘N2’. This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4, or 8, and must be selected such that the PLL output frequency (FOSC) is in the range of 12.5 MHz to 80 MHz, which generates device operating speeds of 6.25-40 MIPS. EQUATION 8-2: 2 M Divide by 2-513 PLLPOST 12.5-80 MHz Here(1) FOSC N2 Divide by 2, 4, 8 This frequency range must be satisfied at all times. 2011-2012 Microchip Technology Inc. DS75018C-page 125 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.4 Oscillator Control Registers OSCCON: OSCILLATOR CONTROL REGISTER(1,3) REGISTER 8-1: U-0 R-0 — R-0 R-0 COSC<2:0> U-0 R/W-y — R/W-y NOSC<2:0> R/W-y (2) bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 U-0 R/W-0 CLKLOCK IOLOCK LOCK — CF — — OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 111 = Fast RC Oscillator (FRC) with divide-by-n 110 = Fast RC Oscillator (FRC) with divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Reserved 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with PLL 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2) 111 = Fast RC Oscillator (FRC) with divide-by-n 110 = Fast RC Oscillator (FRC) with divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Reserved 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with PLL 000 = Fast RC Oscillator (FRC) bit 7 CLKLOCK: Clock Lock Enable bit If clock switching is enabled and FSCM is disabled, FCKSM<1:0> (FOSC<7:6>) bits = 0b01): 1 = Clock switching is disabled, system clock source is locked 0 = Clock switching is enabled, system clock source can be modified by clock switching bit 6 IOLOCK: Peripheral Pin Select Lock bit 1 = Peripherial Pin Select is locked, write to Peripheral Pin Select registers is not allowed 0 = Peripherial Pin Select is not locked, write to Peripheral Pin Select registers is allowed bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled Note 1: 2: 3: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillator (Part IV)” (DS70307) in the “dsPIC33F/PIC24H Family Reference Manual” for details. Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. This register is reset only on a Power-on Reset (POR). DS75018C-page 126 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED) bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: 2: 3: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillator (Part IV)” (DS70307) in the “dsPIC33F/PIC24H Family Reference Manual” for details. Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. This register is reset only on a Power-on Reset (POR). 2011-2012 Microchip Technology Inc. DS75018C-page 127 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-2: R/W-0 CLKDIV: CLOCK DIVISOR REGISTER(2) R/W-0 ROI R/W-1 R/W-1 R/W-0 R/W-0 DOZEN(1) DOZE<2:0> R/W-0 R/W-0 FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 PLLPOST<1:0> U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits 111 = FCY/128 110 = FCY/64 101 = FCY/32 100 = FCY/16 011 = FCY/8 (default) 010 = FCY/4 001 = FCY/2 000 = FCY/1 bit 11 DOZEN: Doze Mode Enable bit(1) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio is forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 111 = FRC divide-by-256 110 = FRC divide-by-64 101 = FRC divide-by-32 100 = FRC divide-by-16 011 = FRC divide-by-8 010 = FRC divide-by-4 001 = FRC divide-by-2 000 = FRC divide-by-1 (default) bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler) 11 = Output/8 10 = Reserved 01 = Output/4 (default) 00 = Output/2 bit 5 Unimplemented: Read as ‘0’ bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 11111 = Input/33 • • • 00001 = Input/3 00000 = Input/2 (default) Note 1: 2: This bit is cleared when the ROI bit is set and an interrupt occurs. This register is reset only on a Power-on Reset (POR). DS75018C-page 128 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV8 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 111111111 = 513 • • • 000110000 = 50 (default) • • • 000000010 = 4 000000001 = 3 000000000 = 2 Note 1: This register is reset only on a Power-on Reset (POR). 2011-2012 Microchip Technology Inc. DS75018C-page 129 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center frequency + 11.625% (8.23 MHz) 011110 = Center frequency + 11.25% (8.20 MHz) • • • 000001 = Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.375% (7.345 MHz) • • • 100001 = Center frequency – 11.625% (6.52 MHz) 100000 = Center frequency – 12% (6.49 MHz) Note 1: 2: x = Bit is unknown OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. This register is reset only on a Power-on Reset (POR). DS75018C-page 130 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER(1) REGISTER 8-5: R/W-0 R-0 R/W-1 U-0 U-0 ENAPLL APLLCK SELACLK — — R/W-1 R/W-1 R/W-1 APSTSCLR<2:0>(2) bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL FRCSEL — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ENAPLL: Auxiliary PLL Enable bit 1 = APLL is enabled 0 = APLL is disabled bit 14 APLLCK: APLL Locked Status bit (read-only) 1 = Indicates that auxiliary PLL is in lock 0 = Indicates that auxiliary PLL is not in lock bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit 1 = Auxiliary oscillators provides the source clock for auxiliary clock divider 0 = Primary PLL (FVCO) provides the source clock for auxiliary clock divider bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider bits(2) 111 = Divided by 1 110 = Divided by 2 101 = Divided by 4 100 = Divided by 8 011 = Divided by 16 010 = Divided by 32 001 = Divided by 64 000 = Divided by 256 bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit 1 = Primary oscillator is the clock source 0 = No clock input is selected bit 6 FRCSEL: Select Reference Clock Source for Auxiliary PLL bit 1 = Selects FRC clock for auxiliary PLL 0 = Input clock source is determined by ASRCSEL bit setting bit 5-0 Unimplemented: Read as ‘0’ Note 1: 2: This register is reset only on a Power-on Reset (POR). The auxiliary clock postscaler must be configured to divide-by-1 (APSTSCLR<2:0> = 111) for proper operation of the PWM module. 2011-2012 Microchip Technology Inc. DS75018C-page 131 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-6: R/W-0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER U-0 ROON — R/W-0 ROSSLP R/W-0 R/W-0 R/W-0 ROSEL R/W-0 RODIV<3:0> R/W-0 (1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 7 U-0 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is enabled on REFCLK0 pin(2) 0 = Reference oscillator output is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Run in Sleep bit 1 = Reference oscillator output continues to run in Sleep 0 = Reference oscillator output is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Oscillator crystal used as the reference clock 0 = System clock used as the reference clock bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits(1) 1111 = Reference clock divided by 32,768 1110 = Reference clock divided by 16,384 1101 = Reference clock divided by 8,192 1100 = Reference clock divided by 4,096 1011 = Reference clock divided by 2,048 1010 = Reference clock divided by 1,024 1001 = Reference clock divided by 512 1000 = Reference clock divided by 256 0111 = Reference clock divided by 128 0110 = Reference clock divided by 64 0101 = Reference clock divided by 32 0100 = Reference clock divided by 16 0011 = Reference clock divided by 8 0010 = Reference clock divided by 4 0001 = Reference clock divided by 2 0000 = Reference clock bit 7-0 Unimplemented: Read as ‘0’ Note 1: 2: x = Bit is unknown The reference oscillator output must be disabled (ROON = 0) before writing to these bits. This pin is remappable; refer to Section 10.6 “Peripheral Pin Select (PPS)” for more information. DS75018C-page 132 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-7: U-0 LFSR: LINEAR FEEDBACK SHIFT REGISTER R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 LFSR<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LFSR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-0 LFSR<14:0>: Pseudo Random FRC Trim Value bits 2011-2012 Microchip Technology Inc. x = Bit is unknown DS75018C-page 133 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.5 Clock Switching Operation Applications are free to switch among any of the four clock sources (primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, devices have a safeguard lock built into the switch process. Note: 8.5.1 Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD<1:0> Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch among the different primary submodes without reprogramming the device. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. 2. 3. ENABLING CLOCK SWITCHING To enable clock switching, the FCKSM1 Configuration bit in the FOSC Configuration register must be programmed to ‘0’. (Refer to Section 22.1 “Configuration Bits” for further details.) If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. 4. The NOSC<2:0> control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC<2:0> bits (OSCCON<14:12>) reflect the clock source selected by the FNOSC Configuration bits. 6. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at ‘0’ at all times. 8.5.2 OSCILLATOR SWITCHING SEQUENCE To perform a clock switch, the following basic sequence is required: 1. 2. 3. 4. 5. If desired, read the COSC<2:0> bits to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSC<2:0> control bits for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. DS75018C-page 134 5. The clock switching hardware compares the COSC<2:0> status bits with the new value of the NOSC<2:0> control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware waits until the Oscillator Start-up Timer (OST) expires. If the new source is using the PLL, the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC<2:0> bit values are transferred to the COSC<2:0> status bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM is enabled). Note 1: The processor continues to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: Refer to Section 42. “Oscillator (Part IV)” (DS70307) in the “dsPIC33F/ PIC24H Family Reference Manual” for details. 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.6 Fail-Safe Clock Monitor (FSCM) 8.7 The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate, even in the event of an oscillator failure. The FSCM function is enabled by programming. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer. The pseudo-random generator is implemented with a 15-bit Linear Feedback Shift Register (LFSR), which is a shift register with a few exclusive OR gates. The shift register is clocked by the PWM clock and is a read-only register. The purpose of this feature is to provide the ability to randomly change the period or the active portion of the PWM. In the event of an oscillator failure, the FSCM generates a clock failure trap event and switches the system clock over to the FRC oscillator. Then, the application program can either attempt to restart the oscillator or execute a controlled shutdown. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. A firmware routine can be used to read “n” random bits from the LFSR register and combine them, by either summing or performing another logical operation with the PWM period of the Duty Cycle registers. The result will be a PWM signal whose nominal period (or duty cycle) is the desired one, but whose effective value changes randomly. This capability will help in reducing the EMI/EMC emissions by spreading the power over a wider frequency range. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. FIGURE 8-3: Pseudo-Random Generator Figure 8-3 provides a block diagram of the LFSR. LFSR BLOCK DIAGRAM All Zero Detect LFSR 15 D Q0 D Q1 D Q2 D Q3 D Q4 D Q5 D Q6 D Q7 D Q8 D Q9 D Q10 D Q11 D Q12 D Q13 D Q14 CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q 2011-2012 Microchip Technology Inc. DS75018C-page 135 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 136 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 9.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer (WDT) and Power-Saving Modes” (DS70196) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. These devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. Devices can manage power consumption in four different ways: • • • • Clock Frequency Instruction-Based Sleep and Idle modes Software Controlled Doze mode Selective Peripheral Control in Software Combinations of these methods can be used to selectively tailor an application’s power consumption while still maintaining critical application features, such as timing-sensitive communications. 9.1 Clock Frequency and Clock Switching These devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC<2:0> bits (OSCCON<10:8>). The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 8.0 “Oscillator Configuration”. EXAMPLE 9-1: 9.2 Instruction-Based Power-Saving Modes The devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembler syntax of the PWRSAV instruction is shown in Example 9-1. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to wake-up. 9.2.1 SLEEP MODE The following occur in Sleep mode: • The system clock source is shut down. If an on-chip oscillator is used, it is turned off. • The device current consumption is reduced to a minimum, provided that no I/O pin is sourcing current. • The Fail-Safe Clock Monitor does not operate since the system clock source is disabled. • The LPRC clock continues to run in Sleep mode if the WDT is enabled. • The WDT, if enabled, is automatically cleared prior to entering Sleep mode. • Some device features or peripherals may continue to operate. This includes items, such as the Input Change Notification (ICN) on the I/O ports or peripherals that use an external clock input. • Any peripheral that requires the system clock source for its operation is disabled. The device will wake-up from Sleep mode on any of these events: • Any interrupt source that is individually enabled • Any form of device Reset • A WDT time-out On wake-up from Sleep mode, the processor restarts with the same clock source that was active when Sleep mode was entered. PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE PWRSAV #IDLE_MODE ; Put the device into SLEEP mode ; Put the device into IDLE mode 2011-2012 Microchip Technology Inc. DS75018C-page 137 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Peripheral Module Disable”). • If the WDT or FSCM is enabled, the LPRC also remains active. The device will wake-up from Idle mode on any of these events: • Any interrupt that is individually enabled • Any device Reset • A WDT time-out On wake-up from Idle mode, the clock is reapplied to the CPU and instruction execution will begin (2-4 clock cycles later), starting with the instruction following the PWRSAV instruction, or the first instruction in the ISR. 9.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction is held off until entry into Sleep or Idle mode has completed. The device then wakes up from Sleep or Idle mode. 9.3 Doze Mode The preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. In some circumstances, this may not be practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. Programs can use Doze mode to selectively reduce power consumption in event-driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU Idles, waiting for something to invoke an interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. 9.4 Peripheral Module Disable The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers will have no effect and read values will be invalid. A peripheral module is enabled only if both the associated bit in the PMD register is cleared and the peripheral is supported by the specific dsPIC® DSC variant. If the peripheral is present in the device, it is enabled in the PMD register by default. Note: If a PMD bit is set, the corresponding module is disabled after a delay of one instruction cycle. Similarly, if a PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. DS75018C-page 138 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 9.5 PMD Control Registers REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — — — T2MD T1MD — PWMMD(1) — bit 15 bit 8 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 I2C1MD — U1MD(2) — SPI1MD(2) — — ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled bit 10 Unimplemented: Read as ‘0’ bit 9 PWMMD: PWM Module Disable bit(1) 1 = PWM module is disabled 0 = PWM module is enabled bit 8 Unimplemented: Read as ‘0’ bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled bit 6 Unimplemented: Read as ‘0’ bit 5 U1MD: UART1 Module Disable bit(2) 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 Unimplemented: Read as ‘0’ bit 3 SPI1MD: SPI1 Module Disable bit(2) 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 ADCMD: ADC Module Disable bit 1 = ADC module is disabled 0 = ADC module is enabled Note 1: 2: x = Bit is unknown Once the PWM module is re-enabled (PWMMD is set to ‘1’ and then set to ‘0’), all PWM registers must be re-initialized. This bit is not implemented in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 139 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC1MD(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — OC1MD(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘0’ bit 8 IC1MD: Input Capture 1 Module Disable bit(1) 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7-1 Unimplemented: Read as ‘0’ bit 0 OC1MD: Output Compare 1 Module Disable bit(2) 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled Note 1: 2: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS001/101A/102A devices. This bit is not implemented in the dsPIC33FJ06GS001 device. DS75018C-page 140 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — CMPMD(1) — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Analog Comparator Module Disable bit(1) 1 = Analog comparator module is disabled 0 = Analog comparator module is enabled bit 9-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS101A/102A devices. REGISTER 9-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 — — — — REFOMD — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 REFOMD: Reference Clock Generator Module Disable bit 1 = Reference clock generator module is disabled 0 = Reference clock generator module is enabled bit 2-0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. x = Bit is unknown DS75018C-page 141 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-5: U-0 PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 U-0 — — U-0 — U-0 — R/W-0 U-0 (1) PWM4MD — R/W-0 PWM2MD R/W-0 (2) PWM1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11 PWM4MD: PWM Generator 4 Module Disable bit(1) 1 = PWM Generator 4 module is disabled 0 = PWM Generator 4 module is enabled bit 10 Unimplemented: Read as ‘0’ bit 9 PWM2MD: PWM Generator 2 Module Disable bit(2) 1 = PWM Generator 2 module is disabled 0 = PWM Generator 2 module is enabled bit 8 PWM1MD: PWM Generator 1 Module Disable bit 1 = PWM Generator 1 module is disabled 0 = PWM Generator 1 module is enabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: 2: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS102A/202A devices. This bit is not implemented in dsPIC33FJ06GS001/101A devices. DS75018C-page 142 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-6: U-0 PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 — — U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 (1) CMP2MD CMP1MD(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 CMP2MD: Analog Comparator 2 Module Disable bit(1) 1 = Analog Comparator 2 module is disabled 0 = Analog Comparator 2 module is enabled bit 8 CMP1MD: Analog Comparator 1 Module Disable bit(1) 1 = Analog Comparator 1 module is disabled 0 = Analog Comparator 1 module is enabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS101A/102A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 143 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-7: PMD8: PERIPHERAL MODULE DISABLE CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — CCSMD(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 CCSMD: Constant Current Source Module Disable bit(1) 1 = Constant current source module is disabled 0 = Constant current source module is enabled bit 0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown This bit is not implemented in dsPIC33FJ06GS101A/102A/202A devices. DS75018C-page 144 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.0 I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “I/O Ports” (DS70193) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. All of the device pins (except VDD, VSS, MCLR and OSC1/CLKI) are shared among the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 10.1 When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin can be read, but the output driver for the parallel port bit is disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. Parallel I/O (PIO) Ports Generally a parallel I/O port that shares a pin with a peripheral is subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. 2011-2012 Microchip Technology Inc. DS75018C-page 145 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data I/O Peripheral Module Enable Peripheral Output Enable 1 Output Enable 0 Peripheral Output Data PIO Module WR TRIS Output Data 0 Read TRIS Data Bus 1 D Q I/O Pin CK TRIS Latch D WR LAT + WR PORT Q CK Data Latch Read LAT Input Data Read PORT DS75018C-page 146 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.2 Open-Drain Configuration In addition to the PORT, LAT and TRIS registers for data control, some digital only port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (for example, 5V), on any desired 5V tolerant pins, by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. Refer to the “Pin Diagrams” section for the available pins and their functionality. 10.3 Configuring Analog Port Pins The ADPCFG and TRIS registers control the operation of the Analog-to-Digital port pins. The port pins that are to function as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The ADPCFG register has a default value of 0x0000; therefore, all pins that share ANx functions are analog (not digital) by default. When the PORT register is read, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin, defined as a digital input (including the ANx pins), can cause the input buffer to consume current that exceeds the device specifications. EXAMPLE 10-1: MOV MOV NOP BTSS 0xFF00, W0 W0, TRISBB PORTB, #13 10.4 I/O Port Write/Read Timing One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. An example is shown in Example 10-1. 10.5 Input Change Notification The Input Change Notification function of the I/O ports allows devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature can detect input Change-of-States (COS), even in Sleep mode when the clocks are disabled. Depending on the device pin count, up to 16 external signals (CNx pin) can be selected (enabled) for generating an interrupt request on a Change-of-State. Four control registers are associated with the CN module. The CNEN1 register contains the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pin. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source connected to the pin and eliminate the need for external resistors when the push button or keypad devices are connected. The pull-ups are enabled separately, using the CNPU1 register, which contains the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. PORT WRITE/READ EXAMPLE ; ; ; ; 2011-2012 Microchip Technology Inc. Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Delay 1 cycle Next Instruction DS75018C-page 147 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.6 Peripheral Pin Select (PPS) Peripheral Pin Select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The Peripheral Pin Select configuration feature operates over a fixed subset of digital I/O pins. Programmers can independently map the input and/or output of most digital peripherals to any one of these I/O pins. Peripheral Pin Select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 10.6.1 AVAILABLE PINS The Peripheral Pin Select feature is used with a range of up to 16 pins. The number of available pins depends on the particular device and its pin count. Pins that support the Peripheral Pin Select feature include the designation, “RPn”, in their full pin designation, where “RP” designates a remappable peripheral and “n” is the remappable pin number. 10.6.2 10.6.2.1 The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 10-1 through Register 10-15). Each register contains sets of 6-bit fields, with each set associated with one of the remappable peripherals. Programming a given peripheral’s bit field with an appropriate 6-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any bit field corresponds to the maximum number of Peripheral Pin Selections supported by the device. Figure 10-2 illustrates the remappable pin selection for the U1RX input. Note: The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or output is being mapped. For input mapping only, the Peripheral Pin Select (PPS) functionality does not have priority over the TRISx settings. Therefore, when configuring the RPx pin for input, the corresponding bit in the TRISx register must also be configured for input (i.e., set to ‘1’). FIGURE 10-2: CONTROLLING PERIPHERAL PIN SELECT Peripheral Pin Select features are controlled through two sets of Special Function Registers: one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. Input Mapping REMAPPABLE MUX INPUT FOR U1RX U1RXR<5:0> 0 RP0 1 RP1 2 U1RX Input to Peripheral RP2 15 RP15 DS75018C-page 148 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Function Name Register Configuration Bits INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> Timer1 External Clock T1CK RPINR2 T1CKR<5:0> Timer2 External Clock T2CK RPINR3 T2CKR<5:0> IC1 RPINR7 IC1R<5:0> Input Name External Interrupt 1 Input Capture 1 Output Compare Fault A OCFA RPINR11 OCFAR<5:0> UART1 Receive U1RX RPINR18 U1RXR<5:0> UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<5:0> SPI Data Input 1 SDI1 RPINR20 SDI1R<5:0> SPI Clock Input 1 SCK1 RPINR20 SCK1R<5:0> SPI Slave Select Input 1 SS1 RPINR21 SS1R<5:0> PWM Fault Input FLT1 RPINR29 FLT1R<5:0> PWM Fault Input FLT2 RPINR30 FLT2R<5:0> PWM Fault Input FLT3 RPINR30 FLT3R<5:0> PWM Fault Input FLT4 RPINR31 FLT4R<5:0> PWM Fault Input FLT5 RPINR31 FLT5R<5:0> PWM Fault Input FLT6 RPINR32 FLT6R<5:0> PWM Fault Input FLT7 RPINR32 FLT7R<5:0> PWM Fault Input FLT8 RPINR33 FLT8R<5:0> External Synchronization Signal to PWM Master Time Base SYNCI1 RPINR33 SYNCI1R<5:0> External Synchronization Signal to PWM Master Time Base SYNCI2 RPINR34 SYNCI2R<5:0> 2011-2012 Microchip Technology Inc. DS75018C-page 149 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.6.2.2 Output Mapping FIGURE 10-3: In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Like the RPINRx registers, each register contains sets of 6-bit fields, with each set associated with one RPn pin (see Register 10-16 through Register 10-25). The value of the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-2 and Figure 10-3). The list of peripherals for output mapping also includes a null value of ‘00000’ because of the mapping technique. This permits any given pin to remain unconnected from the output of any of the pin selectable peripherals. MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPORn<5:0> Default U1TX Output Enable U1RTS Output Enable 0 3 4 Output Enable OC1 Output Enable PWM4L Output Enable 18 45 Default 0 U1TX Output 3 U1RTS Output 4 Output Data OC1 Output PWM4L Output TABLE 10-2: Function RPn 18 45 OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) RPORn<5:0> NULL 000000 Output Name RPn tied to default port pin U1TX 000011 RPn tied to UART1 transmit U1RTS 000100 RPn tied to UART1 Ready-to-Send SDO1 000111 RPn tied to SPI1 data output SCK1 001000 RPn tied to SPI1 clock output SS1 001001 RPn tied to SPI1 slave select output OC1 010010 RPn tied to Output Compare 1 SYNCO1 100101 RPn tied to external device synchronization signal via PWM master time base REFCLKO 100110 REFCLK output signal ACMP1 100111 RPn tied to Analog Comparator 1 output ACMP2 101000 RPn tied to Analog Comparator 2 output PWM4H 101100 RPn tied to PWM output pins associated with PWM Generator 4 PWM4L 101101 RPn tied to PWM output pins associated with PWM Generator 4 DS75018C-page 150 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.6.2.3 Virtual Pins Four virtual RPn pins (RP32, RP33, RP34 and RP35) are supported, which are identical in functionality to all other RPn pins, with the exception of pinouts. These four pins are internal to the devices and are not connected to a physical device pin. These pins provide a simple way for inter-peripheral connection without utilizing a physical pin. For example, the output of the analog comparator can be connected to RP32 and the PWM Fault input can be configured for RP32 as well. This configuration allows the analog comparator to trigger PWM Faults without the use of an actual physical pin on the device. 10.6.3 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dsPIC33F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit pin select lock 10.6.3.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON<6>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all of the Peripheral Pin Selects to be configured with a single unlock sequence, followed by an update to all control registers, then locked with a second lock sequence. 10.6.3.2 Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered. 10.6.3.3 Configuration Bit Pin Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (FOSC<5>) Configuration bit blocks the IOLOCK bit from being cleared, after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 0x46 to OSCCON<7:0>. Write 0x57 to OSCCON<7:0>. Clear (or set) IOLOCK as a single operation. Note: MPLAB® C30 provides built-in C language functions for unlocking the OSCCON register: __builtin_write_OSCCONL(value) __builtin_write_OSCCONH(value) See the MPLAB C30 Help files for more information. 2011-2012 Microchip Technology Inc. DS75018C-page 151 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.7 1. 2. In some cases, certain pins, as defined in Table 25-9 under “Injection Current”, have internal protection diodes to VDD and VSS. The term, “Injection Current”, is also referred to as “Clamp Current”. On designated pins, with sufficient external current limiting precautions by the user, I/O pin input voltages are allowed to be greater or less than the data sheet absolute maximum ratings with respect to the VSS and VDD supplies. Note that when the user application forward biases either of the high or low side internal input clamp diodes, that the resulting current being injected into the device that is clamped internally by the VDD and VSS power rails, may affect the ADC accuracy by four to six counts. I/O pins that are shared with any analog input pin (i.e., ANx) are always analog pins by default after any Reset. Consequently, any pin(s) configured as an analog input pin, automatically disables the digital input pin buffer. As such, any attempt to read a digital input pin will always return a ‘0’, regardless of the digital logic level on the pin if the analog pin is configured. To use a pin as a digital I/O pin on a shared ANx pin, the user application needs to configure the Analog Pin register in the ADC module (i.e., ADPCFG) by setting the appropriate bit that corresponds to that I/O port pin to a ‘1’. On devices with more than one ADC, both analog pin configurations for both ADC modules must be configured as a digital I/O pin for that pin to function as a digital I/O pin. Note: 3. I/O Helpful Tips Although it is not possible to use a digital input pin when its analog function is enabled, it is possible to use the digital I/O output function, TRISx = 0x0, while the analog function is also enabled. However, this is not recommended, particularly if the analog input is connected to an external analog voltage source, which would create signal contention between the analog signal and the output pin driver. Most I/O pins have multiple functions. Referring to the device pin diagrams in the data sheet, the priorities of the functions allocated to any pins are indicated by reading the pin name from left-to-right. The left most function name takes precedence over any function to its right in the naming convention; for example: AN2/CMP1C/CMP2A/RA2. This indicates that AN2 is the highest priority in this example and will supersede all other functions to its right in the list. Those other functions to its right, even if enabled, would not work as long as any other function to its left was enabled. This rule applies to all of the functions listed for a given pin. DS75018C-page 152 4. 5. Each CN pin has a configurable internal weak pull-up resistor. The pull-ups act as a current source connected to the pin and eliminates the need for external resistors in certain applications. The internal pull-up is to ~(VDD – 0.8), not VDD. This is still above the minimum VIH of CMOS and TTL devices. When driving LEDs directly, the I/O pin can source or sink more current than what is specified in the VOH/IOH and VOL/IOL DC Characteristics specification. The respective IOH and IOL current rating only applies to maintaining the corresponding output at or above the VOH, and at or below the VOL levels. However, for LEDs, unlike digital inputs of an externally connected device, they are not governed by the same minimum VIH/VIL levels. An I/O pin output can safely sink or source any current less than that listed in the “Absolute Maximum Ratings(1)” in Section 25.0, Electrical Characteristics of this data sheet. For example: VOH = 2.4V @ IOL = -6 mA and VDD = 3.3V The maximum output current sourced by any 4x I/O pin = 15 mA. LED source current <15 mA is technically permitted. Refer to the VOH/IOH graphs in Section 26.0 “DC and AC Device Characteristics Graphs” for additional information. 10.8 I/O Resources Many useful resources related to I/O are provided on the Microchip web site (www.microchip.com). 10.8.1 KEY RESOURCES • “dsPIC33F/PIC24H Family Reference Manual”, Section 10. “I/O Ports” (DS70193) • Code Samples • Application Notes • Software Libraries • Webinars • All related “dsPIC33F/PIC24H Family Reference Manual” Sections • Development Tools 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.9 Peripheral Pin Select Registers The following registers are implemented for remappable peripheral configuration: Not all Output Remappable Peripheral registers are implemented on all devices. See the register description of the specific register for further details. • 15 Input Remappable Peripheral Registers • 19 Output Remappable Peripheral Registers Note: Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0. See Section 10.6.3.1 “Control Register Lock” for a specific command sequence. REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 INT1R<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT1R<5:0>: Assign External Interrupt 1 (INTR1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. DS75018C-page 153 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 INT2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INTR2) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS75018C-page 154 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-3: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T1CKR<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T1CKR<5:0>: Assign Timer1 External Clock (T1CK) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. DS75018C-page 155 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-4: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T2CKR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR<5:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS75018C-page 156 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC1R<5:0>(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits(1) 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A/102A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 157 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OCFAR<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Compare A (OCFA) to the Corresponding RPn Pin bits(1) 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device. DS75018C-page 158 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1CTSR<5:0>(1) bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR<5:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits(1) 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U1RXR<5:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits(1) 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 159 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-8: U-0 RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 — R/W-1 R/W-1 — R/W-1 R/W-1 SCK1R<5:0> R/W-1 R/W-1 (1) bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SDI1R<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R<5:0>: Assign SPI1 Clock Input (SCK1) to the Corresponding RPn Pin bits(1) 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI1R<5:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits(1) 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device. DS75018C-page 160 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-9: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SS1R<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R<5:0>: Assign SPI1 Slave Select Input (SS1) to the Corresponding RPn Pin bits(1) 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 161 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-10: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT1R<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT1R<5:0>: Assign PWM Fault Input 1 (FLT1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ DS75018C-page 162 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-11: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT3R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT3R<5:0>: Assign PWM Fault Input 3 (FLT3) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FLT2R<5:0>: Assign PWM Fault Input 2 (FLT2) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 2011-2012 Microchip Technology Inc. DS75018C-page 163 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-12: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT5R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT4R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT5R<5:0>: Assign PWM Fault Input 5 (FLT5) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FLT4R<5:0>: Assign PWM Fault Input 4 (FLT4) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS75018C-page 164 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-13: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT7R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT6R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT7R<5:0>: Assign PWM Fault Input 7 (FLT7) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FLT6R<5:0>: Assign PWM Fault Input 6 (FLT6) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 2011-2012 Microchip Technology Inc. DS75018C-page 165 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-14: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SYNCI1R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT8R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SYNCI1R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FLT8R<5:0>: Assign PWM Fault Input 8 (FLT8) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS75018C-page 166 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-15: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SYNCI2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SYNCI2R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 2011-2012 Microchip Technology Inc. DS75018C-page 167 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-16: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP1R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP0R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP1R<5:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP0R<5:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 10-2 for peripheral function numbers) REGISTER 10-17: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP3R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP3R<5:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP2R<5:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-2 for peripheral function numbers) DS75018C-page 168 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-18: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP5R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP4R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP5R<5:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP4R<5:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 10-2 for peripheral function numbers) REGISTER 10-19: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP7R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP6R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP7R<5:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP6R<5:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 10-2 for peripheral function numbers) 2011-2012 Microchip Technology Inc. DS75018C-page 169 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-20: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP9R<5:0>(1) bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) — RP8R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP9R<5:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits(1) (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP8R<5:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits(1) (see Table 10-2 for peripheral function numbers) Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices. REGISTER 10-21: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP11R<5:0>(1) — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP10R<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP11R<5:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits(1) (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP10R<5:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits(1) (see Table 10-2 for peripheral function numbers) Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices. DS75018C-page 170 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-22: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP13R<5:0>(1) bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) — RP12R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP13R<5:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits(1) (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP12R<5:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits(1) (see Table 10-2 for peripheral function numbers) Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices. REGISTER 10-23: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP15R<5:0>(1) — bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP14R<5:0>(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP15R<5:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits(1) (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP14R<5:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits(1) (see Table 10-2 for peripheral function numbers) Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 171 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-24: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP33R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP32R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP33R<5:0>: Peripheral Output Function is Assigned to RP33 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP32R<5:0>: Peripheral Output Function is Assigned to RP32 Output Pin bits (see Table 10-2 for peripheral function numbers) REGISTER 10-25: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP35R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP34R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP35R<5:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP34R<5:0>: Peripheral Output Function is Assigned to RP34 Output Pin bits (see Table 10-2 for peripheral function numbers) DS75018C-page 172 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 11.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock applications. A block diagram of Timer1 is shown in Figure 11-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). The Timer1 module can operate in one of the following modes: • • • • In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous and Asynchronous Counter modes, the input clock is derived from the external clock input at the T1CK pin. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Timer1 modes are determined by the following bits: • Timer1 Clock Source Control bit: TCS (T1CON<1>) • Timer1 Synchronization Control bit: TSYNC (T1CON<2>) • Timer1 Gate Control bit: TGATE (T1CON<6>) The Timer1 module is a 16-bit timer, which can serve as a time counter for the Real-Time Clock (RTC) or operate as a free-running interval timer/counter. The Timer1 control bit settings for different operating modes are given in the Table 11-1. The Timer1 module has the following unique features over other timers: TABLE 11-1: • Can be operated from the low-power 32 kHz crystal oscillator available on the device • Can be operated in Asynchronous Counter mode from an external clock source • The Timer1 External Clock Input (T1CK) can optionally be synchronized to the internal device clock and the clock synchronization is performed after the prescaler FIGURE 11-1: Timer mode Gated Timer mode Synchronous Counter mode Asynchronous Counter mode Mode TIMER1 MODE SETTINGS TCS TGATE TSYNC Timer1 0 0 x Gated Timer1 0 1 x Synchronous Counter 1 x 1 Asynchronous Counter 1 x 0 16-BIT TIMER1 MODULE BLOCK DIAGRAM Falling Edge Detect Gate Sync 1 Set T1IF Flag 0 FP 10 Prescaler (/n) 00 TCKPS<1:0> TMR1 Reset TGATE 0 T1CK x1 Prescaler (/n) TCKPS<1:0> 2011-2012 Microchip Technology Inc. Sync TSYNC Comparator 1 Equal TGATE TCS PR1 DS75018C-page 173 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 11.1 Timer1 Control Register REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> U-0 R/W-0 R/W-0 U-0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ DS75018C-page 174 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 12.0 TIMER2 FEATURES In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is derived from the external clock input at the TxCK pin. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). The Timer modes are determined by the following bits: • TCS (TxCON<1>): Timer Clock Source Control bit • TGATE (TxCON<6>): Timer Gate Control bit The Timer control bit settings for different operating modes are given in Table 12-1. TABLE 12-1: Mode 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. TCS TGATE Timer 0 0 Gated Timer 0 1 Synchronous Counter 1 x 12.1 Timer2 is a Type B timer with an external clock input (TxCK) that is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler. 1. 2. • Timer mode • Gated Timer mode • Synchronous Counter mode 3. 4. 5. Select the timer prescaler ratio using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the Timer Period value into the PRx register. If interrupts are required, set the Timerx Interrupt Enable bit, TxIE. Use the priority bits, TxIP<2:0>, to set the interrupt priority. Set the TON bit. TYPE B TIMER BLOCK DIAGRAM (x = 2) Gate Sync FP Falling Edge Detect Prescaler (/n) TCKPS<1:0> 00 Sync Set TxIF Flag 0 TMRx x1 Comparator Reset TGATE Equal TGATE TCS 2011-2012 Microchip Technology Inc. 1 10 Prescaler (/n) TCKPS<1:0> TxCK 16-Bit Operation To configure any of the timers for individual 16-bit operation: The Timer2 module can operate in one of the following modes: FIGURE 12-1: TIMER MODE SETTINGS PRx DS75018C-page 175 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 12.2 Timer2 Control Register REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> U-0 U-0 R/W-0 U-0 — — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit 1 = Starts 16-bit timer 0 = Stops 16-bit timer bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinues timer operation when device enters Idle mode 0 = Continues timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit 1 = External clock from T2CK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ DS75018C-page 176 x = Bit is unknown 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 13.0 INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The input capture module is useful in applications requiring frequency (period) and pulse measurement. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the IC1 pin. The events that cause a capture event are listed below in three categories: FIGURE 13-1: • Simple Capture Event modes: - Capture timer value on every falling edge of input at IC1 pin - Capture timer value on every rising edge of input at IC1 pin • Capture timer value on every edge (rising and falling) • Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at IC1 pin - Capture timer value on every 16th rising edge of input at IC1 pin The input capture module uses the Timer2 module as its timer; however, it can use either an internal or external clock. Other operational features include: • Device wake-up from capture pin during CPU Sleep and Idle modes • Interrupt on input capture event • 4-word FIFO buffer for capture values: - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled • Use of input capture to provide additional sources of external interrupts INPUT CAPTURE BLOCK DIAGRAM TMR2 16 Edge Detection Logic and Clock Synchronizer Prescaler Counter (1, 4, 16) IC1 Pin ICM<2:0> (IC1CON<2:0>) Mode Select FIFO 3 FIFO R/W Logic ICOV, ICBNE (IC1CON<4:3>) IC1BUF ICI<1:0> IC1CON System Bus 2011-2012 Microchip Technology Inc. Interrupt Logic Set Flag IC1IF (in IFS0 Register) DS75018C-page 177 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 13.1 Input Capture Registers REGISTER 13-1: IC1CON: INPUT CAPTURE 1 CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 ICTMR(1) R/W-0 ICI<1:0> R-0, HC R-0, HC ICOV ICBNE R/W-0 R/W-0 R/W-0 ICM<2:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture Timer Select bit(1) 1 = TMR2 contents are captured on capture event 0 = Reserved bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode. Rising edge detect only; all other control bits are not applicable. 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling). ICI<1:0> bits do not control interrupt generation for this mode. 000 = Input capture module is turned off Note 1: This bit is not available in dsPIC33FJ06GS001/101A/102A devices. DS75018C-page 178 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 14.0 OUTPUT COMPARE output pulse, or a sequence of output pulses, by changing the state of the output pin on the compare match events. The output compare module can also generate interrupts on compare match events. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Output Compare” (DS70209) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). The output compare module has multiple operating modes: • • • • • • • 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Note: The output compare module is not implemented in the dsPIC33FJ06GS001 device. If a Fault condition is detected on the OCFA pin, the output pin(s) of the output compare module are placed in tri-state. The user may elect to use a pull-down or pull-up resistor on the PWM pin to provide for a desired state if a Fault condition occurs. The output compare module can select either Timer1 or Timer2 for its time base. The module compares the value of the timer with the value of one or two Compare registers, depending on the operating mode selected. The state of the output pin changes when the timer value matches the Output Compare register value. The output compare module generates either a single FIGURE 14-1: Active-Low One-Shot mode Active-High One-Shot mode Toggle mode Delayed One-Shot mode Continuous Pulse mode PWM mode without Fault Protection PWM mode with Fault Protection OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit, OC1IF OC1RS Output Logic OC1R 3 OCM<2:0> Mode Select Comparator S R Q OC1 Output Enable OCFA 16 TMR2 2011-2012 Microchip Technology Inc. TMR2 Rollover DS75018C-page 179 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 14.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to avoid malfunctions. Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OC1CON<2:0>) register. Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes. The user TABLE 14-1: Refer to Section 13. “Output Compare” (DS70209) in the “dsPIC33F/PIC24H Family Reference Manual” for OC1R and OC1RS register restrictions. OUTPUT COMPARE MODES OCM<2:0> 000 Note: Mode Module Disabled OC1 Pin Initial State OC1 Interrupt Generation Controlled by GPIO register — 001 Active-Low One-Shot 0 OC1 rising edge 010 Active-High One-Shot 1 OC1 falling edge 011 Toggle 100 Delayed One-Shot Current output is maintained OC1 rising and falling edge 0 OC1 falling edge 0 OC1 falling edge 101 Continuous Pulse 110 PWM without Fault Protection ‘0’ if OC1R is zero, ‘1’ if OC1R is non-zero No interrupt 111 PWM with Fault Protection ‘0’ if OC1R is zero, ‘1’ if OC1R is non-zero OCFA falling edge for OC1 to OC4 FIGURE 14-2: OUTPUT COMPARE OPERATION Output Compare Mode Enabled Timerx is Reset on Period Match OC1RS TMRx OC1R Active-Low One-Shot (OCM<2:0> = 001) Active-High One-Shot (OCM<2:0> = 010) Toggle (OCM<2:0> = 011) Delayed One-Shot (OCM<2:0> = 100) Continuous Pulse (OCM<2:0> = 101) PWM (OCM<2:0> = 110 or 111) DS75018C-page 180 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 14.2 Output Compare Control Registers REGISTER 14-1: OC1CON: OUTPUT COMPARE 1 CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC U-0 — — — OCFLT — R/W-0 R/W-0 R/W-0 OCM<2:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare 1 halts in CPU Idle mode 0 = Output Compare 1 continues to operate in CPU Idle mode x = Bit is unknown bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) bit 3 Unimplemented: Read as ‘0’ bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OC1, Fault pin is enabled 110 = PWM mode on OC1, Fault pin is disabled 101 = Initializes OC1 pin low, generates continuous output pulses on OC1 pin 100 = Initializes OC1 pin low, generates single output pulse on OC1 pin 011 = Compare event toggles OC1 pin 010 = Initializes OC1 pin high, compare event forces OC1 pin low 001 = Initializes OC1 pin low, compare event forces OC1 pin high 000 = Output compare channel is disabled 2011-2012 Microchip Technology Inc. DS75018C-page 181 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 182 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 15.0 HIGH-SPEED PWM Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 43. “High-Speed PWM” (DS70323) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The high-speed PWM module supports a wide variety of PWM modes and output formats. This PWM module is ideal for power conversion applications, such as: • • • • • • • AC/DC Converters DC/DC Converters Power Factor Correction (PFC) Uninterruptible Power Supply (UPS) Inverters Battery Chargers Digital Lighting 15.1 Features Overview The high-speed PWM module incorporates the following features: • Two to three PWM generators with four to six outputs • Individual time base and duty cycle for each of the six PWM outputs • Dead time for rising and falling edges: • Duty cycle resolution of 1.04 ns(1,2) • Dead-time resolution of 1.04 ns(1,2) • Phase-shift resolution of 1.04 ns(1,2) • Frequency resolution of 1.04 ns(1,2) Note 1: Resolution is 8.32 ns in Center-Aligned PWM mode. 2: Resolution is 8.32 ns for dsPIC33FJ06GS001 devices. 2011-2012 Microchip Technology Inc. • Supported PWM modes: - Standard Edge-Aligned - True Independent Output - Complementary - Center-Aligned - Push-Pull - Multiphase - Variable Phase - Fixed Off Time - Current Reset - Current Limit • Independent Fault/Current-Limit inputs for each of the six PWM outputs • Output override control • Special Event Trigger • PWM capture feature • Prescaler for input clock • Dual trigger from PWM to ADC • PWMxH, PWMxL output pin swapping • Remappable PWM4H, PWM4L pins • On-the-fly PWM frequency, duty cycle and phase-shift changes • Disabling of individual PWM generators to reduce power consumption • Leading-Edge Blanking (LEB) functionality • PWM output chopping (see Note 1) Note 1: The chopping function performs a logical AND of the PWM outputs with a very high-frequency clock signal. The chopping frequency is typically hundreds or thousands of time higher in frequency, as compared to the PWM frequency. Chopping a PWM signal constrains the use of a pulse transformer to cross the isolation barrier. Figure 15-1 conceptualizes the PWM module in a simplified block diagram. Figure 15-2 illustrates how the module hardware is partitioned for each PWM output pair for the Complementary PWM mode. Each functional unit of the PWM module is discussed in subsequent sections. The PWM module contains three PWM generators. The module has up to six PWM output pins: PWM1H, PWM1L, PWM2H, PWM2L, PWM4H and PWM4L. For complementary outputs, these six I/O pins are grouped into H/L pairs. DS75018C-page 183 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 15.2 Feature Description The PWM module is designed for applications that require: • High-resolution at high PWM frequencies • The ability to drive Standard, Edge-Aligned, Center-Aligned Complementary mode, and Push-Pull mode outputs • The ability to create multiphase PWM outputs For Center-Aligned mode, the duty cycle, period, phase and dead-time resolutions will be 8.32 ns. Two common, medium power converter topologies are push-pull and half-bridge. These designs require the PWM output signal to be switched between alternate pins, as provided by the Push-Pull PWM mode. A multiphase PWM is often used to improve DC/DC Converter load transient response, and reduce the size of output filter capacitors and inductors. Multiple DC/ DC Converters are often operated in parallel, but phase-shifted in time. A single PWM output, operating at 250 kHz, has a period of 4 s, but an array of four PWM channels staggered by 1 s each, yields an effective switching frequency of 1 MHz. Multiphase PWM applications typically use a fixed-phase relationship. A variable phase PWM is useful in Zero Voltage Transition (ZVT) power converters. Here, the PWM duty cycle is always 50%, and the power flow is controlled by varying the relative phase-shift between the two PWM generators. A phase-shifted PWM describes the situation where each PWM generator provides outputs, but the phase relationship between the generator outputs is specifiable and changeable. DS75018C-page 184 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 15-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-SPEED PWM PWMCONx Pin and Mode Control LEBCONx Control for Blanking External Input Signals TRGCONx ADC Trigger Control Dead-Time Control ALTDTRx, DTRx PWM Enable and Mode Control PTCON MDC Master Duty Cycle Register PDC1 MUX Latch PWM Generator 1 Comparator Channel 1 Dead-Time Generator PWM1H Channel 2 Dead-Time Generator PWM2H PWM1L Timer 16-Bit Data Bus MUX Latch PWM Generator 2(2) Comparator Timer Phase PDC4 MUX Latch PWM Generator 4(3) Comparator Timer Phase PTPER PWM4H(1) PWM4L(1) Chop Clock Generator Fault Control Logic Special Event Comparison Value Pin Override Control Special Event Postscaler Special Event Trigger Fault Mode and Pin Control 1: These pins are remappable. 2: This PWM generator is not available in dsPIC33FJ06GS001/101A devices. 3: This PWM generator is only available in dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302A devices. 2011-2012 Microchip Technology Inc. FLTX(1) SYNCO1(1) SYNCIX(1) External Time Base Synchronization FCLCONx Note CHOP Master Time Base Comparator IOCONx Channel 4 Dead-Time Generator Timer Period PTMR SEVTCMP PWM2L Fault CLMT Override Logic PDC2 PWM User, Current-Limit and Fault Override and Routing Logic Phase DS75018C-page 185 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 15-2: PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE Phase Offset TMRx < PDC Timer/Counter PWM Override Logic Dead-Time Logic M U X PWMXH M U X PWMXL Duty Cycle Comparator PWM Duty Cycle Register Channel Override Values Fault Override Values Fault Pin 15.3 Fault Pin Assignment Logic PWM Control Registers The following registers control the operation of the high-speed PWM module. • • • • • • • • • • • • PTCON: PWM Time Base Control Register PTCON2: PWM Clock Divider Select Register 2 PTPER: PWM Master Time Base Register(1) SEVTCMP: PWM Special Event Compare Register MDC: PWM Master Duty Cycle Register PWMCONx: PWMx Control Register PDCx: PWMx Generator Duty Cycle Register(1) PHASEx: PWMx Primary Phase Shift Register DTRx: PWMx Dead-Time Register ALTDTRx: PWMx Alternate Dead-Time Register SDCx: PWMx Secondary Duty Cycle Register(1) SPHASEx: PWMx Secondary Phase Shift Register DS75018C-page 186 Fault Active • TRGCONx: PWMx Trigger Control Register • IOCONx: PWMx I/O Control Register • FCLCONx: PWMx Fault Current-Limit Control Register • TRIGx: PWMx Primary Trigger Compare Value Register • STRIGx: PWMx Secondary Trigger Compare Value Register • LEBCONx: PWMx Leading-Edge Blanking Control Register • PWMCAPx: Primary PWMx Time Base Capture Register • CHOP: PWM Chop Clock Generator Register • AUXCONx: PWMx Auxiliary Control Register 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-1: R/W-0 PTEN bit 15 R/W-0 (1) bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5-4 bit 3-0 Note 1: R/W-0 HS/HC-0 R/W-0 R/W-0 — PTSIDL SESTAT SEIEN EIPU(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCSRC<1:0>(1) R/W-0 R/W-0 SYNCPOL(1) SYNCOEN(1) bit 8 R/W-0 R/W-0 SEVTPS<3:0>(1) bit 0 Legend: R = Readable bit -n = Value at POR bit 14 bit 13 U-0 — SYNCEN bit 7 bit 15 PTCON: PWM TIME BASE CONTROL REGISTER HC = Hardware Clearable bit W = Writable bit ‘1’ = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PTEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled Unimplemented: Read as ‘0’ PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode SESTAT: Special Event Interrupt Status bit 1 = Special event interrupt is pending 0 = Special event interrupt is not pending SEIEN: Special Event Interrupt Enable bit 1 = Special event interrupt is enabled 0 = Special event interrupt is disabled EIPU: Enable Immediate Period Updates bit(1) 1 = Active Period register is updated immediately 0 = Active Period register updates occur on PWM cycle boundaries SYNCPOL: Synchronization Input/Output Polarity bit(1) 1 = SYNCIx and SYNCO1 polarity is inverted (active-low) 0 = SYNCIx and SYNCO1 are active-high SYNCOEN: Primary Time Base Sync Enable bit(1) 1 = SYNCO1 output is enabled 0 = SYNCO1 output is disabled SYNCEN: External Time Base Synchronization Enable bit(1) 1 = External synchronization of primary time base is enabled 0 = External synchronization of primary time base is disabled Unimplemented: Read as ‘0’ SYNCSRC<1:0>: Synchronous Source Selection bits(1) 11 = Reserved 10 = Reserved 01 = SYNCI2 00 = SYNCI1 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates a Special Event Trigger on every sixteenth compare match event • • • 0001 = 1:2 Postscaler generates a Special Event Trigger on every second compare match event 0000 = 1:1 Postscaler generates a Special Event Trigger on every compare match event These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user application must program the Period register with a value that is slightly larger than the expected period of the external synchronization input signal. 2011-2012 Microchip Technology Inc. DS75018C-page 187 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide-by-64, maximum PWM timing resolution 101 = Divide-by-32, maximum PWM timing resolution 100 = Divide-by-16, maximum PWM timing resolution 011 = Divide-by-8, maximum PWM timing resolution 010 = Divide-by-4, maximum PWM timing resolution 001 = Divide-by-2, maximum PWM timing resolution 000 = Divide-by-1, maximum PWM timing resolution (power-on default) Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. REGISTER 15-3: R/W-1 PTPER: PWM MASTER TIME BASE REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PTPER <15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PTPER <7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown PTPER<15:0>: PWM Master Time Base (PMTMR) Period Value bits The minimum value that can be loaded into the PTPER register is 0x0010 and the maximum value is 0xFFF8. DS75018C-page 188 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-4: R/W-0 SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP <15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP <7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 SEVTCMP<15:3>: Special Event Compare Count Value bits bit 2-0 Unimplemented: Read as ‘0’ REGISTER 15-5: R/W-0 x = Bit is unknown MDC: PWM MASTER DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<15:8>(1,2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<7:0>(1,2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown MDC<15:0>: Master PWM Duty Cycle Value bits(1,2) The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period – 0x0008. As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of operation), the PWM duty cycle resolution will degrade from 1 LSb to 3 LSbs. 2011-2012 Microchip Technology Inc. DS75018C-page 189 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-6: HS/HC-0 PWMCONx: PWMx CONTROL REGISTER HS/HC-0 FLTSTAT(1) CLSTAT (1) HS/HC-0 TRGSTAT R/W-0 FLTIEN R/W-0 CLIEN R/W-0 R/W-0 (3) TRGIEN ITB R/W-0 MDCS(3) bit 15 bit 8 R/W-0 R/W-0 DTC<1:0> U-0 — U-0 — U-0 — R/W-0 CAM (2,3) R/W-0 (4) XPRES R/W-0 IUE bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTSTAT: Fault Interrupt Status bit(1) 1 = Fault interrupt is pending 0 = No Fault interrupt is pending; this bit is cleared by setting FLTIEN = 0 bit 14 CLSTAT: Current-Limit Interrupt Status bit(1) 1 = Current-limit interrupt is pending 0 = No current-limit interrupt is pending; this bit is cleared by setting CLIEN = 0 bit 13 TRGSTAT: Trigger Interrupt Status bit 1 = Trigger interrupt is pending 0 = No trigger interrupt is pending; this bit is cleared by setting TRGIEN = 0 bit 12 FLTIEN: Fault Interrupt Enable bit 1 = Fault interrupt is enabled 0 = Fault interrupt is disabled and the FLTSTAT bit is cleared bit 11 CLIEN: Current-Limit Interrupt Enable bit 1 = Current-limit interrupt is enabled 0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared bit 10 TRGIEN: Trigger Interrupt Enable bit 1 = A trigger event generates an interrupt request 0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared bit 9 ITB: Independent Time Base Mode bit(3) 1 = PHASEx/SPHASEx register provides time base period for this PWM generator 0 = PTPER register provides timing for this PWM generator bit 8 MDCS: Master Duty Cycle Register Select bit(3) 1 = MDC register provides duty cycle information for this PWM generator 0 = PDCx/SDCx register provides duty cycle information for this PWM generator bit 7-6 DTC<1:0>: Dead-Time Control bits 11 = Reserved 10 = Dead-time function is disabled 01 = Negative dead time actively applied for all output modes 00 = Positive dead time actively applied for all output modes bit 5-3 Unimplemented: Read as ‘0’ Note 1: 2: 3: 4: Software must clear the interrupt status here and the corresponding IFSx bit in the interrupt controller. The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. To operate in External Period Reset mode, configure the CLMOD (FCLCONx<8>) bit = 0 and ITB (PWMCONx<9>) bit = 1. DS75018C-page 190 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER (CONTINUED) bit 2 CAM: Center-Aligned Mode Enable bit(2,3) 1 = Center-Aligned mode is enabled 0 = Center-Aligned mode is disabled bit 1 XPRES: External PWM Reset Control bit(4) 1 = Current-limit source resets time base for this PWM generator if it is in Independent Time Base mode 0 = External pins do not affect PWM time base bit 0 IUE: Immediate Update Enable bit 1 = Updates to the active MDC/PDCx/SDCx registers are immediate 0 = Updates to the active MDC/PDCx/SDCx registers are synchronized to the PWM time base Note 1: 2: 3: 4: Software must clear the interrupt status here and the corresponding IFSx bit in the interrupt controller. The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. To operate in External Period Reset mode, configure the CLMOD (FCLCONx<8>) bit = 0 and ITB (PWMCONx<9>) bit = 1. 2011-2012 Microchip Technology Inc. DS75018C-page 191 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-7: R/W-0 PDCx: PWMx GENERATOR DUTY CYCLE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown PDCx<15:0>: PWMx Generator # Duty Cycle Value bits(2) In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both the PWMxH and PWMxL. The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period-0x0008. As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs. REGISTER 15-8: R/W-0 SDCx: PWMx SECONDARY DUTY CYCLE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDCx<15:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDCx<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown SDCx<15:0>: Secondary Duty Cycle for PWMxL Output Pin bits(2) The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the SDCx register controls the PWMxL duty cycle. The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period-0x0008. As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs. DS75018C-page 192 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-9: R/W-0 PHASEx: PWMx PRIMARY PHASE SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8>(1,2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0>(1,2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown PHASEx<15:0>: PWMx Phase Shift Value or Independent Time Base Period for PWM Generator bits(1,2) If the ITB (PWMCONx<9>) bit = 0, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10), PHASEx<15:0> = Phase shift value for PWMxH and PWMxL outputs. • True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11), PHASEx<15:0> = Phase shift value for PWMxL only. If the ITB (PWMCONx<9>) bit = 1, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10), PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL. • True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11), PHASEx<15:0> = Independent time base period value for PWMxL only. • The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008, while the maximum pulse width generated corresponds to a value of Period-0x0008. 2011-2012 Microchip Technology Inc. DS75018C-page 193 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<15:8>(1,2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<7:0>(1,2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits(1,2) (used in Independent PWM mode only) If the ITB (PWMCONx<9>) bit = 0, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10), SPHASEx<15:0> = Not used. • True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11), PHASEx<15:0> = Phase shift value for PWMxL only. If the ITB (PWMCONx<9>) bit = 1, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10), SPHASEx<15:0> = Not used. • True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11), PHASEx<15:0> = Independent time base period value for PWMxL only. DS75018C-page 194 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 . REGISTER 15-11: DTRx: PWMx DEAD-TIME REGISTER U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits REGISTER 15-12: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALTDTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALTDTR <7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits 2011-2012 Microchip Technology Inc. DS75018C-page 195 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-13: TRGCONx: PWMx TRIGGER CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 TRGDIV<3:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 R/W-0 U-0 DTM(1) — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSTRT<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits 1111 = Trigger output for every 16th trigger event 1110 = Trigger output for every 15th trigger event 1101 = Trigger output for every 14th trigger event 1100 = Trigger output for every 13th trigger event 1011 = Trigger output for every 12th trigger event 1010 = Trigger output for every 11th trigger event 1001 = Trigger output for every 10th trigger event 1000 = Trigger output for every 9th trigger event 0111 = Trigger output for every 8th trigger event 0110 = Trigger output for every 7th trigger event 0101 = Trigger output for every 6th trigger event 0100 = Trigger output for every 5th trigger event 0011 = Trigger output for every 4th trigger event 0010 = Trigger output for every 3rd trigger event 0001 = Trigger output for every 2nd trigger event 0000 = Trigger output for every trigger event bit 11-8 Unimplemented: Read as ‘0’ bit 7 DTM: Dual Trigger Mode bit(1) 1 = Secondary trigger event is combined with the primary trigger event to create the PWM trigger. 0 = Secondary trigger event is not combined with the primary trigger event to create the PWM trigger; two separate PWM triggers are generated bit 6 Unimplemented: Read as ‘0’ bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits 111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled • • • 000010 = Wait 2 PWM cycles before generating the first trigger event after the module is enabled 000001 = Wait 1 PWM cycle before generating the first trigger event after the module is enabled 000000 = Wait 0 PWM cycle before generating the first trigger event after the module is enabled Note 1: The secondary generator cannot generate PWM trigger interrupts. DS75018C-page 196 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 PENH PENL POLH POLL R/W-0 R/W-0 PMOD<1:0>(1) R/W-0 R/W-0 OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 FLTDAT<1:0>(2) OVRDAT<1:0> R/W-0 R/W-0 CLDAT<1:0>(2) R/W-0 R/W-0 SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PENH: PWMxH Output Pin Ownership bit 1 = PWM module controls PWMxH pin 0 = GPIO module controls PWMxH pin bit 14 PENL: PWMxL Output Pin Ownership bit 1 = PWM module controls PWMxL pin 0 = GPIO module controls PWMxL pin bit 13 POLH: PWMxH Output Pin Polarity bit 1 = PWMxH pin is active-low 0 = PWMxH pin is active-high bit 12 POLL: PWMxL Output Pin Polarity bit 1 = PWMxL pin is active-low 0 = PWMxL pin is active-high bit 11-10 PMOD<1:0>: PWMx I/O Pin Mode bits(1) 11 = PWM I/O pin pair is in the True Independent Output mode 10 = PWM I/O pin pair is in the Push-Pull Output mode 01 = PWM I/O pin pair is in the Redundant Output mode 00 = PWM I/O pin pair is in the Complementary Output mode bit 9 OVRENH: Override Enable for PWMxH Pin bit 1 = OVRDAT<1> provides data for output on PWMxH pin 0 = PWM generator provides data for PWMxH pin bit 8 OVRENL: Override Enable for PWMxL Pin bit 1 = OVRDAT<0> provides data for output on PWMxL pin 0 = PWM generator provides data for PWMxL pin bit 7-6 OVRDAT<1:0>: Data for PWMxH and PWMxL Pins if Override is Enabled bits If OVERENH = 1 then OVRDAT<1> provides data for PWMxH. If OVERENL = 1 then OVRDAT<0> provides data for PWMxL. bit 5-4 FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(2) IFLTMOD (FCLCONx<15>) = 0, Normal Fault mode: If Fault is active, then FLTDAT<1> provides the state for PWMxH. If Fault is active, then FLTDAT<0> provides the state for PWMxL. IFLTMOD (FCLCONx<15>) = 1, Independent Fault mode: If current-limit is active, then FLTDAT<1> provides the state for PWMxH. If Fault is active, then FLTDAT<0> provides the state for PWMxL. Note 1: 2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. State represents the active/inactive state of the PWM module depending on the POLH and POLL bit settings. 2011-2012 Microchip Technology Inc. DS75018C-page 197 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMODE is Enabled bits(2) IFLTMOD (FCLCONx<15>) = 0, Normal Fault mode: If current-limit is active, then CLDAT<1> provides the state for PWMxH. If current-limit is active, then CLDAT<0> provides the state for PWMxL. IFLTMOD (FCLCONx<15>) = 1, Independent Fault mode: CLDAT<1:0> is ignored. bit 1 SWAP<1:0>: SWAP PWMxH and PWMxL pins 1 = PWMxH output signal is connected to PWMxL pin and PWMxL signal is connected to PWMxH pins 0 = PWMxH and PWMxL pins are mapped to their respective pins bit 0 OSYNC: Output Override Synchronization bit 1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base 0 = Output overrides via the OVRDAT<1:0> bits occur on next CPU clock boundary Note 1: 2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. State represents the active/inactive state of the PWM module depending on the POLH and POLL bit settings. DS75018C-page 198 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLSRC<4:0>(2,3) IFLTMOD R/W-0 R/W-0 CLPOL(1) CLMOD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSRC<4:0>(2,3) R/W-0 R/W-0 FLTPOL(1) R/W-0 FLTMOD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IFLTMOD: Independent Fault Mode Enable bit 1 = Independent Fault mode: Current-limit input maps FLTDAT<1> to PWMxH output and Fault input maps FLTDAT<0> to PWMxL output. The CLDAT<1:0> bits are not used for override functions. 0 = Normal Fault mode: Current-limit feature maps CLDAT<1:0> bits to the PWMxH and PWMxL outputs. The PWM Fault feature maps FLTDAT<1:0> to the PWMxH and PWMxL outputs. bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWMx # Generator bits(2,3) 11111 = Reserved • • • 01000 = Reserved 00111 = Fault 8 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 9 CLPOL: Current-Limit Polarity for PWMx Generator # bit(1) 1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high bit 8 CLMOD: Current-Limit Mode Enable bit for PWMx Generator # bit 1 = Current-limit function is enabled 0 = Current-limit function is disabled Note 1: 2: 3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. When Independent Fault mode is enabled (IFLTMOD<1:0> = 1), and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. When Independent Fault mode is enabled (IFLTMOD<1:0> = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. 2011-2012 Microchip Technology Inc. DS75018C-page 199 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3) 11111 = Reserved • • • 01000 = Reserved bit 7-3 00111 = Fault 8 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 2 FLTPOL: Fault Polarity for PWMx Generator # bit(1) 1 = The selected Fault source is active-low 0 = The selected Fault source is active-high bit 1-0 FLTMOD<1:0>: Fault Mode for PWMx Generator # bits 11 = Fault input is disabled 10 = Reserved 01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle) 00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition) Note 1: 2: 3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. When Independent Fault mode is enabled (IFLTMOD<1:0> = 1), and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. When Independent Fault mode is enabled (IFLTMOD<1:0> = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. DS75018C-page 200 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-16: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 TRGCMP<15:3>: Trigger Control Value bits When primary PWM functions in local time base, this register contains the compare values that can trigger the ADC module. bit 2-0 Unimplemented: Read as ‘0’ REGISTER 15-17: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STRGCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STRGCMP<7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 STRGCMP<15:3>: Secondary Trigger Control Value bits When secondary PWM functions in local time base, this register contains the compare values that can trigger the ADC module. bit 2-0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. DS75018C-page 201 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-18: LEBCONx: PWMx LEADING-EDGE BLANKING CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN R/W-0 R/W-0 LEB<6:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEB<4:0> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PHR: PWMxH Rising Edge Trigger Enable bit 1 = Rising edge of PWMxH will trigger LEB counter 0 = LEB ignores rising edge of PWMxH bit 14 PHF: PWMxH Falling Edge Trigger Enable bit 1 = Falling edge of PWMxH will trigger LEB counter 0 = LEB ignores falling edge of PWMxH bit 13 PLR: PWMxL Rising Edge Trigger Enable bit 1 = Rising edge of PWMxL will trigger LEB counter 0 = LEB ignores rising edge of PWMxL bit 12 PLF: PWMxL Falling Edge Trigger Enable bit 1 = Falling edge of PWMxL will trigger LEB counter 0 = LEB ignores falling edge of PWMxL bit 11 FLTLEBEN: Fault Input LEB Enable bit 1 = Leading-edge blanking is applied to selected Fault input 0 = Leading-edge blanking is not applied to selected Fault input bit 10 CLLEBEN: Current-Limit LEB Enable bit 1 = Leading-edge blanking is applied to selected current-limit input 0 = Leading-edge blanking is not applied to selected current-limit input bit 9-3 LEB<6:0>: Leading-Edge Blanking for Current-Limit and Fault Inputs bits The value is 8.32 nsec increments. bit 2-0 Unimplemented: Read as ‘0’ DS75018C-page 202 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-19: PWMCAPx: PRIMARY PWMx TIME BASE CAPTURE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWMCAP<15:8>(1,2) bit 15 bit 8 R-0 R-0 R-0 PWMCAP<7:3> R-0 R-0 (1,2) U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 PWMCAP<15:3>: Captured PWM Time Base Value bits(1,2) The value in this register represents the captured PWM time base value when a leading edge is detected on the current-limit input. bit 2-0 Unimplemented: Read as ‘0’ Note 1: 2: The capture feature is only available on primary output (PWMxH). This feature is active only after LEB processing on the current-limit input signal is complete. REGISTER 15-20: CHOP: PWM CHOP CLOCK GENERATOR REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 CHPCLKEN — — — — — R/W-0 R/W-0 CHOPCLK<6:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHOPCLK<4:0> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHPCLKEN: Enable Chop Clock Generator bit 1 = Chop clock generator is enabled 0 = Chop clock generator is disabled bit 14-10 Unimplemented: Read as ‘0’ bit 9-3 CHOPCLK<6:0>: Chop Clock Divider bits The frequency of the chop clock signal is given by the following expression: Chop Frequency = 1/(16.64 * (CHOPCLK<6:0> + 1) * Primary Master PWM Input Clock/PCLKDIV<2:0>) bit 2-0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. DS75018C-page 203 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-21: AUXCONx: PWMx AUXILIARY CONTROL REGISTER R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 UW-0 HRPDIS HRDDIS — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 CHOPSEL<3:0> R/W-0 R/W-0 R/W-0 CHOPHEN CHOPLEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HRPDIS: High-Resolution PWMx Period Disable bit 1 = High-resolution PWMx period is enabled 0 = High-resolution PWMx period is disabled bit 14 HRDDIS: High-Resolution PWMx Duty Cycle Disable bit 1 = High-resolution PWMx duty cycle is enabled 0 = High-resolution PWMx duty cycle is disabled bit 13-6 Unimplemented: Read as ‘0’ bit 5-2 CHOPSEL<3:0>: PWMx Chop Clock Source Select bits The selected signal will enable and disable (CHOP) the selected PWMx outputs. 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = Reserved 0100 = PWM4H is selected as CHOP clock source 0011 = Reserved 0010 = PWM2H is selected as CHOP clock source 0001 = PWM1H is selected as CHOP clock source 0000 = Chop clock generator is selected as CHOP clock source bit 1 CHOPHEN: PWMxH Output Chopping Enable bit 1 = PWMxH chopping function is enabled 0 = PWMxH chopping function is disabled bit 0 CHOPLEN: PWMxL Output Chopping Enable bit 1 = PWMxL chopping function is enabled 0 = PWMxL chopping function is disabled DS75018C-page 204 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 16.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 18. “Serial Peripheral Interface (SPI)” (DS70206) of the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 16-1: The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift registers, display drivers, Analog-to-Digital Converters, etc. The SPI module is compatible with Motorola® SPI and SIOP. Each SPI module consists of a 16-bit shift register, SPIxSR (where x = 1 or 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates status conditions. The serial interface consists of 4 pins: • • • • SDIx (serial data input) SDOx (serial data output) SCKx (shift clock input or output) SSx (active-low slave select) In Master mode operation, SCKx is a clock output; in Slave mode, it is a clock input. SPI MODULE BLOCK DIAGRAM SCKx SSx 1:1 to 1:8 Secondary Prescaler Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable Master Clock bit 0 SDIx FCY SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus 2011-2012 Microchip Technology Inc. DS75018C-page 205 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 16.1 1. In Frame mode, if there is a possibility that the master may not be initialized before the slave: a) If FRMPOL (SPIxCON2<13>) = 1, use a pull-down resistor on SSx. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: 2. This will insure that during power-up and initialization the master/slave will not lose Sync due to an errant SCK transition that would cause the slave to accumulate data shift errors for both transmit and receive appearing as corrupted data. To avoid invalid slave read data to the master, the user’s master software must ensure enough time for slave software to fill its write buffer before the user application initiates a master write/read cycle. It is always advisable to preload the SPIxBUF Transmit register in advance of the next master transaction cycle. SPIxBUF is transferred to the SPI Shift register and is empty once the data transmission begins. 16.2 SPI Resources Many useful resources related to SPI are provided on the Microchip web site (www.microchip.com). 16.2.1 KEY RESOURCES • Section 18. “Serial Peripheral Interface (SPI)” (DS70206) • Code Samples • Application Notes • Software Libraries • Webinars • All related “dsPIC33F/PIC24H Family Reference Manual” Sections • Development Tools FRMEN (SPIxCON2<15>) = 1 and SSEN (SPIxCON1<7>) = 1 are exclusive and invalid. In Frame mode, SCKx is continuous and the Frame Sync pulse is active on the SSx pin, which indicates the start of a data frame. Note: 4. This insures that the first frame transmission after initialization is not shifted or corrupted. In Non-Framed 3-Wire mode, (i.e., not using SSx from a master): a) If CKP (SPIxCON1<6>) = 1, always place a pull-up resistor on SSx. b) If CKP = 0, always place a pull-down resistor on SSx. Note: 3. SPI Helpful Tips Not all third-party devices support Frame mode timing. Refer to the SPI electrical characteristics for details. In Master mode only, set the SMP bit (SPIxCON1<9>) to a ‘1’ for the fastest SPI data rate possible. The SMP bit can only be set at the same time or after the MSTEN bit (SPIxCON1<5>) is set. DS75018C-page 206 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 16.3 SPI Control Registers REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded; the user software has not read the previous data in the SPIxBUF register 0 = No overflow has occurred bit 5-2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty Automatically set in hardware when the CPU writes to the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive is complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads the SPIxBUF location, reading SPIxRXB. 2011-2012 Microchip Technology Inc. DS75018C-page 207 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 SSEN(3) CKP R/W-0 R/W-0 MSTEN R/W-0 R/W-0 R/W-0 SPRE<2:0>(2) R/W-0 PPRE<1:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx Pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx Pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data is sampled at end of data output time 0 = Input data is sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode)(3) 1 = SSx pin is used for Slave mode 0 = SSx pin is not used by module; pin is controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: 2: 3: This bit is not used in Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). Do not set both Primary and Secondary prescalers to a value of 1:1. This bit must be cleared when FRMEN = 1. DS75018C-page 208 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: This bit is not used in Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). Do not set both Primary and Secondary prescalers to a value of 1:1. This bit must be cleared when FRMEN = 1. 2011-2012 Microchip Technology Inc. DS75018C-page 209 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as Frame Sync pulse input/output) 0 = Framed SPIx support disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame Sync pulse input (slave) 0 = Frame Sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame Sync pulse is active-high 0 = Frame Sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame Sync pulse coincides with first bit clock 0 = Frame Sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application DS75018C-page 210 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 17.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 17.1 Operating Modes The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode specifications, as well as 7-bit and 10-bit addressing. The I2C module can operate either as a slave or a master on an I2C bus. The following types of I2C operation are supported: • • • I2C slave operation with 7-bit addressing I2C slave operation with 10-bit addressing I2C master operation with 7-bit or 10-bit addressing For details about the communication sequence in each of these modes, please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections. The Inter-Integrated Circuit™ (I2C™) module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard with a 16-bit interface. The I2C module has a 2-pin interface: • The SCL1 pin is the clock • The SDA1 pin is data The I2C module offers the following key features: • I2C interface supporting both Master and Slave modes of operation • I2C Slave mode supports 7-bit and 10-bit addressing • I2C Master mode supports 7-bit and 10-bit addressing • I2C port allows bidirectional transfers between master and slaves • Serial clock synchronization for I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) • I2C supports multi-master operation, detects bus collision and arbitrates accordingly 2011-2012 Microchip Technology Inc. DS75018C-page 211 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 17-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2C1RCV SCL1 Read Shift Clock I2C1RSR LSb SDA1 Address Match Match Detect Write I2C1MSK Write Read I2C1ADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2C1STAT Collision Detect Read Write I2C1CON Acknowledge Generation Read Clock Stretching Write I2C1TRN LSb Read Shift Clock Reload Control BRG Down Counter Write I2C1BRG Read TCY/2 DS75018C-page 212 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 17.2 I2C Registers • I2C1TRN is the transmit register to which bytes are written during a transmit operation • The I2C1ADD register holds the slave address • A status bit, ADD10, indicates 10-Bit Address mode • The I2C1BRG acts as the Baud Rate Generator (BRG) reload value I2C1CON and I2C1STAT are control and status registers, respectively. The I2C1CON register is readable and writable. The lower six bits of I2C1STAT are read-only. The remaining bits of the I2CSTAT are read/write: • I2C1RSR is the shift register used for shifting data internal to the module and the user application has no access to it • I2C1RCV is the receive buffer and the register to which data bytes are written, or from which data bytes are read REGISTER 17-1: In receive operations, I2C1RSR and I2C1RCV together form a double-buffered receiver. When I2C1RSR receives a complete byte, it is transferred to I2C1RCV, and an interrupt pulse is generated. I2C1CON: I2C1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2C1 Enable bit 1 = Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins 0 = Disables the I2C1 module; all I2C pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCL1 Release Control bit (when operating as I2C slave) 1 = Releases SCL1 clock 0 = Holds SCL1 clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear at beginning of slave transmission. Hardware is clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses Acknowledged 0 = IPMI mode is disabled bit 10 A10M: 10-Bit Slave Address bit 1 = I2C1ADD is a 10-bit slave address 0 = I2C1ADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled 2011-2012 Microchip Technology Inc. DS75018C-page 213 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER (CONTINUED) bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2C1RSR (module is enabled for reception) 0 = General call address is disabled bit 6 STREN: SCL1 Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enables software or receives clock stretching 0 = Disables software or receives clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiates Acknowledge sequence on SDA1 and SCL1 pins and transmits ACKDT data bit. Hardware is clear at end of master Acknowledge sequence. 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware is clear at end of eighth bit of master receive data byte. 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDA1 and SCL1 pins. Hardware is clear at end of master Stop sequence. 0 = Stop condition is not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDA1 and SCL1 pins. Hardware is clear at end of master Repeated Start sequence. 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDA1 and SCL1 pins. Hardware is clear at end of master Start sequence. 0 = Start condition is not in progress DS75018C-page 214 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: HS = Hardware Settable bit’ HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = NACK is received from slave 0 = ACK is received from slave Hardware is set or clear at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at beginning of master transmission. Hardware is clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware is set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when address matches general call address. Hardware is clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at match of 2nd byte of matched 10-bit address. Hardware is clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write to the I2C1TRN register failed because the I2C module is busy 0 = No collision Hardware is set at occurrence of write to I2C1TRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2C1RCV register is still holding the previous byte 0 = No overflow Hardware is set at attempt to transfer I2C1RSR to I2C1RCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was the device address Hardware is clear at device address match. Hardware is set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. 2011-2012 Microchip Technology Inc. DS75018C-page 215 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware is set or clear after reception of I 2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2C1RCV is full 0 = Receive is not complete, I2C1RCV is empty Hardware is set when I2C1RCV is written with received byte. Hardware is clear when software reads I2C1RCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2C1TRN is full 0 = Transmit is complete, I2C1TRN is empty Hardware is set when software writes I2C1TRN. Hardware is clear at completion of data transmission. DS75018C-page 216 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 17-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address bit x Select bits 1 = Enables masking for bit x of incoming message address; bit match not required in this position 0 = Disables masking for bit x; bit match required in this position 2011-2012 Microchip Technology Inc. DS75018C-page 217 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 218 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Universal Asynchronous Receiver Transmitter (UART) module is a serial I/O module. The UART is a full-duplex, asynchronous system that can communicate with peripheral devices, such as personal computers, LIN/J2602, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the U1CTS and U1RTS pins, and also includes an IrDA® encoder and decoder. Note: The dsPIC33FJ06GS001 device does not have a UART module. FIGURE 18-1: The primary features of the UART module are: • Full-duplex, 8-bit or 9-bit data transmission through the U1TX and U1RX pins • Even, Odd or No Parity options (for 8-bit data) • One or two Stop bits • Hardware flow control option with U1CTS and U1RTS pins • Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler • Baud rates ranging from 10 Mbps to 38 bps at 40 MIPS • 4-deep First-In First-Out (FIFO) transmit data buffer • 4-deep FIFO receive data buffer • Parity, framing and buffer overrun error detection • Support for 9-bit mode with address detect (9th bit = 1) • Transmit and Receive interrupts • Separate interrupt for all UART error conditions • Loopback mode for diagnostic support • Support for Sync and Break characters • Support for automatic baud rate detection • IrDA encoder and decoder logic • 16x baud clock output for IrDA® support A simplified block diagram of the UART module is shown in Figure 18-1. The UART module consists of these key hardware elements: • BRG • Asynchronous transmitter • Asynchronous receiver UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control U1RTS/BCLK U1CTS UART Receiver U1RX UART Transmitter U1TX 2011-2012 Microchip Technology Inc. DS75018C-page 219 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 18.1 1. 2. UART Helpful Tips In multinode, direct-connect UART networks, UART receive inputs react to the complementary logic level defined by the URXINV bit (U1MODE<4>), which defines the Idle state, the default of which is logic high, (i.e., URXINV = 0). Because remote devices do not initialize at the same time, it is likely that one of the devices, because the RX line is floating, will trigger a Start bit detection and will cause the first byte received after the device has been initialized to be invalid. To avoid this situation, the user should use a pull-up or pull-down resistor on the RX pin, depending on the value of the URXINV bit. a) If URXINV = 0, use a pull-up resistor on the RX pin. b) If URXINV = 1, use a pull-down resistor on the RX pin. The first character received on a wake-up from Sleep mode, caused by activity on the UxRX pin of the UART module, will be invalid. In Sleep mode, peripheral clocks are disabled. By the time the oscillator system has restarted and stabilized from Sleep mode, the baud rate bit sampling clock, relative to the incoming UxRX bit timing, is no longer synchronized. This results in the first character being invalid; this is to be expected. DS75018C-page 220 18.2 UART Resources Many useful resources related to UART are provided on the Microchip web site (www.microchip.com). 18.2.1 KEY RESOURCES • Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” • Code Samples • Application Notes • Software Libraries • Webinars • All related “dsPIC33F/PIC24H Family Reference Manual” Sections • Development Tools 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 18.3 UART Registers REGISTER 18-1: U1MODE: UART1 MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 UARTEN(1,3) — USIDL(3) IREN(2,3) RTSMD(3) — R/W-0 R/W-0 UEN<1:0>(3) bit 15 bit 8 R/W-0, HC WAKE(3) R/W-0 R/W-0, HC (3) LPBACK (3) ABAUD R/W-0 R/W-0 (3) URXINV BRGH (3) R/W-0 R/W-0 (3) PDSEL<1:0> R/W-0 STSEL(3) bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UART1 Enable bit(1,3) 1 = UART1 is enabled; all UART1 pins are controlled by UART1, as defined by UEN<1:0> 0 = UART1 is disabled; all UART1 pins are controlled by port latches; UART1 power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: Stop in Idle Mode bit(3) 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2,3) 1 = IrDA® encoder and decoder are enabled 0 = IrDA® encoder and decoder are disabled bit 11 RTSMD: Mode Selection for U1RTS Pin bit(3) 1 = U1RTS pin is in Simplex mode 0 = U1RTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UART1 Pin Enable bits(3) 11 = U1TX, U1RX and BCLK pins are enabled and used; U1CTS pin is controlled by port latches 10 = U1TX, U1RX, U1CTS and U1RTS pins are enabled and used 01 = U1TX, U1RX and U1RTS pins are enabled and used; U1CTS pin is controlled by port latches 00 = U1TX and U1RX pins are enabled and used; U1CTS and U1RTS/BCLK pins are controlled by port latches bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit(3) 1 = UART1 will continue to sample the U1RX pin; interrupt is generated on falling edge; bit is cleared in hardware on following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UART1 Loopback Mode Select bit(3) 1 = Enable Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit(3) 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (0x55) before other data; cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed Note 1: 2: 3: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. This feature is only available for the 16x BRG mode (BRGH = 0). This bit is not available in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 221 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 18-1: U1MODE: UART1 MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit(3) 1 = U1RX Idle state is ‘0’ 0 = U1RX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit(3) 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits(3) 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit(3) 1 = Two Stop bits 0 = One Stop bit Note 1: 2: 3: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. This feature is only available for the 16x BRG mode (BRGH = 0). This bit is not available in the dsPIC33FJ06GS001 device. DS75018C-page 222 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 18-2: R/W-0 U1STA: UART1 STATUS AND CONTROL REGISTER R/W-0 UTXISEL1(2) UTXINV (2) R/W-0 UTXISEL0 U-0 (2) R/W-0, HC (2) — UTXBRK R/W-0 (1,2) UTXEN R-0 R-1 (2) UTXBF TRMT(2) bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0>(2) R/W-0 (2) ADDEN R-1 RIDLE R-0 (2) R-0 (2) PERR R/C-0 (2) FERR (2) OERR R-0 URXDA(2) bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits(2) 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies that there is at least one character open in the transmit buffer) bit 14 UTXINV: Transmit Polarity Inversion bit(2) If IREN = 0: 1 = U1TX Idle state is ‘0’ 0 = U1TX Idle state is ‘1’ If IREN = 1: 1 = IrDA® encoded U1TX Idle state is ‘1’ 0 = IrDA encoded U1TX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: Transmit Break bit(2) 1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: Transmit Enable bit(1,2) 1 = Transmit is enabled, U1TX pin is controlled by UART1 0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; U1TX pin is controlled by port bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)(2) 1 = Transmit buffer is full 0 = Transmit buffer is not full; at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only)(2) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued Note 1: 2: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. This bit is not available in the dsPIC33FJ06GS001 device. 2011-2012 Microchip Technology Inc. DS75018C-page 223 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 18-2: U1STA: UART1 STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits(2) 11 = Interrupt is set on U1RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on U1RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the U1RSR to the receive buffer; receive buffer has one or more characters bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)(2) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only)(2) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only)(2) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only)(2) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)(2) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the U1RSR to the empty state. bit 0 URXDA: Receive Buffer Data Available bit (read-only)(2) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: 2: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. This bit is not available in the dsPIC33FJ06GS001 device. DS75018C-page 224 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 19.0 HIGH-SPEED 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 44. “High-Speed 10-Bit ADC” (DS70321) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 family of devices provides high-speed successive approximation, Analog-to-Digital conversions to support applications such as AC-to-DC and DC-to-DC Power Converters. 19.1 Features Overview The ADC module comprises the following features: • • • • • • • • • • 10-bit resolution Unipolar inputs One Successive Approximation Register (SAR) Up to eight external input channels Up to two internal analog inputs Dedicated result register for each analog input ±1 LSB accuracy at 3.3V Single supply operation 2 Msps conversion rate at 3.3V Low-power CMOS technology 19.2 Module Description This ADC module is designed for applications that require low latency between the request for conversion and the resultant output data. Typical applications include: Up to three inputs may be sampled at a time (two inputs from the dedicated Sample-and-Hold circuits and one from the shared Sample-and-Hold circuit). If multiple inputs request conversion, the ADC will convert them in a sequential manner, starting with the lowest order input. This ADC design provides each pair of analog inputs (AN1, AN0), (AN3, AN2),..., the ability to specify its own trigger source out of a maximum of sixteen different trigger sources. This capability allows this ADC to sample and convert analog inputs that are associated with PWM generators operating on independent time bases. The user application typically requires synchronization between analog data sampling and PWM output to the application circuit. The very high-speed operation of this ADC module allows “data on demand”. In addition, several hardware features have been added to the peripheral interface to improve real-time performance in a typical DSP-based application: • • • • Result alignment options Automated sampling External conversion start control Two internal inputs to monitor INTREF and EXTREF input signals (not available in dsPIC33FJ06GS101A/102A devices) Block diagrams of the ADC module are shown in Figure 19-1 through Figure 19-5. 19.3 Module Functionality The high-speed, 10-bit ADC module is designed to support power conversion applications when used with the high-speed PWM module. The ADC has one SAR and only one conversion can be processed at a time, yielding a conversion rate of 2 Msps or the equivalent of one 10-bit conversion, in half a microsecond (0.5 µs). The ADC module supports up to eight external analog inputs and two internal analog inputs. To monitor reference voltage, two internal inputs, AN12 and AN13, are connected to the EXTREF and INTREF voltages, respectively. Note: The dsPIC33FJ06GS101A/102A devices do not have the internal connection to EXTREF. The analog reference voltage is defined as the device supply voltage (AVDD/AVSS). • AC/DC Power Supplies • DC/DC Converters • Power Factor Correction (PFC) This ADC works with the high-speed PWM module in power control applications that require high-frequency control loops. This small conversion delay reduces the “phase lag” between measurement and control system response. 2011-2012 Microchip Technology Inc. DS75018C-page 225 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-1: ADC BLOCK DIAGRAM FOR THE dsPIC33FJ06GS001 DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits Eight 16-Bit Registers Bus Interface SAR Core AN12(1) (EXTREF) Data Format AN0 AN1 Shared Sample-and-Hold AN2 AN3 AN6 AN7 AN13(2) (INTREF) Note 1: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. 2: AN13 (INTREF) is an internal analog input and is not available on a pin. DS75018C-page 226 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-2: ADC BLOCK DIAGRAM FOR THE dsPIC33FJ06GS101A DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 Eight 16-Bit Registers Bus Interface SAR Core Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN6 AN7 2011-2012 Microchip Technology Inc. DS75018C-page 227 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS102A DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 Eight 16-Bit Registers Bus Interface SAR Core Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN4 AN5 DS75018C-page 228 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS202A DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 SAR Core Eight 16-Bit Registers Bus Interface AN12(1) (EXTREF) Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN4 AN5 AN13(2) (INTREF) Note 1: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. 2: AN13 (INTREF) is an internal analog input and is not available on a pin. 2011-2012 Microchip Technology Inc. DS75018C-page 229 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-5: ADC BLOCK DIAGRAM FOR dsPIC33FJ09GS302 DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 SAR Core Eight 16-Bit Registers Bus Interface AN12(1) (EXTREF) Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN4 AN5 AN6 AN7 AN13(2) (INTREF) Note 1: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. 2: AN13 (INTREF) is an internal analog input and is not available on a pin. DS75018C-page 230 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 19.4 ADC Control Registers Note: The ADC module uses the following control and status registers: • • • • • • • ADCON: ADC Control Register ADSTAT: ADC Status Register ADBASE: ADC Base Register(1) ADPCFG: ADC Port Configuration Register ADCPC0: ADC Convert Pair Control Register 0 ADCPC1: ADC Convert Pair Control Register 1 ADCPC3: ADC Convert Pair Control Register 3(1) A unique feature of the ADC module is its ability to sample inputs in an asynchronous manner. Individual Sample-and-Hold circuits can be triggered independently of each other. The ADCON register controls the operation of the ADC module. The ADSTAT register displays the status of the conversion processes. The ADPCFG register configures the port pins as analog inputs or as digital I/Os. The ADCPCx registers control the triggering of the ADC conversions. See Register 19-1 through Register 19-7 for detailed bit configurations. REGISTER 19-1: R/W-0 ADCON: ADC CONTROL REGISTER U-0 ADON — R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 ADSIDL SLOWCLK(1) — GSWTRG — FORM(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 EIE(1) ORDER(1) SEQSAMP(1) ASYNCSAMP(1) U-0 R/W-0 — R/W-1 R/W-1 ADCS<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC module is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 SLOWCLK: Enable Slow Clock Divider bit(1) 1 = ADC is clocked by the auxiliary PLL (ACLK) 0 = ADC is clocked by the primary PLL (FVCO) bit 11 Unimplemented: Read as ‘0’ bit 10 GSWTRG: Global Software Trigger bit When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this bit is not auto-clearing). bit 9 Unimplemented: Read as ‘0’ Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0). 2011-2012 Microchip Technology Inc. DS75018C-page 231 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-1: ADCON: ADC CONTROL REGISTER (CONTINUED) bit 8 FORM: Data Output Format bit(1) 1 = Fractional (DOUT = dddd dddd dd00 0000) 0 = Integer (DOUT = 0000 00dd dddd dddd) bit 7 EIE: Early Interrupt Enable bit(1) 1 = Interrupt is generated after first conversion is completed 0 = Interrupt is generated after second conversion is completed bit 6 ORDER: Conversion Order bit(1) 1 = Odd numbered analog input is converted first, followed by conversion of even numbered input 0 = Even numbered analog input is converted first, followed by conversion of odd numbered input bit 5 SEQSAMP: Sequential Sample Enable bit(1) 1 = Shared Sample-and-Hold (S&H) circuit is sampled at the start of the second conversion if ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion. 0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not currently busy with an existing conversion process. If the shared S&H is busy at the time the dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion cycle. bit 4 ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1) 1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger pulse is detected 0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling process in two ADC clock cycles bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits(1) 111 = FADC/8 110 = FADC/7 101 = FADC/6 100 = FADC/5 011 = FADC/4 (default) 010 = FADC/3 001 = FADC/2 000 = FADC/1 Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0). DS75018C-page 232 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-2: ADSTAT: ADC STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/C-0, HS U-0 U-0 R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS — P6RDY — — P3RDY(1) P2RDY(2) P1RDY P0RDY bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 P6RDY: Conversion Data for Pair 6 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 5-4 Unimplemented: Read as ‘0’ bit 3 P3RDY: Conversion Data for Pair 3 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 2 P2RDY: Conversion Data for Pair 3 Ready bit(2) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 1 P1RDY: Conversion Data for Pair 1 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 0 P0RDY: Conversion Data for Pair 0 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. Note 1: 2: This bit is not implemented in dsPIC33FJ06GS102A/202A devices. This bit is not implemented in dsPIC33FJ06GS001/101A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 233 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-3: R/W-0 ADBASE: ADC BASE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (2) ADBASE<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADBASE<7:1>(2) U-0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 ADBASE<15:1>: ADC Base Register bits(2) This register contains the base address of the user’s ADC Interrupt Service Routine (ISR) jump table. This register, when read, contains the sum of the ADBASE register contents and the encoded value of the PxRDY status bits. The encoder logic provides the bit number of the highest priority PxRDY bits, where P0RDY is the highest priority and P6RDY is the lowest priority. bit 0 Unimplemented: Read as ‘0’ Note 1: 2: As an alternative to using the ADBASE register, the ADCP0-6 ADC Pair Conversion Complete Interrupts can be used to invoke A to D conversion completion routines for individual ADC input pairs. The encoding results are shifted left two bits, so bits 1-0 of the result are always zero. DS75018C-page 234 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-4: ADPCFG: ADC PORT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 PCFG7(1) PCFG6 (1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 PCFG<7:6>: Analog-to-Digital Port Configuration Control bits(1) 1 = Port pin is in Digital mode; port read input is enabled; Analog-to-Digital input multiplexer is connected to AVSS 0 = Port pin is in Analog mode; port read input is disabled; Analog-to-Digital samples pin voltage bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 PCFG<3:0>: Analog-to-Digital Port Configuration Control bits 1 = Port pin is in Digital mode; port read input is enabled; Analog-to-Digital input multiplexer is connected to AVSS 0 = Port pin is in Analog mode; port read input is disabled; Analog-to-Digital samples pin voltage Note 1: 2: This bit is not implemented in dsPIC33FJ06GS102A/202A devices. This bit is not implemented in dsPIC33FJ06GS001/101A devices. 2011-2012 Microchip Technology Inc. DS75018C-page 235 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-5: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 R/W-0 IRQEN1 bit 15 R/W-0 PEND1 R/W-0 IRQEN0 bit 7 R/W-0 PEND0 bit 14 bit 13 bit 12-8 Note 1: R/W-0 R/W-0 R/W-0 TRGSRC1<4:0> R/W-0 R/W-0 bit 8 R/W-0 SWTRG0 R/W-0 R/W-0 R/W-0 TRGSRC0<4:0> R/W-0 R/W-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 SWTRG1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IRQEN1: Interrupt Request Enable 1 bit 1 = Enables IRQ generation when requested conversion of channels AN3 and AN2 is completed 0 = IRQ is not generated PEND1: Pending Conversion Status 1 bit 1 = Conversion of channels AN3 and AN2 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG1: Software Trigger 1 bit 1 = Starts conversion of AN3 and AN2 (if selected by the TRGSRCx bits)(1) This bit is automatically cleared by hardware when the PEND1 bit is set. 0 = Conversion has not started TRGSRC1<4:0>: Trigger 1 Source Selection bits Selects trigger source for conversion of analog channels AN3 and AN2. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = Reserved 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = Reserved 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = Reserved 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then conversion will be performed when the conversion resources are available. DS75018C-page 236 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-5: bit 7 bit 6 bit 5 bit 4-0 Note 1: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) IRQEN0: Interrupt Request Enable 0 bit 1 = Enables IRQ generation when requested conversion of channels AN1 and AN0 is completed 0 = IRQ is not generated PEND0: Pending Conversion Status 0 bit 1 = Conversion of channels AN1 and AN0 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG0: Software Trigger 0 bit 1 = Starts conversion of AN1 and AN0 (if selected by the TRGSRCx bits)(1) This bit is automatically cleared by hardware when the PEND0 bit is set. 0 = Conversion has not started TRGSRC0<4:0>: Trigger 0 Source Selection bits Selects trigger source for conversion of analog channels AN1 and AN0. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = Reserved 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = Reserved 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = Reserved 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then conversion will be performed when the conversion resources are available. 2011-2012 Microchip Technology Inc. DS75018C-page 237 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-6: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 R/W-0 IRQEN3(1) bit 15 R/W-0 PEND3(1) R/W-0 IRQEN2(2) bit 7 R/W-0 PEND2(2) bit 14 bit 13 bit 12-8 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC3<4:0>(1) R/W-0 bit 8 R/W-0 SWTRG2(2) R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC2<4:0>(2) R/W-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 SWTRG3(1) W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IRQEN3: Interrupt Request Enable 3 bit(1) 1 = Enables IRQ generation when requested conversion of channels AN7 and AN6 is completed 0 = IRQ is not generated PEND3: Pending Conversion Status 3 bit(1) 1 = Conversion of channels AN7 and AN6 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG3: Software Trigger 3 bit(1) 1 = Starts conversion of AN7 and AN6 (if selected by the TRGSRCx bits)(3) This bit is automatically cleared by hardware when the PEND3 bit is set. 0 = Conversion has not started TRGSRC3<4:0>: Trigger 3 Source Selection bits(1) Selects trigger source for conversion of analog channels AN7 and AN6. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = Reserved 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = Reserved 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = Reserved 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled Note 1: 2: 3: This bit is available in dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices only. This bit is available in dsPIC33FJ06GS102A/201A and dsPIC33FJ09GS302 devices only. The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, conversion will be performed when the conversion resources are available. DS75018C-page 238 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-6: bit 7 bit 6 bit 5 bit 4-0 ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) IRQEN2: Interrupt Request Enable 2 bit(2) 1 = Enables IRQ generation when requested conversion of channels AN5 and AN4 is completed 0 = IRQ is not generated PEND2: Pending Conversion Status 2 bit(2) 1 = Conversion of channels AN5 and AN4 is pending; set when selected trigger is asserted. 0 = Conversion is complete SWTRG2: Software Trigger 2 bit(2) 1 = Starts conversion of AN5 and AN4 (if selected by the TRGSRCx bits)(3) This bit is automatically cleared by hardware when the PEND2 bit is set. 0 = Conversion has not started TRGSRC2<4:0>: Trigger 2 Source Selection bits(2) Selects trigger source for conversion of analog channels AN5 and AN4. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = Reserved 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = Reserved 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = Reserved 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled Note 1: 2: 3: This bit is available in dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices only. This bit is available in dsPIC33FJ06GS102A/201A and dsPIC33FJ09GS302 devices only. The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, conversion will be performed when the conversion resources are available. 2011-2012 Microchip Technology Inc. DS75018C-page 239 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-7: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN6 PEND6 SWTRG6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC6<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IRQEN6: Interrupt Request Enable 6 bit 1 = Enable IRQ generation when requested conversion of channels AN13 and AN12 is completed 0 = IRQ is not generated bit 6 PEND6: Pending Conversion Status 6 bit 1 = Conversion of channels AN13 and AN 12 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG6: Software Trigger 6 bit 1 = Starts conversion of AN13 (INTREF) and AN12 (EXTREF) if selected by TRGSRC bits(2) This bit is automatically cleared by hardware when the PEND6 bit is set. 0 = Conversion has not started Note 1: 2: If other conversions are in progress, conversion will be performed when the conversion resources are available. AN13 is internally connected to Vref in all devices. AN12 is internally connected to the EXTREF pin in the dsPIC33FJ06001/202A and dsPIC33FJ09GS302 devices. The dsPIC33FJ06GS101A/102A devices not have an EXTREF pin; therefore, any data read on the corresponding AN12 input will be invalid. DS75018C-page 240 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-7: bit 4-0 ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3(1) (CONTINUED) TRGSRC6<4:0>: Trigger 6 Source Selection bits Selects trigger source for conversion of analog channels AN13 and AN12. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = Reserved 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = Reserved 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = Reserved 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled Note 1: 2: If other conversions are in progress, conversion will be performed when the conversion resources are available. AN13 is internally connected to Vref in all devices. AN12 is internally connected to the EXTREF pin in the dsPIC33FJ06001/202A and dsPIC33FJ09GS302 devices. The dsPIC33FJ06GS101A/102A devices not have an EXTREF pin; therefore, any data read on the corresponding AN12 input will be invalid. 2011-2012 Microchip Technology Inc. DS75018C-page 241 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 242 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 20.0 HIGH-SPEED ANALOG COMPARATOR • • • • DACOUT pin to provide DAC output DACOUT amplifier (1x, 1.8x) Selectable hysteresis DAC has three ranges of operation: - AVDD/2 - Internal Reference (INTREF) - External Reference (EXTREF) • ADC sample and convert trigger capability • Disable capability reduces power consumption • Functional support for PWM module: - PWM duty cycle control - PWM period control - PWM Fault detect Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 45. “High-Speed Analog Comparator” (DS70296) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 20.2 Figure 20-1 shows a functional block diagram of one analog comparator from the high-speed analog comparator module. The analog comparator provides high-speed operation with a typical delay of 20 ns. The comparator has a typical offset voltage of ±5 mV. The negative input of the comparator is always connected to the DAC circuit. The positive input of the comparator is connected to an analog multiplexer that selects the desired source pin. The high-speed analog comparator module monitors current and/or voltage transients that may be too fast for the CPU and ADC to capture. 20.1 Features Overview The SMPS comparator module offers the following major features: • • • • • The analog comparator input pins are typically shared with pins used by the Analog-to-Digital Converter (ADC) module. Both the comparator and the ADC can use the same pins at the same time. This capability enables a user to measure an input voltage with the ADC and detect voltage transients with the comparator. Eight selectable comparator inputs Up to two analog comparators 10-bit DAC for each analog comparator Programmable output polarity Interrupt generation capability FIGURE 20-1: Module Description HIGH-SPEED ANALOG COMPARATOR MODULE BLOCK DIAGRAM INSEL<1:0> CMPxA(1) CMPxB(1) M U X CMPxC(1) Trigger to PWM CMPx(1) 0 1 CMPxD(1) Pulse Stretcher and Digital Filter Status CMPPOL RANGE AVDD/2 INTREF Interrupt Request M U X (2) DAC AVSS EXTREF(2) Note 1: 2: 3: 10 AMP HGAIN Output Buffer(3) CMREF DACOUT DACOE x = 1 and 2. For the INTREF and EXTREF values, refer to the DAC Module Specifications (Table 25-42) in Section 25.0 “Electrical Characteristics”. The output buffer is shared between the DACs and only one DAC can be enabled to drive this buffer. 2011-2012 Microchip Technology Inc. DS75018C-page 243 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 20.3 Module Applications This module provides a means for the SMPS dsPIC DSC devices to monitor voltage and currents in a power conversion application. The ability to detect transient conditions and stimulate the dsPIC DSC processor and/or peripherals, without requiring the processor and ADC to constantly monitor voltages or currents, frees the dsPIC DSC to perform other tasks. The comparator module has a high-speed comparator, an associated 10-bit DAC and a DAC output amplifier that provide a programmable reference voltage to the inverting input of the comparator. The polarity of the comparator output is user-programmable. The output of the module can be used in the following modes: • • • • • Generate an Interrupt Trigger an ADC Sample and Convert Process Truncate the PWM Signal (current limit) Truncate the PWM Period (current minimum) Disable the PWM Outputs (Fault latch) The output of the comparator module may be used in multiple modes at the same time, such as: 1) generate an interrupt, 2) have the ADC take a sample and convert it, and 3) truncate the PWM output in response to a voltage being detected beyond its expected value. The comparator module can also be used to wake-up the system from Sleep or Idle mode when the analog input voltage exceeds the programmed threshold voltage. 20.4 DAC The range of the DAC is controlled via an analog multiplexer that selects either AVDD/2, an internal reference source, INTREF, or an external reference source, EXTREF. The full range of the DAC (AVDD/2) will typically be used when the chosen input source pin is shared with the ADC. The reduced range option (INTREF) will likely be used when monitoring current levels using a current sense resistor. Usually, the measured voltages in such applications are small (<1.25V); therefore, the option of using a reduced reference range for the comparator extends the available DAC resolution in these applications. The use of an external reference enables the user to connect to a reference that better suits their application. DACOUT, shown in Figure 20-1, can only be associated with a single comparator at a given time. Note: It should be ensured in software that multiple DACOE bits are not set. The output on the DACOUT pin will be indeterminate if multiple comparators enable the DAC output. DS75018C-page 244 20.5 DAC Buffer Gain The output of the DAC is buffered/amplified via the DAC buffer. The block functions as a 1x gain amplifier or as a 1.8x gain amplifier. The gain selection is controlled via the HGAIN bit in the CMPCONx register. Using the 1.8x gain option will raise the reference voltage to the analog comparator to a maximum of 2.8V. Using a higher reference voltage for the analog comparator can improve the signal-to-noise ratio in an application. 20.6 Comparator Input Range The comparator has an input voltage range from -0.2V to AVDD + 0.2V, making it a rail-to-rail input. 20.7 Digital Logic The CMPCONx register (see Register 20-1) provides the control logic that configures the High-Speed Analog Comparator module. The digital logic provides a pulse stretcher. The analog comparator can respond to very fast transient signals. After the comparator output is given the desired polarity, the signal is passed to this pulse stretching circuit. The pulse stretching circuit has an asynchronous set function and a delay circuit that insure the minimum pulse width is three system clock cycles wide so that the attached circuitry can properly respond. The stretch circuit is followed by a digital filter. The digital filter is enabled via the FLTREN bit in the CMPCONx register. The digital filter operates with the clock specified via the FCLKSEL bit in the CMPCONx register. The comparator signal must be stable in a high or low state for at least three of the selected clock cycles for it to pass through the digital filter. During Sleep mode, the clock signal inputs to the module are disabled. However, the module’s analog components may continue to function in a reduced power manner to allow the user to wake-up the device when a signal is applied to a comparator input. In Sleep mode, the clocks are stopped; however, the analog comparator signal has an asynchronous connection across the filter that allows interrupts to be generated regardless of the stopped clocks. The comparator can be disabled while in Idle mode if the CMPSIDL bit is set. If a device has multiple comparators, and any CMPSIDL bit is set, the entire group of comparators will be disabled while in Idle mode. The advantage is reduced power consumption. Moreover, this behavior reduces complexity in the design of the clock control logic for this module. 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 20.8 Hysteresis 20.9 An additional feature of the module is hysteresis control. Hysteresis can be enabled or disabled and its amplitude can be controlled by the HYSSEL<1:0> bits in the CMPCONx register. Three different values are available: 15 mV, 30 mV and 45 mV. It is also possible to select the edge (rising or falling) to which hysteresis is to be applied. Hysteresis control prevents the comparator output from continuously changing state because of small perturbations (noise) at the input (see Figure 20-2). FIGURE 20-2: HYSTERESIS CONTROL Interaction with I/O Buffers If the module is enabled and a pin has been selected as the source for the comparator, then the chosen I/O pad must disable the digital input buffer associated with the pad to prevent excessive currents in the digital buffer due to analog input voltages. 20.10 DAC Output Range The DAC has a limitation for the maximum reference voltage input of (AVDD – 1.5) volts. An external reference voltage input should not exceed this value or the reference DAC output will become indeterminate. 20.11 Analog Comparator Registers Output The high-speed analog comparator controlled by the following registers: module is • CMPCONx: Comparator Control x Register • CMPDACx: Comparator DAC Control x Register Hysteresis Range (15 mV/30 mV/45 mV) Input 2011-2012 Microchip Technology Inc. DS75018C-page 245 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 20-1: R/W-0 CMPCONx: COMPARATOR CONTROL x REGISTER U-0 CMPON(1) — R/W-0 CMPSIDL R/W-0 (1) R/W-0 (1) HYSSEL<1:0> R/W-0 FLTREN R/W-0 (1) FCLKSEL R/W-0 (1) DACOE(1) bit 15 bit 8 R/W-0 R/W-0 INSEL<1:0>(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EXTREF(1) HYSPOL(1) CMPSTAT(1) HGAIN(1) CMPPOL(1) RANGE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMPON: Comparator Operating Mode bit(1) 1 = Comparator module is enabled 0 = Comparator module is disabled (reduces power consumption) bit 14 Unimplemented: Read as ‘0’ bit 13 CMPSIDL: Stop in Idle Mode bit(1) 1 = Discontinues module operation when device enters Idle mode. 0 = Continues module operation in Idle mode If a device has multiple comparators, any CMPSIDL bit that is set to ‘1’ disables all comparators while in Idle mode. bit 12-11 HYSSEL<1:0>: Comparator Hysteresis Select bits(1) 11 = 45 mV hysteresis 10 = 30 mV hysteresis 01 = 15 mV hysteresis 00 = No hysteresis is selected bit 10 FLTREN: Digital Filter Enable bit(1) 1 = Digital filter is enabled 0 = Digital filter is disabled bit 9 FCLKSEL: Digital Filter and Pulse Stretcher Clock Select bit(1) 1 = Digital filter and pulse stretcher operate with the PWM clock 0 = Digital filter and pulse stretcher operate with the system clock bit 8 DACOE: DAC Output Enable(1) 1 = DAC analog voltage is output to DACOUT pin(2) 0 = DAC analog voltage is not connected to DACOUT pin bit 7-6 INSEL<1:0>: Input Source Select for Comparator bits(1) 11 = Select CMPxD input pin 10 = Select CMPxC input pin 01 = Select CMPxB input pin 00 = Select CMPxA input pin Note 1: 2: 3: This bit is not implemented in dsPIC33FJ06GS101A/102A devices. DACOUT can be associated only with a single comparator at any given time. The software must ensure that multiple comparators do not enable the DAC output by setting their respective DACOE bit. For the INTREF value, refer to the DAC Module Specifications (Table 25-42) in Section 25.0 “Electrical Characteristics”. DS75018C-page 246 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 20-1: CMPCONx: COMPARATOR CONTROL x REGISTER (CONTINUED) bit 5 EXTREF: Enable External Reference bit(1) 1 = External source provides reference to DAC (maximum DAC voltage determined by external voltage source) 0 = Internal reference sources provide reference to DAC (maximum DAC voltage determined by RANGE bit setting) bit 4 HYSPOL: Comparator Hysteresis Polarity Select bit(1) 1 = Hysteresis is applied to the falling edge of the comparator output 0 = Hysteresis is applied to the rising edge of the comparator output bit 3 CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit(1) bit 2 HGAIN: DAC Gain Enable bit(1) 1 = Reference DAC output to comparator is scaled at 1.8x 0 = Reference DAC output to comparator is scaled at 1.0x bit 1 CMPPOL: Comparator Output Polarity Control bit(1) 1 = Output is inverted 0 = Output is non-inverted bit 0 RANGE: Selects DAC Output Voltage Range bit(1) 1 = High Range: Max DAC Value = AVDD/2, 1.65V at 3.3V AVDD 0 = Low Range: Max DAC Value = INTREF(3) Note 1: 2: 3: This bit is not implemented in dsPIC33FJ06GS101A/102A devices. DACOUT can be associated only with a single comparator at any given time. The software must ensure that multiple comparators do not enable the DAC output by setting their respective DACOE bit. For the INTREF value, refer to the DAC Module Specifications (Table 25-42) in Section 25.0 “Electrical Characteristics”. 2011-2012 Microchip Technology Inc. DS75018C-page 247 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 20-2: CMPDACx: COMPARATOR DAC CONTROL x REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 CMREF<9:8>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMREF<7:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 CMREF<9:0>: Comparator Reference Voltage Select bits(1) 1111111111 = (CMREF * INTREF/1024) or (CMREF * (AVDD/2)/1024) volts depending on RANGE bit or (CMREF * EXTREF/1024) if EXTREF is set • • • 0000000000 = 0.0 volts Note 1: These bits are not implemented in dsPIC33FJ06GS101A/102A devices. DS75018C-page 248 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 21.0 CONSTANT CURRENT SOURCE Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The constant current source module is a precision current generator and is used in conjunction with ADC to measure the resistance of external resistors connected to device pins. 21.1 Features Overview The constant current source module offers the following major features: • Constant current generator (10 µA nominal) • Internal selectable connection to one out of four pins • Enable/disable bit 21.2 Module Description Figure 21-1 shows a functional block diagram of the constant current source module. It consists of a precision current generator with a nominal value of 10 µA. The module can be enabled and disabled using the ISRCEN bit in the ISRCCON register. The output of the current generator is internally connected to one out of up to 4 pins. The OUTSEL<2:0> bits in the ISRCCON register allow selection of the target pin. The current source is calibrated during testing. FIGURE 21-1: CONSTANT CURRENT SOURCE MODULE BLOCK DIAGRAM Constant Current Source ISRC1 M U X ISRC2 ISRC3 ISRC4 ISRCEN 2011-2012 Microchip Technology Inc. OUTSEL<2:0> DS75018C-page 249 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 21.3 Current Source Control Register REGISTER 21-1: ISRCCON: CONSTANT CURRENT SOURCE CONTROL REGISTER(1) R/W-0 U-0 U-0 U-0 U-0 ISRCEN — — — — R/W-0 R/W-0 R/W-0 OUTSEL<2:0> bit 15 bit 8 U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 ISRCCAL<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ISRCEN: Current Source Enable bit 1 = Current source is enabled 0 = Current source is disabled bit 14-11 Unimplemented: Read as ‘0’ bit 10-8 OUTSEL<2:0>: Output Current Select bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = Select input pin, ISRC4 (AN4) 011 = Select input pin, ISRC3 (AN5) 010 = Select input pin, ISRC2 (AN6) 001 = Select input pin, ISRC1 (AN7) 000 = No output is selected bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ISRCCAL<5:0>: Current Source Calibration bits The calibration value must be copied from Flash address, 0x800840, into these bits. Refer to the Constant Current Source Calibration Register (Register 22-1) in Section 22.0 “Special Features” for more information. Note 1: This register is available in the dsPIC33FJ09GS302 device only. DS75018C-page 250 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 22.0 SPECIAL FEATURES Configuration Bits Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “Programming and Diagnostics” (DS70207) and Section 25. “Device Configuration” (DS70194) in the “dsPIC33F/PIC24H Family Reference Manual”, which are available from the Microchip web site (www.microchip.com). The configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 22-1 and Table 22-2. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration byte for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 family of devices includes several features that are included to maximize application flexibility and reliability, and minimize cost through elimination of external components. These features are: • • • • • • • 22.1 Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming™ (ICSP™) In-Circuit Emulation Brown-out Reset (BOR) Note: Configuration data is reloaded on all types of device Resets. The upper 2 bytes of all Flash Configuration Words in program memory should always be ‘1111 1111 1111 1111’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘1’s to these locations has no effect on device operation. Note: Performing a page erase operation on the last page of program memory, clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory The Configuration Flash Byte maps are shown in Table 22-1 and Table 22-2. The Constant Current Source Calibration register is shown in Register 22-1. 2011-2012 Microchip Technology Inc. DS75018C-page 251 Address CONFIGURATION FLASH BYTES FOR dsPIC33FJ06GS001/101A/X02A DEVICES Name Bits 23-8 Bit 7 — — 000FF0 FICD — Reserved(1) 000FF4 FWDT — FWDTEN 000FF6 FOSC — 000FF8 FOSCSEL — IESO 000FFA FGS — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 JTAGEN Reserved(2) — — OSCIOFNC Bit 1 Bit 0 ICS<1:0> PLLKEN WDTPRE IOL1WAY — — — — — — — — — — — GCP GWRP Bit 1 Bit 0 FCKSM<1:0> WDTPOST<3:0> POSCMD<1:0> FNOSC<2:0> Legend: — = unimplemented, read as ‘1’. Note 1: This bit is reserved for use by development tools. 2: This bit is reserved; program as ‘0’. TABLE 22-2: Address CONFIGURATION FLASH BYTES FOR dsPIC33FJ09GS302 DEVICES Name Bits 23-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — — 0017F0 FICD — Reserved(1) — JTAGEN Reserved(2) 0017F4 FWDT — FWDTEN — PLLKEN WDTPRE 0017F6 FOSC — IOL1WAY — — 0017F8 FOSCSEL — IESO — — — — 0017FA FGS — — — — — — FCKSM<1:0> Legend: — = unimplemented, read as ‘1’. Note 1: This bit is reserved for use by development tools. 2: This bit is reserved; program as ‘0’. ICS<1:0> WDTPOST<3:0> OSCIOFNC POSCMD<1:0> FNOSC<2:0> — GCP GWRP 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 252 TABLE 22-1: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 22-1: CONSTANT CURRENT SOURCE CALIBRATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 CCSCAL<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-6 Unimplemented: Read as ‘0’ bit 5-0 CCSCAL<5:0>: Constant Current Source Calibration bits The value of these bits must be copied into the ISRCCAL<5:0> bits (ISRCCON<5:0>). Refer to the Current Source Control register (Register 21-1) in Section 21.0 “Constant Current Source”. 2011-2012 Microchip Technology Inc. DS75018C-page 253 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 22-3: dsPIC33F CONFIGURATION BITS DESCRIPTION Bit Field Description GCP General Segment Code-Protect bit 1 = User program memory is not code-protected 0 = Code protection is enabled for the entire program memory space GWRP General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO Two-Speed Oscillator Start-up Enable bit 1 = Start up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start up device with user-selected oscillator source FNOSC<2:0> Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIVN) 110 = Reserved; do not use 101 = Low-Power RC Oscillator (LPRC) 100 = Reserved; do not use 011 = Primary Oscillator with PLL module (MS + PLL, EC + PLL) 010 = Primary Oscillator (MS, HS, EC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIVN + PLL) 000 = Fast RC Oscillator (FRC) FCKSM<1:0> Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations OSCIOFNC OSC2 Pin Function bit (except in MS and HS modes) 1 = OSC2 is the clock output 0 = OSC2 is the general purpose digital I/O pin POSCMD<1:0> Primary Oscillator Mode Select bits 11 = Primary Oscillator is disabled 10 = HS Crystal Oscillator mode (10 MHz-32 MHz) 01 = MS Crystal Oscillator mode (3 MHz-10 MHz) 00 = EC (External Clock) mode (DC-32 MHz) FWDTEN Watchdog Timer Enable bit 1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register will have no effect) 0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WDTPRE Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST<3:0> Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 DS75018C-page 254 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 22-3: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Description PLLKEN PLL Lock Enable bit 1 = Clock switch to PLL source will wait until the PLL lock signal is valid 0 = Clock switch will not wait for the PLL lock signal JTAGEN JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled ICS<1:0> ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use 2011-2012 Microchip Technology Inc. DS75018C-page 255 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 22.2 On-Chip Voltage Regulator The devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR (less than 5 ohms) capacitor (such as tantalum or ceramic) must be connected to the VCAP pin (Figure 22-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Table 25-13, located in Section 25.1 “DC Characteristics”. Note: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin. On a POR, it takes approximately 20 s for the on-chip voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down. FIGURE 22-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2,3) 3.3V 22.3 Brown-out Reset (BOR) The Brown-out Reset (BOR) module is based on an internal voltage reference circuit. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (for example, missing portions of the AC cycle waveform due to bad power transmission lines or voltage sags due to excessive current draw when a large inductive load is turned on). A BOR generates a Reset pulse which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FNOSC<2:0> and POSCMD<1:0>). If an oscillator mode is selected, the BOR activates the Oscillator Start-up Timer (OST). The system clock is held until the OST expires. If the PLL is used, the clock is held until the LOCK bit (OSCCON<5>) is ‘1’. Concurrently, the PWRT time-out (TPWRT) is applied before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of, TFSCM = 100, is applied. The total delay in this case is TFSCM. The BOR status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. dsPIC33F VDD CEFC 10 µF Tantalum VCAP VSS Note 1: These are typical operating voltages. Refer to Table 25-13 located in Section 25.1 “DC Characteristics” for the full operating ranges of VDD. 2: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin. 3: Typical VCAP pin voltage = 2.5V when VDD VDDMIN. DS75018C-page 256 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 22.4 Watchdog Timer (WDT) 22.4.2 The Watchdog Timer (WDT) is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 22.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit (FWDT<4>). With a 32 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPOST<3:0> Configuration bits (FWDT<3:0>), which allow the selection of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC<2:0> bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution Note: SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP bit (RCON<3>) or IDLE bit (RCON<2>) will need to be cleared in software after the device wakes up. 22.4.3 ENABLING WDT The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register (FWDT<7>). When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user application to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. The WDT flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. FIGURE 22-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle SWDTEN FWDTEN LPRC Clock WDTPOST<3:0> WDTPRE WDT Wake-up RS Prescaler (Divide-by-N1) RS Postscaler (Divide-by-N2) 1 0 WDT Reset WDT Window Select CLRWDT Instruction 2011-2012 Microchip Technology Inc. DS75018C-page 257 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 22.5 JTAG Interface 22.7 In-Circuit Debugger A JTAG interface is implemented, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface will be provided in future revisions of this document. The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 devices provide simple debugging functionality through the PGECx (Emulation/ Debug Clock) and PGEDx (Emulation/Debug Data) pin functions. 22.6 Any of the three pairs of debugging clock/data pins can be used: In-Circuit Serial Programming The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 family of digital signal controllers can be serially programmed while in the end application circuit. This is done with two lines for clock and data, and three other lines for power, ground and the programming sequence. Serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. Serial programming also allows the most recent firmware or a custom firmware to be programmed. Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for details about In-Circuit Serial Programming (ICSP™). • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. Any of the three pairs of programming clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 DS75018C-page 258 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 23.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections. The instruction set for this family of dsPIC33F devices is identical to the instruction set for dsPIC30F devices. Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into five basic categories: • • • • • Word or byte-oriented operations Bit-oriented operations Literal operations DSP operations Control operations Table 23-1 shows the general symbols used in describing the instructions. The dsPIC33F instruction set summary in Table 23-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand, which is typically a register ‘Wb’ without any address modifier • The second source operand, which is typically a register ‘Ws’ with or without an address modifier • The destination of the result, which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) The literal instructions that involve data movement can use some of the following operands: • A literal value to be loaded into a W register or file register (specified by ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand, which is a register ‘Wb’ without any address modifier • The second source operand, which is a literal value • The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier The MAC class of DSP instructions can use some of the following operands: • The accumulator (A or B) to be used (required operand) • The W registers to be used as the two operands • The X and Y address space prefetch operations • The X and Y address space prefetch destinations • The accumulator write-back destination The other DSP instructions do not involve any multiplication and can include: • The accumulator to be used (required) • The source or destination operand (designated as Wso or Wdo, respectively) with or without an address modifier • The amount of shift specified by a W register, ‘Wn’, or a literal value The control instructions can use some of the following operands: • A program memory address • The mode of the table read and table write instructions • The file register specified by the value, ‘f’ • The destination, which could be either the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’ 2011-2012 Microchip Technology Inc. DS75018C-page 259 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the Program Counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA TABLE 23-1: (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. Note: For more details on the instruction set, refer to the “16-Bit MCU and DSC Programmer’s Reference Manual” (DS70157). SYMBOLS USED IN OPCODE DESCRIPTIONS Field #text Description Means “literal defined by text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator Write-Back Destination Address register {W13, [W13]+ = 2} bit4 4-bit bit selection field (used in word-addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0x0000...0x1FFF} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor Working register pair (Direct Addressing) DS75018C-page 260 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 Working registers {W0..W15} Wnd One of 16 Destination Working registers {W0...W15} Wns One of 16 Source Working registers {W0...W15} WREG W0 (Working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X Data Space Prefetch Address register for DSP instructions {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7} Wy Y Data Space Prefetch Address register for DSP instructions {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7} 2011-2012 Microchip Technology Inc. DS75018C-page 261 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 1 2 3 4 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR Assembly Syntax # of # of Words Cycles Description Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z OA,OB,SA,SB ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z f,#bit4 Bit Clear f 1 1 None 5 BCLR BCLR BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater Than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater Than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater Than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater Than 1 1 (2) None BRA LE,Expr Branch if Less Than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less Than or Equal 1 1 (2) None BRA LT,Expr Branch if Less Than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less Than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A Overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B Overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None None 7 8 9 BSET BSW BTG BRA SA,Expr Branch if Accumulator A Saturated 1 1 (2) BRA SB,Expr Branch if Accumulator B Saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None DS75018C-page 262 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C Z BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f=f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb – Ws – C) 1 1 C,DC,N,OV,Z 18 19 20 CP CP0 CPB 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, Skip if = 1 1 (2 or 3) None 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, Skip if > 1 1 (2 or 3) None 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, Skip if < 1 1 (2 or 3) None 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, Skip if 1 1 (2 or 3) None 25 DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C 26 DEC DEC f f=f–1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z DEC2 f f=f–2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None 27 28 DEC2 DISI 2011-2012 Microchip Technology Inc. DS75018C-page 263 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV None 30 DIVF DIVF 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None Wm,Wn 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z C,DC,N,OV,Z 39 40 41 INC INC2 IOR INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z OA,OB,OAB, SA,SB,SAB 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd , AWB Multiply and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f None 45 46 47 MAC MOV MOVSAC Move WREG to f 1 1 MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None Prefetch and Store Accumulator 1 1 None MOVSAC DS75018C-page 264 Acc,Wx,Wxd,Wy,Wyd,AWB 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd , AWB Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z 52 53 54 NEG NOP POP NEG f f=f+1 1 1 NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z NOP No Operation 1 1 None NOPR No Operation 1 1 None POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) 1 2 None Pop Shadow Registers 1 1 All f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None POP.S 55 PUSH PUSH Push Shadow Registers 1 1 None Go into Sleep or Idle mode 1 1 WDTO,Sleep Expr Relative Call 1 2 None Wn Computed Call 1 2 None REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None PUSH.S 56 PWRSAV PWRSAV 57 RCALL RCALL RCALL 58 REPEAT #lit1 59 RESET RESET Software Device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW Return with Literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z 64 65 RLNC RRC #lit10,Wn 2011-2012 Microchip Technology Inc. DS75018C-page 265 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 66 67 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC SAC Assembly Syntax # of # of Words Cycles Description Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None Ws,Wnd Wnd = Sign-Extended Ws 1 1 C,N,Z None 68 SE SE 69 SETM SETM f f = 0xFFFF 1 1 SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z C,DC,N,OV,Z 70 71 72 73 74 75 76 SFTAC SL SUB SUBB SUBR SUBBR SWAP SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N 83 ZE DS75018C-page 266 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 24.0 DEVELOPMENT SUPPORT The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C® for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 24.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2011-2012 Microchip Technology Inc. DS75018C-page 267 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 24.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 24.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 24.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 24.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 24.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS75018C-page 268 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 24.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 24.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2011-2012 Microchip Technology Inc. 24.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 24.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer’s PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. DS75018C-page 269 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 24.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 24.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 24.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS75018C-page 270 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 25.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS(3).................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS, when VDD 3.0V(3) .................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to Vss, when VDD < 3.0V(3) ........................................ -0.3V to (VDD + 0.3V) Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin(2) ...........................................................................................................................250 mA Maximum current sourced/sunk by any 4x I/O pin ..................................................................................................15 mA Maximum current sourced/sunk by any 16x I/O pin ................................................................................................45 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports(2) ...............................................................................................................200 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 25-2). 3: See the “Pin Diagrams” section for 5V tolerant pins. 2011-2012 Microchip Technology Inc. DS75018C-page 271 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 25.1 DC Characteristics TABLE 25-1: OPERATING MIPS vs. VOLTAGE Maximum MIPS Characteristic VDD Range (in Volts) — VBOR-3.6V(1) -40°C to +85°C 40 — VBOR-3.6V(1) -40°C to +125°C 40 Note 1: Temp Range (in °C) dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table 25-11 for BOR values. TABLE 25-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typ. Max. Unit Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Industrial Temperature Devices Extended Temperature Devices Power Dissipation Internal Chip Power Dissipation: PINT = VDD x (IDD – IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: I/O = ({VDD – VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 25-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ. Max. Unit Notes Package Thermal Resistance, 18-Pin SOIC JA 57 — °C/W 1 Package Thermal Resistance, 18-pin PDIP JA 66 — °C/W 1 Package Thermal Resistance, 20-pin SSOP JA 64 — °C/W 1 Package Thermal Resistance, 28-Pin QFN-S JA 34 — °C/W 1 Package Thermal Resistance, 28-pin SSOP JA 71 — °C/W 1 Package Thermal Resistance, 28-Pin SOIC JA 47 — °C/W 1 Package Thermal Resistance, 28-Pin SPDIP JA 45 — °C/W 1 Package Thermal Resistance, 36-Pin VTLA JA 29 — °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS75018C-page 272 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param. Symbol Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ.(1) Max. Units VBOR — 3.6 V Conditions Operating Voltage DC10 VDD Supply Voltage(4) DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal — — VSS V DC17 SVDD VDD Rise Rate(3) to Ensure Internal Power-on Reset Signal 0.03 — — V/ms Note 1: 2: 3: 4: Industrial and Extended 0-3.0V in 0.1s Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. This is the limit to which VDD may be lowered without losing RAM data. These parameters are characterized but not tested in manufacturing. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table 25-11 for BOR values. 2011-2012 Microchip Technology Inc. DS75018C-page 273 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Typical(1) Operating Current Max. Units Conditions (IDD)(2) DC20d 15 23 mA -40°C DC20a 15 23 mA +25°C DC20b 15 23 mA +85°C DC20c 15 23 mA +125°C DC21d 23 34 mA -40°C DC21a 23 34 mA +25°C DC21b 23 34 mA +85°C DC21c 23 34 mA +125°C DC22d 25 38 mA -40°C DC22a 25 38 mA +25°C DC22b 25 38 mA +85°C DC22c 25 38 mA +125°C DC23d 34 51 mA -40°C DC23a 34 51 mA +25°C DC23b 34 51 mA +85°C DC23c 34 51 mA +125°C DC24d 43 64 mA -40°C DC24a 43 64 mA +25°C DC24b 43 64 mA +85°C DC24c 43 64 mA +125°C DC25d 83 125 mA -40°C DC25a 83 125 mA +25°C DC25b 83 125 mA +85°C 83 125 mA +125°C DC25c Note 1: 2: 3: 3.3V 10 MIPS 3.3V 16 MIPS(3) 3.3V 20 MIPS(3) 3.3V 30 MIPS(3) 3.3V 40 MIPS(3) 3.3V 40 MIPS See Note 2, except PWM and ADC are operating at maximum speed (PTCON2 = 0x0000) Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD; WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all zeroed) • CPU is executing while(1) statement These parameters are characterized but not tested in manufacturing. DS75018C-page 274 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Typical(1) Max. Units Conditions Idle Current (IIDLE): Core Off Clock On Base Current(2) DC40d 13 21 mA -40°C DC40a 13 21 mA +25°C DC40b 13 21 mA +85°C DC40c 13 21 mA +125°C DC41d 16 24 mA -40°C DC41a 16 24 mA +25°C DC41b 16 24 mA +85°C DC41c 16 24 mA +125°C DC42d 17 27 mA -40°C DC42a 17 27 mA +25°C DC42b 17 27 mA +85°C DC42c 17 27 mA +125°C DC43d 20 32 mA -40°C DC43a 20 32 mA +25°C DC43b 20 32 mA +85°C DC43c 20 32 mA +125°C DC44d 23 37 mA -40°C DC44a 23 37 mA +25°C DC44b 23 37 mA +85°C 23 37 mA +125°C DC44c Note 1: 2: 3: 3.3V 10 MIPS 3.3V 16 MIPS(3) 3.3V 20 MIPS(3) 3.3V 30 MIPS(3) 3.3V 40 MIPS Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Base Idle current is measured as follows: • CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD; WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all zeroed) These parameters are characterized but not tested in manufacturing. 2011-2012 Microchip Technology Inc. DS75018C-page 275 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Typical(1) Max. Units 500 A Conditions PD)(2,4) Power-Down Current (I DC60d 125 -40°C DC60a 135 500 A +25°C DC60b 235 500 A +85°C DC60c 565 950 A +125°C DC61d 40 50 A -40°C DC61a 40 50 A +25°C DC61b 40 50 A +85°C 80 90 A +125°C DC61c Note 1: 2: 3: 4: 3.3V Base Power-Down Current 3.3V Watchdog Timer Current: IWDT(3) Data in the Typical column is at 3.3V, +25°C unless otherwise stated. IPD current is measured as follows: • CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • All peripheral modules are disabled (PMDx bits are all ‘1’s) • VREGS bit (RCON<8>) = 1 (i.e., core regulator is set to standby while the device is in Sleep mode) The current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. These currents are measured on the device containing the most memory in this family. DS75018C-page 276 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Typical(1) Max. Doze Ratio Units Conditions Doze Current (IDOZE)(2) DC73a 30 45 1:2 mA DC73f 16 23 1:64 mA DC73g 16 23 1:128 mA DC70a 30 45 1:2 mA DC70f 16 23 1:64 mA DC70g 16 23 1:128 mA DC71a 30 45 1:2 mA DC71f 16 23 1:64 mA DC71g 16 23 1:128 mA DC72a 30 45 1:2 mA DC72f 16 23 1:64 mA DC72g 16 23 1:128 mA Note 1: 2: -40°C 3.3V 40 MIPS +25°C 3.3V 40 MIPS +85°C 3.3V 40 MIPS +125°C 3.3V 40 MIPS Data in the Typical column is at 3.3V, +25°C unless otherwise stated. IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows: • Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD; WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all zeroed) • CPU is executing while(1) statement 2011-2012 Microchip Technology Inc. DS75018C-page 277 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Symbol VIL Characteristic Min. Typ.(1) Max. Units Conditions Input Low Voltage DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 I/O Pins with OSC1 VSS — 0.2 VDD V DI18 SDA1, SCL1 VSS — 0.3 VDD V SMBus disabled SDA1, SCL1 VSS — 0.8 V SMBus enabled DI19 VIH Input High Voltage DI20 DI21 I/O Pins Not 5V Tolerant(4) I/O Pins 5V Tolerant(4) 0.7 VDD 0.7 VDD — — VDD 5.5 V V DI28 DI29 SDA1, SCL1 SDA1, SCL1 0.7 VDD 2.1 — — 5.5 5.5 V V SMBus disabled SMBus enabled — 250 — A VDD = 3.3V, VPIN = VSS — — ±2 A VSS VPIN VDD, Pin at high-impedance — — ±8 A VSS VPIN VDD, Pin at high-impedance ICNPU CNx Pull-up Current IIL Input Leakage Current(2,3,4) DI30 DI50 I/O Pins: 4x Sink Driver Pins RA0-RA2, RB0-RB2, RB5-RB10, RB15 16x Sink Driver Pins RA3, RA4, RB3, RB4, RB11-RB14 DI55 MCLR — — ±2 A VSS VPIN VDD DI56 OSC1 — — ±2 A VSS VPIN VDD, XT and HS modes Note 1: 2: 3: 4: 5: 6: 7: 8: 9: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. See the “Pin Diagrams” section for the list of 5V tolerant I/O pins. VIL source < (VSS – 0.3); characterized but not tested. Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V; characterized but not tested. Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit; characterized but not tested. DS75018C-page 278 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Symbol IICL Characteristic IICT 3: 4: 5: 6: 7: 8: 9: Units Conditions 0 — -5(5,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP and RB5 0 — +5(6,7,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, RB5 and digital 5V tolerant designated pins -20(9) — +20(9) mA Absolute instantaneous sum of all ± input injection currents from all I/O pins ( | IICL + | IICH | ) IICT Total Input Injection Current (sum of all I/O and control pins) Note 1: 2: Max. Input High Injection Current DI60b DI60c Typ.(1) Input Low Injection Current DI60a IICH Min. Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. See the “Pin Diagrams” section for the list of 5V tolerant I/O pins. VIL source < (VSS – 0.3); characterized but not tested. Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V; characterized but not tested. Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit; characterized but not tested. 2011-2012 Microchip Technology Inc. DS75018C-page 279 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH DO20A VOH1 Note 1: Characteristic Min. Typ. Max. Units Output Low Voltage I/O Pins: 4x Sink Driver Pins – RA0-RA2, RB0-RB2, RB5-RB10, RB15 — — 0.4 V IOL 6 mA, VDD = 3.3V(1) Output Low Voltage I/O Pins: 16x Sink Driver Pins – RA3, RA4, RB3, RB4, RB11-RB14 — — 0.4 V IOL 18 mA, VDD = 3.3V(1) Output High Voltage I/O Pins: 4x Source Driver Pins – RA0-RA2, RB0-RB2, RB5-RB10, RB15 2.4 — — V IOH -6 mA, VDD = 3.3V(1) Output High Voltage I/O Pins: 16x Source Driver Pins – RA3, RA4, RB3, RB4, RB11-RB14 2.4 — — V IOH -18 mA, VDD = 3.3V(1) Output High Voltage I/O Pins: 4x Source Driver Pins – RA0-RA2, RB0-RB2, RB5-RB10, RB15 1.5 — — V IOH -12 mA, VDD = 3.3V(1) 2.0 — — IOH -11 mA, VDD = 3.3V(1) 3.0 — — IOH -3 mA, VDD = 3.3V(1) Output High Voltage I/O Pins: 16x Source Driver Pins – RA3, RA4, RB3, RB4, RB11-RB14 1.5 — — 2.0 — — IOH -25 mA, VDD = 3.3V(1) 3.0 — — IOH -8 mA, VDD = 3.3V(1) V Conditions IOH -30 mA, VDD = 3.3V(1) These parameters are characterized, but not tested. TABLE 25-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param. Symbol Standard Operating Conditions: 3.0V to 3.6V(3) (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Characteristic BOR Event on VDD Transition High-to-Low BOR Event is Tied to VDD Core Voltage Decrease Min.(1) Typ. Max. Units 2.55 — 2.96 V Conditions (See Note 2) BO10 VBOR Note 1: 2: 3: These parameters are for design guidance only and are not tested in manufacturing. The device will operate as normal until the VDDMIN threshold is reached. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. DS75018C-page 280 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Symbol Characteristic Min. Typ.(1) Max. Units Conditions Program Flash Memory D130 EP Cell Endurance 10,000 — — D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated, -40C to +125C D135 IDDP Supply Current during Programming — 10 — mA D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles, TA = +85°C(2) D137b TPE Page Erase Time 19.5 — 27.3 ms TPE = 168517 FRC cycles, TA = +125°C(2) D138a TWW Word Write Cycle Time 42.3 — 55.9 µs TWW = 355 FRC cycles, TA = +85°C(2) D138b TWW Word Write Cycle Time 41.1 — 57.6 µs TWW = 355 FRC cycles, TA = +125°C(2) Note 1: 2: E/W -40C to +125C Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Other conditions: FRC = 7.37 MHz, TUN<5:0> = ‘b011111 (for Minimum), TUN<5:0> = ‘b100000 (for Maximum). This parameter depends on the FRC accuracy (see Table 25-20) and the value of the FRC Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and Maximum time, see Section 5.3 “Programming Operations”. TABLE 25-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: Param. Symbol CEFC Note 1: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Characteristics External Filter Capacitor Value(1) Min. Typ. Max. Units 4.7 10 — F Comments Capacitor must be low series resistance (< 0.5 Ohms) Typical VCAP voltage = 2.5 volts when VDD VDDMIN. 2011-2012 Microchip Technology Inc. DS75018C-page 281 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 25.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 AC characteristics and timing parameters. TABLE 25-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Table 25-1. AC CHARACTERISTICS FIGURE 25-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2 15 pF for OSC2 output VSS TABLE 25-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param. Symbol Characteristic Min. Typ. Max. Units Conditions DO50 COSCO OSC2 Pin — — 15 pF In XT and HS modes when external clock is used to drive OSC1 DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode DO58 CB SCL1, SDA1 — — 400 pF In I2C™ mode DS75018C-page 282 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 OS30 OS30 Q4 OSC1 OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 25-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol OS10 FIN Min. Typ.(1) Max. Units External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) DC — 40 MHz EC Oscillator Crystal Frequency 3.0 10 — — 10 32 MHz MHz XT HS Characteristic Conditions OS20 TOSC TOSC = 1/FOSC 12.5 — DC ns OS25 TCY Instruction Cycle Time(2) 25 — DC ns OS30 TosL, TosH External Clock in (OSC1) High or Low Time 0.375 x TOSC — 0.625 x TOSC ns EC OS31 TosR, TosF External Clock in (OSC1) Rise or Fall Time — — 20 ns EC OS40 TckR CLKO Rise Time(3) — 5.2 — ns — 5.2 — ns 14 16 18 mA/V Time(3) OS41 TckF CLKO Fall OS42 GM External Oscillator Transconductance(4) Note 1: 2: 3: 4: VDD = 3.3V TA = +25ºC Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing. 2011-2012 Microchip Technology Inc. DS75018C-page 283 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic Min. Typ.(1) Max. Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 0.8 — 8 MHz OS51 FSYS On-Chip VCO System Frequency 100 — 200 MHz OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 mS -3 0.5 3 % OS53 DCLK Note 1: 2: (2) CLKO Stability (Jitter) Conditions ECPLL, XTPLL modes Measured over 100 ms period Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks use this formula: D CLK Peripheral Clock Jitter = ----------------------------------------------------------------------F OSC ------------------------------------------------------------ Peripheral Bit Rate Clock For example: FOSC = 32 MHz, DCLK = 3%, SPI bit rate clock (i.e., SCK) is 2 MHz. D CLK 3% 3% SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75% 4 16 MHz- 32 ------------------ 2 MHz TABLE 25-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic Min. Typ.(1) Max. Units OS56 FHPOUT On-Chip 16x PLL CCO Frequency 112 118 120 MHz OS57 FHPIN On-Chip 16x PLL Phase Detector Input Frequency 7.0 7.37 7.5 MHz OS58 TSU Frequency Generator Lock Time — — 10 µs Note 1: Conditions Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. DS75018C-page 284 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for Extended Min. Typ. Max. Units Conditions Internal FRC Accuracy @ FRC Frequency = 7.37 MHz (1) F20a FRC -2 — +2 % -40°C TA +85°C VDD = 3.0-3.6V F20b FRC -5 — +5 % -40°C TA +125°C VDD = 3.0-3.6V Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift. TABLE 25-20: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ. Max. Units Conditions LPRC @ 32.768 kHz(1) F21a LPRC -20 — +20 % -40°C TA +85°C VDD = 3.0-3.6V F21b LPRC -70 — +70 % -40°C TA +125°C VDD = 3.0-3.6V Note 1: The change of LPRC frequency as VDD changes. 2011-2012 Microchip Technology Inc. DS75018C-page 285 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 25-1 for load conditions. TABLE 25-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. DO31 DO32 Symbol TIOR TIOF Min. Typ.(1) Max. Units I/O Pins: 4x Sink Driver Pins RA0-RA2, RB0-RB2, RB5-RB10, RB15 — 10 25 ns I/O Pins: 16x Sink Driver Pins RA3, RA4, RB3, RB4, RB11-RB14 — 6 15 ns I/O Pins: 4x Sink Driver Pins RA0-RA2, RB0-RB2, RB5-RB10, RB15 — 10 25 ns I/O Pins: 16x Sink Driver Pins RA3, RA4, RB3, RB4, RB11-RB14 — 6 15 ns Characteristic DI35 TINP INTx Pin High or Low Time (input) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. DS75018C-page 286 Conditions Refer to Figure 25-1 for test conditions Refer to Figure 25-1 for test conditions 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR PWRT Time-out SY11 SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 25-1 for load conditions. TABLE 25-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SY10 TMCL MCLR Pulse Width (low) 2 — — s -40°C to +125°C SY11 TPWRT Power-up Timer Period — 64 — ms -40°C to +125°C -40°C to +125°C SY12 TPOR Power-on Reset Delay SY13 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset SY30 TOST Oscillator Start-up Time Note 1: 2: 3 10 30 s 0.68 0.72 1.2 s — 1024 TOSC — — TOSC = OSC1 period These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2011-2012 Microchip Technology Inc. DS75018C-page 287 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-5: TIMER1 AND TIMER2 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 25-1 for load conditions. TABLE 25-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. TA10 TA11 TA15 Symbol TTXH TTXL TTXP Characteristic Min. Typ. Max. Units Synchronous, no prescaler TCY + 20 — — ns Synchronous, with prescaler (TCY + 20)/N — — ns Asynchronous 20 — — ns Synchronous, no prescaler TCY + 20 — — ns Synchronous, with prescaler (TCY + 20)/N — — ns Asynchronous 20 — — ns 2 TCY + 40 — — ns Greater of: 40 ns or (2 TCY + 40)/N — — — Asynchronous 40 — — ns T1CK Oscillator Input Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>)) DC — 50 kHz 0.75 TCY + 40 — 1.75 TCY + 40 — TxCK High Time TxCK Low Time TxCK Input Synchronous, Period no prescaler Synchronous, with prescaler OS60 Ft1 TA20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: Conditions Must also meet Parameter TA15, N = prescale value (1, 8, 64, 256) Must also meet Parameter TA15, N = prescale value (1, 8, 64, 256) N = prescale value (1, 8, 64, 256) Timer1 is a Type A. DS75018C-page 288 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic Min. Typ. Max. Units Conditions TB10 TTXH TxCK High Time Synchronous Greater of: 20 ns or (TCY + 20)/N — — ns Must also meet Parameter TB15 N = prescale value (1, 8, 64, 256) TB11 TTXL TxCK Low Time Synchronous Greater of: 20 ns or (TCY + 20)/N — — ns Must also meet Parameter TB15 N = prescale value (1, 8, 64, 256) TB15 TTXP TxCK Input Period Synchronous, no prescaler TCY + 40 — — ns N = prescale value (1, 8, 64, 256) — 1.5 TCY — Synchronous, with prescaler TB20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment 2011-2012 Microchip Technology Inc. Greater of: 20 ns or (TCY + 40)/N 0.5 TCY DS75018C-page 289 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-6: INPUT CAPTURE (CAP1) TIMING CHARACTERISTICS IC1 IC10 IC11 IC15 Note: Refer to Figure 25-1 for load conditions. TABLE 25-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Characteristic(1) Param. Symbol IC10 TccL IC1 Input Low Time No prescaler IC11 TccH IC1 Input High Time No prescaler IC15 TccP IC1 Input Period Min. Max. Units 0.5 TCY + 20 — ns With prescaler 10 — ns 0.5 TCY + 20 — ns 10 — ns (TCY + 40)/N — ns With prescaler Note 1: Conditions N = prescale value (1, 4, 16) These parameters are characterized but not tested in manufacturing. FIGURE 25-7: OUTPUT COMPARE MODULE (OC1) TIMING CHARACTERISTICS OC1 (Output Compare or PWM Mode) OC10 OC11 Note: Refer to Figure 25-1 for load conditions. TABLE 25-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol Characteristic(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ. Max. Units Conditions OC10 TccF OC1 Output Fall Time — — — ns See Parameter DO32 OC11 TccR OC1 Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing. DS75018C-page 290 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 Active OC1 Tri-State TABLE 25-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol Characteristic(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ. Max. Units OC15 TFD Fault Input to PWM I/O Change — — TCY + 20 ns OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns Note 1: These parameters are characterized but not tested in manufacturing. 2011-2012 Microchip Technology Inc. Conditions DS75018C-page 291 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-9: HIGH-SPEED PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTx MP20 PWMx FIGURE 25-10: HIGH-SPEED PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 25-1 for load conditions. TABLE 25-28: HIGH-SPEED PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions MP10 TFPWM PWM Output Fall Time — 2.5 — ns MP11 TRPWM PWM Output Rise Time — 2.5 — ns TFD Fault Input to PWM I/O Change — — 15 ns TFH Minimum PWM Fault Pulse Width 8 — — ns DTC<10> = 10 MP31 TPDLY Tap Delay 1.04 — — ns ACLK = 120 MHz MP32 ACLK PWM Input Clock — — 120 MHz MP20 MP30 Note 1: 2: 3: See Note 2, Note 3 These parameters are characterized but not tested in manufacturing. This parameter is a maximum allowed input clock for the PWM module. The maximum value for this parameter applies to dsPIC33FJ06GS101A/102A/202A/302 devices only. DS75018C-page 292 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Maximum Data Rate Master Transmit Only (Half-Duplex) Master Transmit/Receive (Full-Duplex) Slave Transmit/Receive (Full-Duplex) CKE CKP SMP 15 MHz Table 25-30 — — 0,1 0,1 0,1 9 MHz — Table 25-31 — 1 0,1 1 9 MHz — Table 25-32 — 0 0,1 1 15 MHz — — Table 25-33 1 0 0 11 MHz — — Table 25-34 1 1 0 15 MHz — — Table 25-35 0 1 0 11 MHz — — Table 25-36 0 0 0 FIGURE 25-11: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx SP30, SP31 Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure 25-1 for load conditions. 2011-2012 Microchip Technology Inc. DS75018C-page 293 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx LSb SP30, SP31 Note: Refer to Figure 25-1 for load conditions. TABLE 25-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions SP10 TscP Maximum SCKx Frequency — — 15 MHz SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, TscL2doV SDOx Data Output Valid after SCKx Edge — 6 20 ns SP36 TdiV2scH, TdiV2scL SDOx Data Output Setup to First SCKx Edge 30 — — ns Note 1: 2: 3: 4: See Note 3 These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS75018C-page 294 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 25-1 for load conditions. TABLE 25-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions See Note 3 See Parameter DO32 and Note 4 See Parameter DO31 and Note 4 See Parameter DO32 and Note 4 See Parameter DO31 and Note 4 SP10 SP20 TscP TscF Maximum SCKx Frequency SCKx Output Fall Time — — — — 9 — MHz ns SP21 TscR SCKx Output Rise Time — — — ns SP30 TdoF SDOx Data Output Fall Time — — — ns SP31 TdoR SDOx Data Output Rise Time — — — ns SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 111 ns. The clock generated in master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. SP36 SP40 SP41 Note 1: 2: 3: 4: 2011-2012 Microchip Technology Inc. DS75018C-page 295 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 SP30, SP31 SDIx MSb In LSb Bit 14 - - - - - -1 MSb SDOx SP30, SP31 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 25-1 for load conditions. TABLE 25-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions -40ºC to +125ºC and see Note 3 See Parameter DO32 and Note 4 See Parameter DO31 and Note 4 See Parameter DO32 and Note 4 See Parameter DO31 and Note 4 SP10 TscP Maximum SCKx Frequency — — 9 MHz SP20 TscF SCKx Output Fall Time — — — ns SP21 TscR SCKx Output Rise Time — — — ns SP30 TdoF SDOx Data Output Fall Time — — — ns SP31 TdoR SDOx Data Output Rise Time — — — ns SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 111 ns. The clock generated in master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. SP36 SP40 SP41 Note 1: 2: 3: 4: DS75018C-page 296 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions. 2011-2012 Microchip Technology Inc. DS75018C-page 297 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 15 MHz SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 6 20 ns SP36 TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge 30 — — ns SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 30 — — ns SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns SP50 TssL2scH, TssL2scL SSx to SCKx or SCKx Input 120 — — ns SP51 TssH2doZ SSx to SDOx Output High-Impedance 10 — 50 ns See Note 4 SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns See Note 4 SP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 50 ns Note 1: 2: 3: 4: See Note 3 These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must not violate this specification. Assumes 50 pF load on all SPIx pins. DS75018C-page 298 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions. 2011-2012 Microchip Technology Inc. DS75018C-page 299 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 11 MHz SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 6 20 ns SP36 TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge 30 — — ns SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 30 — — ns SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns SP50 TssL2scH, TssL2scL SSx to SCKx or SCKx Input 120 — — ns SP51 TssH2doZ SSx to SDOx Output High-Impedance 10 — 50 ns See Note 4 SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns See Note 4 SP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 50 ns Note 1: 2: 3: 4: See Note 3 These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not violate this specification. Assumes 50 pF load on all SPIx pins. DS75018C-page 300 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-17: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions. 2011-2012 Microchip Technology Inc. DS75018C-page 301 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 15 MHz SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 6 20 ns SP36 TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge 30 — — ns SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 30 — — ns SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns SP50 TssL2scH, TssL2scL SSx to SCKx or SCKx Input 120 — — ns SP51 TssH2doZ SSx to SDOx Output High-Impedance 10 — 50 ns See Note 4 SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns See Note 4 Note 1: 2: 3: 4: See Note 3 These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must not violate this specification. Assumes 50 pF load on all SPIx pins. DS75018C-page 302 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions. 2011-2012 Microchip Technology Inc. DS75018C-page 303 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 11 MHz SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 6 20 ns SP36 TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge 30 — — ns SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 30 — — ns SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns SP50 TssL2scH, TssL2scL SSx to SCKx or SCKx Input 120 — — ns SP51 TssH2doZ SSx to SDOx Output High-Impedance 10 — 50 ns See Note 4 SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns See Note 4 Note 1: 2: 3: 4: See Note 3 These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not violate this specification. Assumes 50 pF load on all SPIx pins. DS75018C-page 304 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-19: I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL1 IM31 IM34 IM30 IM33 SDA1 Start Condition Stop Condition Note: Refer to Figure 25-1 for load conditions. FIGURE 25-20: I2C1 BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCL1 IM11 IM26 IM10 IM25 IM33 SDA1 In IM40 IM40 IM45 SDA1 Out Note: Refer to Figure 25-1 for load conditions. 2011-2012 Microchip Technology Inc. DS75018C-page 305 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-37: I2C1 BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Min.(1) Max. Units TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s (2) TCY/2 (BRG + 1) — s Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s — 300 ns 20 + 0.1 CB 300 ns Param. Symbol IM10 Characteristic 1 MHz mode IM11 THI:SCL IM20 TF:SCL IM21 TR:SCL IM25 SDA1 and SCL1 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(2) — 100 ns SDA1 and SCL1 100 kHz mode Rise Time 400 kHz mode — 1000 ns TSU:DAT Data Input Setup Time 20 + 0.1 CB 300 ns 1 MHz mode(2) — 300 ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns mode(2) 40 — ns 100 kHz mode 0 — s 1 MHz IM26 THD:DAT Data Input Hold Time IM30 TSU:STA IM31 Start Condition Setup Time THD:STA Start Condition Hold Time IM33 TSU:STO Stop Condition Setup Time IM34 THD:STO Stop Condition Hold Time IM40 TAA:SCL Output Valid From Clock 400 kHz mode 0 0.9 s 1 MHz mode(2) 0.2 — s 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s (2) 1 MHz mode TCY/2 (BRG + 1) — s 100 kHz mode TCY/2 (BRG + 1) — ns 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns 100 kHz mode — 3500 ns 400 kHz mode — 1000 ns mode(2) — 400 ns 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s 1 MHz mode(2) 0.5 — s 1 MHz IM45 TBF:SDA Bus Free Time IM50 CB Bus Capacitive Loading — 400 pF IM51 TPGD Pulse Gobbler Delay 65 390 ns Note 1: 2: 3: Conditions CB is specified to be from 10 pF to 400 pF CB is specified to be from 10 pF to 400 pF Only relevant for Repeated Start condition After this period the first clock pulse is generated Time the bus must be free before a new transmission can start See Note 3 I2 BRG is the value of the C™ Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Maximum pin capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only). Typical value for this parameter is 130 ns. DS75018C-page 306 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-21: I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL1 IS34 IS31 IS30 IS33 SDA1 Start Condition FIGURE 25-22: Stop Condition I2C1 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCL1 IS30 IS26 IS31 IS25 IS33 SDA1 In IS40 IS40 IS45 SDA1 Out 2011-2012 Microchip Technology Inc. DS75018C-page 307 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-38: I2C1 BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol IS10 IS11 IS20 IS21 IS25 TLO:SCL THI:SCL TF:SCL TR:SCL TSU:DAT Characteristic Clock Low Time Clock High Time SDA1 and SCL1 Fall Time SDA1 and SCL1 Rise Time Data Input Setup Time Min. Max. Units 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(2) 0.5 — s 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(2) — 100 ns 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(2) — 300 ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns mode(2) 1 MHz IS26 IS30 IS31 IS33 IS34 IS40 THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time THD:STO Stop Condition Hold Time TAA:SCL Output Valid From Clock 100 — ns 100 kHz mode 0 — s 400 kHz mode 0 0.9 s 1 MHz mode(2) 0 0.3 s 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 1 MHz mode(2) 0.25 — s 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s 1 MHz mode(2) 0.25 — s 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 1 MHz mode(2) 0.6 — s 100 kHz mode 4000 — ns 400 kHz mode 600 — ns 1 MHz mode(2) 250 100 kHz mode 0 3500 ns 400 kHz mode 0 1000 ns 1 MHz IS45 IS50 Note 1: TBF:SDA Bus Free Time CB mode(2) CB is specified to be from 10 pF to 400 pF CB is specified to be from 10 pF to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated ns 0 350 ns 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s 1 MHz mode(2) 0.5 — s — 400 pF Bus Capacitive Loading Conditions Time the bus must be free before a new transmission can start Maximum pin capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only). DS75018C-page 308 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 = TABLE 25-39: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V and 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS(2) Param. Symbol Characteristic Min. Typ. Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply — — — — AVDD is internally connected to VDD on 18-pin and 28-pin devices. See parameters (DC10) in Table 25-4. AD02 AVSS Module VSS Supply — — — — AVSS is internally connected to VSS on 18-pin and 28-pin devices AD10 VINH-VINL Full-Scale Input Span VSS — VDD V AD11 VIN AVSS — AVDD V AD12 IAD Analog Input AD13 Absolute Input Voltage — Operating Current — 8 — mA Leakage Current — ±0.6 — A VINL = AVSS = 0V, AVDD = 3.3V, Source Impedance = 100 RIN Recommended Impedance — — 100 of Analog Voltage Source DC Accuracy @ 1.5 Msps for 18 and 28-Pin Devices AD20a Nr Resolution AD21a INL Integral Nonlinearity -0.5 -0.3/+0.5 +1.2 LSb See Note 3 AD17 10 data bits AD22a DNL Differential Nonlinearity -0.9 ±0.6 +0.9 LSb See Note 3 AD23a GERR Gain Error — 10 20 LSb See Note 3 AD24a EOFF Offset Error — 10 20 LSb See Note 3 — — — — Guaranteed AD25a — Monotonicity (1) DC Accuracy @ 2.0 Msps for 18 and 28-Pin Devices AD20b Nr Resolution AD21b INL Integral Nonlinearity AD22b DNL Differential Nonlinearity AD23b GERR AD24b EOFF AD25b — 10 data bits -1 ±1.5 +2.8 LSb -1.5 ±2 +2.8 LSb Gain Error — 10 20 LSb Offset Error — 10 20 LSb Monotonicity(1) — — — — Guaranteed DC Accuracy @ 2.0 Msps for 20 and 36-Pin Devices AD20c Nr Resolution 10 data bits AD21c INL Integral Nonlinearity > -2 ±0.5 <2 LSb See Note 3 AD22c DNL Differential Nonlinearity > -1 ±0.5 <1 LSb See Note 3 AD23c GERR Gain Error — 10 20 LSb See Note 3 AD24c EOFF Offset Error — 10 20 LSb See Note 3 Monotonicity(1) — — — — Guaranteed AD25c Note 1: 2: 3: — The Analog-to-Digital conversion result never decreases with an increase in input voltage and has no missing codes. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function, but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table 25-11 for BOR values. These parameters are characterized by similarity, but are not tested in manufacturing. 2011-2012 Microchip Technology Inc. DS75018C-page 309 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-39: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. Standard Operating Conditions: 3.0V and 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended (2) Symbol Characteristic Min. Typ. Max. Units Conditions Dynamic Performance AD30 THD Total Harmonic Distortion — -73 — dB AD31 SINAD Signal to Noise and Distortion — 58 — dB AD32 SFDR Spurious Free Dynamic Range — -73 — dB AD33 FNYQ Input Signal Bandwidth — — 1 MHz AD34 ENOB Effective Number of Bits — 9.4 — bits Note 1: 2: 3: The Analog-to-Digital conversion result never decreases with an increase in input voltage and has no missing codes. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function, but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table 25-11 for BOR values. These parameters are characterized by similarity, but are not tested in manufacturing. TABLE 25-40: 10-BIT HIGH-SPEED ADC MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic Min. Typ.(1) Max. Units — ns Conditions Clock Parameters AD50b TAD ADC Clock Period AD55b tCONV Conversion Time AD56b FCNV Throughput Rate 35.8 — Conversion Rate Devices with Single SAR — 14 TAD — — — — 2.0 Msps 10 s Timing Parameters AD63b tDPU Note 1: Time to Stabilize Analog Stage from ADC Off to ADC On 1.0 — These parameters are characterized but not tested in manufacturing. FIGURE 25-23: ANALOG-TO-DIGITAL CONVERSION TIMING PER INPUT tCONV Trigger Pulse TAD ADC Clock ADC Data ADBUFxx 9 Old Data 8 2 1 0 New Data CONV DS75018C-page 310 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-41: HIGH-SPEED ANALOG COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS(2) Param. Symbol Characteristic Min. Typ. Max. Units -58 +14/-40 66 mV CM10 VIOFF Input Offset Voltage CM11 VICM Input Common-Mode Voltage Range(1) 0 — AVDD V CM14 TRESP Large Signal Response 21 30 49 ns Note 1: 2: Comments V+ input step of 100 mv while V- input held at AVDD/2. Delay measured from analog input pin to PWM output pin. These parameters are for design guidance only and are not tested in manufacturing. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table 25-11 for BOR values. TABLE 25-42: DAC MODULE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC and DC CHARACTERISTICS(2) Param. Symbol Characteristic DA01 (1) EXTREF External Voltage Reference Reference(1) Min. Typ. Max. Units 0 — AVDD – 1.6 V 1.15 1.25 1.35 DA08 INTREF Internal Voltage DA02 CVRES Resolution DA03 INL Integral Nonlinearity Error -7 -1 +7 LSB DA04 DNL Differential Nonlinearity Error -5 -0.5 +5 LSB 10 V Bits DA05 EOFF Offset Error 0.4 -0.8 2.6 % DA06 EG Gain Error 0.4 -1.8 5.2 % DA07 TSET Settling Time(1) 711 1551 2100 ns Note 1: 2: Comments AVDD = 3.3V, DACREF = (AVDD/2)V Measured when RANGE = 1 (high range) and the CMREF<9:0> bits transition from 0x1FF to 0x300 Parameters are for design guidance only and are not tested in manufacturing. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table 25-11 for BOR values. 2011-2012 Microchip Technology Inc. DS75018C-page 311 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-43: DAC OUTPUT (DACOUT PIN) DC SPECIFICATIONS DC CHARACTERISTICS(1) Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param. Symbol Characteristic DA11 — DA12 DA13 DA14 DA15 Min. Resistive Output Load 3K Impedance CLOAD Output Load — Capacitance Output Current Drive 200 IOUT Strength VRANGE Output Drive Voltage AVSS + 250 mV Range at Current Drive of 200 mA AVSS + 5 mV VLRANGE Output Drive Voltage Range at Reduced Current Drive of 50 mA Current Consumed — IDD when Module Is Enabled Typ. Max. Units — — Ohm — 35 pF 300 — µA — AVDD – 900 mV V — AVDD – 500 mV V — 1.3 x IOUT µA RLOAD Comments Including output pin capacitance Sink and source Module will always consume this current even if no load is connected to the output Output Impedance — 820 — Ohms when Module is Enabled — 10 10 mV DA30 VOFFSET Input Offset Voltage Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table 25-11 for BOR values. DA16 ROUTON TABLE 25-44: DAC GAIN STAGE TO COMPARATOR SPECIFICATIONS DC CHARACTERISTICS Param. Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended (1) Symbol Characteristic DA15 IDD Current Consumed when Module Is Enabled. DA32 G Amplifier Gain Min. Typ. Max. Units Conditions — 60 — µA Module will always consume this current even if no load is connected to the output — 1.0 — — — 1.8 — — DA33 GBWP Gain Bandwidth Product — 2.0 — MHz At 1 pF load capacitance. Measured with sine wave output signal of 1V peak-to-peak with a midpoint value of 1.2V. Voltage excursion from 0.7 to 1.7V. DA34 SR Slew Rate — 5 — V/µs Slew rate between 10% and 90% of AVDD DA07 TS Settling Time — 200 — ns Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table 25-11 for BOR values. DS75018C-page 312 Settling time to 3% 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-45: CONSTANT CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Param. Symbol Characteristic CC01 IDD CC02 IREG CC03 IOUT Note 1: Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended (1) Min. Typ. Max. Units Current Consumption — 30 — µA Regulation of Current with Voltage On — ±3 — % Current Output at Terminal — 10 — µA Conditions Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table 25-11 for BOR values. 2011-2012 Microchip Technology Inc. DS75018C-page 313 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 314 2011-2012 Microchip Technology Inc. DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 26-1: VOH – 4x DRIVER PINS FIGURE 26-3: 0.040 -0.030 3.6V -0.025 0.035 3.3V -0.020 3V Absolute Maximum -0.015 3.6V 3.3V 0.030 IOL (A) IOH (A) VOL – 4x DRIVER PINS 3V 0.025 0.020 Absolute Maximum 0.015 -0.010 0.010 -0.005 0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 0.000 0.00 4.00 1.00 VOH (V) FIGURE 26-2: FIGURE 26-4: VOH – 16x DRIVER PINS -0.080 3.6V -0.060 IOH (A) 3.00 4.00 VOL – 16x DRIVER PINS 0.120 3.6V 0.100 3.3V 3.3V 0.080 -0.050 Absolute Maximum -0.040 3V -0.030 IOL (A) -0.070 2.00 VOL (V) 3V 0.060 Absolute Maximum 0.040 DS75018C-page 315 -0.020 0.020 -0.010 0.000 0.00 1.00 2.00 VOH (V) 3.00 4.00 0.000 0.00 1.00 2.00 VOL (V) 3.00 4.00 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. 26.0 FIGURE 26-7: TYPICAL IPD CURRENT @ VDD = 3.3V 450 90 400 85 IDD Current (mA) IPD Current (µA) 350 300 250 200 150 80 75 70 65 100 60 50 55 0 TYPICAL IDD CURRENT @ VDD = 3.3V, +25ºC 50 -40 -20 0 20 40 60 80 100 10 120 15 20 Temperature (Celsius) FIGURE 26-6: 25 30 35 40 MIPS TYPICAL IDOZE CURRENT @ VDD = 3.3V TYPICAL IIDLE CURRENT @ VDD = 3.3V, +25ºC FIGURE 26-8: 40 20 35 18 16 IIDLE Current (mA) 2011-2012 Microchip Technology Inc. IDOZE Current (mA) 30 25 20 15 14 12 10 8 6 4 10 2 5 0 10 0 1 1:1 2 1:2 1:83 Doze Ratio 4 1:64 5 1:128 15 20 25 MIPS 30 35 40 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 316 FIGURE 26-5: TYPICAL FRC FREQUENCY @ VDD = 3.3V 7.38 32.6 32.55 LPRC Frequency (kHz) 7.36 FRC Frequency (MHz) TYPICAL LPRC FREQUENCY @ VDD = 3.3V FIGURE 26-11: 7.34 7.32 7.3 32.5 32.45 32.4 32.35 32.3 7.28 -40 -20 0 20 40 60 Temperature (Celsius) 7.26 -40 -20 0 20 40 60 80 100 120 100 120 Temperature (Celsius) FIGURE 26-10: TYPICAL INTREF @ VDD = 3.3V 1.25 1.24 1.24 INTREF (V) 1.23 1.23 1.22 1.22 DS75018C-page 317 1.21 1.21 1.20 -40 -20 0 20 40 60 Temperature (Celsius) 80 80 100 120 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. FIGURE 26-9: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 318 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC (.300”) dsPIC30F3012 30I/P e3 0610017 Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX dsPIC33FJ06 GS101-I/SO YYWWNNN 0830235 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: e3 dsPIC33FJ12 MC201-I/SS e3 0730235 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. 2011-2012 Microchip Technology Inc. DS75018C-page 319 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 27.1 Package Marking Information (Continued) 28-Lead SPDIP Example dsPIC33FJ16MC 102-E/SP e3 0730235 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead QFN-S XXXXXXXX XXXXXXXX YYWWNNN 36-Lead VTLA XXXXXXXX XXXXXXXX YYWWNNN DS75018C-page 320 Example dsPIC33FJ16MC 102-E/SO e3 0730235 Example 33FJ16MC 102-E/SS e3 0730235 Example 33FJJ16MC 102E/MM e3 0730235 Example 33FJJ16MC 102E/TL e3 0730235 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 27.2 Package Details /HDG3ODVWLF'XDO,Q/LQH3±PLO%RG\>3',3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 A L c A1 b1 b e eB 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RSWR6HDWLQJ3ODQH $ ± ± 0ROGHG3DFNDJH7KLFNQHVV $ %DVHWR6HDWLQJ3ODQH $ ± ± 6KRXOGHUWR6KRXOGHU:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' 7LSWR6HDWLQJ3ODQH / /HDG7KLFNQHVV F E E H% ± ± 8SSHU/HDG:LGWK /RZHU/HDG:LGWK 2YHUDOO5RZ6SDFLQJ %6& 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 6LJQLILFDQW&KDUDFWHULVWLF 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2011-2012 Microchip Technology Inc. DS75018C-page 321 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS75018C-page 322 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2012 Microchip Technology Inc. DS75018C-page 323 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS75018C-page 324 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 /HDG3ODVWLF6KULQN6PDOO2XWOLQH66±PP%RG\>6623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV L 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ ± %6& ± 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / )RRWSULQW / 5() /HDG7KLFNQHVV F ± )RRW$QJOH /HDG:LGWK E ± 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2011-2012 Microchip Technology Inc. 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DS75018C-page 327 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS75018C-page 328 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2012 Microchip Technology Inc. DS75018C-page 329 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS75018C-page 330 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2012 Microchip Technology Inc. DS75018C-page 331 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 /HDG6NLQQ\3ODVWLF'XDO,Q/LQH63±PLO%RG\>63',3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RSWR6HDWLQJ3ODQH $ ± ± 0ROGHG3DFNDJH7KLFNQHVV $ %DVHWR6HDWLQJ3ODQH $ ± ± 6KRXOGHUWR6KRXOGHU:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' 7LSWR6HDWLQJ3ODQH / /HDG7KLFNQHVV F E E H% ± ± 8SSHU/HDG:LGWK /RZHU/HDG:LGWK 2YHUDOO5RZ6SDFLQJ %6& 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 6LJQLILFDQW&KDUDFWHULVWLF 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS75018C-page 332 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. DS75018C-page 333 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 334 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 /HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH00±[[PP%RG\>4)16@ ZLWKPP&RQWDFW/HQJWK 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 2011-2012 Microchip Technology Inc. DS75018C-page 335 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 336 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2011-2012 Microchip Technology Inc. DS75018C-page 337 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 338 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 APPENDIX A: REVISION HISTORY This is the initial released version of this document. Where applicable, new sections were added to each peripheral chapter that provide information and links to related resources, as well as helpful tips. For examples, see Section 18.1 “UART Helpful Tips” and Section 18.1 “UART Helpful Tips”. Revision B (February 2012) The data sheet status was updated from Advance Information to Preliminary. This revision includes formatting changes and minor typographical updates throughout the data sheet text. In addition, all occurrences to the package known as TLA were updated to VTLA. Revision A (July 2011) All other major changes are referenced by their respective section in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, ADC and Comparators” The previous content was reorganized and is now presented as the first page of the data sheet. Section 2.0 “Guidelines for Getting Started with 16-Bit Digital Signal Controllers” Updated the Recommended Minimum Connection diagram (see Figure 2-1). Section 4.0 “Memory Organization” Updated the Program Memory Map (see Figure 4-1). Relocated the Referenced Sources content, which was previously presented in Section 1.0 “Device Overview”. Updated bits 10-8 in IPC27 of the Interrupt Controller Register Map for dsPIC33FJ06GS001 Devices (see Table 4-4). Renamed the CHOPCLK<6:0> bits in the CHOP register to: CHOP<6:0> in the High-Speed PWM Register Map (see Table 4-12). Removed RPINR11 from the Peripheral Pin Select Input Register Map for the dsPIC33FJ06GS001 Device (see Table 4-24). Added the REFOMD bit to PMD4 in the PMD Register Map for the dsPIC33FJ06GS001 device (see Table 4-34). Section 21.0 “Constant Current Added the Current Source Calibration bits (ISRCCAL<5:0>) to the Current Source” Source Control register (see Register 21-1). Section 22.0 “Special Features” Added the Constant Current Source Calibration Register (see Register 22-1). Section 25.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings(1). Added Note 1 to the Operating MIPS vs. Voltage specification (see Table 25-1). Updated all DC Characteristics: I/O Pin Output Specifications (see Table 25-10). Updated the typical value for Parameters F20a and F20b in the Internal FRC Accuracy specification (see Table 25-19). Updated the minimum and maximum values for Parameter TA20, and the minimum value for Parameter TA11 in the Timer1 External Clock Timing Requirements (see Table 25-23). Updated the OC/PWM Module Timing Characteristics diagram (see Figure 25-8). Updated the minimum and maximum values for the Simple OC/PWM Mode Timing Requirements (see Table 25-27). Added Note 4 and Note 5 to the 10-Bit, High-Speed ADC Module Specifications (see Table 25-39). Section 26.0 “DC and AC Added new chapter. Device Characteristics Graphs” 2011-2012 Microchip Technology Inc. DS75018C-page 339 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Revision C (August 2012) This revision includes minor typographical updates and content corrections. Major changes include new figures in Section 26.0 “DC and AC Device Characteristics Graphs”, updated values in Table 25-39 in Section 25.0 “Electrical Characteristics” and updated package drawings in Section 27.0 “Packaging Information”. DS75018C-page 340 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 INDEX A C AC Characteristics ............................................................ 282 Internal LPRC Accuracy............................................ 285 Internal RC Accuracy ................................................ 285 Load Conditions ........................................................ 282 Temperature and Voltage Specifications .................. 282 Alternate Interrupt Vector Table (AIVT) .............................. 87 Arithmetic Logic Unit (ALU)................................................. 31 Assembler MPASM Assembler................................................... 268 Auxiliary Clock Generation................................................ 125 C Compilers MPLAB C18.............................................................. 268 Capacitor on Internal Voltage Regulator (VCAP)................. 18 Clock Switching ................................................................ 134 Enabling.................................................................... 134 Sequence ................................................................. 134 Code Examples Port Write/Read ........................................................ 147 PWRSAV Instruction Syntax .................................... 137 Code Protection ................................................................ 251 Configuration Bits ............................................................. 251 Description................................................................ 254 Configuring Analog Port Pins............................................ 147 Constant Current Source Description................................................................ 249 Features ................................................................... 249 CPU Barrel Shifter............................................................... 35 Control Registers........................................................ 28 Data Addressing Overview ......................................... 25 DSP Engine Overview ................................................ 25 MCU Special Features ............................................... 26 Special Features....................................................... 251 CPU Clocking System ...................................................... 124 PLL Configuration..................................................... 125 Selection................................................................... 124 Sources .................................................................... 124 Customer Change Notification Service............................. 346 Customer Notification Service .......................................... 346 Customer Support............................................................. 346 B Bit-Reversed Addressing .................................................... 69 Example ...................................................................... 70 Implementation ........................................................... 69 Sequence Table (16-Entry)......................................... 70 Block Diagrams 16-Bit Timer1 Module................................................ 173 Boost Converter Implementation ................................ 21 Connections for On-Chip Voltage Regulator............. 256 Constant Current Source .......................................... 249 CPU Core.................................................................... 26 Digital PFC.................................................................. 21 DSP Engine ................................................................ 32 dsPIC33FJ06GS001 Device ADC ............................ 226 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 ........................................... 14 dsPIC33FJ06GS101A Device ADC .......................... 227 dsPIC33FJ06GS102A Device ADC .......................... 228 dsPIC33FJ06GS202A Device ADC .......................... 229 dsPIC33FJ09GS302 Device ADC ............................ 230 High-Speed Analog Comparator............................... 243 Hysteresis Control..................................................... 245 I2C............................................................................. 212 Input Capture ............................................................ 177 Interleaved PFC .......................................................... 22 MCLR Pin Connections............................................... 18 Multiplexing of Remappable Output for RPn............. 150 Oscillator System ...................................................... 123 Output Compare ....................................................... 179 Partitioned Output Pair, Complementary PWM Mode ....................................................... 186 Phase-Shifted Full-Bridge Converter .......................... 23 PLL............................................................................ 125 Recommended Minimum Connection......................... 18 Remappable MUX Input for U1RX............................ 148 Reset System.............................................................. 79 Shared Port Structure ............................................... 146 Simplified Conceptual High-Speed PWM ................. 185 Single-Phase Synchronous Buck Converter............... 22 SPI ............................................................................ 205 Type B Timer2 .......................................................... 175 UART ........................................................................ 219 Watchdog Timer (WDT) ............................................ 257 Brown-out Reset (BOR) ............................................ 251, 256 2011-2012 Microchip Technology Inc. D DAC .................................................................................. 244 Buffer Gain ............................................................... 244 Output Range ........................................................... 245 Data Accumulators and Adder/Subtracter .......................... 33 Data Space Write Saturation ...................................... 35 Overflow and Saturation ............................................. 33 Round Logic ............................................................... 34 Write Back .................................................................. 34 Data Address Space........................................................... 39 Alignment.................................................................... 39 Memory Map for Devices with 1 Kbyte of RAM .......... 41 Memory Map for Devices with 256 Bytes of RAM ...... 40 Near Data Space ........................................................ 39 Software Stack ........................................................... 66 Width .......................................................................... 39 X and Y Data .............................................................. 42 DC and AC Characteristics Graphs and Tables ................................................... 315 DC Characteristics Doze Current (IDOZE)................................................ 277 I/O Pin Input Specifications ...................................... 278 I/O Pin Output Specifications.................................... 280 Idle Current (IIDLE) .................................................... 275 Operating Current (IDD) ............................................ 274 Operating MIPS vs. Voltage ..................................... 272 Power-Down Current (IPD)........................................ 276 Program Memory...................................................... 281 Temperature and Voltage Specifications.................. 273 DS75018C-page 341 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DC Specifications DAC Output (DACOUT Pin) ...................................... 312 Development Support ....................................................... 267 Doze Mode........................................................................ 138 DSC Guidelines................................................................... 17 Basic Connection Requirements................................. 17 Decoupling Capacitors ................................................ 17 DSP Engine......................................................................... 31 Multiplier...................................................................... 33 E Electrical Characteristics................................................... 271 Absolute Maximum Ratings ...................................... 271 Equations Device Operating Frequency .................................... 124 FOSC Calculation....................................................... 125 Maximum Page Erase Time........................................ 76 Minimum Page Erase Time......................................... 76 XT with PLL Mode Example...................................... 125 Errata .................................................................................. 11 F Fail-Safe Clock Monitor (FSCM) ....................................... 135 Flash Program Memory....................................................... 75 Control Registers ........................................................ 76 Operations .................................................................. 76 Table Instructions........................................................ 75 Flexible Configuration ....................................................... 251 H High-Speed 10-Bit ADC .................................................... 225 Description ................................................................ 225 Features .................................................................... 225 Functionality .............................................................. 225 High-Speed Analog Comparator ....................................... 243 Applications............................................................... 244 Control Registers ...................................................... 245 DAC .......................................................................... 244 Digital Logic .............................................................. 244 Hysteresis ................................................................. 245 Input Range .............................................................. 244 Interaction with I/O Buffers........................................ 245 High-Speed PWM ............................................................. 183 Control Registers ...................................................... 186 I I/O Ports ............................................................................ 145 Helpful Tips ............................................................... 152 Parallel I/O (PIO)....................................................... 145 Resources ................................................................. 152 Write/Read Timing .................................................... 147 I2 C Operating Modes ...................................................... 211 Registers ................................................................... 213 In-Circuit Debugger ........................................................... 258 In-Circuit Emulation........................................................... 251 In-Circuit Serial Programming (ICSP) ....................... 251, 258 Analog, Digital Pins Configuration .............................. 20 Pins ............................................................................. 19 Input Capture .................................................................... 177 Input Change Notification.................................................. 147 DS75018C-page 342 Instruction Addressing Modes ............................................ 66 File Register Instructions ............................................ 66 Fundamental Modes Supported ................................. 67 MAC Instructions ........................................................ 67 MCU Instructions ........................................................ 66 Move and Accumulator Instructions............................ 67 Other Instructions ....................................................... 67 Instruction Set Overview................................................................... 262 Summary .................................................................. 259 Instruction-Based Power-Saving Modes........................... 137 Idle ............................................................................ 138 Sleep ........................................................................ 137 Interfacing Program and Data Memory Spaces.................. 71 Internal RC Oscillator Use with WDT........................................................... 257 Internet Address ............................................................... 346 Interrupt Control and Status Registers ............................... 90 IECx ............................................................................ 90 IFSx ............................................................................ 90 INTCON1 .................................................................... 90 INTCON2 .................................................................... 90 INTTREG .................................................................... 90 IPCx ............................................................................ 90 Interrupt Setup Procedures............................................... 122 Initialization ............................................................... 122 Interrupt Disable ....................................................... 122 Interrupt Service Routine .......................................... 122 Trap Service Routine ................................................ 122 Interrupt Vector Table (IVT) ................................................ 87 Interrupts Coincident with Power Save Instructions ......... 138 J JTAG Boundary Scan Interface ........................................ 251 JTAG Interface.................................................................. 258 L LEBCONx (PWMx Leading-Edge Blanking Control) ........ 202 M Master Clear (MCLR).......................................................... 18 Memory Organization ......................................................... 37 Microchip Internet Web Site.............................................. 346 Modulo Addressing ............................................................. 68 Applicability................................................................. 69 Operation Example ..................................................... 68 Start and End Address ............................................... 68 W Address Register Selection .................................... 68 MPLAB ASM30 Assembler, Linker, Librarian ................... 268 MPLAB Integrated Development Environment Software .............................................. 267 MPLAB PM3 Device Programmer .................................... 270 MPLAB REAL ICE In-Circuit Emulator System ................ 269 MPLINK Object Linker/MPLIB Object Librarian ................ 268 O Open-Drain Configuration................................................. 147 Oscillator External Pins .............................................................. 19 Value Conditions on Start-up...................................... 20 Oscillator Configuration .................................................... 123 Output Compare ............................................................... 179 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 P Packaging ......................................................................... 319 Details ....................................................................... 321 Marking ..................................................................... 319 Peripheral Module Disable (PMD) .................................... 138 Peripheral Pin Select (PPS) .............................................. 148 Registers................................................................... 153 Pinout I/O Descriptions ....................................................... 15 Power-on Reset (POR) ....................................................... 84 Power-Saving Features .................................................... 137 Clock Frequency and Switching................................ 137 Program Address Space ..................................................... 37 Construction................................................................ 71 Data Access from Program Memory Using Program Space Visibility ..................................... 74 Data Access from Program Memory Using Table Instructions ............................................... 73 Data Access from, Address Generation...................... 72 Memory Maps ............................................................. 37 Table Read Instructions TBLRDH ............................................................. 73 TBLRDL .............................................................. 73 Visibility Operation ...................................................... 74 Program Memory Interrupt Vector ........................................................... 38 Organization................................................................ 38 Reset Vector ............................................................... 38 Pseudo-Random Generator .............................................. 135 R Reader Response ............................................................. 347 Reference Clock Generation............................................. 125 Register Maps Configuration Flash Bytes (dsPIC33FJ06GS001/101A/X02A) ................... 252 Configuration Flash Bytes (dsPIC33FJ09GS302) ...................................... 252 Registers ACLKCON (Auxiliary Clock Divisor Control) ............. 131 ADCON (ADC Control) ............................................. 231 ADCPC0 (ADC Convert Pair Control 0).................... 236 ADCPC1 (ADC Convert Pair Control 1).................... 238 ADCPC3 (ADC Convert Pair Control 3).................... 240 ADPCFG (ADC Port Configuration) .......................... 235 ADSTAT (ADC Status).............................................. 233 ALTDTRx (PWMx Alternate Dead-Time) .................. 195 AUXCONx (PWM Auxiliary Control) ......................... 204 CHOP (PWM Chop Clock Generator)....................... 203 CLKDIV (Clock Divisor)............................................. 128 CMPCONx (Comparator Control x) .......................... 246 CMPDACx (Comparator DAC Control x) .................. 248 Constant Current Source Calibration ........................ 253 CORCON (Core Control) ...................................... 30, 91 DTRx (PWMx Dead-Time) ........................................ 195 FCLCONx (PWMx Fault Current-Limit Control) ........ 199 I2C1CON (I2C1 Control)........................................... 213 I2C1MSK (I2C1 Slave Mode Address Mask)............ 217 I2C1STAT (I2C1 Status) ........................................... 215 IC1CON (Input Capture 1 Control)............................ 178 IEC0 (Interrupt Enable Control 0) ............................. 101 IEC1 (Interrupt Enable Control 1) ............................. 102 IEC3 (Interrupt Enable Control 3) ............................. 103 IEC4 (Interrupt Enable Control 4) ............................. 103 IEC5 (Interrupt Enable Control 5) ............................. 104 IEC6 (Interrupt Enable Control 6) ............................. 105 IEC7 (Interrupt Enable Control 7) ............................. 106 2011-2012 Microchip Technology Inc. IFS0 (Interrupt Flag Status 0) ..................................... 95 IFS1 (Interrupt Flag Status 1) ..................................... 96 IFS3 (Interrupt Flag Status 3) ..................................... 97 IFS4 (Interrupt Flag Status 4) ..................................... 97 IFS5 (Interrupt Flag Status 5) ..................................... 98 IFS6 (Interrupt Flag Status 6) ..................................... 99 IFS7 (Interrupt Flag Status 7) ................................... 100 INTCON1 (Interrupt Control 1) ................................... 92 INTCON2 (Interrupt Control 2) ................................... 94 INTTREG (Interrupt Control and Status) .................. 121 IOCONx (PWMx I/O Control).................................... 197 IPC0 (Interrupt Priority Control 0) ............................. 107 IPC1 (Interrupt Priority Control 1) ............................. 108 IPC14 (Interrupt Priority Control 14) ......................... 113 IPC16 (Interrupt Priority Control 16) ......................... 113 IPC2 (Interrupt Priority Control 2) ............................. 109 IPC20 (Interrupt Priority Control 20) ......................... 114 IPC23 (Interrupt Priority Control 23) ......................... 115 IPC24 (Interrupt Priority Control 24) ......................... 116 IPC25 (Interrupt Priority Control 25) ......................... 117 IPC27 (Interrupt Priority Control 27) ......................... 118 IPC28 (Interrupt Priority Control 28) ......................... 119 IPC29 (Interrupt Priority Control 29) ......................... 120 IPC3 (Interrupt Priority Control 3) ............................. 110 IPC4 (Interrupt Priority Control 4) ............................. 111 IPC5 (Interrupt Priority Control 5) ............................. 112 IPC7 (Interrupt Priority Control 7) ............................. 112 ISRCCON (Constant Current Source Control) ......... 250 LFSR (Linear Feedback Shift) .................................. 133 MDC (PWM Master Duty Cycle)............................... 189 NVMCON (Flash Memory Control)............................. 77 NVMKEY (Nonvolatile Memory Key) .......................... 78 OC1CON (Output Compare 1 Control)..................... 181 OSCCON (Oscillator Control)................................... 126 OSCTUN (Oscillator Tuning) .................................... 130 PDCx (PWMx Generator Duty Cycle)....................... 192 PHASEx (PWMx Primary Phase Shift)..................... 193 PLLFBD (PLL Feedback Divisor) ............................. 129 PMD1 (Peripheral Module Disable Control 1) .......... 139 PMD2 (Peripheral Module Disable Control 2) .......... 140 PMD3 (Peripheral Module Disable Control 3) .......... 141 PMD4 (Peripheral Module Disable Control 4) .......... 141 PMD6 (Peripheral Module Disable Control 6) .......... 142 PMD7 (Peripheral Module Disable Control 7) .......... 143 PMD8 (Peripheral Module Disable Control 8) .......... 144 PTCON (PWM Time Base Control) .......................... 187 PTCON2 (PWM Clock Divider Select 2)................... 188 PTPER (PWM Master Time Base) ........................... 188 PWMCAPx (Primary PWMx Time Base Capture) .... 203 PWMCONx (PWMx Control) .................................... 190 RCON (Reset Control)................................................ 80 REFOCON (Reference Oscillator Control) ............... 132 RPINR0 (Peripheral Pin Select Input 0) ................... 153 RPINR1 (Peripheral Pin Select Input 1) ................... 154 RPINR11 (Peripheral Pin Select Input 11) ............... 158 RPINR18 (Peripheral Pin Select Input 18) ............... 159 RPINR2 (Peripheral Pin Select Input 2) ................... 155 RPINR20 (Peripheral Pin Select Input 20) ............... 160 RPINR21 (Peripheral Pin Select Input 21) ............... 161 RPINR29 (Peripheral Pin Select Input 29) ............... 162 RPINR3 (Peripheral Pin Select Input 3) ................... 156 RPINR30 (Peripheral Pin Select Input 30) ............... 163 RPINR31 (Peripheral Pin Select Input 31) ............... 164 RPINR32 (Peripheral Pin Select Input 32) ............... 165 RPINR33 (Peripheral Pin Select Input 33) ............... 166 RPINR34 (Peripheral Pin Select Input 34) ............... 167 DS75018C-page 343 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 RPINR7 (Peripheral Pin Select Input 7) .................... 157 RPOR0 (Peripheral Pin Select Output 0) .................. 168 RPOR1 (Peripheral Pin Select Output 1) .................. 168 RPOR16 (Peripheral Pin Select Output 16) .............. 172 RPOR17 (Peripheral Pin Select Output 17) .............. 172 RPOR2 (Peripheral Pin Select Output 2) .................. 169 RPOR3 (Peripheral Pin Select Output 3) .................. 169 RPOR4 (Peripheral Pin Select Output 4) .................. 170 RPOR5 (Peripheral Pin Select Output 5) .................. 170 RPOR6 (Peripheral Pin Select Output 6) .................. 171 RPOR7 (Peripheral Pin Select Output 7) .................. 171 SDCx (PWMx Secondary Duty Cycle) ...................... 192 SEVTCMP (PWM Special Event Compare).............. 189 SPHASEx (PWMx Secondary Phase Shift) .............. 194 SPIxCON1 (SPIx Control 1) ...................................... 208 SPIxCON2 (SPIx Control 2) ...................................... 210 SPIxSTAT (SPIx Status and Control) ....................... 207 SR (CPU STATUS) ..................................................... 91 SR (CPU Status) ......................................................... 28 STRIGx (PWMx Secondary Trigger Compare Value)................................................ 201 T1CON (Timer1 Control)........................................... 174 T2CON (Timer2 Control)........................................... 176 TRGCONx (PWMx Trigger Control).......................... 196 TRIGx (PWMx Primary Trigger Compare Value) ...... 201 U1MODE (UART1 Mode) ......................................... 221 U1STA (UART1 Status and Control) ........................ 223 Reset Brown-out Reset (BOR) ........................................ 79, 84 Configuration Mismatch Reset (CM) ........................... 79 Illegal Condition Device Reset (IOPUWR) .................. 79 Illegal Opcode ..................................................... 79 Security ............................................................... 79 Uninitialized W Register...................................... 79 Illegal Device Reset .................................................... 85 Illegal Opcode ............................................................. 85 Master Clear Reset (MCLR) ....................................... 79 Power-on Reset (POR) ............................................... 79 Power-up Timer Reset (PWRT) .................................. 84 Software RESET Instruction ....................................... 79 System Reset Cold Reset .......................................................... 82 Warm Reset ........................................................ 82 Trap Conflict................................................................ 85 Trap Conflict Reset (TRAPR)...................................... 79 Uninitialized W Register .............................................. 85 Watchdog Timer Out Reset (WDTO) .......................... 79 Reset Sequence.................................................................. 87 Revision History ................................................................ 339 S Serial Peripheral Interface (SPI) ....................................... 205 SFR Maps Change Notification for dsPIC33FJ06GS001, dsPIC33FJ06GS101A...... 45 Change Notification for dsPIC33FJ06GS102A, dsPIC33FJ06GS202A, dsPIC33FJ09GS302...... 45 Constant Current Source ............................................ 56 CPU Core.................................................................... 43 High-Speed 10-Bit ADC for dsPIC33FJ06GS001, dsPIC33FJ06GS101A......................................... 56 High-Speed 10-Bit ADC for dsPIC33FJ06GS102A, dsPIC33FJ06GS202A......................................... 57 High-Speed 10-Bit ADC for dsPIC33FJ09GS302 ....... 58 High-Speed PWM ....................................................... 52 High-Speed PWM Generator 1 ................................... 52 DS75018C-page 344 High-Speed PWM Generator 2 for dsPIC33FJ06GS102A, dsPIC33FJ06GS202A, dsPIC33FJ09GS302...............................................53 High-Speed PWM Generator 4 for dsPIC33FJ06GS001, dsPIC33FJ06GS101A, dsPIC33FJ09GS302 ........54 I2C1 .................................................................................55 Input Capture for dsPIC33FJ06GS202A, dsPIC33FJ09GS302...............................................51 Interrupt Controller for dsPIC33FJ06GS001 ..................46 Interrupt Controller for dsPIC33FJ06GS002A................48 Interrupt Controller for dsPIC33FJ06GS101A................47 Interrupt Controller for dsPIC33FJ06GS202A................49 Interrupt Controller for dsPIC33FJ09GS302 ..................50 NVM.................................................................................63 Output Compare for dsPIC33FJ06GS101A, dsPIC33FJ06GS102A, dsPIC33FJ06GS202A, dsPIC33FJ09GS302...............................................51 Peripheral Pin Select Input for dsPIC33FJ06GS001 .....59 Peripheral Pin Select Input for dsPIC33FJ06GS101A, dsPIC33FJ06GS102A ............................................59 Peripheral Pin Select Input for dsPIC33FJ06GS202A, dsPIC33FJ09GS302...............................................60 Peripheral Pin Select Output for dsPIC33FJ06GS001, dsPIC33FJ06GS101A ............................................60 Peripheral Pin Select Output for dsPIC33FJ06GS102A, dsPIC33FJ06GS202A, dsPIC33FJ09GS302 ........61 PMD for dsPIC33FJ06GS001..................................... 64 PMD for dsPIC33FJ06GS101A .................................. 64 PMD for dsPIC33FJ06GS102A .................................. 64 PMD for dsPIC33FJ06GS202A .................................. 65 PMD for dsPIC33FJ09GS302..................................... 65 PORTA ....................................................................... 62 PORTB for dsPIC33FJ06GS001, dsPIC33FJ06GS101A ............................................62 PORTB for dsPIC33FJ06GS102A, dsPIC33FJ06GS202A, dsPIC33FJ09GS302 ........62 SPI1 for dsPIC33FJ06GS101A, dsPIC33FJ06GS102A, dsPIC33FJ09GS202A, dsPIC33FJ09GS302 ........55 System Control ................................................................63 Timers..............................................................................51 UART1 for dsPIC33FJ06GS101A, dsPIC33FJ06GS102A, dsPIC33FJ06GS202A, dsPIC33FJ09GS302 ........................................... 55 Software RESET Instruction (SWR) ................................... 85 Software Simulator (MPLAB SIM) .................................... 269 Software Stack Pointer, Frame Pointer CALL Stack Frame ..................................................... 66 Symbols Used in Opcode Descriptions ............................ 260 T Thermal Packaging Characteristics .................................. 272 Timer1............................................................................... 173 Timer2............................................................................... 175 Timing Diagrams Analog-to-Digital Conversion per Input..................... 310 Brown-out Situations................................................... 84 External Clock........................................................... 283 High-Speed PWM ..................................................... 292 High-Speed PWM Fault ............................................ 292 I/O ............................................................................. 286 I2C1 Bus Data (Master Mode) .................................. 305 I2C1 Bus Data (Slave Mode) .................................... 307 I2C1 Bus Start/Stop Bits (Master Mode)................... 305 I2C1 Bus Start/Stop Bits (Slave Mode)..................... 307 Input Capture (CAP1) ............................................... 290 OC/PWM................................................................... 291 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Output Compare (OC1)............................................. 290 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ............................... 287 SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) ........................................... 296 SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) ........................................... 295 SPIx Master Mode (Half-Duplex, Transmit Only, CKE = 0) ........................................................... 293 SPIx Master Mode (Half-Duplex, Transmit Only, CKE = 1) ........................................................... 294 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) ........................................... 303 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) ........................................... 301 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) ........................................... 297 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) ........................................... 299 System Reset.............................................................. 83 Timer1, Timer2 External Clock ................................. 288 Timing Specifications 10-Bit High-Speed ADC ............................................ 309 10-Bit High-Speed ADC Requirements..................... 310 Auxiliary PLL Clock ................................................... 284 Capacitive Loading Requirements on Output Pins ....................................................... 282 Constant Current Source .......................................... 313 DAC .......................................................................... 311 DAC Gain Stage to Comparator ............................... 312 External Clock Requirements ................................... 283 High-Speed ADC Comparator .................................. 311 High-Speed PWM Requirements.............................. 292 I/O Requirements...................................................... 286 I2C1 Bus Data Requirements (Master Mode)........... 306 I2C1 Bus Data Requirements (Slave Mode)............. 308 Input Capture Requirements..................................... 290 Output Compare Requirements ................................ 290 PLL Clock.................................................................. 284 2011-2012 Microchip Technology Inc. Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements......................................... 287 Simple OC/PWM Mode Requirements ..................... 291 SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Requirements.................... 296 SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Requirements.................... 295 SPIx Master Mode (Half-Duplex, Transmit Only) Requirements ................................................... 294 SPIx Maximum Data Clock Rate Summary.............. 293 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Requirements.................... 304 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Requirements.................... 302 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Requirements.................... 298 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Requirements.................... 300 Timer1 External Clock Requirements....................... 288 Timer2 External Clock Requirements....................... 289 U Universal Asynchronous Receiver Transmitter (UART) .................................................. 219 Helpful Tips............................................................... 220 Resources ................................................................ 220 Using the RCON Status Bits............................................... 86 V Voltage Regulator (On-Chip) ............................................ 256 W Watchdog Timer (WDT)............................................ 251, 257 Watchdog Timer Time-out Reset (WDTO) ......................... 85 WWW Address ................................................................. 346 WWW, On-Line Support ..................................................... 11 DS75018C-page 345 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 346 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. 2011-2012 Microchip Technology Inc. DS75018C-page 347 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Questions: Literature Number: DS75018C 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS75018C-page 348 2011-2012 Microchip Technology Inc. dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 06 GS0 01 T - E / SP - XXX Examples: a) dsPIC33FJ06GS001-I/SS: SMPS dsPIC33, 6-Kbyte program memory, 20-pin, Industrial temp.,SSOP package. Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: GS0 GS1 GS2 GS3 = = = = Switch Mode Power Supply (SMPS) family Switch Mode Power Supply (SMPS) family Switch Mode Power Supply (SMPS) family Switch Mode Power Supply (SMPS) family Pin Count: 01 02 = = 18-pin, 20-pin 28-pin, 36-pin Temperature Range: I E = = -40C to+85C (Industrial) -40C to+125C (Extended) Package: P SO SS SP MM TL = = = = = = Plastic Dual In-line – 300 mil (PDIP) Plastic Small Outline – Wide – 7.50 mm body (SOIC) Plastic Shrink Small Outline – 5.30 mm body (SSOP) Skinny Plastic Dual In-Line – 300 mil body (SPDIP) Plastic Quad Flat, No Lead Package – 6x6x0.9 mm body (QFN-S) Very Thin Leadless Array – 5x5x0.9 mm body (VTLA) 2011-2012 Microchip Technology Inc. DS75018C-page 349 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 350 2011-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-494-7 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2011-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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