CYPRESS CY62147EV30LL

CY62147EV30 MoBL®
4-Mbit (256K x 16) Static RAM
■
Very high speed: 45 ns
■
Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (IO0 through IO15) are placed
in a high impedance state when:
■
Wide voltage range: 2.20V to 3.60V
■
Deselected (CE HIGH)
■
Pin compatible with CY62147DV30
■
Outputs are disabled (OE HIGH)
■
Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 7 μA (Industrial)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE [1] and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A17).
■
Available in Pb-free 48-ball VFBGA (single/dual CE option) and
44-pin TSOPII packages
■
Byte power down feature
Features
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the Truth Table on page 9 for a
complete description of read and write modes.
Functional Description
The CY62147EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
Logic Block Diagram
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
256K x 16
RAM Array
IO0–IO7
IO8–IO15
A17
A15
A16
A13
A14
CIRCUIT
A11
CE
BHE
BLE
POWER DOWN
A12
COLUMN DECODER
BHE
WE
[1]
CE
OE
BLE
Note
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
Cypress Semiconductor Corporation
Document #: 38-05440 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 31, 2009
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CY62147EV30 MoBL®
Product Portfolio
Power Dissipation
Product
Range
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
Typ[2]
Min
CY62147EV30LL
Max
Standby ISB2 (μA)
f = fmax
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
Ind’l/Auto-A
2.2
3.0
3.6
45 ns
2
2.5
15
20
1
7
Auto-E
2.2
3.0
3.6
55 ns
2
3
15
25
1
20
Pin Configuration
Figure 1. 48-Ball VFBGA (Single Chip Enable) [3, 4]
Figure 2. 48-Ball VFBGA (Dual Chip Enable)[3, 4]
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
CE2
A
IO0
B
IO8
BHE
A3
A4
CE1
IO0
B
IO1
IO2
C
IO9
IO10
A5
A6
IO1
IO2
C
A7
IO3
VCC
D
VSS
IO11
A17
A7
IO3
VCC
D
NC
A16
IO4
VSS
E
VCC
IO12
NC
A16
IO4
VSS
E
IO13
A14
A15
IO5
IO6
F
IO14
IO13
A14
A15
IO5
IO6
F
IO15
NC
A12
A13
WE
IO7
G
IO15
NC
A12
A13
WE
IO7
G
NC
A8
A9
A10
A11
NC
H
NC
A8
A9
A10
A11
NC
H
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
IO8
BHE
A3
A4
CE
IO9
IO10
A5
A6
VSS
IO11
A17
VCC
IO12
IO14
Figure 3. 44-Pin TSOP II [3]
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
NC
A8
A9
A10
A11
A12
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°.
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
Document #: 38-05440 Rev. *G
Page 2 of 13
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CY62147EV30 MoBL®
DC Input Voltage [5, 6] ............ –0.3V to 3.9V (VCCmax + 0.3V)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ............................. –0.3V to + 3.9V (VCCmax + 0.3V)
DC Voltage Applied to Outputs
in High-Z State [5, 6] ............... –0.3V to 3.9V (VCCmax + 0.3V)
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current ..................................................... >200 mA
Operating Range
Ambient
Temperature
VCC [7]
Ind’l/Auto-A –40°C to +85°C
2.2V to
3.6V
Device
Range
CY62147EV30LL
Auto-E
–40°C to +125°C
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
Description
45 ns (Ind’l/Auto-A)
Test Conditions
Output HIGH
Voltage
Output LOW
Voltage
Min
Typ
[2]
Max
55 ns (Auto-E)
Typ [2]
Min
Unit
Max
IOH = –0.1 mA
2.0
2.0
V
IOH = –1.0 mA, VCC > 2.70V
2.4
2.4
V
IOL = 0.1 mA
0.4
0.4
V
IOL = 2.1 mA, VCC = 2.70V
0.4
0.4
V
1.8
VCC + 0.3
V
VIH
Input HIGH
Voltage
VCC = 2.2V to 2.7V
1.8
VCC + 0.3
VIL
Input LOW
Voltage
VCC= 2.7V to 3.6V
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VCC = 2.2V to 2.7V
–0.3
0.6
–0.3
0.6
V
IIX
Input Leakage
Current
VCC= 2.7V to 3.6V
GND < VI < VCC
–0.3
0.8
–0.3
0.8
V
–1
+1
–4
+4
μA
IOZ
Output Leakage GND < VO < VCC, Output Disabled
Current
–1
+1
–4
+4
μA
ICC
VCC Operating
Supply Current
f = fmax = 1/tRC VCC = VCC(max)
IOUT = 0 mA
f = 1 MHz
CMOS levels
15
20
2
2.5
15
25
mA
2
3
ISB1
Automatic CE
Power Down
Current —
CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V, VIN < 0.2V
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
1
7
1
20
μA
ISB2 [8]
Automatic CE
Power Down
Current —
CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
1
7
1
20
μA
Capacitance
For all packages.[9]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
10
10
pF
pF
Notes
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.
8. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05440 Rev. *G
Page 3 of 13
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CY62147EV30 MoBL®
Thermal Resistance[9]
Parameter
Test Conditions
VFBGA
Package
TSOP II
Package
Unit
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
75
77
°C/W
10
13
°C/W
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Figure 4. AC Test Load and Waveforms
R1
VCC
OUTPUT
VCC
10%
GND
Rise Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.50V
3.0V
Unit
R1
16667
1103
Ω
R2
15385
1554
Ω
RTH
8000
645
Ω
VTH
1.20
1.75
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for Data Retention
ICCDR[8]
Data Retention Current
tCDR
tR
[9]
Conditions
Min
Max Unit
1.5
VCC= 1.5V, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Ind’l/Auto-A
Operation Recovery Time
V
0.8
Auto-E
Chip Deselect to Data Retention Time
[10]
Typ [2]
7
μA
12
0
ns
tRC
ns
Figure 5. Data Retention Waveform[1, 11]
DATA RETENTION MODE
VCC
CE or
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
BHE.BLE
Notes
10. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
11. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05440 Rev. *G
Page 4 of 13
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CY62147EV30 MoBL®
Switching Characteristics
Over the Operating Range [12, 13]
45 ns (Ind’l/Auto-A)
Parameter
55 ns (Auto-E)
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
45
55
ns
tDOE
OE LOW to Data Valid
22
25
ns
tLZOE
OE LOW to LOW Z[14]
OE HIGH to High
tHZOE
CE LOW to Low
tLZCE
45
55
45
10
Z[14]
55
10
5
Z[14, 15]
10
ns
ns
5
18
Z[14, 15]
ns
ns
20
10
ns
ns
tHZCE
CE HIGH to High
tPU
CE LOW to Power Up
tPD
CE HIGH to Power Down
45
55
ns
tDBE
BLE/BHE LOW to Data Valid
45
55
ns
0
Z[14]
tLZBE
BLE/BHE LOW to Low
tHZBE
BLE/BHE HIGH to HIGH Z[14, 15]
Write
18
20
0
10
ns
10
18
ns
ns
20
ns
Cycle[16]
tWC
Write Cycle Time
45
55
ns
tSCE
CE LOW to Write End
35
40
ns
tAW
Address Setup to Write End
35
40
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Setup to Write Start
0
0
ns
tPWE
WE Pulse Width
35
40
ns
tBW
BLE/BHE LOW to Write End
35
40
ns
tSD
Data Setup to Write End
25
25
ns
tHD
Data Hold from Write End
0
0
ns
High-Z[14, 15]
tHZWE
WE LOW to
tLZWE
WE HIGH to Low-Z[14]
18
10
20
10
ns
ns
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Load and Waveforms on page 4.
13. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
16. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05440 Rev. *G
Page 5 of 13
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CY62147EV30 MoBL®
Switching Waveforms
Figure 6. Read Cycle No. 1 (Address Transition Controlled)[17, 18]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 7. Read Cycle No. 2 (OE Controlled)[1, 18, 19]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
ICC
50%
50%
ISB
Notes
17. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 38-05440 Rev. *G
Page 6 of 13
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CY62147EV30 MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (WE Controlled)[1, 16, 20, 21]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA IO
tSD
NOTE 22
tHD
DATAIN
tHZOE
Figure 9. Write Cycle No. 2 (CE Controlled)[1, 16, 20, 21]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
tHD
DATAIN
NOTE 22
tHZOE
Document #: 38-05440 Rev. *G
Page 7 of 13
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CY62147EV30 MoBL®
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW)[1, 21]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA IO
NOTE 22
tHD
DATAIN
tLZWE
tHZWE
Figure 11. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[1, 21]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA IO
NOTE 22
tSD
tHD
DATAIN
tLZWE
Notes
20. Data I/O is high impedance if OE = VIH.
21. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
22. During this period, the IOs are in output state. Do not apply input signals.
Document #: 38-05440 Rev. *G
Page 8 of 13
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CY62147EV30 MoBL®
Truth Table
1
CE[ ]
WE
OE
BHE
BLE
H
X
X
X
X
High Z
Deselect/Power Down
Standby (ISB)
L
X
X
H
H
High Z
Deselect/Power Down
Standby (ISB)
L
H
L
L
L
Data Out (IO0–IO15)
Read
Active (ICC)
L
H
L
H
L
Data Out (IO0–IO7);
IO8–IO15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data Out (IO8–IO15);
IO0–IO7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
L
X
H
L
Data In (IO0–IO7);
IO8–IO15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data In (IO8–IO15);
IO0–IO7 in High Z
Write
Active (ICC)
IOs
Mode
Power
Ordering Information
Speed
(ns)
45
55
Ordering Code
Package
Diagram
Package Type
CY62147EV30LL-45BVI
51-85150 48-Ball Very Fine Pitch Ball Grid Array [23]
CY62147EV30LL-45BVXI
51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free) [23]
CY62147EV30LL-45B2XI
51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free) [24]
CY62147EV30LL-45ZSXI
51-85087 44-Pin Thin Small Outline Package II (Pb-Free)
CY62147EV30LL-45BVXA
51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free) [23]
CY62147EV30LL-45ZSXA
51-85087 44-Pin Thin Small Outline Package II (Pb-Free)
CY62147EV30LL-55ZSXE
51-85087 44-Pin Thin Small Outline Package II (Pb-Free)
Operating
Range
Industrial
Automotive-A
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Notes
23. This BGA package is offered with single chip enable.
24. This BGA package is offered with dual chip enable.
Document #: 38-05440 Rev. *G
Page 9 of 13
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CY62147EV30 MoBL®
Package Diagrams
Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
0.55 MAX.
6.00±0.10
0.10 C
0.21±0.05
0.25 C
B
0.15(4X)
Document #: 38-05440 Rev. *G
1.00 MAX
0.26 MAX.
SEATING PLANE
C
51-85150-*D
Page 10 of 13
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CY62147EV30 MoBL®
Package Diagrams (continued)
Figure 13. 44-Pin TSOP II, 51-85087
51-85087-*A
Document #: 38-05440 Rev. *G
Page 11 of 13
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CY62147EV30 MoBL®
Document History Page
Document Title: CY62147EV30 MoBL® 4-Mbit (256K x 16) Static RAM
Document Number: 38-05440
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
201861
AJU
01/13/04
New Data Sheet
*A
247009
SYT
See ECN
Changed from Advanced Information to Preliminary
Moved Product Portfolio to Page 2
Changed Vcc stabilization time in footnote #8 from 100 μs to 200 μs
Removed Footnote #15(tLZBE) from Previous Revision
Changed ICCDR from 2.0 μA to 2.5 μA
Changed typo in Data Retention Characteristics(tR) from 100 μs to tRC ns
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to
18 ns for 45 ns Speed Bin
Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns
for 45 ns Speed Bin
Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
Speed Bin
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed Ordering Information to include Pb-Free Packages
*B
414807
ZSD
See ECN
Changed from Preliminary information to Final
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62147EV30
Changed ball E3 from DNU to NC.
Removed redundant foot note on DNU.
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ values from 0.7 μA to 1 μA and Max values from
2.5 μA to 7 μA.
Changed ICCDR from 2.5 μA to 7 μA.
Added ICCDR typical value.
Changed AC test load capacitance from 50 pF to 30 pF on Page #4.
Changed tLZOE from 3 ns to 5 ns
Changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns
Changed tHZCE from 22 ns to 18 ns
Changed tPWE from 30 ns to 35 ns.
Changed tSD from 22 ns to 25 ns.
Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering information table and replaced the Package Name column
with Package Diagram.
*C
464503
NXR
See ECN
Included Automotive Range in product offering
Updated the Ordering Information
*D
925501
VKN
See ECN
Added Preliminary Automotive-A information
Added footnote #9 related to ISB2 and ICCDR
Added footnote #14 related AC timing parameters
*E
1045701
VKN
See ECN
Converted Automotive-A and Automotive -E specs from preliminary to final
*F
2577505
VKN/PYRS
10/03/08
Added -45B2XI part (Dual CE option)
*G
2681901
VKN/PYRS
04/01/09
Added CY62147EV30LL-45ZSXA in the ordering information table
Document #: 38-05440 Rev. *G
Page 12 of 13
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CY62147EV30 MoBL®
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
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psoc.cypress.com/solutions
psoc.cypress.com/low-power
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wireless.cypress.com
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image.cypress.com
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psoc.cypress.com/can
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psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05440 Rev. *G
Revised March 31, 2009
Page 13 of 13
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trademarks of their respective holders.
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