PRELIMINARY TECHNICAL DATA Charge Pump Regulator & COM Driver for Color TFT Panel ADM8840 Preliminary Technical Data a FEATURES Programmable COM Driver to prevent Screen-Burn 3 Voltages (5.0V,15.0V,-15.0V) from one 3V Supply Power Efficiency optimised for use with TFT in mobile phones Low Quiescent Current Low Shutdown Current (<5uA) Shutdown Function FUNCTIONAL BLOCK DIAGRAM -15V VOLTAGE INVERTER C9 C4+ 0.22 F C4 0.22 F C4- +15V ADM8840 C2+ TRIPLE VOLTAGE TRIPLER C8 0.22 F C7 2.2 F C2 0.22 F C2C3+ C3 APPLICATIONS Handheld Instruments TFT LCD Panels Cellular Phones DOUBLE C3- OSCILLATOR TIMING GENERATOR 0.22 F 5VIN +5V 5VOUT SHDN SHUTDOWN CONTROL LDO VOLTAGE REGULATOR DISCHARGE VOUT C1+ C6 C1 3.3 F VOLTAGE DOUBLER CONTROL LOGIC C10 3.3 F C1- 4.7 F V CC C5+ VOLTAGE ADDER C5 3.3 F C5DAC1_IN DAC1_SD VREF GENERAL DESCRIPTION The ADM8840 combines a charge pump regulator and a Common Line (COM) driver in a single chip solution for use in TFT LCD’s. The device provides an LCD controller and grayscale DAC supply voltage of 5.0V (±2%), 2 gate drive voltages of +15V and -15V and a COM driver voltage. This COM Driver voltage alternates the polarity of the Common line voltage every line (or every frame) on the display in order to prevent screen-burn occuring over time. The ADM8840 is powered by a single 3.0V supply. ADD_OUT 8 CLK DATA CS / LDAC The COM_OUT amplitude can be programmed from 4.0V to 7.0V in steps of 28mV. The COM_OUT centre voltage can be programmed to 0.9V to 2.8V in steps of 14mV. INT/EXT DAC 1 DAC 2 INT/EXT DAC 2 SERIAL INTERFACE C11 4.7 F + - 8 TRANS_OUT C12 4.7 F LEVEL TRANSLATOR COM_IN POWER BUFFER COM_OUT_AC C13 4.7 F + COM_OUT DAC2_SD DAC2_IN 5.5k⍀ C PANE L 22nF The ADM8840 has an internal 100KHz oscillator for driving the charge pumps. The COM Driver section of the ADM8840 can be used to generate the alternate frame or line inversion of the COM line of the LCD panel. The ADM8840 receives the COM clock from the controller with a frequency up to 10kHz and allows programmable conditioning of its amplitude and centre voltage through the use of on-board DAC’s. This allows programmable elimination of display flicker caused by the COM inversion. DAC 1 GND The ADM8840 provides power up sequencing of the -15V and +15V gate drive outputs, ensuring the -15V starts to power up before the +15V. The ADM8840 has a number of power save features, including low power Shutdown. The 5.0V output consumes the most power, so Power Efficiency is also maximised on this output with an oscillator enabling scheme (Green IdleTM). The ADM8840 is fabricated using CMOS technology for minimal power consumption. The part is packaged in a 32pin LFCSP package. TM Green Idle is a registered trademark of Analog Devices Inc. REV. PrG 2/03 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2003 PRELIMINARY TECHNICAL DATA ADM8840 -15V VOLTAGE INVERTER C9 C4+ 0.22 F C4 0.22 F C4- +15V ADM8840 C8 C2+ TRIPLE VOLTAGE TRIPLER 0.22 F C2 0.22 F C2C3+ DOUBLE C3 0.22 F C3- OSCILLATOR TIMING GENERATOR 5VIN +5V 5VOUT SHDN SHUTDOWN CONTROL C7 2.2 F LDO VOLTAGE REGULATOR DISCHARGE VOUT C1+ VOLTAGE DOUBLER CONTROL LOGIC C6 C10 C1 3.3 F 3.3 F C1- 4.7 F V CC C5+ VOLTAGE ADDER C5 3.3 F C5DAC1_IN DAC1_SD VREF ADD_OUT 8 CLK DATA CS / LDAC DAC 1 INT/EXT DAC 1 C11 4.7 F + SERIAL INTERFACE - 8 DAC 2 TRANS_OUT INT/EXT DAC 2 C12 4.7 F LEVEL TRANSLATOR COM_IN POWER BUFFER COM_OUT_AC C13 4.7 F + COM_OUT DAC2_SD - DAC2_IN 5.5k⍀ C PA NE L 22nF GND ADM8840 FUNCTIONAL BLOCK DIAGRAM –2– REV. PrG 2/03 PRELIMINARY TECHNICAL DATA (VCC = +3V-10%,+20%, TA=-40°C to +85°C unless otherwise noted ) F; C2,C3,C4,C8,C9=0.22 F; C6,C11,C12,C13=4.7 F; C7 =2.2 C1,C5,C10=3.3 F PARAMETER Input Voltage,V CC Supply Current,I CC Min Typ Max Units 2.7 3.3 750 3.6 V uA 5 CHARGE PUMP REGULATOR +5.0V OUTPUT Output Voltage Output Current Output Ripple Transient Response +15.0V OUTPUT Output Voltage Output Current Output Ripple -15.0V OUTPUT Output Voltage Output Current Output Ripple Charge-Pump Frequency DIGITAL INPUT PINS Input Voltage, VIH 4.9 5.0 Center Voltage Center Voltage Stepsize Center Voltage Accuracy uA 5.1 5 10 5 14.0 15.0 50 50 16.0 150 -16.0 -150 -15.0 -50 50 -14.0 TBD 100 TBD 0.7V CC 0.3VCC 1 10 Digital Input Current Digital Input Capacitance COM DRIVER COM_OUT Amplitude Amplitude Stepsize Amplitude Accuracy ADM8840-SPECIFICATIONS 4 7 28 <10% 0.9 1.8 14 <10% 2.8 V mA mV p-p us O/Ps Unloaded; COM_IN Low; DAC1_SD, DAC2_SD Low Shutdown Mode DAC1_IN and DAC2_IN should be open circuit because there is a voltage on these pins due to the output of the DAC. IL = 10uA to 5mA 5mA load IL stepped from 10uA to 5mA V uA mV p-p IL = 1uA to 100uA V uA mV p-p IL = -1uA to -100uA I L =100uA I L =-100uA kHz V V A pF V mV % V mV % 1 TBD s us PANEL Load Capacitance 20 nF POWER EFFICIENCY 70 % Rise/Fall Time Center Voltage Settling Time Test Conditions Note 1. V COM_OUT =5V; DAC1 loaded with preset values; Measured at TRANS_OUT DAC1 preset values is 1V and Vcom should be 6V V CENTER =1.8V; DAC2 loaded with preset values DAC2 preset values is 500mV and Vcentre should be 1.5V. C PANEL =20nF 5VOUT Load = 5mA; +/-15V Load = +/-100uA; COM_IN Freq = 10kHz; C PANEL = 20nF; Vcc=2.7V; Note 2 NOTES 1. Guaranteed by Design. Not 100% Production Tested. 2. COM Driver load is defined as the load current flowing through C13 with DACs loaded with preset values. * Specifications are target values and are subject to change without notice. REV. PrG 2/03 –3– PRELIMINARY TECHNICAL DATA ADM8840 Timing Specifications PARAMETER VCC = +3V-10%,+20%, TA=-40°C to +85°C Min POWER-UP SEQUENCE 5V Rise time, TR5V +15V Rise time, TR15V -15V Fall time, TF15V Delay between VCC rise and SHDN rise, TDELAY1 Delay between -15V fall and +15V rise, TDELAY2 Typ Max Units Test Conditions /Comments TBD TBD TBD us ms ms 10% to 90%, Figure 2 10% to 90%, Figure 2 90% to 10%, Figure 2 TBD ms Figure 2 TBD ms Figure 2 POWER- DOWN SEQUENCE 5V Fall time, TF5V +15V Fall time, TF15V -15V Rise time, TR15V TBD TBD TBD ms ms ms 90% to 10%, Figure 2 90% to 10%, Figure 2 10% to 90%, Figure 2 SERIAL INTERFACE t1 TBD ns t2 t3 t4 TBD TBD TBD ns ns ns t5 TBD ns t6 t7 TBD TBD ns ns CS/LDAC falling edge to SCLK Rising Edge; Note 1; Note2 SCLK High Pulsewidth; Note 1; Note2 SCLK Low Pulsewidth; Note 1; Note2 Minumum CS/LDAC high time; Note 1; Note2 SCLK Rising Edge to CS/LDAC Rising Edge; Note 1; Note2 DATA Setup time; Note 1; Note2 DATA Hold time; Note 1; Note2 NOTES 1. Guaranteed by Design. Not 100% Production Tested. 2. See Timing Diagram in Figure 4. * Specifications are target values and are subject to change without notice. ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS* o (TA=25 C unless otherwise noted.) Model -0.3 V to +4.0 V -0.3 V to +4.0 V 10 seconds Temperature Range Package Option ADM8840ACP -40°C to +85°C C2- C3+ 25 C4- C2+ C4+ GND -15VOUT 26 24 C3- C1+ 1 TOP VIEW VCC 2 (NOT TO SCALE) 23 15VOUT 22 VCC VOUT 3 5VOUT 4 21 C5- 5VIN 5 20 C5+ 19 ADD_OUT SHDN 6 17 GND 12 13 14 15 16 COM_OUT DAC1_IN 10 11 COM_OUT_AC DAC2_SD 8 TRANS_OUT DAC1_SD 7 18 COM_IN 9 –4– 28 27 ADM8840 SCLK 32-Lead LFCSP Package: ⍜JA = 28°C/Watt 30 29 DATA THERMAL CHARACTERISTICS 32 31 CS/LDAC *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATION C1- -0.3 V to +6.0 V -17 V to +0.3 V -0.3 V to +17 V -40°C to +85°C 50mW -65°C to +150°C Class I CP-32 DAC2_IN Supply Voltage Input Voltage on Digital Inputs Output Short Circuit Duration to GND Output Voltage +5.0V Output -15.0V Output +15.0V Output Operating Temperature Range Power Dissipation Storage Temperature Range ESD REV. PrG 2/03 PRELIMINARY TECHNICAL DATA ADM8840 PIN FUNCTION DESCRIPTION Pin Mnemonic Function 1,32 C1+,C1- External capacitor C1 is connected between these pins. A 3.3F capacitor is recommended. 2, 22 V CC 3 VOUT Positive Supply Voltage Input. Connect this pin to 3V supply. A 4.7F decoupling capacitor should be attached close to pin 2. Voltage Doubler Output. This was derived by doubling the 3V supply. A 3.3F capacitor to ground is required on this pin. 4 +5VOUT +5.0V output pin. This was derived by doubling and regulating the +3V supply. A 2.2F capcitor to ground is required on this pin to stabilise the regulator. 5 +5VIN +5.0V input pin. This is the input to the voltage tripler and inverter charge pump circuits. 6 SHDN Digital Input. 3V CMOS Logic. Active low shutdown control. This shuts down the timing generator and enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0V. 7 DAC1_SD Switches over to external DAC1 input when asserted. 9 DAC1_IN Input for external DAC1 signal. 17, 31 GND Device Ground Pin. 13 SCLK External Clock Input. Used to load DAC 1 with COM Voltage amplitude and DAC 2 with COM Centre Voltage. 12 DATA Digital Data Input to both DAC’s 1 and 2. 11 CS / LDAC Dual function pin. 1.Chip Select. Digital Input Logic. Chip Select for Digital Interface. 2. Load DAC. Digital Input Logic. DAC’s 1 and 2 perform a conversion on a low-to-high transition. 18 COM_IN Clock Input from digital controller chip. This input is level shifted, offset and inverted to provide a COM Voltage output swing at a frequency of the COM_IN input. 16 COM_OUT_AC COM_OUT_AC outputs the COM_IN signal inverted and level shifted by the value programmed on DAC 1. A 4.7F capacitor is connected between this pin and COM_OUT. 14 COM_OUT The AC output on COM_OUT_AC is added to the center voltage programmed on DAC2 so that the desired amplitude, centered about the correct center voltage appears on COM_OUT. The load capacitance seen by this pin is the bulk capaci tance of the panel, typically 20nF. 8 DAC2_SD Switches over to external DAC2 input when asserted. 10 DAC2_IN Input for external DAC2 signal. 15 TRANS_OUT Level Translator Reference Output Voltage. This is the voltage that the value on DAC 1 is gained up to to provide the upper voltage for the Level Translator. A voltage of between 4.0V and 7.0V can be output here. A 4.7F cap is recommended for this pin. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM8840 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. PrG 2/03 –5– PRELIMINARY TECHNICAL DATA ADM8840 PIN FUNCTION DESCRIPTION (Contd.) Pin Mnemonic Function 19 ADD_OUT Voltage Adder Output Pin. (unregulated output of first then used as the supply for Translator Output Voltage. 20,21 C5+,C5- External capacitor C5 is connected between these pins. recommended. 23 +15VOUT +15.0V output pin. This was derived by tripling the +5.0V regulated output. A 0.22F capacitor is required on this pin. 29,28 C4+,C4- External capacitor C4 is connected between these pins. recommended. A 0.22F capacitor is 25,24 C3+,C3- External capacitor C3 is connected between these pins. recommended. A 0.22F capacitor is 27,26 C2+,C2- External capacitor C2 is connected between these pins. recommended. A 0.22F capacitor is 30 -15VOUT -15.0V output pin. This was derived by inverting the +15.0V output. A 0.22F capacitor is required on this pin. This is voltage generated by adding VOUT stage doubler) to VCC. This summed voltage is the gain stage which generates the Level A 4.7F capacitor is recommended for this pin. A 3.3F capacitor is COM_OUT VOLTAGE POWER SEQUENCING The COM Driver section of the ADM8840 can be used to generate the alternate frame or line inversion of the COM line of the LCD panel. The ADM8840 receives the COM clock (with frequency up to 10kHz) from the controller and allows programmable conditioning of its amplitude and centre voltage through the use of on-board DAC’s 1 and 2. This allows programmable elimination of display flicker caused by the COM inversion. In order for the TFT panel to power up correctly, the gate drive supplies must be sequenced such that the -15V supply starts up before the +15V supply. The ADM8840 controls this sequence. When the device is turned on, the ADM8840 allow the -15V output to ramp immediately, but holds off the +15V output. It continues to do this until the negative output has reached -3V. At this point, the positive output is enabled and allowed to ramp to +15V. This sequence is highlighted in figure 2. The COM_OUT amplitude can be programmed from 4.0V to 7.0V in steps of 28mV. The COM_OUT centre voltage can be programmed from 0.9V to 2.8V in steps of 14mV. Figure 1 below shows a typical output from the COM_OUT pin. If programmable operation is not required the DACs can be shutdown with the DAC1_SD and DAC2_SD pins and an analog voltage applied to the DAC1_IN and DAC2_IN pins to set up the amplitude and centre voltage at COM_OUT. tDELAY1 VCC SHDN tR5V 90% +5V tF5V 10% tR15V 90% +15V 4.0Vto7.0V tF15V 10% tDELAY2 0.9V->1.8V->2.8V -15V 0V -3V 90% tRM15V 10% tFM15V A MPL ITUDE : 4 .0V to 7 .0V Figure 1. COM_OUT Voltage CE NTR E V O LT AG E: 0.9 V ->1.8 V->2.8 V COM_OUT 0V Figure 2. Power Sequence –6– REV. PrG 2/03 PRELIMINARY TECHNICAL DATA ADM8840 SERIAL INTERFACE DAC 2 which sets the Centre Voltage of the output. The individual data bits are then read in one by one on the DATA line. After the DAC_SEL bit and the 8 data bits have been read there is a pause to ensure the shift register outputs are stable. Then a rising edge on the CS/LDAC input loads the 8 bits on the shift register outputs into the relevent DAC (and the DAC outputs will change accordingly). Note that if CS/ LDAC goes high before all 8 data bits are read in then incorrect data will be loaded into the DACs. All bits on the DATA line are read in on each rising edge of the SCLK signal. The COM Driver section of the ADM8840 uses a serial interface to input data and transfer it into the DACs. Figure 3, below, shows the operation of the serial interface. The data is transmitted along the serial DATA line, along with a serial clock signal, SCLK. This data is read into a Shift Register. When the 8 bits are sucessfully stored in the Shift Register a low-to-high transition on the CS/LDAC input causes the latch to load the 8-bits of data into the relevent DAC. This function is also shown in the waveforms in Figure 4 below. A falling edge on the CS/LDAC input initiates the data read into the shift register. The first bit of the datastream is the DAC Select Bit (DAC_SEL) which determines which internal DAC the data will be written to. A ‘1’ selects DAC 1 which sets the Amplitude of the output and a ‘0’ selects When the ADM8840 comes out of shutdown the DACs are preset with default values generating a COM_OUT Amplitude of 6V with a Centre voltage of 1.5V. 8 DATA BITS DATA DAC 1 LATCH SHIFT REGISTER DAC 1 OUT DAC 1 (AMPLITUDE) SCLK DAC_SEL BIT DAC 2 LATCH DAC 2 OUT DAC 2 (CENTRE VOLTAGE) DAC SELECT CS/LDAC Figure 3. Serial Interface Diagram t1 t4 t3 t2 CS / LDAC SCLK DATA D AC SEL D0 D1 D2 D3 D4 D5 D6 D7 t7 t6 t5 Figure 4. Serial Interface Waveforms REV. PrG 2/03 –7– PRELIMINARY TECHNICAL DATA ADM8840 DAC2 Setup The resolution of DAC2 is 4.7mV this is scaled up by 3 to give you the COM_OUT centre voltage resolution of 14mV (4.7mV * 3 = 14mV). The COM_OUT centre voltage is given by, (Binary Code/255)(1.188)(3)= COM_OUT DC Voltage. A table of the min, max and typical values for COM_OUT centre voltage is given in the Table 2 below. DAC1 Setup The resolution of DAC1 is 4.7mV this is scaled up by 6 to give COM_OUT amplitude resolution of 28mV (4.7mV * 6 = 28mV). The COM_OUT amplitude Vp-p is given by, (Binary Code/255)(1.188)(6)= Vp-p (COM_OUT). A table of the min, max and typical values for COM_OUT amplitude is given in the Table 1 below. Table 1 COM_OUT amplitude Voltage COM_OUT amplitude voltage (Max) (Typ) (Min) Binary Bits written to DAC1 Integer DAC1_IN Voltage 7.016V 11111011 251 1.667V 6.9882 11111010 250 1.6623 ......... ............. ..... ........... 6.0098V 11010111 215 1.0011V .......... ............. ..... ........... 4.0531V 10010001 145 671.7mV 4.0025V 10010000 144 667mV Table 2 COM_OUT centre voltage COM_OUT centre voltage (Max) (Typ) (Min) Binary Bits written to DAC2 Integer DAC2_IN Voltage 2.8092V 2.7952V 11001001 11001000 201 200 933mV 928mV ........... 1.5094V .............. 01101100 ...... 108 .......... 503.9mV ........... .............. ...... .......... 0.9224V 0.9084V 01000010 01000001 66 65 304.7mV 300mV –8– REV. PrG 2/03 PRELIMINARY TECHNICAL DATA ADM8840 BOOSTING THE CURRENT DRIVE OF THE +/-15V SUPPLY The ADM8840 +/-15V output can deliver 100uA of current in the typical configuration, as shown in Figure 5. In this configuration the 5Vout (pin 4) is connected to 5Vin (pin 5), as can be seen on block diagram Page 1 of this data sheet. It is possible to configure the ADM8840 to supply up to 400uA on the +/-15V outputs, by changing its configuration slightly, as shown in Figure 6. -15V VOLTAGE INVERTER C9 C4+ 0.22 F C4 0.22 F C4- +15V ADM8840 VOLTAGE TRIPLER C2C3+ C3- TIMING GENERATOR 0.22 F C2 0.22 F DOUBLE OSCILLATOR C8 C2+ TRIPLE C3 0.22 F Current Boost Configuration Connection 5VIN +5V 5VOUT SHDN SHUTDOWN CONTROL C7 2.2 F LDO VOLTAGE REGULATOR DISCHARGE VOUT -15V C10 C1+ VOLTAGE INVERTER C9 C4+ 0.22 F C4 0.22 F C6 V CC +15V C8 C2+ TRIPLE VOLTAGE TRIPLER DAC1_SD C3 C3- OSCILLATOR TIMING GENERATOR 0.22 F VREF 5VIN +5V 5VOUT SHDN SHUTDOWN CONTROL C7 ADD_OUT 2.2 F 8 LDO VOLTAGE REGULATOR DISCHARGE CLK DATA CS / LDAC VOUT C10 C1+ C6 C1 3.3 F VOLTAGE DOUBLER CONTROL LOGIC V CC C5+ VOLTAGE ADDER DAC 1 INT/EXT DAC 1 DAC 2 INT/EXT DAC 2 SERIAL INTERFACE C11 4.7 F + - 8 TRANS_OUT C12 4.7 F 3.3 F C1- 4.7 F C5 3.3 F C5DAC1_IN C2C3+ DOUBLE C5+ VOLTAGE ADDER 0.22 F C2 0.22 F 3.3 F C1- 4.7 F C4- ADM8840 C1 3.3 F VOLTAGE DOUBLER CONTROL LOGIC LEVEL TRANSLATOR COM_IN C5 PO WER BUFFER COM_OUT_AC C13 4.7 F + 3.3 F COM_OUT DAC2_SD C5DAC1_IN - DAC2_IN 5k ⍀ C PANEL 22nF DAC1_SD VREF ADD_OUT 8 CLK DATA CS / LDAC DAC 1 INT/EXT DAC 1 DAC 2 INT/EXT DAC 2 SERIAL INTERFACE C11 4.7 F + GND - 8 C12 4.7 F LEVEL TRANSLATOR COM_IN COM_OUT_AC C13 4.7 F + COM_OUT DAC2_SD DAC2_IN Figure 6. Current Boost Configuration TRANS_OUT POWER BUFFER 5k ⍀ C PANE L 22nF The configuration in Figure 6, can supply up to 400uA of current on both the +15V and the -15V outputs. If the load on the +/-15V does not draw any current the voltage on the +/-15V outputs can rise up to +/-16.5V.In this configuration Vout (pin 3) is connected to 5Vin (pin 5). GND Figure 5. Typical Configuration REV. PrG 2/03 –9– PRELIMINARY TECHNICAL DATA ADM8840 OUTLINE DIMENSIONS Dimensions Shown in Inches and (mm). 32-Lead 5X5 Chip Scale Package (CP-32) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 25 0.009 (0.24) 24 0.197 (5.0) BSC SQ 0.010 (0.25) MIN 32 1 PIN 1 INDICATOR TOP VIEW 0.187 (4.75) BSC SQ 0.031 (0.80) MAX 0.026 (0.65) NOM 12. MAX 0.035 (0.90) MAX 0.033 (0.85) NOM SEATING PLANE 0.020 (0.50) BSC 0.008 (0.20) REF –10– 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 0.128 (3.25) 0.122 (3.10) SQ 0.116 (2.95) BOTTOM VIEW 17 16 9 8 0.138 (3.50) REF 0.002 (0.05) 0.0004 (0.01) 0.0 (0.00) REV. PrG 2/03