HCPL-2602, HCPL-2612 High CMR Line Receiver Optocouplers Data Sheet Description The HCPL-2602/12 are optically coupled line receivers that combine a GaAsP light emitting diode, an input current regulator and an integrated high gain photo detector. The input regulator serves as a line termination for line receiver applications. It clamps the line voltage and regulates the LED current so line reflections do not interfere with circuit performance. The regulator allows a typical LED current of 8.5 mA before it starts to shunt excess current. The output of the detector IC is an open collector Schottky clamped transistor. An enable input gates the detector. The internal detector shield provides a guaranteed common mode transient immunity specification of 1000 V/ms for the 2602, and 3500 V/ms for the 2612. DC specifications are defined similar to TTL logic. The optocoupler ac and dc operational parameters are guaranteed from 0°C to 70°C allowing troublefree interfacing with digital logic circuits. An input current of 5 mA will sink an eight gate fan-out (TTL) at the output. Functional Diagram NC 1 8 VCC IN+ 2 7 VE IN– 3 6 VO CATHODE 4 5 GND SHIELD Features • 1000 V/µs minimum Common Mode Rejection (CMR) at VCM = 50 V for HCPL-2602 and 3.5 kV/µs minimum CMR at VCM = 300 V for HCPL-2612 • Line termination included – no extra circuitry required • Accepts a broad range of drive conditions • LED protection minimizes LED efficiency degradation • High speed: 10 MBd (limited by transmission line in many applications) • Guaranteed AC and DC performance over temperature: 0°C to 70°C • External base lead allows “LED peaking” and LED current adjustment • Safety approval UL recognized – 3750 V rms for 1 Minute CSA approved • MIL-PRF-38534 hermetic version available (HCPL-1930/1) Applications • Isolated line receiver • Computer-peripheral interface • Microprocessor system interface • Digital isolation for A/D, D/A conversion • Current sensing • Instrument input/output isolation • Ground loop elimination • Pulse transformer replacement • Power transistor isolation in motor drives TRUTH TABLE (POSITIVE LOGIC) LED ON OFF ON OFF ON OFF ENABLE H H L L NC NC OUTPUT L H H H L H A 0.1 µF bypass capacitor must be connected between pins 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The HCPL-2602/12 are useful as line receivers in high noise environments that conventional line receivers cannot tolerate. The higher LED threshold voltage provides improved immunity to differential noise and the internally shielded detector provides orders of magnitude improvement in common mode rejection with little or no sacrifice in speed. Selection Guide Minimum CMR dV/dt (V/µs) VCM (V) Input OnCurrent (mA) NA NA 5 8-Pin DIP (300 Mil) Output Enable Single Channel Package YES 6N137 NO 5,000 50 YES 1,000 YES HCPL-2602[1] 3,500 300 YES HCPL-2612[1] 1,000 50 YES HCPL-261A NO 1,000 1,000 50 YES NO 12.5 HCNW2601 HCPL-0611 HCNW2611 HCPL-0661 HCPL-061A HCPL-263A HCPL-261N HCPL-063A HCPL-061N HCPL-263N [3] Notes: 1. HCPL-2602/2612 devices include input current regulator. 2. 15 kV/µs with VCM = 1 kV can be achieved using Avago application circuit. 3. Enable is available for single channel products only, except for HCPL-193X devices. 2 Single and Dual Channel Packages HCPL-0631 HCPL-4661 YES Hermetic Single Channel Package HCNW137 HCPL-0601 HCPL-2611 50 Dual Channel Package Widebody Hermetic HCPL-0630 HCPL-2631 1,000 1,000[2] Single Channel Package HCPL-0600 HCPL-2601 NO 3 Dual Channel Package HCPL-2630 NO 10,000 Small-Outline SO-8(400 Mil) HCPL-063N HCPL-193X HCPL-56XX HCPL-66XX Ordering Information HCPL-2602/HCPL-2612 is UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part RoHS non RoHS Number Compliant Compliant HCPL-2602 -000E no option HCPL-2612 -300E #300 -500E #500 Package 300 mil DIP-8 Surface Mount Gull Wing Tape & Reel X X X X X Quantity 50 per tube 50 per tube 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-2602-500E to order product of Gull Wing Surface Mount package in Tape and Reel packaging and RoHS compliant. Example 2: HCPL-2612 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and RoHS compliant will use ‘–XXXE.’ Schematic + II 2 IF ICC 8 IO 6 VCC VO VI – 3 90 Ω SHIELD IE 5 7 VE 4 USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS REQUIRED (SEE NOTE 1). 3 GND Package Outline Drawings 8-Pin DIP Package 7.62 ± 0.25 (0.300 ± 0.010) 9.65 ± 0.25 (0.380 ± 0.010) 8 7 6 5 6.35 ± 0.25 (0.250 ± 0.010) TYPE NUMBER DATE CODE A XXXXZ YYWW RU 1 2 3 4 UL RECOGNITION 1.78 (0.070) MAX. 1.19 (0.047) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 5° TYP. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). 2.92 (0.115) MIN. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 0.65 (0.025) MAX. 1.080 ± 0.320 (0.043 ± 0.013) 2.54 ± 0.25 (0.100 ± 0.010) 8-Pin DIP Package with Gull Wing Surface Mount Option 300 LAND PATTERN RECOMMENDATION 9.65 ± 0.25 (0.380 ± 0.010) 8 7 6 1.016 (0.040) 5 6.350 ± 0.25 (0.250 ± 0.010) 1 2 3 10.9 (0.430) 4 1.27 (0.050) 1.19 (0.047) MAX. 1.780 (0.070) MAX. 9.65 ± 0.25 (0.380 ± 0.010) 7.62 ± 0.25 (0.300 ± 0.010) 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 0.635 ± 0.130 2.54 (0.025 ± 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 4 2.0 (0.080) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 12° NOM. Regulatory Information The HCPL-2602/2612 have been approved by the following organizations: Solder Reflow Thermal Profile 300 TEMPERATURE (°C) PREHEATING RATE 3°C + 1°C/–0.5°C/SEC. REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK TEMP. 245°C PEAK TEMP. 240°C PEAK TEMP. 230°C 200 2.5°C ± 0.5°C/SEC. SOLDERING TIME 200°C 30 SEC. 160°C 150°C 140°C UL Recognized under UL 1577, Component Recognition Program, File E55361. 30 SEC. 3°C + 1°C/–0.5°C 100 PREHEATING TIME 150°C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 200 CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. 250 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE tp Tp TEMPERATURE TL Tsmax 20-40 SEC. 260 +0/-5 °C 217 °C RAMP-UP 3 °C/SEC. MAX. 150 - 200 °C RAMP-DOWN 6 °C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. tL 60 to 150 SEC. 25 t 25 °C to PEAK TIME NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 °C, Tsmin = 150 °C Note: Non-halide flux should be used. Insulation and Safety Related Specifications Parameter Symbol Value Min. External Air Gap L(I01) 7.1 (External Clearance) Min. External Tracking L(I02) 7.4 Path (External Creepage) Min. Internal Plastic 0.08 Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 200 IIIa Units mm mm mm V Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance with CECC 00802. 5 Absolute Maximum Ratings (No Derating Required up to 85°C) Parameter Symbol Storage Temperature TS Operating Temperature TA Forward Input Current II Reverse Input Current IIR Input Current, Pin 4 Supply Voltage (1 Minute Maximum) VCC Enable Input Voltage (Not to Exceed VCC by VE more than 500 mV) Output Collector Current IO Output Collector Voltage (Selection for Higher VO Output Voltages up to 20 V is Available.) Output Collector Power Dissipation PO Lead Solder Temperature TLS Min. -55 -40 -10 Recommended Operating Conditions Symbol Min. Max. Units Input Current, Low Level IIL 0 250 µA Input Current, High Level IIH 5* 60 mA Supply Voltage, Output VCC 4.5 5.5 V High Level Enable Voltage VEH 2.0 VCC V Low Level Enable Voltage VEL 0 0.8 V Fan Out (@ RL = 1 kΩ) N 5 TTL Loads Output Pull-up Resistor RL 330 4K Ω Operating Temperature TA 0 70 °C *The initial switching threshold is 5 mA or less. It is recommended that an input current between 6.3 mA and 10 mA be used to obtain best performance and to provide at least 20% LED degradation guardband. 6 Units °C °C mA mA mA V V 50 7 mA V 40 mW 260°C for 10 sec., 1.6 mm below seating plane See Package Outline Drawings section Solder Reflow Temperature Profile Parameter Max. 125 85 60 60 10 7 VCC + 0.5 Electrical Characteristics Over recommended temperature (TA = 0°C to +70°C) unless otherwise specified. See note 1. Parameter Sym. Min. Typ.* Max. Units Fig. High Level Output Current IOH 5.5 100 µA VCC = 5.5 V, VO = 5.5 V, II = 250 µA, VE = 2.0 V 1 Low Level Output Voltage VOL 0.35 0.6 V VCC = 5.5 V, II = 5 mA, VE = 2.0 V, IOL (Sinking) = 13 mA 2, 4, 5, 14 High Level Supply Current ICCH 7.5 10 mA VCC = 5.5 V, II = 0 mA, VE = 0.5 V Low Level Supply Current ICCL 10 13 mA VCC = 5.5 V, II = 60 mA, VE = 0.5 V High Level Enable Current IEH -0.7 -1.6 mA VCC = 5.5 V, VE = 2.0 V Low Level Enable Current IEL -0.9 -1.6 mA VCC = 5.5 V, VE = 0.5 V High Level Enable Voltage VEH Low Level Enable Voltage VEL Input Voltage VI 2.0 V 0.8 2.0 2.4 2.3 2.7 0.95 VR 0.75 Input Capacitance CIN 90 Note 10 V V Input Reverse Voltage *All typicals at VCC = 5 V, TA = 25°C. 7 Test Conditions II = 5 mA II = 60 mA V IR = 5 mA pF VI = 0 V, f = 1 MHz 3 Switching Specifications Over recommended temperature (TA = 0°C to +70°C), VCC = 5 V, II = 7.5 mA, unless otherwise specified. Parameter Symbol Propagation Delay Time to High Output Level tPLH Propagation Delay Time to Low Output Level tPHL Pulse Width Distortion Device Min. Typ.* 20 48 25 |tPHL-tPLH| Max. Units 75 ns 100 ns 75 ns 100 ns 35 ns 40 ns Test Conditions Note 6, 7, 8 3 6, 7, 8 4 9 13 TA = 25°C TA = 25°C 50 3.5 Fig. RL = 350 Ω CL = 15 pF Propagation Delay Skew tPSK Output Rise Time (10-90%) tr 24 ns 12 Output Fall Time (90-10%) tf 10 ns 12 Propagation Delay Time of Enable from VEH to VEL tELH 30 ns Propagation Delay Time of Enable from VEL to VEH tEHL Common Mode Transient Immunity at High Output Level |CMH| Common Mode Transient Immunity at Low Output Level |CML| 20 HCPL-2602 1000 ns 10,000 12, 13 RL = 350 Ω, CL = 15 pF, VEL = 0 V, VEH = 3 V 10, 11 5 RL = 350 Ω, CL = 15 pF, VEL = 0 V, VEH = 3 V 10, 11 6 13 7, 9, 10 13 8, 9 10 VCM = 50 V V/µs HCPL-2612 3500 15,000 HCPL-2602 1000 10,000 VCM = 300 V VCM = 50 V V/µs HCPL-2612 3500 VCM = 300 V 15,000 VO(MIN) = 2 V, RL = 350 Ω, II = 0 mA, TA = 25°C VO(MAX) = 0.8 V, RL = 350 Ω, II = 7.5 mA, TA = 25°C *All typicals at VCC = 5 V, TA = 25°C. Package Characteristics All Typicals at TA = 25°C Parameter Input-Output Momentary Withstand Voltage* Input-Output Resistance Input-Output Capacitance Sym. VISO RI-O CI-O Min. 3750 Typ. 1012 0.6 Max. Units V rms Ω pF Test Conditions RH ≤ 50%, t = 1 min., TA = 25°C VI-O = 500 Vdc f = 1 MHz Fig. Note 2, 11 2 2 *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.” 8 VCC = 5.5 V VO = 5.5 V VE = 2 V II = 250 µA 10 5 0 -60 -40 -20 0 20 40 60 80 100 IO = 12.8 mA 0.3 VCC = 5 V TA = 25 °C RL = 350 Ω 3 RL = 1 KΩ 2 RL = 4 KΩ 1 0 1 2 3 4 5 6 IF – FORWARD INPUT CURRENT – mA Figure 4. Typical output voltage vs. forward input current. 9 IO = 6.4 mA 0.2 IO = 9.6 mA 0.1 -60 -40 -20 0°C 2.2 25°C 70°C 2.0 1.8 1.6 1.4 1.0 0 20 40 60 80 100 70 VCC = 5 V VE = 2 V VOL = 0.6 V 60 II = 10-15 mA 50 II = 5.0 mA 40 20 -60 -40 -20 2.4 1.2 Figure 2. Typical low level output voltage vs. temperature. IOL – LOW LEVEL OUTPUT CURRENT – mA VO – OUTPUT VOLTAGE – V 6 0 IO = 16 mA TA – TEMPERATURE – °C Figure 1. Typical high level output current vs. temperature. 4 VCC = 5.5 V VE = 2 V II = 5 mA 0.4 TA – TEMPERATURE – °C 5 2.6 0.5 VI – INPUT VOLTAGE – V 15 VOL – LOW LEVEL OUTPUT VOLTAGE – V IOH – HIGH LEVEL OUTPUT CURRENT – µA Notes: 1. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 15. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm. 2. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 3. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 4. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 5. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge of the output pulse. 6. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge of the output pulse. 7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V). 8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT < 0.8 V). 9. For sinusoidal voltages, |dvCM| –––––– = πfCMVCM (p-p) dt max 10. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR performance. 11. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage of ≥ 4500 for one second (leakage detection current limit, Ii-o ≤ 5 µA). 12. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the operating condition range. 13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information. 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 5. Typical low level output current vs. temperature. 0 10 20 30 40 50 II – INPUT CURRENT – mA Figure 3. Typical input characteristics. 60 +5 V INPUT MONITORING NODE 1 VCC 8 2 7 3 6 0.1µF BYPASS RL *CL RM 4 GND 100 OUTPUT VO MONITORING NODE tP – PROPAGATION DELAY – ns II PULSE GEN. Z O = 50 Ω t f = t r = 5 ns 5 *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. I I = 7.50 mA INPUT II I I = 3.75 mA t PHL t PLH 75 tPLH , RL = 350 Ω tPLH , RL = 1 KΩ 30 tPHL , RL = 350 Ω 1 KΩ 4 KΩ 7 5 9 11 15 13 PWD – PULSE WIDTH DISTORTION – ns tP – PROPAGATION DELAY – ns tPLH , RL = 4 KΩ 45 20 tPLH , RL = 350 Ω 0 20 40 60 80 100 TA – TEMPERATURE – °C 40 RL = 4 kΩ 30 VCC = 5 V II = 7.5 mA 20 10 RL = 350 kΩ 0 RL = 1 kΩ -10 -60 -40 -20 II – PULSE INPUT CURRENT – mA 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 8. Typical propagation delay vs. pulse input current. PULSE GEN. Z O = 50 Ω t f = t r = 5 ns tPLH , RL = 1 KΩ 40 Figure 7. Typical propagation delay vs. temperature. VCC = 5 V TA = 25°C 90 tPLH , RL = 4 KΩ tPHL , RL = 350 Ω 1 KΩ 60 4 KΩ 1.5 V Figure 6. Test circuit for tPHL and tPLH. 60 80 0 -60 -40 -20 OUTPUT VO 105 VCC = 5 V II = 7.5 mA Figure 9. Typical pulse width distortion vs. temperature. INPUT VE MONITORING NODE +5 V VCC 8 2 7 3 6 4 5 0.1 µF R BYPASS L *CL GND *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. 3.0 V INPUT VE 1.5 V t EHL OUTPUT VO Figure 10. Test circuit for tEHL and tELH. 10 t ELH 1.5 V OUTPUT VO MONITORING NODE tE – ENABLE PROPAGATION DELAY – ns 7.5 mA II 1 120 VCC = 5 V VEH = 3 V VEL = 0 V 90 II = 7.5 mA tELH, RL = 4 kΩ 60 tELH, RL = 1 kΩ 30 tELH, RL = 350 Ω tEHL, RL = 350 Ω, 1 kΩ, 4 kΩ 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 11. Typical enable propagation delay vs. temperature. tr, tf – RISE, FALL TIME – ns VCC = 5 V II = 7.5 mA tRISE tFALL II 1 VCC 8 2 7 3 6 B A RL = 4 kΩ 300 290 60 +5 V 0.1 µF BYPASS 350 Ω OUTPUT VO MONITORING NODE RL = 1 kΩ 4 40 0 -60 -40 -20 5 VCM RL = 350 Ω 20 GND + – PULSE GENERATOR Z O = 50 Ω RL = 350 Ω, 1 kΩ, 4 kΩ 0 20 40 60 80 100 TA – TEMPERATURE – °C VCM (PEAK) VCM Figure 12. Typical rise and fall time vs. temperature. VO VO 0V 5V SWITCH AT A: II = 0 mA CMH VO (MIN.) SWITCH AT B: II = 7.5 mA VO (MAX.) 0.5 V CML Figure 13. Test circuit for common mode transient immunity and typical waveforms. ITH – INPUT THRESHOLD CURRENT – mA GND BUS (BACK) VCC = 5.0 V VO = 0.6 V 5 VCC BUS (FRONT) NC 4 0.1µF 3 RL = 350 Ω NC 2 RL = 1 kΩ 1 OUTPUT 1 NC RL = 4 kΩ 0 -60 -40 -20 0.1µF 0 20 40 60 ENABLE (IF USED) 80 100 TA – TEMPERATURE – °C Figure 14. Typical input threshold current vs. temperature. NC OUTPUT 2 10 mm MAX. (SEE NOTE 1) Figure 15. Recommended printed circuit board layout. 11 ENABLE (IF USED) Using the HCPL-2602/12 Line Receiver Optocouplers The primary objectives to fulfill when connecting an optocoupler to a transmission line are to provide a minimum, but not excessive, LED current and to properly terminate the line. The internal regulator in the HCPL2602/12 simplifies this task. Excess current from variable drive conditions such as line length variations, line driver differences, and power supply fluctuations are shunted by the regulator. In fact, with the LED current regulated, the line current can be increased to improve the immunity of the system to differential-mode-noise and to enhance the data rate capability. The designer must keep in mind the 60 mA input current maximum rating of the HCPL2602/12 in such cases, and may need to use series limiting or shunting to prevent overstress. Design of the termination circuit is also simplified; in most cases the transmission line can simply be connected directly to the input terminals of the HCPL-2602/12 without the need for additional series or shunt resistors. If reversing line drive is used it may be desirable to use two HCPL2602/12 or an external Schottky diode to optimize data rate. Polarity Non-Reversing Drive High data rates can be obtained with the HCPL-2602/12 with polarity non-reversing drive. Figure (a) illustrates how a 74S140 line driver can be used with the HCPL-2602/12 and shielded, twisted pair or coax cable without any additional components. There are some reflections due to the “active termination,” but they do not 12 interfere with circuit performance because the regulator clamps the line voltage. At longer line lengths, tPLH increases faster than tPHL since the switching threshold is not exactly halfway between asymptotic line conditions. If optimum data rate is desired, a series resistor and peaking capacitor can be used to equalize tPLH and tPHL. In general, the peaking capacitance should be as large as possible; however, if it is too large it may keep the regulator from achieving turn-off during the negative (or zero) excursions of the input signal. A safe rule: make C ≤16t where: C = peaking capacitance in picofarads t = data bit interval in nanoseconds Polarity Reversing Drive A single HCPL-2602/12 can also be used with polarity reversing drive (Figure b). Current reversal is obtained by way of the substrate isolation diode (substrate to collector). Some reduction of data rate occurs, however, because the substrate diode stores charge, which must be removed when the current changes to the forward direction. The effect of this is a longer tPHL. This effect can be eliminated and data rate improved considerably by use of a Schottky diode on the input of the HCPL-2602/12. For optimum noise rejection as well as balanced delays, a splitphase termination should be used along with a flip-flop at the output (Figure c). The result of current reversal in split-phase operation is seen in Figure (c) with switches A and B both OPEN. The coupler inputs are then connected in ANTI-SERIES; however, because of the higher steady-state termination voltage, in comparison to the single HCPL-2602/12 termination, the forward current in the substrate diode is lower and consequently there is less junction charge to deal with when switching. Closing switch B with A open is done mainly to enhance common mode rejection, but also reduces propagation delay slightly because line-to-line capacitance offers a slight peaking effect. With switches A and B both CLOSED, the shield acts as a current return path which prevents either input substrate diode from becoming reversed biased. Thus the data rate is optimized as shown in Figure (c). Improved Noise Rejection Use of additional logic at the output of two HCPL-2602/12s, operated in the split phase termination, will greatly improve system noise rejection in addition to balancing propagation delays as discussed earlier. A NAND flip-flop offers infinite common mode rejection (CMR) for NEGATIVELY sloped common mode transients but requires tPHL > tPLH for proper operation. A NOR flip-flop has infinite CMR for POSITIVELY sloped transients but requires tPHL < tPLH for proper operation. An exclusive-OR flipflop has infinite CMR for common mode transients of EITHER polarity and operates with either tPHL > tPLH or tPHL < tPLH. With the line driver and transmission line shown in Figure (c), tPHL > tPLH, so NAND gates are preferred in the R-S flip-flop. A higher drive amplitude or Figure a. Polarity non-reversing. Figure b. Polarity reversing, single ended. <1 <1 Figure c. Polarity reversing, split phase. Figure d. Flip-flop configurations. 13 different circuit configuration could make tPHL < tPLH, in which case NOR gates would be preferred. If it is not known whether tPHL > tPLH or tPHL < tPLH, or if the drive conditions may vary over the boundary for these conditions, the exclusive-OR flip-flop of Figure (d) should be used. RS-422 and RS-423 Line drivers designed for RS-422 and RS-423 generally provide adequate voltage and current for operating the HCPL-2602/12. Most drivers also have characteristics allowing the HCPL-2602/12 to be connected directly to the driver terminals. Worst case drive conditions, however, would require current shunting to prevent overstress of the HCPL2602/12. Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 6). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing 14 the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 16, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPHL or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 17 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 17 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges. DATA II INPUTS 50% CLOCK 1.5 V VO II DATA 50% OUTPUTS VO 1.5 V t PSK Figure 16. Illustration of propagation delay skew - tPSK. 15 t PSK CLOCK t PSK Figure 17. Parallel data transmission example. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2154EN AV01-0568EN July 18, 2007