Small Outline, 5 Lead, High CMR, High Speed, Logic Gate Optocouplers Technical Data HCPL-M600 HCPL-M601 HCPL-M611 Features Description • Surface Mountable • Very Small, Low Profile JEDEC Registered Package Outline • Compatible with Infrared Vapor Phase Reflow and Wave Soldering Processes • Internal Shield for High Common Mode Rejection (CMR) HCPL-M601: 10,000 V/µs at VCM = 50 V HCPL-M611: 15,000 V/µs at VCM = 1000 V • High Speed: 10 Mbd • LSTTL/TTL Compatible • Low Input Current Capability: 5 mA • Guaranteed ac and dc Performance over Temperature: -40°C to 85°C • Recognized under the Component Program of U.L. (File No. E55361) for Dielectric Withstand Proof Test Voltage of 2500 Vac, 1 Minute These small outline high CMR, high speed, logic gate optocouplers are single channel devices in a five lead miniature footprint. They are electrically equivalent to the following Agilent optocouplers (except there is no output enable feature): SO-5 Package Standard DIP SO-8 Package HCPL-M600 6N137 HCPL-0600 HCPL-M601 HCPL-2601 HCPL-0601 HCPL-M611 HCPL-2611 HCPL-0611 The SO-5 JEDEC registered (MO155) package outline does not require “through holes” in a PCB. This package occupies approximately one fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The HCPL-M600/01/11 optically coupled gates combine a GaAsP light emitting diode and an integrated high gain photon detector. The output of the detector I.C. is an Open-collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/µs for the HCPL-M601, and 10,000 V/µs for the HCPLM611. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40°C to 85°C allowing trouble free system performance. CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 2 The HCPL-M600/01/11 are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate, and are recommended for use in extremely high ground or induced noise environments. Outline Drawing (JEDEC MO-155) ANODE 1 4.4 ± 0.1 (0.173 ± 0.004) MXXX XXX 6 7.0 ± 0.2 (0.276 ± 0.008) VCC 5 VOUT CATHODE 3 4 GND Applications • Isolated Line Receiver • Simplex/Multiplex Data Transmission • Computer-Peripheral Interface • Microprocessor System Interface • Digital Isolation for A/D, D/A Conversion • Switching Power Supply • Instrument Input/Output Isolation • Ground Loop Elimination • Pulse Transformer Replacement 0.4 ± 0.05 (0.016 ± 0.002) 3.6 ± 0.1* (0.142 ± 0.004) 0.102 ± 0.102 (0.004 ± 0.004) 2.5 ± 0.1 (0.098 ± 0.004) 0.15 ± 0.025 (0.006 ± 0.001) 7° MAX. 0.71 MIN. (0.028) 1.27 BSG (0.050) MAX. LEAD COPLANARITY = 0.102 (0.004) DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006) "Agilent" IS MARKED ON THE UNDERSIDE OF THE PACKAGE Pin Location (for reference only) Schematic 0.3 (0.01) 4.4 (0.17) + IF ICC 6 1 IO 5 VCC VO 1.3 (0.05) 2.5 (0.10) – 4 3 GND HCPL-M601/11 SHIELD 0.9 (0.04) 0.5 (0.02) 7.2 (0.28) USE OF A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN PINS 6 AND 4 (SEE NOTE 1). TRUTH TABLE (POSITIVE LOGIC) OUTPUT LED L ON H OFF 3 Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current, Low Level IFL* 0 250 µA Input Current, High Level IFH 5 15 mA Supply Voltage, Output VCC 4.5 5.5 V 5 TTL Loads Fan Out (RL = 1 kΩ) N Output Pull-Up Resistor RL 330 4,000 Ω Operating Temperature TA -40 85 °C * The off condition can also be guaranteed by ensuring that VF(off) ≤ 0.8 volts. Absolute Maximum Ratings TEMPERATURE – °C (No Derating Required up to 85°C) Storage Temperature .................................................... -55°C to +125°C Operating Temperature .................................................. -40°C to +85°C Forward Input Current - IF (see Note 2) ....................................... 20 mA Reverse Input Voltage - VR ................................................................. 5 V Supply Voltage - VCC (1 Minute Maximum) ........................................ 7 V Output Collector Current - IO ........................................................ 50 mA Output Collector Power Dissipation ............................................ 85 mW Output Collector Voltage - VO ............................................................ 7 V (Selection for higher output voltages up to 20 V is available) Infrared and Vapor Phase Reflow Temperature ....................... see below 260 240 220 200 180 160 140 120 100 80 60 40 20 0 ∆T = 145°C, 1°C/SEC ∆T = 115°C, 0.3°C/SEC ∆T = 100°C, 1.5°C/SEC 0 1 2 3 4 5 6 7 8 9 10 11 TIME – MINUTES Maximum Solder Reflow Thermal Profile. (Note: Use of Non-Chlorine Activated Fluxes is Recommended.) 12 4 Insulation Related Specifications Parameter Symbol Value Units Min. External Air Gap (Clearance) L(IO1) ≥5 mm Measured from input terminals to output terminals Min. External Tracking Path (Creepage) L(IO2) ≥5 mm Measured from input terminals to output terminals 0.08 mm Through insulation distance conductor to conductor 175 V Min. Internal Plastic Gap (Clearance) Tracking Resistance CTI Isolation Group (per DIN VDE 0109) IIIa Conditions DIN IEC 112/VDE 0303 Part 1 Material Group DIN VDE 0109 Electrical Specifications Over recommended temperature (TA = -40°C to 85°C) unless otherwise specified. (See note 1.) Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Input Threshold Current ITH 2 5 mA VCC = 5.5 V, IO ≥13 mA, VO = 0.6 V 13 High Level Output Current IOH 5.5 100 µA VCC = 5.5 V, VO = 5.5 V IF = 250 µA 1 Low Level Output Voltage VOL 0.4 0.6 V VCC = 5.5 V, IF = 5 mA, IOL (Sinking) = 13 mA 2, 4, 5, 13 High Level Supply Current ICCH 4 7.5 mA VCC = 5.5 V, IF = 0 mA, Low Level Supply Current ICCL 6 10.5 Input Forward Voltage VF 1.4 1.75 Note VCC = 5.5 V, IF = 10 mA, V TA = 25°C 3 1.5 1.3 1.85 IF = 10 mA IR = 10 µA Input Reverse Breakdown Voltage BVR Input Capacitance CIN 60 pF Input Diode Temperature Coefficient ∆VF /∆TA -1.6 mV/°C Input-Output Insulation VISO Resistance (Input-Output) RI-O 1012 Ω VI-O = 500 V 3 Capacitance (Input-Output) CI-O 0.6 pF f = 1 MHz 3 *All typicals at TA = 25°C, VCC = 5 V. 5 2500 VRMS VF = 0V, f = 1 MHz IF = 10 mA RH ≤ 50%, t = 1 min. 12 3, 4 5 Switching Specifications Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified. Parameter Symbol Propagation Delay Time to High Output Level tPLH Propagation Delay Time to Low Output Level tPHL Propagation Delay Skew tPSK Device HCPL- Min. Typ.* Max. Unit 20 48 75 ns Test Conditions TA = 25°C 6, 7 100 25 50 75 Fig. Note 8 TA = 25°C 6, 7 RL = 350 Ω 100 3.5 Output Rise Time (10%-90%) trise 24 Output Fall Time (10%-90%) tfall Common Mode Transient Immunity at High Output Level |CM H| Common Mode Transient Immunity at Low Output Level |CM H| 6 8 40 Pulse Width |tPHL - tPLH| Distortion 5 10, 11 35 CL = 15 pF 9 10 10 10 10 M600 10,000 M601 5,000 10,000 M611 10,000 15,000 VO(min) = 2 V RL = 350 Ω VCM = 50 V IF = 0 mA VCM = 1000 V TA = 25°C M600 10,000 VCM = 10 V M601 5,000 10,000 M611 10,000 15,000 V/µs VCM = 10 V 11 7, 9 VO(max) = 0.8 V 11 RL = 350 Ω VCM = 50 V IF = 7.5 mA VCM = 1000 V T A = 25°C 8, 9 *All typicals at TA = 25°C, VCC = 5 V. Notes: 1. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler. The total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. 3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together. 4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 VRMS for 1 second (Leakage detection current limit, II-O ≤ 5 µA). 5. The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 6. The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V). 8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT > 0.8 V). 9. For sinusoidal voltages, (|dVCM|/dt)max = πfCMVCM(p-p). 10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information. 11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the worst case operating condition range. VCC = 5.5 V VO = 5.5 V IF = 250 µA 10 5 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C 0.5 VCC = 5.5 V IF = 5.0 mA 0.4 IO = 12.8 mA IO = 16 mA 0.3 IO = 6.4 mA 0.2 IO = 9.6 mA 0.1 -60 -40 -20 0 20 40 60 80 100 100 IF – FORWARD CURRENT – mA 15 VOL – LOW LEVEL OUTPUT VOLTAGE – V IOH – HIGH LEVEL OUTPUT CURRENT – µA 6 TA = 25°C 10 1.0 0.1 0.01 0.001 1.10 TA – TEMPERATURE – °C Figure 1. High Level Output Current vs. Temperature. Figure 2. Low Level Output Voltage vs. Temperature. IF + VF – 1.20 1.30 1.40 1.50 1.60 VF – FORWARD VOLTAGE – VOLTS Figure 3. Input Diode Forward Characteristic. VO – OUTPUT VOLTAGE – V 6 VCC = 5 V TA = 25 °C 5 4 RL = 350 Ω 3 PULSE GEN. ZO = 50 Ω tf = tr = 5 ns RL = 1 KΩ 2 RL = 4 KΩ +5 V IF 1 1 0 VCC 6 0.1µF BYPASS 0 1 2 3 4 5 6 5 IF – FORWARD INPUT CURRENT – mA RL *CL INPUT MONITORING NODE 3 GND 4 RM Figure 4. Output Voltage vs. Forward Input current. IOL – LOW LEVEL OUTPUT CURRENT – mA *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. 80 VCC = 5.0 V VOL = 0.6 V IF = 7.5 mA INPUT IF 60 IF = 10 mA, 15 mA IF = 3.75 mA tPHL tPLH OUTPUT VO 40 IF = 5.0 mA 20 Figure 6. Test Circuit for tPHL and t PLH. 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 5. Low Level Output Current vs. Temperature. 1.5 V OUTPUT VO MONITORING NODE 105 VCC = 5.0 V IF = 7.5 mA 80 tP – PROPAGATION DELAY – ns tP – PROPAGATION DELAY – ns 100 tPLH , RL = 4 KΩ tPHL , RL = 350 Ω 1 KΩ 60 4 KΩ tPLH , RL = 1 KΩ 40 tPLH , RL = 350 Ω 20 0 -60 -40 -20 0 20 40 80 100 60 Figure 7. Propagation Delay vs. Temperature. tr, tf – RISE, FALL TIME – ns VCC = 5.0 V TA = 25°C tPLH , RL = 4 KΩ 90 75 tPLH , RL = 350 Ω 60 tPLH , RL = 1 KΩ 45 30 tPHL , RL = 350 Ω 1 KΩ 4 KΩ 7 5 11 9 13 15 40 RL = 4 kΩ 30 VCC = 5.0 V IF = 7.5 mA 20 10 RL = 1 kΩ -10 -60 -40 -20 0 +5 V 1 290 VCC 6 A 60 5 VFF RL = 1 kΩ 40 3 RL = 350 Ω 0 -60 -40 -20 RL = 350 Ω, 1 kΩ, 4 kΩ 0 20 40 60 80 100 Figure 10. Rise and Fall Time vs. Temperature. GND 0.1 µF BYPASS 350 Ω OUTPUT VO MONITORING NODE 4 _ + PULSE GENERATOR ZO = 50 Ω TA – TEMPERATURE – °C VCM (PEAK) VCM 0V dVF/dT – FORWARD VOLTAGE TEMPERATURE COEFFICIENT – mV/°C VO 5V -2.4 VO 0.5 V -2.2 SWITCH AT A: IF = 0 mA Figure 11. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. -1.8 -1.6 -1.4 1 10 100 IF – PULSE INPUT CURRENT – mA Figure 12. Temperature Coefficient for Forward Voltage vs. Input Current. CMH VO (MIN.) SWITCH AT B: IF = 7.5 mA VO (MAX.) -2.0 -1.2 0.1 60 80 100 Figure 9. Pulse Width Distortion vs. Temperature. B 20 40 IF RL = 4 kΩ 300 20 TA – TEMPERATURE – °C Figure 8. Propagation Delay vs. Pulse Input Current. tRISE tFALL RL = 350 kΩ 0 IF – PULSE INPUT CURRENT – mA TA – TEMPERATURE – °C VCC = 5.0 V IF = 7.5 mA PWD – PULSE WIDTH DISTORTION – ns 7 CML 8 Propagation Delay, PulseWidth Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 15, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 11 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 16 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, and input current, and power supply ranges. ITH – INPUT THRESHOLD CURRENT – mA 9 6 5 VCC = 5.0 V VO = 0.6 V VCC1 5V 6 3 IF RL = 1 kΩ 0.1 µF BYPASS 3 4 20 40 60 80 100 GND 2 SHIELD 2 1 RL = 4 kΩ 0 1 VF GND 1 0 -60 -40 -20 5 *D1 2 1 * DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. TA – TEMPERATURE – °C Figure 13. Input Threshold Current vs. Temperature. Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit. DATA IF INPUTS 50% CLOCK 1.5 V VO IF DATA 50% OUTPUTS VO VCC 2 390 Ω 470 4 RL = 350 Ω 5V 1.5 V tPSK CLOCK tPSK Figure 15. Illustration of Propagation Delay Skew – tPSK. tPSK Figure 16. Parallel Data Transmission Example. www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies Obsoletes 5091-9635E (10/93) 5966-4942E (11/99)