AVAGO ACPL-061L

ACPL-061L, ACPL-064L, ACPL-M61L,
ACPL-W61L, ACPL-K64L
Ultra Low Power 10 MBd Digital CMOS Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The Avago ultra low power ACPL-x6xL digital optocouplers
combine an AlGaAs light emitting diode (LED) and an
integrated high gain photodetector. The optocoupler
consumes extremely low power, at maximum 1.3mA IDD2
current per channel across temperature. With a forward
LED current as low as 1.6 mA most microprocessors can
directly drive the LED.
x Ultra-low IDD current: 1.3 mA/channel maximum
An internal Faraday shield provides a guaranteed common
mode transient immunity specification of 20 kV/Ps.
Maximum AC and DC circuit isolation is achieved while
maintaining TTL/CMOS compatibility.
x Guaranteed AC and DC performance over wide
temperature: –40°C to +105°C
The optocouplers CMOS outputs are slew-rate controlled
and is designed to allow the rise and fall time to be controlled over a wide load capacitance range.
x Safety approval
– UL 1577 recognized – 3750 Vrms for 1 minute for
ACPL-061L/064L/M61L and 5000 Vrms* for 1 minute
for ACPL-W61L/K64L
– CSA Approval
– IEC/EN/DIN EN 60747-5-5 approval for Reinforced
Insulation (approved for ACPL-M61L, pending
approval for ACPL-064L/W61L/K64L/061L)
The ACPL-x6xL series operates from both 3.3 V and 5 V
supply voltages with guaranteed AC and DC performance
from –40°C to +105°C.
These low-power optocouplers are suitable for high speed
logic interface applications.
ACPL-M61L
Cathode
x Built-in slew-rate controlled outputs
x 20 kV/Ps minimum Common Mode Rejection (CMR) at
VCM = 1000 V
x High speed: 10 MBd minimum
x Wide package selection: SO-5, SO-8, stretched SO-6
and stretched SO-8
x RoHS compliant
Functional Diagrams
Anode
x Low input current: 1.6 mA
Applications
ACPL-064L
6
VDD
5
Vo
Anode1
1
8
VDD
Cathode1
2
7
Vo1
Cathode2
3
6
Vo2
Anode2
4
5
GND
1
3
4
GND
x Communication interfaces: RS485, CANBus and I2C
x Microprocessor system interfaces
x Digital isolation for A/D and D/A convertors
SHIELD
ACPL-061L^
NC
1
ACPL-W61L
8
VDD
n
ati7o NC
Anode 2
m
r
nfo
ry I
6 Vo
a
n
Cathode 3 limi
e
r
P
NC
4
SHIELD
5
GND
ACPL-K64L
Anode
1
6
VDD
NC*
2
5
Vo
Cathode
3
4
SHIELD
GND
TRUTH TABLE
(POSITIVE LOGIC)
Anode1
1
8
VDD
Cathode1
2
7
Vo1
LED
OUTPUT
Cathode2
3
6
Vo2
ON
L
Anode2
4
5
GND
OFF
H
SHIELD
* Pin 7 of the ACPL-061L is not connected
A 0.1 PF bypass capacitor must be connected between pins VDD and GND.
^ Advanced information, may subject to changes.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
The ACPL-061L, ACPL-064L and ACPL-M61L are UL Recognized with an isolation voltage of 3750 Vrms for 1 minute per
UL1577. The ACPL-W61L and ACPL-K64L are UL Recognized with an isolation voltage of 5000 Vrms for 1 minute per
UL1577. All devices are RoHS compliant.
Option
Part number
RoHS
Compliant
Package
Surface Mount
ACPL-061L^
-000E
SO-8
X
ACPL-064L
ACPL-M61L
ACPL-W61L
X
X
-560E
X
X
-000E
SO-8
X
-560E
X
X
X
X
X
X
-560E
-000E
-500E
Stretched
S08
-560E
X
1500 per reel
1500 per reel
X
1500 per reel
100 per tube
-560E
Stretched
S06
1500 per reel
X
-500E
-000E
Quantity
100 per tube
X
SO-5
IEC/EN/
DIN EN
60747-5-5
X
-500E
-000E
UL 5000 Vrms /
1 Minute
rating
100 per tube
-500E
-500E
ACPL-K64L
Tape
& Reel
X
1500 per reel
X
X
X
X
X
X
X
X
X
100 per tube
1000 per reel
X
X
X
X
X
X
X
X
1500 per reel
1000 per reel
80 per tube
1000 per reel
X
1000 per reel
To form an ordering part number, choose a part number from the part number column and combine it with the desired
option from the option column.
Example 1:
The part number ACPL-M61L-560E describes an optocoupler with a surface mount SO-5 package; delivered in Tape and
Reel with 1500 parts per reel; with IEC/EN/DIN EN 60747-5-5 Safety Approval; and full RoHS compliance.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
^ Advanced information, may subject to changes.
2
Package Outline Drawings
ACPL-061L and ACPL-064L SO-8 Package
8
7
6
5
5.994 ± 0.203
(0.236 ± 0.008)
XXXV
YWW
3.937 ± 0.127
(0.155 ± 0.005)
LAND PATTERN RECOMMENDATION
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
PIN ONE
1
2
3
4
0.406 ± 0.076
(0.016 ± 0.003)
1.9 (0.075)
1.270 BSC
(0.050)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
7°
45° X
0.432
(0.017)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
* Total package length (inclusive of mold flash)
5.207 ± 0.254 (0.205 ± 0.010)
Dimensions in Millimeters (Inches).
Lead coplanarity = 0.10 mm (0.004 inches) max.
Option number 500 not marked.
Note: Floating lead protrusion is 0.15 mm (6 mils) max.
0.203 ± 0.102
(0.008 ± 0.004)
0.305 MIN.
(0.012)
ACPL-M61L SO-5 Package
MXXX
XXX
4.4 ± 0.1
(0.173 ± 0.004)
7.0 ± 0.2
(0.276 ± 0.008)
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
2.5 ± 0.1
(0.098 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
0.216 ± 0.038
(0.0085 ± 0.0015)
7° MAX.
1.27 BSC
(0.050)
0.71
(0.028) MIN
Dimensions in Millimeters (Inches)
* Maximum mold flash on each side is 0.15 mm (0.006)
Note: Floating lead protrusion is 0.15 mm (6 mils) max.
3
MAX. LEAD COPLANARITY
= 0.102 (0.004)
ACPL-W61L Stretched SO-6 Package
LAND PATTERN RECOMMENDATION
12.65 (0.498)
1.27 (0.050) BSG
0.381 0.127
(0.015 0.005)
1
6
2
5
3
4
+0.127
6.807 0
(0.268 +0.005)
- 0.000
0.45 (0.018)
7°
45°
+0.254
4.580 0
+0.010
(0.180
)
- 0.000
0.76 (0.030)
1.91 (0.075)
1.590 0.127
(0.063 0.005)
7°
3.180 0.127
(0.125 0.005)
0.20 0.10
(0.008 0.004)
0.750 0.250
(0.0295 0.010)
11.50 0.250
(0.453 0.010)
Dimensions in Millimeters (Inches).
Lead coplanarity = 0.1 mm (0.004 inches).
ACPL-K63L Stretched SO-8 Package
LAND PATTERN RECOMMENDATION
12.650 (0.5)
1.270 (0.050) BSG
0.381 0.13
(0.015 0.005)
0.450 (0.018)
1
8
2
7
3
6
4
5
7°
45°
)
1.905 (0.1)
1.590 0.127
(0.063 0.005)
7°
6.807 0.127
(0.268 0.005)
11.5 0.250
(0.453 0.010)
4
(0.230
+0.25
0
+0.010
- 0.000
3.180 0.127
(0.125 0.005)
0.200 0.100
(0.008 0.004)
0.750 0.250
(0.0295 0.010)
5.850
Dimensions in Millimeters (Inches).
Lead coplanarity = 0.1 mm (0.004 inches).
Reflow Soldering Profile
The recommended reflow soldering conditions are per JEDEC Standard J-STD-020 (latest revision). Non-halide flux
should be used.
Regulatory Information
The ACPL-061L, ACPL-064L, ACPL-M61L, ACPL-W61L and ACPL-K64L are pending approval by the following organizations:
IEC/EN/DIN EN 60747-5-5 (Option 060 only)
UL
Approval under UL 1577 component recognition program up to VISO = 3750 VRMS for the ACPL-M61L/061L/064L and
VISO = 5000 VRMS for the ACPL-W61L/K64L, File E55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.
Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-061L
ACPL-064L
ACPL-M61L
ACPL-W61L
ACPL-K64L
Units
Conditions
Minimum External
Air Gap
(External Clearance)
L(101)
4.9
5
8
mm
Measured from input terminals to
output terminals, shortest distance
through air.
Minimum External
Tracking
(External Creepage)
L(102)
4.8
5
8
mm
Measured from input terminals to
output terminals, shortest distance
path along body.
0.08
0.08
0.08
mm
Through insulation distance
conductor to conductor, usually
the straight line distance thickness
between the emitter and detector.
175
175
175
V
DIN IEC 112/VDE 0303 Part 1
IIIa
IIIa
IIIa
Minimum Internal
Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking
Index)
Isolation Group
5
CTI
Material Group
(DIN VDE 0110, 1/89, Table 1)
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060)
Characteristic
Description
ACPL-061L^/
ACPL- 064L/
ACPL- M61L
Symbol
Installation classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 100 Vrms
I – IV
I – III
I – II
ACPL-W61L/
ACPL- K64L
Unit
I – IV
I – IV
I – III
I – III
Climatic Classification
55/105/21
55/105/21
Pollution Degree (DIN VDE 0110/39)
2
2
Maximum Working Insulation Voltage
VIORM
560
1140
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875=VPR, 100% Production Test with tm =1 sec,
Partial discharge < 5 pC
VPR
1063
2137
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6=VPR, Type and Sample Test, tm = 10 sec,
Partial discharge < 5 pC
VPR
896
1824
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
6000
8000
Vpeak
Safety-limiting values – maximum values allowed in the event of a failure.
Case Temperature
Input Current**
Output Power**
TS
IS, INPUT
PS, OUTPUT
150
150
600
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RS
>109
>109
:
*
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
** Refer to the following figure for dependence of PS and IS on ambient temperature.
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
105
°C
Reverse Input Voltage
VR
5
V
Supply Voltage
VDD
6.5
V
Average Forward Input Current
IF
–
8
mA
Peak Forward Input Current
(IF at 1 Ps pulse width, <10% duty cycle)
IF(TRAN)
–
1
A
≤1 Ps Pulse Width,
<300 pulses per second
80
mA
≤1 Ps Pulse Width,
<10% Duty Cycle
10
mA
Output Current
IO
Output Voltage
VO
VDD +0.5
V
Input Power Dissipation
PI
14
mW
Output Power Dissipation
PO
20
mW
Lead Solder Temperature
TLS
260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Package Outline Drawings section
6
–0.5
Condition
Recommended Operating Conditions
Parameter
Symbol
Min
Max
Operating Temperature
TA
- 40
105
°C
Input Current, Low Level
IFL
0
250
PA
Input Current, High Level
IFH
1.6
6.0
mA
Power Supply Voltage
VDD
2.7
Forward Input Voltage
VF (OFF)
Logic Low Input Voltage
VIL
0
Units
5.5
V
0.8
V
0.8
V
Electrical Specifications (DC)
Over the recommended temperature (TA = –40°C to +105°C) and supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specifications are at VDD = 5 V and TA = 25°C.
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Input Forward Voltage
VF
0.95
1.3
1.7
V
IF = 2 mA
Input Reverse
Breakdown Voltage
BVR
3
5
V
IR = 10 PA
Logic High Output Voltage
VOH
VDD - 0.1
VDD
V
IF = 0 mA, VI = 0 V (RT = 1.68 k:) or
(RT = 870 :), IO = -20 PA
Figure 11
VDD - 1.0
VDD
V
IF = 0 mA, VI = 0 V (RT = 1.68 k:) or
(RT = 870 :), IO = -3.2 mA
Figure 11
Logic Low Output Voltage
VOL
0.03
0.1
V
IF = 2 mA, VI = 5 V (RT = 1.68 k:) or
VI = 3.3V (RT = 870 :), IO = 20 PA
Figure 11
0.18
0.4
V
IF = 2 mA, VI = 5 V (RT = 1.68 k:) or
VI = 3.3V (RT = 870 :), IO = 3.2 mA
Figure 11
Input Threshold Current
ITH
0.7
1.3
mA
Logic Low Output Supply
Current
IDDL
0.8
1.3
mA
Logic High Output Supply
Current
IDDH
0.8
1.3
mA
Input Capacitance
CIN
60
pF
f = 1 MHz, VF = 0 V
Input Diode Temperature
Coefficient
'VF/'TA
-1.6
mV/°C
IF = 2 mA
7
Switching Specifications (AC)
Over the recommended temperature (TA = –40°C to +105°C) and supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specifications are at VDD = 5 V, TA = 25°C.
Parameter
Symbol
Propagation Delay Time
to Logic Low Output [1]
Typ
Max
Units
Test Conditions
tPHL
46
80
ns
IF = 2 mA, VI = 5 V, RT = 1.68 k:,
CL = 15 pF, CMOS Signal Levels.
Propagation Delay Time
to Logic High Output [1]
tPLH
40
80
ns
Pulse Width
tPW
Pulse Width Distortion [2]
PWD
Propagation Delay Skew [3]
tPSK
Output Rise Time
(10% – 90%)
tR
Output Fall Time
(90% - 10%)
Min
100
ns
6
tF
30
ns
30
ns
IF = 2 mA, VI = 3.3 V, RT = 870 :,
CL = 15 pF, CMOS Signal Levels.
Figure 11
12
ns
IF = 2 mA, VI = 5 V, RT = 1.68 k:,
CL = 15 pF, CMOS Signal Levels.
Figure 11
10
ns
IF = 2 mA, VI = 3.3 V, RT = 870 :,
CL = 15 pF, CMOS Signal Levels.
Figure 11
12
ns
IF = 2 mA, VI = 5 V, RT = 1.68 k:,
CL = 15 pF, CMOS Signal Levels.
Figure 11
10
ns
IF = 2 mA, VI = 3.3 V, RT = 870 :,
CL = 15 pF, CMOS Signal Levels.
Figure 11
Static Common Mode
Transient Immunity at
Logic High Output [4]
| CMH |
20
35
kV/Ps
VCM = 1000 V, TA = 25°C, IF = 0 mA,
VI = 0 V (RT =1.68 k:) or (RT = 870:),
CL = 15 pF, CMOS Signal Levels.
Figure 11
Static Common Mode
Transient Immunity at
Logic Low Output [5]
| CML |
20
35
kV/Ps
VCM = 1000 V, TA = 25°C, VI = 5 V
(RT = 1.68 k:) or VI = 3.3 V
(RT = 870:), IF = 2 mA, CL= 15 pF,
CMOS Signal Levels.
Figure 11
Dynamic Common Mode
Transient Immunity [6]
CMRD
35
kV/Ps
VCM = 1000 V, TA = 25°C, IF = 2 mA,
VI = 5 V (RT = 1.68 k:) or VI = 3.3 V
(RT = 870:), 10MBd datarate, the
absolute increase of PWD < 10ns
Figure 11
8
Package Characteristics
All typicals are at TA = 25°C.
Parameter
Symbol
Part Number
Min
Input-Output Insulation
VISO
ACPL-061L^
ACPL-064L
ACPL-M61L
3750
ACPL-W61L
ACPL-K64L
5000
Typ
Max
Units
Test Conditions
Vrms
RH < 50% for 1 min.
TA = 25°C
Input-Output Resistance
RI-O
1012
:
VI-O = 500 V
Input-Output Capacitance
CI-O
0.6
pF
f = 1 MHz, TA = 25°C
^ Advanced information, may subject to changes.
Notes:
1. tPHL propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% VDD of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% level of the rising edge of the VO
signal.
2. PWD is defined as |tPHL - tPLH|.
3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
6. CMD is the maximum tolerable rate of the common mode voltage during data transmission to assure that the absolute increase of the PWD is less
than 10 ns.
9
1
Ith - INPUT THRESHOLD CURRENT - mA
IF - FORWARD CURRENT - mA
10
TA = 25°C
1
IF
0.1
VF
0.01
1.1
0.6
0.4
0.2
1.3
1.4
VF - FORWARD VOLTAGE - V
1.5
40
TA - TEMPERATURE - °C
80
120
Figure 3. Typical logic high output supply current versus temperature.
20
40
60
80
TA - TEMPERATURE - °C
100
120
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
3.3V
5V
0
40
80
TA - TEMPERATURE - °C
120
60
tp - PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION - ns
tp - PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION - ns
0
Figure 4. Typical logic low output supply current versus temperature.
60
50
40
30
20
TPHL_5.0V
TPLH_5.0V
PWD_5.0V
10
0
1.5
2
2.5
3 3.5
4 4.5
5
IF - PULSE INPUT CURRENT - mA
5.5
Figure 5. Typical switching speed versus pulse input with a 5 V supply
voltage.
10
-20
Figure 2. Typical input threshold current versus temperature.
3.3V
5V
0
-40
IDDL - LOGIC LOW OUTPUT SUPPLY
CURRENT - mA
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
-10
3.3v
5v
0
1.2
Figure 1. Typical input diode forward current characteristic.
IDDH - LOGIC HIGH OUTPUT SUPPLY
CURRENT - mA
0.8
6
50
40
30
20
TPHL_3.3V
TPLH_3.3V
PWD_3.3V
10
0
-10
1.5
2
2.5
3 3.5
4 4.5
5
IF - PULSE INPUT CURRENT -mA
5.5
Figure 6. Typical switching speed versus pulse input current with a 3.3 V
supply voltage.
6
Supply Bypassing, LED Bias Resistors and PC Board
Layout
1.8
VF - FORWARD VOLTAGE - V
1.7
The ACPL-x6xL optocouplers are extremely easy to use
and feature high speed, push-pull CMOS outputs. Pull-up
resistors are not required.
1.6
1.5
1.4
The external components required for proper operation
are the input limiting resistors and the output bypass
capacitor. Capacitor values should be 0.1 PF.
1.3
1.2
1.1
1
-40
-20
0
20
40
60
TA - Temperature - °C
80
For each capacitor, the total lead length connecting the
capacitor to the VDD and GND pins should not exceed
20 mm.
100
Figure 7. Typical VF versus temperature.
For ACPL-M61L/W61L:
For ACPL-061L/064L/K64L:
VDD = 3.3 V: R1 = 510 : ± 1%, R2 = 360 : ± 1%
VDD = 3.3 V: R1 = 430 : ± 1%, R2 = 430 : ± 1%
VDD = 5.0 V: R1 = 1000 : ± 1%, R2 = 680 : ± 1%
VDD = 5.0 V: R1 = 845 : ± 1%, R2 = 845 : ± 1%
RT = R1 + R2 R1/R2 ≈ 1.5
RT = R1 + R2
VI
R1 IF
1
VDD
6
5
VI
Vo
R2
GND1
R2
3
GND1
R1 IF
4
GND2
1
8
VDD
2
7
Vo
XXX
YWW
XXX
YWW
C
3
4
C
GND1
GND2
3
4
GND2
VI
ACPL-W61L
1
8
VDD
2
7
Vo1
R2
R1 IF
3
4
6
5
ACPL-064L/K64L
C = 0.1PF
Figure 8. Recommended printed circuit board layout and input current limiting resistor selection.
11
GND2
R2
Vo
R2
GND1
R1 IF
XXX
YWW
5
VI
VDD
6
XXX
YWW
2
C
ACPL-061L
R1 IF
1
6
5
ACPL-M61L
VI
R1/R2 ≈ 1
C
Vo2
GND2
Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew
Propagation delay is a figure of merit which describes how
quickly a logic signal propagates through a system. The
propagation delay from low-to-high (tPLH) is the amount
of time required for an input signal to propagate to the
output, causing the output to change from low to high.
Similarly, the propagation delay from high-to-low (tPHL)
is the amount of time required for the input signal to
propagate to the output, causing the output to change
from high-to-low (see Figure 9).
Pulse-width distortion (PWD) results when tPLH and tPHL
differ in value. PWD is defined as the difference between
tPLH and tPHL. PWD determines the maximum data rate of
a transmission system. PWD can be expressed in percent
by dividing the PWD (in ns) by the minimum pulse width
(in ns) being transmitted. Typically, a PWD of 20-30% of
the minimum pulse width is tolerable; the exact figure
depends on the particular application (RS232, RS422,
T-1, etc.).
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applications where synchronization of signals on parallel data lines is a concern.
If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
different times. If this difference in propagation delays is
large enough, it will determine the maximum rate at which
parallel data can be sent through the optocouplers.
Propagation delay skew is defined as the difference
between the minimum and maximum propagation
delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions
(i.e., the same supply voltage, output load, and operating
temperature). As shown in Figure 10, if the inputs of a
VI
50%
group of optocouplers are switched either ON or OFF at
the same time, tPSK is the difference between the shortest
propagation delay, either tPLH or tPHL, and the longest
propagation delay, either tPLH or tPHL. As mentioned
earlier, tPSK can determine the maximum parallel data
transmission rate.
Figure 10 is the timing diagram of a typical parallel data
application with both the clock and the data lines being
sent through optocouplers. The figure shows data and
clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both
edges of the clock signal are being used to clock the data;
if only one edge were used, the clock signal would need
to be twice as fast.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an
optocoupler.
Figure 10 shows that there will be uncertainty in both
the data and the clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived.
From these considerations, the absolute minimum pulse
width that can be sent through optocouplers in a parallel
application is twice tPSK. A cautious design should use a
slightly longer pulse width to ensure that any additional
uncertainty in the rest of the circuit does not cause a
problem.
The tPSK specified optocouplers offer the advantages of
guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the
recommended temperature, and power supply ranges.
DATA
INPUTS
2.5 V,
CMOS
VO
CLOCK
tPSK
VI
50%
DATA
OUTPUTS
tPSK
CLOCK
VO
2.5 V,
CMOS
tPSK
Figure 9. Propagation delay skew waveform
12
Figure 10. Parallel data transmission example
Optocoupler CMR Performance
The principal protection against common mode noise,
comes from the fundamental isolation properties of the
optocoupler, and this in turn is directly related to the
Input-Output leakage capacitance of the optocoupler.
To provide maximum protection to circuitry connected to
the input or output of the optocoupler the leakage capacitance is minimized by having large separation distances
at all points in the optocoupler construction, including
the LED/photodiode interface.
In addition to the optocouplers basic physical construction, additional circuit design steps mitigate the effects of
common mode noise. The most important of these is the
Faraday shield on the photodetector stage.
A Faraday shield is effective in optocouplers because
the internal modulation frequency (light) is many orders
of magnitude higher than the common mode noise
frequency.
Improving CMR Performance at the Application Level
In an end application it desirable that the optocouplers
common mode isolation be as close as possible to that
indicated in the data sheet specifications. The first step
in meeting this goal is to ensure maximum separation
between PCB interconnects on either side of the optocoupler is maintained and that PCB tracks beneath the
optocoupler are avoided.
It is inevitable that a certain amount of CMR noise will be
coupled into the inputs and this can potentially result in
false-triggering of the input. This problem is frequently
observed in devices with input high input impedance.
In some cases this can cause momentary missing pulses
and may even cause input circuitry to latch-up in some
alternate technologies.
The ACPL-x6xL optocoupler family does not have an input
latch-up issue. Even at very high CMR levels such as those
experienced in end equipment level tests (for example
IEC61000-4-4) the ACPL-x6xL series is immune to latch-up
because of the simple diode structure of the LED.
In some cases achieving the rated data sheet CMR performance level is not possible in an application. This is
often because of the practical need to actually connect
the isolator input to the output of a dynamically changing
signal rather than tying the input statically to VDD or GND.
A data sheet CMR “specmanship” issue is often seen with
alternative technology isolators that are based on AC
encoding techniques.
13
To address the need to define achievable end application
performance on data sheets, the ACPL-x6xL optocouplers
include an additional typical performance specification
for dynamic CMR in the electrical parameter table. The
dynamic CMR specification indicates the typical achievable CMR performance as the input is being toggled on or
off during a CMR transient.
The logic output the ACPL-x6xL optocouplers is mainly
controlled by LED current level, and since the LED current
features very fast rise and fall times, dynamic noise
immunity is essentially the same as static noise immunity.
Despite their immunity to input latch-up and the
excellent dynamic CMR immunity, ACPL-x6xL optocoupler devices are still potentially vulnerable to missoperation caused by the LED being turned either on
or off during a CMR disturbance. If the LED status could
be ensured by design, the overall application level CMR
performance would be that of the photodetector. To
benefit from the inherently high CMR capabilities of the
ACPL-x6xL family, some simple steps about operating the
LED at the application level should be taken.
In particular, ensure that the LED stays either on or off
during a CMR transient. Some common design techniques
to accomplish this are:
Keep the LED On:
i) Overdrive the LED with a higher than required forward
current.
Keep the LED Off:
i) Reverse bias the LED during the off state.
ii) Minimize the off-state impedance across the anode
and cathode of the LED during the off state.
All these methods allow the full CMR capability of the
ACPL-x6xL family to be achieved, but they do have
practical implementation issues or require a compromise
on power consumption.
There is, however, an effective method to meet the goal
of maintaining the LED status during a CMR event with
no other design compromises other than adding a single
resistor.
This CMR optimization takes advantage of the differential
connection to the LED. By ensuring the common mode
impedances at both the cathode and anode of the LED
are equal, the CMR transient on the LED is effectively
canceled. As shown in Figure 11, this is easily achieved by
using two, instead of one, input bias resistors.
Split LED Bias Resistor for Optimum CMR
Figure 11 shows the recommended drive circuit for the
ACPL-x6xL that gives optimum common-mode rejection.
The two current setting resistors balance the common
mode impedances at the LED’s anode and cathode.
Common-mode transients can capacitively couple from
the LED anode (or cathode) to the output-side ground
causing current to be shunted away from the LED (which
is not wanted when the LED should be on) or conversely
cause current to be injected into the LED (which is not
wanted when the LED should be off ).
Figure 12 shows the parasitic capacitances (CLA and
CLC) between the LED’s anode and cathode, and output
ground. Also shown in Figure 12 on the input side is an
AC-equivalent circuit.
switching threshold (ITH), CML also depends on the extent
to which ILP and ILN balance each other. In other words,
any condition where a common-mode transient causes a
momentary decrease in IF (i.e. when dVCM/dt > 0 and |IFP|
> |IFN|, referring to Table 1). will cause a common-mode
failure for transients which are fast enough.
Likewise for a common-mode transient that occurs when
the LED is off (i.e. CMH, since the output is at "high" state),
if an imbalance between ILP and ILN results in a transient
IF equal to or greater than the switching threshold of the
optocoupler, the transient “signal” may cause the output
to spike below 2 V, which constitutes a CMH failure.
Table 1 shows the directions of ILP and ILN depend on the
polarity of the common-mode transient. For transients
occurring when the LED is on, common-mode rejection
(CML, since the output is at "low" state) depends on
LED current (IF). For conditions where IF is close to the
The resistors recommended in Figure 11 include both
the output impedance of the logic driver circuit and
the external limiting resistor. The balanced ILED-setting
resistors help equalize the common mode voltage change
at the anode and cathode. This reduces ILED changes
caused by transient coupling through the parasitic capacitors CLA and CLC shown in Figure 12.
For ACPL-M61L/W61L:
For ACPL-061L/064L/K64L:
VDD2 = 3.3 V: R1 = 510 : ± 1%, R2 = 360 : ± 1%
VDD = 3.3 V: R1 = 430 : ± 1%, R2 = 430 : ± 1%
VDD2 = 5.0 V: R1 = 1000 : ± 1%, R2 = 680 : ± 1%
VDD = 5.0 V: R1 = 845 : ± 1%, R2 = 845 : ± 1%
RT = R1 + R2 R1/R2 ≈ 1.5
RT = R1 + R2
R1/R2 ≈ 1
R1
VDD2
VDD
VO
0.1PF
R2
74LS04 or any
totem-pole output
logic gate
Shield
GND1
Figure 11. Recommended high-CMR drive circuit for the ACPL-x6xL.
14
GND2
For ACPL-M61L/W61L:
For ACPL-061L/064L/K64L:
VDD2 = 3.3 V: R1 = 510 : ± 1%, R2 = 360 : ± 1%
VDD = 3.3 V: R1 = 430 : ± 1%, R2 = 430 : ± 1%
VDD2 = 5.0 V: R1 = 1000 : ± 1%, R2 = 680 : ± 1%
VDD = 5.0 V: R1 = 845 : ± 1%, R2 = 845 : ± 1%
RT = R1 + R2
RT = R1 + R2
R1/R2 ≈ 1.5
R1/R2 ≈ 1
VDD2
R1
ILP
VO
CLA
0.1PF
R2
ILN
CLC
GND2
Shield
Figure 12. AC equivalent circuit of ACPL-x6xL.
Table 1. Common Mode Pulse Polarity and LED Current Transients
If |ILP| < |ILN|
LED current IF
is momentarily:
If |ILP| > |ILN|
LED Current IF
is momentarily:
If dVCM/dt Is:
Then ILP flows:
and ILN flows:
positive (> 0)
away from the LED
anode through CLA
away from the LED
cathode through CLC
increased
decreased
negative (< 0)
toward the LED
anode through CLA
toward the LED
cathode through CLC
decreased
increased
15
Glitch Free Power-up and Power-Down Feature.
25
Rise Time (nS)
Upon Powering-up or Powering-down of the optocoupler,
glitches produced in the output are undesirable. Glitches
can lead to false data in the optocoupler application.
ACPL-x6xL has a feature that holds the output in a known
state until VDD is at a safe level. Figure 13 and 14 show
typical output waveforms during Power-up and Powerdown process.
Rise Time (VDD = 5.0V)
30
20
15
10
10pF
33pF
5
Slew-rate controlled outputs Feature
15pF
47pF
22pF
100pF
0
-40
-20
0
20
40
Temperature (°C)
60
80
100
60
80
100
Fall Time (VDD = 5.0V)
25
20
Fall Time (nS)
Typically, the output slew rate (rise and fall time) will vary
with the output load, as more time is needed to charge up
the higher load. The propagation delay and the PWD will
increase with the load capacitance. This will be an issue
especially in parallel communication because different
communication line will have different load capacitances.
However, Avago’s new optocoupler ACPL-x6xL has built in
slew-rate controlled feature, to ensure that the output rise
and fall time remain stable across wide load capacitance.
Figure 15 shows the rise time and fall time for ACPL-x6xL
at 3.3V and 5V.
15
10
5
0
10pF
33pF
-40
-20
15pF
47pF
0
20
40
Temperature (°C)
VDD2
VDD2 =1V (typ)
22pF
100pF
Rise Time (V DD = 3.3V)
25
500μs
High
Impedence
20
Rise Time (nS)
Output
High
Impedence
i. LED is off
15
10
10pF
33pF
5
Figure 13. VDD Ramp when LED is off.
15pF
47pF
22pF
100pF
0
-40
VDD2 =2V (typ)
-20
0
20
40
Temperature (°C)
60
80
100
Fall Time (V DD = 3.3V)
VDD2
25
VDD2 =1V (typ)
Output
High
Impedence
15
10
10pF
33pF
5
500μs
ii. LED is on
Figure 14. VDD Ramp when LED is on.
16
High
Impedence
Rise Time (nS)
20
discharge delay,
depending on the power
supply slew rate
15pF
47pF
22pF
100pF
0
-40
-20
0
20
40
Temperature (°C)
60
80
100
Figure 15. Rise and Fall time of ACPL-x6xL across wide load capacitance
Speed Improvement
V DD2 = 5 V, I F = 2 mA
T PHL
50
t P or PWD (ns)
A peaking capacitor can be placed across the input current
limit resistor (Figure 11) to achieve enhanced speed performance. The value of the peaking cap is dependent
to the rise and fall time of the input signal and supply
voltages and LED input driving current (IF). Figure 12
shows significant improvement of propagation delay and
pulse with distortion with added peak capacitor at driving
current of 2mA and 3.3V/5V power supply.
60
40
T PHL
0
-40
-20
0
20
40
Temp (°C)
60
80
100
(i) VDD2 = 5V, Cpeak = 47pF, R1 = 845Ω
R1
VO
0.1μF
−
VDD2 = 3.3 V, I F = 2 mA
60
T PHL
50
SHIELD
GND 2
Figure 16. Connection of peaking capacitor (Cpeak) in parallel of the input
limiting resistor (R1) to improve speed performance
t P or PWD (ns)
R2
GND 1
No Peaking
With Peaking
PWD
20
V DD2
Vin
T PLH
30
10
C peak
+
T PLH
T PLH
40
30
No Peaking
With Peaking
T PLH
T PHL
20
10
0
-40
PWD
-20
0
20
40
Temp (°C)
60
80
100
(ii) VDD2 = 3.3V, Cpeak = 47pF, R1 = 430Ω
Figure 17. Improvement of tp and PWD with added 47pF peaking capacitor
in parallel of input limiting resistor.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, the A logo and R2Coupler™ are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved.
AV02-2150EN - April 8, 2010