Precision Wide Range (3 nA to 3 mA) High-Side Current Mirror ADL5315 FEATURES Accurately mirrors input current (1:1 ratio) over 6 decades Linearity 1% from 3 nA to 3 mA Stable mirror input voltage Voltage held 1 V below supply using internal reference or can be set externally Adjustable input current limit 2.7 V to 8 V single-supply operation Miniature 8-lead LFCSP (2 mm × 3 mm) FUNCTIONAL BLOCK DIAGRAM ADL5315 VOLTAGE REFERENCE 4 CURRENT LIMITING COMM 20kΩ 3 RLIM CURRENT MIRROR 1:1 5 6 SREF VPOS VSET NC 2 7 APPLICATIONS IOUT INPT 1 8 IPD IPD 05694-001 Optical power monitoring from a single photodiode General voltage biasing with precision current monitoring Voltage-to-current conversion Figure 1. GENERAL DESCRIPTION The ADL5315 is a wide input current range, precision high-side current mirror featuring a stable and user-adjustable input voltage. It is optimized for use with PIN photodiodes, but its flexibility and wide operating range make it suitable for a broad array of additional applications. Over the 3 nA to 3 mA range, the current sourced from the INPT pin is accurately mirrored with a 1:1 ratio and sourced from the IOUT output pin. In a typical photodiode application, the output drives a currentinput logarithmic amplifier to produce a linear-in-dB output representing the optical power incident upon the photodiode. For linear voltage output, a single resistor to ground is all that is required. The photodiode anode can be connected to a high speed transimpedance amplifier for the extraction of the data stream. The voltage at the INPT pin is temperature stable with respect to the voltage at the VSET input pin, which it tracks. A temperature stable reference voltage is provided at the SREF pin, which, when tied to VSET, fixes the voltage at INPT 1.0 V below VPOS. VSET can also be driven from an external source. The VSET input has very low input current and can be driven as low as the bottom rail, facilitating nonloading voltage-tocurrent conversion as well as minimizing dark current in photodiode applications. The ADL5315 also features adjustable input current limiting using an external resistor from RLIM to VPOS. The maximum current sourced by INPT (and IOUT) can be set between 1 mA and 16 mA, beyond which the voltage at INPT falls rapidly from its setpoint. Connecting RLIM directly to VPOS provides basic input short-circuit protection with the default current limit of 16 mA typical. The ADL5315 is available in a 2 mm × 3 mm, 8-lead LFCSP and is specified for operation from −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADL5315 TABLE OF CONTENTS Features .............................................................................................. 1 Noise Performance ..................................................................... 10 Applications....................................................................................... 1 Mirror Response Time............................................................... 10 Functional Block Diagram .............................................................. 1 Input Current Limiting.............................................................. 10 General Description ......................................................................... 1 Applications..................................................................................... 11 Revision History ............................................................................... 2 Average Power Monitoring ....................................................... 11 Specifications..................................................................................... 3 Translinear Log Amp Interfacing............................................. 12 Absolute Maximum Ratings............................................................ 4 Extended Operating Range....................................................... 13 ESD Caution.................................................................................. 4 Using RLIM as a Secondary Monitor ...................................... 13 Pin Configuration and Function Descriptions............................. 5 Characterization Methods ........................................................ 14 Typical Performance Characteristics ............................................. 6 Evaluation Board ............................................................................ 16 Theory of Operation ........................................................................ 9 Outline Dimensions ....................................................................... 17 Bias Control Interface .................................................................. 9 Ordering Guide .......................................................................... 17 REVISION HISTORY 10/05—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADL5315 SPECIFICATIONS VPOS = 5 V, VSET = 4 V, IINPT = 3 μA, TA = 25°C, unless otherwise noted. Table 1. Parameter CURRENT MIRROR OUTPUT Current Gain from INPT to IOUT Current Gain from INPT to IOUT Nonlinearity Small Signal Bandwidth Wideband Noise at IPDM Specified Output Voltage Range IOUT × ROUT Product MIRROR INPUT, VOLTAGE CONTROL Specified Input Current Range, IINPT Specified VSET Voltage Range Incremental Gain from VSET to INPT Incremental Input Resistance at VSET Input Bias Current at VSET SREF Voltage, Relative to VPOS OVERCURRENT PROTECTION INPT Current Limit POWER SUPPLY Supply Voltage Range Quiescent Current Conditions IOUT (Pin 8) −40°C < TA < +85°C 3 nA < IPD < 3 mA IINPT = 3 nA IINPT = 3 μA IINPT = 3 μA, CSET = 2.2 nF Min Typ Max 0.99 0.97 1.00 1.00 0.25 1 1 20 1.01 1.03 1.00 0 IINPT = 3 μA INPT (Pin 1), VSET (Pin 2), SREF (Pin 3) Flows from INPT pin 2.7 V < VPOS < 6.5 V 6.5 V < VPOS < 8 V 0.2 V < VSET < 7.0 V VSET = 4.0 V VSET = 4.0 V 2.7 V < VPOS < 8 V VINPT drops to 0 V, RLIM = 0 Ω VINPT drops to 0 V, RLIM = 3 kΩ VPOS (Pin 6) VPOS − 1 900 3n 0 VPOS − 6.5 0.98 −0.97 16 8 9.6 mA mA 1.8 8.3 8 2.2 10.2 V mA mA −1.04 6.4 2.7 IINPT = 3 μA IINPT = 3 mA Rev. 0 | Page 3 of 20 A/A % kHz MHz nA rms V V A V V V/V GΩ pA V 1 >100 <30 −1.0 3m VPOS − 1 VPOS − 1 1.02 Unit ADL5315 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Input Current at INPT Internal Power Dissipation θJA (Soldered Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Rating 8V 20 mA 500 mW 80°C/W 125°C −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 4 of 20 ADL5315 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADL5315 7 NC SREF 3 TOP VIEW (Not to Scale) 6 VPOS COMM 4 5 RLIM NC = NO CONNECT 05694-002 8 IOUT INPT 1 VSET 2 Figure 2. 8-Lead LFCSP Table 3. Pin Function Descriptions Pin No. 1 2 Mnemonic INPT VSET 3 SREF 4 5 6 7 8 COMM RLIM VPOS N/C IOUT PADDLE Description Input Current. Pin sources current only. Sets Voltage at INPT (Gain = 1). Range 0 V to VPOS − 1.0 V for VPOS < 6.5 V. For VPOS ≥ 6.5 V range, VPOS − 6.5 V to VPOS − 1 V. Optional shielding of INPT trace. Reference Voltage for VSET. Internally generated at VPOS − 1.0 V through 20 kΩ. Can be shorted to VSET for standard mirror operation. Analog Ground. External Resistor to VPOS. Sets current limit at INPT from 1 mA to 16 mA. ILIM = 48 V/(RLIM + 3 kΩ). Positive Supply (2.7 V to 8.0 V). Optional Shielding of IOUT Trace. No connection to die. Output Current. Mirrors current at INPT with a gain of 1.0. Sources current only. Internally connected to COMM, solder to ground. Rev. 0 | Page 5 of 20 ADL5315 TYPICAL PERFORMANCE CHARACTERISTICS VPOS = 5 V, VSET = VSREF, VOUT = 0 V, TA = 25°C, unless otherwise noted. 1.0 10m 2.0 1m 1.5 LINEARITY (%) 1μ IOUT (A) 0.5 0 1m 1.0 100μ 10μ 10m IINPT VS. IOUT, ALL VOLTAGE CONDITIONS –0.5 100μ 0.5 10μ 0 1μ –0.5 100n 100n –1.0 –1.0 10n –1.5 10n 100n 1μ 10μ 100μ 1n 10m 1m VPOS = 2.7V, VSET = VSREF VPOS = 5V, VSET = 2V VPOS = 5V, VSET = VSREF VPOS = 8V, VSET = 2V VPOS = 8V, VSET = VSREF –1.5 –2.0 1n 05694-003 –2.0 1n IOUT (A) 1.5 IINPT (A) 10n 100n 1μ 10μ 100μ 10n 1n 10m 1m IINPT (A) Figure 3. IOUT Linearity vs. IINPT for Multiple Temperatures, Normalized to 25°C and IINPT = 3 μA Figure 6. IOUT Linearity vs. IINPT for Multiple Supply Conditions, Normalized to VPOS = 5 V, VSET = VSREF, and IINPT = 3 μA 3 40 –40°C +25°C +85°C 2 20 1 0 –1 –20 –40 –40°C, VPOS = 2.7V, VSET = VSREF –40°C, VPOS = 5V, VSET = 0V –40°C, VPOS = 5V, VSET = VSREF +25°C, VPOS = 2.7V, VSET = VSREF +25°C, VPOS = 5V, VSET = 0V +25°C, VPOS = 5V, VSET = VSREF +85°C, VPOS = 2.7V, VSET = VSREF +85°C, VPOS = 5V, VSET = 0V +85°C, VPOS = 5V, VSET = VSREF –60 –80 –2 –100 10n 100n 1μ 10μ 100μ 1m 10m IINPT (A) –120 1n 05694-021 –3 1n 10μ 100μ 1m 10m 1nA VPOS = 3.0V 100pA 3.6mA 360μA NSD (A rms/√Hz) VPOS = 7.8V 1.0 0.5 36μA 10pA 360nA 36nA 100fA 3.6nA 100n 1μ 10μ IINPT (A) 100μ 1m 10m 05694-016 10fA 10n Figure 5. Output Wideband Current Noise as a Percentage of IOUT vs. IINPT for Multiple Values of VPOS, CSET = 2.2 nF, BW = 10 MHz Rev. 0 | Page 6 of 20 3.6μA 1pA 1fA 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz FREQUENCY Figure 8. Output Current Noise Density vs. Frequency for Multiple Values of IINPT, VPOS = 4.6 V, VSET = VSREF, CSET = 2.2 nF 05694-007 VPOS = 4.6V 2.0 0 1n 1μ Figure 7. VINPT Variation vs. IINPT for Multiple Temperatures and Voltage, Normalized to VPOS = 5 V, VSET = VSREF, IINPT = 3 μA and 25°C 3.0 1.5 100n IINPT (A) Figure 4. IOUT Linearity vs. IINPT for Multiple Temperatures and Devices Normalized to 25°C and IINPT = 3 μA 2.5 10n 05694-005 VINPT VARIATION (mV) LINEARITY (%) 0 WIDEBAND CURRENT NOISE (%) LINEARITY (%) +25°C, +70°C, +85°C, 0°C, –40°C –40°C 0°C +25°C +70°C +85°C 05694-006 2.0 ADL5315 20 20 15 15 +3 SIGMA 10 5 VINPT DRIFT (mV) AVERAGE 0 –5 +3 SIGMA 5 AVERAGE 0 –5 –10 –10 –3 SIGMA –3 SIGMA –15 –15 0 10 20 30 40 50 60 70 90 80 –20 –40 –30 –20 –10 05694-019 –20 –40 –30 –20 –10 TEMPERATURE (°C) Figure 9. Temperature Drift of VINPT with VSET = VSREF, 3-σ to Either Side of Mean 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) Figure 12. Temperature Drift of VINPT with VSET = 4 V (External Voltage Source), 3-σ to Either Side of Mean 10m 10 5 1m 300μA TO 3mA: T-RISE = <10ns, T-FALL = <300ns 100μ 30μA TO 300μA: T-RISE = <10ns, T-FALL = <300ns 10μ 3μA TO 30μA: T-RISE = <10ns, T-FALL = <1μs 1μ 300nA TO 3nA: T-RISE = <20ns, T-FALL = <5μs 100n 30nA TO 300nA: T-RISE = <5μs, T-FALL = <25μs 0 3μA 30nA –5 3mA 300μA –15 300nA 3nA IOUT (A) –10 30μA –20 –25 –30 10n 100k 1M 10M 100M 1000M FREQUENCY (Hz) T-RISE FOR ALL CURRENTS ≤ 200ns 100nA T-FALL ≤ 9.5ms 3.0 2.5 2.0 1.5 1.0 10μA T-FALL ≤ 180μs 0.5 0 –1.0 0 1 2 3 4 5 6 7 8 9 TIME (ms) 10 05694-018 1mA T-FALL ≤ 600ns –0.5 100 150 200 250 300 350 400 TIME (μs) 4.0 3.5 50 0 Figure 13. Pulse Response of IINPT to IOUT for IOUT in Decades from 3 nA to 3 mA Figure 10. Small-Signal AC Response of IINPT to IOUT for IINPT in Decades from 3 nA to 3 mA 4.5 1n Figure 11. Pulse Response of VSET to VINPT (VSET Pulsed from 0 V to 4 V) for Multiple Values of IINPT 10 ILIM = 48/(RLIM + 3kΩ) 8 VPOS = 2.7V, VSET = VSREF 6 VPOS = 5V, VSET = VSREF 4 2 0 –2 VPOS = 8V, VSET = VSREF –4 –6 –8 –10 0 10 20 30 40 50 RLIM (kΩ) 60 70 80 90 100 05694-020 10k ERROR FROM CALCULATED CURRENT LIMIT (%) 1k 05694-008 –40 100 05694-017 3nA TO 30nA: T-RISE = <100μs, T-FALL = <200μs –35 VINPT (V) NORMALIZED RESPONSE (dB) 0 05694-022 VINPT DRIFT (mV) 10 Figure 14. Current Limit Error in Percent vs. RLIM for Multiple Voltages Rev. 0 | Page 7 of 20 ADL5315 35 1.010 N = 2027 MEAN = –1.00696 SD = 0.00389073 30 1.005 20 +25 (%) VPOS – VINPT (V) 25 +85 1.000 –40 15 10 0.995 2 3 4 5 6 7 VPOS (V) 8 0 –0.97 05694-004 0.990 –0.98 –0.99 –1.00 –1.01 –1.02 –1.03 VSREF – VPOS (V) Figure 15. VPOS − VINPT vs. VPOS for Multiple Temperatures 05694-033 5 Figure 17. Distribution of VSREF − VPOS for VPOS = 5 V and IINPT = 3 μA 25 25 N = 2014 MEAN = 1.00251 SD = 0.00175921 N = 2034 MEAN = 0.00122744 SD = 0.00403179 20 15 15 10 10 5 5 0.993 0.996 0.999 1.002 IOUT/IINPT (A/A) 1.005 1.008 0 –0.03 05694-032 0 0.99 Figure 16. Distribution of IOUT/IINPT for VPOS = 5 V, VSET = 4 V, and IINPT = 3 μA –0.02 –0.01 0 VSET – VINPT (V) 0.01 0.02 0.03 05694-034 (%) (%) 20 Figure 18. Distribution of VSET − VINPT for VPOS = 5 V, VSET = 4 V, and IINPT = 3 μA Rev. 0 | Page 8 of 20 ADL5315 THEORY OF OPERATION ADL5315 4 COMM RLIM 5 RLIM SREF VOLTAGE SUPPLY VPOS 6 0.1μF 2 VSET 1 INPT 0.01μF NC 7 IOUT 8 MIRROR CURRENT OUTPUT 4kΩ 390pF 05694-023 3 2.2nF Figure 19. Basic Connections At the heart of the ADL5315 is a precision 1:1 current mirror with a voltage following characteristic that provides an adjustable bias voltage at the mirror input. This architecture uses a JFET input amplifier to drive the bipolar mirror and maintain stable VINPT voltage, while offering very low leakage current at the INPT pin. The current sourced by the low impedance INPT pin is mirrored and sourced by the high impedance IOUT pin. The ADL5315 provides a setpoint reference pin, SREF, which can be connected to VSET for standard 2-port mirror operation. VSREF is maintained 1.0 V below VPOS over temperature and is independent of input current. When using SREF to set the input voltage, a capacitor should be placed between SREF and ground to filter noise from SREF as well as improve power supply rejection over frequency. A value of 2.2 nF, for example, combined with the 20 kΩ output resistance at SREF, creates a pole at approximately 3 kHz. The voltage at the SREF pin can be lowered to a desired fixed value with the use of a single external resistor from SREF to ground. Mismatch between on-chip and external resistors limits the accuracy of the resultant voltage. In addition, internal clamping to protect the precision bias limits the range. Figure 20 shows an equivalent circuit model of the SREF biasing. The Schottky diode clamp protects the 50 μA current source when SREF is pulled to ground. When VSREF is 1.2 V or higher, the 50 μA current flows to the SREF pin. The current is shunted away and does not appear at the SREF pin for VSREF < 0.6 V. The transition region is between 0.6 V and 1.2 V with a large uncertainty in the pull-down current. It is recommended that a 2-resistor divider from VPOS (with no connection to SREF) or another external bias be used to bias VREF in this transition region. Equations for the SREF voltage with an external pull-down REXT follow: BIAS CONTROL INTERFACE The voltage at the INPT pin, VINPT, is forced to be equal to the voltage applied to VSET by the mirror-biasing loop. The VSET voltage range extends down to ground, allowing the ADL5315 to be used as a voltage-to-current converter with a single resistor from INPT to ground. This capability allows dark current to be minimized in PIN photodiode systems by maintaining a small voltage bias. The VSET control also allows VINPT to be set approximately equal to the load voltage at IOUT. Balancing the mirror voltages in this way provides inherently superior linearity over the widest current range independent of the supply voltage. Only leakage currents from the JFET op amp and ESD devices remain as significant sources of nonlinearity at very low currents. The voltage at VSET can also be used to shield the highly sensitive INPT pin and its board trace from leakage currents, because the two pins operate at approximately the same potential. Care must be taken to provide a low noise VSET signal, since voltage noise at VSET also appears at INPT and is transformed by the input compensation network into current noise. VSREF = REXT (VPOS − 1.0 V ), VSREF ≥ 1.2 V REXT + 20 kΩ VSREF = REXT VPOS , VSREF ≤ 0.6 V REXT + 20 kΩ where the 20 kΩ is the process-dependent internal resistor. Rev. 0 | Page 9 of 20 VPOS ADL5315 VSET 20kΩ SREF 0.9V 50μA CSET REXT 05964-029 The ADL5315 addresses the need for precision high-side monitoring of photodiode current in fiber optic systems and is useful in many nonoptical applications as well. It is optimized for use with ADI’s family of translinear logarithmic amplifiers, which take advantage of the wide input current range of the ADL5315. This arrangement allows the anode of the photodiode to connect directly to a transimpedance amplifier for the extraction of the data stream without the need for a separate optical power monitoring tap. Figure 19 shows the basic connections for the ADL5315. Figure 20. Model of SREF Bias Source with External Pull-Down ADL5315 The VSET control is intended primarily to provide a dc bias voltage for the mirror input, but it is also well behaved in the presence of the VSET transients. The rise time of VINPT is largely independent of input current because the mirror is capable of sourcing large currents to pull up the INPT pin. The fall time, however, is inversely proportional to IINPT because only IINPT is available to discharge the input compensation capacitor and other parasitics (see Figure 11). The mirror output current can vary significantly from zero to several milliamps until VINPT is fully settled. NOISE PERFORMANCE The noise performance for the ADL5315, defined as the rms noise current as a fraction of the output dc current, generally improves with increasing signal current. This partially results from the relationship between the quiescent collector current and the shot noise in the bipolar transistors. At lower signal current levels, the noise contribution from the JFET amplifier and other voltage noise sources appearing at INPT contribute significantly to the current noise. Filtering noise at VSET, whether provided by SREF or generated externally, as well as selecting optimal external compensation components on INPT, minimizes the amount of current noise at IOUT generated by the voltage noise at INPT. MIRROR RESPONSE TIME The response time of IOUT to changes in IINPT is fundamentally a function of input current, with small-signal bandwidth increasing roughly in proportion to IINPT (see Figure 10). The value of the external compensating capacitor on INPT strongly affects the IOUT response time (as well as the VSET to VINPT fall time, as noted in the Bias Control Interface section), although the value must be chosen to maintain stability and prevent noise peaking. INPUT CURRENT LIMITING The ADL5315 provides a resistor-programmable input current limit with a fixed maximum of 16 mA for the RLIM pin tied to VPOS. The fixed maximum provides input short-circuit protection to ground. The current limit is defined as the current that forces VINPT to 0 V (when using a current source on the INPT pin). Resistor RLIM between the VPOS and RLIM pins controls the current limit according to I LIM = 48 V RLIM + 3 kΩ over an RLIM range of 0 to 45 kΩ, corresponding to 16 mA down to 1 mA. Larger values of RLIM can be used for currents below 1 mA (down to approximately 250 μA) with some degradation in accuracy. See Figure 14 for more performance detail. Rev. 0 | Page 10 of 20 ADL5315 APPLICATIONS AVERAGE POWER MONITORING The ADL5315 is primarily designed for wide dynamic range applications, simplifying power monitoring designs where access is only permitted to the cathode of a PIN photodiode or receiver module. Figure 22 shows a typical application where the ADL5315 is used to provide an accurate bias to a PIN diode while simultaneously mirroring the diode current to be measured by a translinear logarithmic amplifier. In applications where a modulated signal is incident upon the photodiode, the average power of the signal can be measured. Figure 21 shows the connections necessary for using the ADL5315 in such a measurement system. The value of the capacitor to ground should be selected to eliminate errors due to modulation of the ADL5315 input current. In this application, the ADL5315 sets the bias voltage on the PIN diode. This voltage is delivered at the INPT pin and is controlled by the voltage at the VSET pin. VSET is driven by the on-board reference VSREF, which is equal to VPOS − 1 V. ADL5315 VOLTAGE REFERENCE The input current, IINPT, is precisely mirrored at a ratio of 1:1 to the IOUT pin. This interface is optimized for use with any of ADI’s translinear logarithmic amplifiers (for example, the AD8304 or AD8305) to offer a precise, wide dynamic range measurement of the optical power incident upon the PIN. CURRENT LIMITING 4 5 RLIM COMM 20kΩ CURRENT MIRROR 1:1 3 CSET 6 SREF VPOS VSET NC 2 If a linear voltage output is preferred at IOUT, a single external resistor to ground is all that is necessary to perform the conversion. VPOS 7 IOUT INPT 1 8 IPD IPD LINEAR VOLTAGE OUTPUT TIA 05694-010 PIN DATA PATH Figure 21. Average Power Monitoring Using the ADL5315 VPOS RLIM = 48V – 3kΩ ILIM ADL5315 VOLTAGE REFERENCE 4 COMM RLIM RLIM 20kΩ CURRENT MIRROR 1:1 3 NODE VOLTAGES VSREF = VPOS – 1V VSET = VINPT CURRENT LIMITING 5 ILIM = 1mA – 16mA 6 SREF VPOS VSET NC 2 THIS CONNECTION IS NOT NECESSARY, BUT REDUCES ERRORS DUE TO LEAKAGE CURRENTS AT LOW SIGNAL LEVELS. 7 VSUM IOUT INPT 1 OPTICAL POWER 8 IPD IPD INPT TIA TRANSLINEAR LOG AMP AD8304, AD8305, ETC. DATA PATH Figure 22. Typical Application Using the ADL5315 Rev. 0 | Page 11 of 20 05694-009 PIN ADL5315 TRANSLINEAR LOG AMP INTERFACING Careful consideration should be made to the layout of the circuit board in this configuration. Leakage current paths in the board itself could lead to measurement errors at the output of the translinear log amp, particularly when measuring the low end of the ADL5315’s dynamic range. It is recommended that when designing such an interface that a guard potential be used to minimize this leakage. This can be done by connecting the translinear log amp’s VSUM pin to the NC pin of the ADL5315, with the VSUM guard trace running on both sides of the IOUT trace. Additional details on using VSUM can be found in the AD8304 or AD8305 data sheets. The VSET pin of the ADL5315 can be used in a similar fashion to guard the INPT trace. The mirror current output, IOUT, of the ADL5315 is designed to interface directly to an Analog Devices translinear logarithmic amplifier, such as the AD8304, AD8305, or ADL5306. Figure 24 shows the basic connections necessary for interfacing the ADL5315 to the AD8305. In this configuration, the designer can use the full current mirror range of the ADL5315 for high accuracy power monitoring. The measured rms noise voltage at the output of the AD8305 vs. the input current is shown in Figure 23, both for the AD8305 by itself and in cascade with the ADL5315. The relatively low noise produced by the ADL5315, combined with the additional noise filtering inherent in the frequency response characteristics of the AD8305, results in minimal degradation to the noise performance of the AD8305. 5.5m 5.0m 4.5m 4.0m AD8305 AND ADL5315 NOISE (V rms) 3.5m 3.0m 2.5m 2.0m 1.5m 1.0m AD8305 ONLY 0 1n 10n 100n 1μ 10μ 100μ 1m IINPT (A) Figure 23. Measured RMS Noise of AD8305 vs. AD8305 Cascaded with ADL5315 ADL5315 VOLTAGE REFERENCE CURRENT LIMITING RLIM 5 6 VPOS VSET NC 2 1 2 7 200kΩ 4.7nF 2kΩ IOUT INPT 1 8 IPD 4 VREF TIA DATA PATH VOUT SCAL AD8305 IREF BFIN INPT VLOG 1kΩ 1nF PIN 13 5 6 7 8 12 11 OUTPUT VOUT = 0.2 × LOG10 (IPDM/1nA) 10 9 0.1μF AD8305 INPUT COMPENSATION NETWORK 3V TO 12V Figure 24. Interfacing the ADL5315 to the AD8305 for High Accuracy PIN Power Monitoring Rev. 0 | Page 12 of 20 05694-011 IPD 3 VRDZ 14 VPOS SREF 15 COMM 16 COMM 3 ILIM = 1mA – 16mA VNEG CURRENT MIRROR 1:1 COMM 20kΩ VNEG RLIM COMM COMM VSUM 4 CSET VPOS RLIM = 48V – 3kΩ ILIM 05694-012 0.5m ADL5315 EXTENDED OPERATING RANGE USING RLIM AS A SECONDARY MONITOR The ADL5315 is specified over an input current range of 3 nA to 3 mA, but the device remains fully functional over the full eight decade range specified for ADI’s flagship translinear logarithmic amplifier, the AD8304 (100 pA to 10 mA). Figure 25 and Figure 26 show the performance of the ADL5315 for this extended operating range vs. various temperature and supply conditions. The RLIM pin can be used as a secondary linear output for monitoring input currents near the upper end of the ADL5315 current range. The RLIM pin sinks a current approximately equal to IINPT/40. The voltage generated by this current through the series combination of an internal 3 kΩ resistor and the external RLIM is compared to a 1.2 V threshold and fed back to the mirror bias to limit IINPT. This extended dynamic range capability allows the ADL5315 to be used in optical power measurement systems, precision test equipment, or any other system that requires accurate, high dynamic range current monitoring. Figure 27 shows the equivalent circuit and one method for using RLIM to form a VSET bias proportional to IINPT, also referred to as automatic photodiode biasing. This configuration is useful in PIN photodiode systems to compensate for photodiode equivalent series resistance (ESR) while maintaining low reverse bias at low signal levels to minimize dark current. Choosing R2 >> RLIM minimizes impact on ILIM and allows the resistor ratio, R2/R1, to be calculated based on maximum photodiode ESR using the following simplified equation. 2.0 –40°C 0°C +25°C +70°C +85°C 1.5 1m 100μ 10μ 1μ 0 –0.5 100n –1.0 10n –1.5 1n where RPDmax is the maximum ESR of the photodiode. 1n 10n 100n 1μ 10μ 100μ 1m 100p 10m IINPT (A) For example, choosing RLIM = 1.82 kΩ (10 mA ILIM), R2 = 100 kΩ, and R1 = 18.2 kΩ compensates for photodiode ESR up to 250 Ω. Figure 25. Extended Operating Range of 100 pA to 10 mA for Multiple Temperatures, Normalized to 25°C and IINPT = 3 μA 10m 1.5 1m 1.0 100μ 0.5 10μ 0 1μ VPOS 100n –0.5 –1.0 VPOS = 2.7V, VSET = VSREF VPOS = 5V, VSET = 2V VPOS = 5V, VSET = VSREF VPOS = 8V, VSET = 2V VPOS = 8V, VSET = VSREF –1.5 –2.0 100p A simple low voltage drop current mirror with a load resistor can replace the differential amplifier shown in Figure 27, although the resulting input current limit is less accurate and will vary with temperature. IOUT (A) IINPT VS. IOUT, ALL VOLTAGE CONDITIONS 1n 10n 100n 1μ IINPT (A) 10μ 100μ 1m RLIM 10n 100p 10m VPOS RLIM 1n R1 05694-031 LINEARITY (%) 2.0 For zero bias at zero input current, the sum of RLIM and R3 must equal R1. For positive bias at zero input current, the sum of RLIM and R3 should be greater than R1. The ratio of VPOS to VSET varies directly. 3kΩ R3 R2 R2 IINPT/40 VSET Figure 26. Extended Operating Range of 100 pA to 10 mA for Multiple Supply Conditions, Normalized to VPOS = 5 V, VSET = VSREF and IINPT = 3 μA 1.2V MIRROR BIAS 05964-035 –2.0 100p R2 40 R PDmax = , R2 >> R LIM , R1 = R3 R1 R LIM IOUT (A) 0.5 05694-030 LINEARITY (%) 1.0 10m +25°C, +70°C, +85°C, 0°C, –40°C Figure 27. Providing Automatic Photodiode Voltage Biasing Using RLIM Pin Rev. 0 | Page 13 of 20 ADL5315 2.2 CHARACTERIZATION METHODS 2.0 During characterization, the ADL5315 was treated as a precision 1:1 current mirror. To make accurate measurements throughout the six-decade current range, calibrated Keithley 236 current sources were used to create and measure the test currents. Measurements at low currents are very susceptible to leakage to the ground plane. To minimize leakage on the characterization board, the VSET pin is connected to traces that buffer VINPT from ground. These traces are connected to the triax guard connector to provide buffering along the cabling. 1.8 VSET VOLTAGE (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 100p 1n 10n 100n 1μ 10μ 100μ 1m 10m IINPT (A) 05694-036 0.2 Figure 28. VSET Voltage vs. IINPT when RLIM Is Configured for Automatic Photodiode Biasing 2.2 2.0 1.8 The primary characterization setup shown in Figure 30 is used to perform all static measurements, including mirror linearity between IINPT and IOUT, VINPT variation vs. IINPT, supply current, and IINPT current limiting. Component selection of the characterization board is similar to that of the evaluation board, except that triax connectors are used instead of SMA. To measure pulse response, noise, and small signal bandwidth, more specialized test setups are used. ADL5315 1.4 INPT KEITHLEY 236 CHARACTERIZATION BOARD 1.2 IOUT 1.0 KEITHLEY 236 VPOS VSET SREF COMM 0.8 0.6 0.4 DC SUPPLIES/DMM 0.2 05694-025 VSET VOLTAGE (V) 1.6 0 1 2 3 4 5 6 7 8 9 IINPT (mA) 10 05694-037 Figure 30. Primary Characterization Setup 0 Figure 29. VSET Voltage vs. IINPT when RLIM Is Configured for Automatic Photodiode Biasing Figure 28 and Figure 29 show the performance of the circuit in Figure 27. The reverse bias across the photodiode is held at a low value for small input currents to minimize dark current. The VSET voltage increases in a linear manner at the higher input currents to maintain accurate photodiode responsivity. The minimum bias level for the configuration above is ~200 mV. The setup in Figure 31 is used to measure the output current noise of the ADL5315. Batteries are used in numerous places to minimize introduced noise and remove the uncertainty resulting from the use of multiple dc supplies. In application, properly bypassed dc supplies provide similar results. The load resistor is chosen for each current to maximize signal-to-noise ratio while maintaining measurement system bandwidth (when combined with the low capacitance JFET buffer). The custom LNA is used to overcome noise floor limitations in the HP89410A signal analyzer. Rev. 0 | Page 14 of 20 ADL5315 + – + 1.5V – + 1.5V – 1.5V HP89410A 2.2nF VPOS SREF VSET + ADL5315 INPT RINPUT VECTOR SIGNAL ANALYZER 9V IOUT +12V – FET BUFFER LNA – –12V 9V 05694-028 RLOAD + Figure 31. Configuration for Noise Spectral Density and Wideband Current Noise INPT Q1 TDS5104 OSCILLOSCOPE VPOS VSET SREF COMM 05694-024 RC AGILENT 33250A PULSE GENERATOR DC SUPPLIES/DMM Figure 32. Configuration for Pulse Response of IINPT to IOUT ADL5315 TDS5104 OSCILLOSCOPE AGILENT 33250A PULSE GENERATOR VSET EVALUATION BOARD KEITHLEY 236 IOUT INPT VPOS Q1 The configuration in Figure 33 is used to measure VINPT while VSET is pulsed. Q1 and RC are used to generate the operating current on the INPT pin. An Agilent 33250A pulse generator is used on the VSET pin to create a 0.0 V to 4.0 V square wave. The setup in Figure 34 was used to measure the small signal ac response from IINPT to IOUT. The AD8138 differential amplifier was used to couple the ac and dc signals together. The ac signal was modulated to a depth of 5% of full scale over frequency. The voltage across RF sets the dc operating point of IINPT. The values of RF are chosen to result in decade changes in IINPT. The ADA4899-1 op amp is used as a transimpedance amplifier for all current conditions. RC IOUT SREF COMM RC 05694-026 RC is chosen according to what current range is desired. For 30 μA and lower, the AD8067 FET input op amp is used in a transimpedance amplifier configuration to allow for viewing on the TDS5104 oscilloscope. For signals greater than 30 μA, the ADA4899-1 replaced the AD8067 to avoid limiting the bandwidth of the ADL5315. ADL5315 EVALUATION BOARD DC SUPPLIES/DMM Figure 33. Configuration for Pulse Response from VSET to VINPT NETWORK ANALYZER RF OUTPUT R A B INPT POWER SPLITTER + – ADL5315 IOUT EVALUATION BOARD VPOS VSET SREF COMM AD8138 EVAL BOARD + RF – 50Ω DC SUPPLIES/DMM Figure 34. Configuration for Small-Signal AC Response Rev. 0 | Page 15 of 20 05694-027 Figure 32 shows the configuration used to measure the pulse response of IINPT to IOUT. To create the test current pulse, Q1 is used in a common base configuration with the Agilent 33250A pulse generator. The output of the 33250A is a negative biased square wave with an amplitude that results in a one decade current step at IOUT. ADL5315 EVALUATION BOARD GND L1 0Ω ADL5315 1 C4 OPEN INPT IOUT 8 R4 4kΩ C3 390pF VSET 2 VSET NC 7 3 SREF VPOS 6 IOUT R5 OPEN SW1 R3 0Ω R1 100Ω R2 10kΩ 4 COMM C1 0.01μF VPOS C2 0.01μF RLIM 5 05694-013 IPD SREF Figure 35. Evaluation Board Schematic (Rev. A) Table 4. Evaluation Board (Rev. A) Configuration Options Function Supply and ground connections. Input Interface: The evaluation board is configured to accept an input current at the SMA connector labeled INPUT. Filtering of this current can be done using L1 and C4. R4, C3 Input Compensation. Provides essential HF compensation at the INPT pin. SREF, VSET, SW1, R1, R6, R7 INPT Bias Voltage. The dc voltage applied to VSET determines the voltage at INPT, VSET = VINPT. Connecting SREF to VSET sets the bias at INPT to be 1 V below VPOS. Opening SW1 allows for VSET to be driven externally via the SMA connector. IOUT, R5 Output/Mirror Current Interface: The output current at the SMA connector labeled IOUT is equal to the value at INPT. R5 allows a resistor to be installed for applications where a scaled voltage referenced to IPD is desirable instead of a current. Current Limiting. An external resistor to VPOS sets the current limit at INPT from 1 mA to 16 mA. ILIM = 48 V/(RLIM + 3 kΩ). The evaluation board is configured such that ILIM = 3.7 mA. Supply Filtering/Decoupling. C1, C2, R3 R2 = 10 kΩ (size 0402) C1 = 0.01 μF (size 0402) C2 = 0.1 μF (size 0603) R3 = 0 Ω (size 0805) 05694-014 R2 Default Conditions Not applicable L1 = 0 Ω (size 0805) C4 = open (size 00603) C3 = 390 pF (size 0805) R4 = 4.02 kΩ (size 0402) SW1 = closed R1 = 100 Ω (size 0402) R6 = R7 = 0 Ω (size 0402) R5 = open (size 0603) 05694-015 Component VPOS, GND INPUT, L1, C4 Figure 36. Component Side Layout Figure 37. Component Side Silkscreen Rev. 0 | Page 16 of 20 ADL5315 OUTLINE DIMENSIONS 1.89 1.74 1.59 3.25 3.00 2.75 1.95 1.75 1.55 TOP VIEW 12° MAX 5 BOTTOM VIEW * 8 EXPOSED PAD 4 2.95 2.75 2.55 PIN 1 INDICATOR 1.00 0.85 0.80 0.60 0.45 0.30 2.25 2.00 1.75 0.55 0.40 0.30 0.15 0.10 0.05 1 0.50 BSC 0.25 0.20 0.15 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF Figure 38. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 2 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-1) Dimensions shown in millimeters ORDERING GUIDE Model ADL5315ACPZ-R7 1 ADL5315ACPZ-WP1, 2 ADL5315-EVAL 1 2 Temperature Range –40°C to +85°C –40°C to +85°C Package Description 8-Lead LFCSP_VD 8-Lead LFCSP_VD Evaluation Board Z = Pb-free part. WP = Waffle pack Rev. 0 | Page 17 of 20 Package Option CP-8-1 CP-8-1 Branding Q0 Q0 ADL5315 NOTES Rev. 0 | Page 18 of 20 ADL5315 NOTES Rev. 0 | Page 19 of 20 ADL5315 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05694–0–10/05(0) Rev. 0 | Page 20 of 20