LINER LTC4271

LTC4274A/LTC4274C
Single PoE/PoE+/LTPoE++
PSE Controller
DESCRIPTION
FEATURES
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The LTC®4274A is a single Power Sourcing Equipment
(PSE) controller capable of delivering up to 90W of LTPoE++
power to a compatible LTPoE++ Powered Device (PD). A
proprietary detection/classification scheme allows mutual
identification between a LTPoE++ PSE and LTPoE++ PD
while remaining compatible and interoperable with existing
Type 1 (13W) and Type 2 (25.5W) PDs. The LTC4274A
feature set is a superset of the popular LTC4274. These
PSE controllers feature low-RON external MOSFETs and
0.25Ω sense resistors which are especially important at
the LTPoE++ current levels to maintain the lowest possible
heat dissipation.
Compliant with IEEE 802.3at Type 1 and 2
Low Power Dissipation
0.25Ω Sense Resistance Per Channel
Very High Reliability 4-Point PD Detection
2-Point Forced Voltage
2-Point Forced Current
High Capacitance Legacy Device Detection
1MHz I2C Compatible Serial Control Interface
Midspan Backoff Timer
Supports 2-Pair and 4-Pair Output Power
Available in Multiple Power Grades
LTC4274A-1: LTPoE++™ 38.7W
LTC4274A-2: LTPoE++ 52.7W
LTC4274A-3: LTPoE++ 70W
LTC4274A-4: LTPoE++ 90W
LTC4274C: PoE 13W
Available in 38-Lead 5mm × 7mm QFN Package
The LTC4274C targets fully automatic PSE systems powering Type 1 (up to 13W) PDs.
Advanced power management features include: a 14-bit
current monitoring ADC, DAC-programmable current limit,
and versatile quick port shutdown. PD Discovery uses
a proprietary dual-mode 4-point detection mechanism
ensuring excellent immunity from false PD detection.
The LTC4274A/LTC4274C includes an I2C serial interface
operable up to 1MHz.
APPLICATIONS
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LTPoE++ PSE Switches/Routers
LTPoE++ PSE Midspans
IEEE 802.3at Type 1 PSE Switches/Routers
IEEE 802.3at Type 1 PSE Midspans
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
LTPoE++ are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
The LTC4274A/LTC4274C is available in multiple power
grades, allowing delivered PD power of 13W, 25.5W, 38.7W,
52.7W, 70W and 90W. These controllers are available in a
38-lead 5mm × 7mm QFN package.
TYPICAL APPLICATION
Complete Single-Port Ethernet High Power Source
3.3V
INT
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND AGND
SMAJ58A
SHDN
0.1μF
VDD
LTC4274A/LTC4274C
VEE SENSE
AUTO
MSD
RESET
MID
GATE OUT
1μF
100V
S1B
0.22μF
100V
PORT
–54V
4274AC TA01
S1B
–54V
4274acfc
1
LTC4274A/LTC4274C
PIN CONFIGURATION
Supply Voltages (Note 1)
AGND – VEE ........................................... –0.3V to 80V
DGND – VEE ........................................... –0.3V to 80V
VDD – DGND ......................................... –0.3V to 5.5V
Digital Pins
SCL, SDAIN, SDAOUT, INT, SHDN, MSD, AD,
RESET, AUTO, MID........... DGND –0.3V to VDD + 0.3V
Analog Pins
GATE, SENSE, OUT ................ VEE –0.3V to VEE + 80V
Operating Temperature Range .................–40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
OUT
AUTO
MSD
RESET
MID
SCL
TOP VIEW
INT
ABSOLUTE MAXIMUM RATINGS
38 37 36 35 34 33 32
SDAOUT 1
31 GATE
NC 2
30 SENSE
SDAIN 3
29 NC
AD3 4
28 NC
AD2 5
27 VEE
AD1 6
26 VEE
VEE
39
AD0 7
25 VEE
DNC 8
24 NC
NC 9
23 NC
DGND 10
22 VEE
NC 11
21 NC
NC 12
20 NC
VEE
AGND
DGND
DGND
SHDN
DGND
VDD
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm = 7mm) PLASTIC QFN
EXPOSED PAD IS VEE (PIN 39) MUST BE SOLDERED TO PCB
TJMAX = 125°C, eJA = 34°C/W
ORDER INFORMATION
LEAD FREE FINISH
LTC4274CIUHF#PBF
TAPE AND REEL
LTC4274CIUHF#TRPBF
PART MARKING
4274C
PACKAGE DESCRIPTION
38-Lead (5mm × 7mm) Plastic QFN
MAX PWR
13W
TEMPERATURE RANGE
–40°C to 85°C
LTC4274AIUHF-1#PBF
LTC4274AIUHF-1#TRPBF
4274A1
38-Lead (5mm × 7mm) Plastic QFN
38.7W
–40°C to 85°C
LTC4274AIUHF-2#PBF
LTC4274AIUHF-2#TRPBF
4274A2
38-Lead (5mm × 7mm) Plastic QFN
52.7W
–40°C to 85°C
LTC4274AIUHF-3#PBF
LTC4274AIUHF-3#TRPBF
4274A3
38-Lead (5mm × 7mm) Plastic QFN
70W
–40°C to 85°C
LTC4274AIUHF-4#PBF
LTC4274AIUHF-4#TRPBF
4274A4
38-Lead (5mm × 7mm) Plastic QFN
90W
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4274acfc
2
LTC4274A/LTC4274C
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V
unless otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
VEE
Main PoE Supply Voltage
AGND – VEE
For IEEE Type 1 Compliant Output
For IEEE Type 2 Compliant Output
For LTPoE++ Compliant Output
l
l
l
45
51
54.75
Undervoltage Lockout
AGND – VEE
l
20
VDD Supply Voltage
VDD – DGND
l
3.0
VDD
MIN
l
Undervoltage Lockout
TYP
MAX
UNITS
57
57
57
V
V
V
25
30
V
3.3
4.3
V
2.2
V
Allowable Digital Ground Offset
DGND – VEE
l
57
V
IEE
VEE Supply Current
(AGND – VEE) = 55V
l
–2.4
–5
mA
IDD
VDD Supply Current
(VDD – DGND) = 3.3V
l
1.1
3
mA
Detection Current – Force Current
First Point, AGND – VOUT = 9V
Second Point, AGND – VOUT = 3.5V
l
l
220
140
240
160
260
180
μA
μA
Detection Voltage – Force Voltage
AGND – VOUT, 5μA ≤ IOUT ≤ 500μA
First Point
Second Point
l
l
7
3
8
4
9
5
V
V
Detection Current Compliance
AGND – VOUT = 0V
l
0.8
0.9
mA
Detection Voltage Compliance
AGND – VOUT, Open Port
l
10.4
12
V
Detection Voltage Slew Rate
AGND – VOUT, CPORT = 0.15μF
l
25
Detection
VOC
0.01
V/μs
Minimum Valid Signature Resistance
l
15.5
17
18.5
kΩ
Maximum Valid Signature Resistance
l
27.5
29.7
32
kΩ
Classification
VCLASS
VMARK
Classification Voltage
AGND – VOUT, 0mA ≤ ICLASS ≤ 50mA
l
16.0
Classification Current Compliance
VOUT = AGND
l
53
61
67
mA
Classification Threshold Current
Class 0 – 1
Class 1 – 2
Class 2 – 3
Class 3 – 4
Class 4 – Overcurrent
l
l
l
l
l
5.5
13.5
21.5
31.5
45.2
6.5
14.5
23
33
48
7.5
15.5
24.5
34.9
50.8
mA
mA
mA
mA
mA
Classification Mark State Voltage
AGND – VOUT, 0.1mA ≤ ICLASS ≤ 10mA
l
7.5
9
10
V
Mark State Current Compliance
VOUT = AGND
l
53
61
67
mA
GATE Pin Pull-Down Current
Port Off, VGATE = VEE + 5V
Port Off, VGATE = VEE + 1V
l
l
0.4
0.08
0.12
mA
mA
30
mA
20.5
V
Gate Driver
GATE Pin Fast Pull-Down Current
VGATE = VEE + 5V
GATE Pin On Voltage
VGATE – VEE, IGATE = 1μA
l
Power Good Threshold Voltage
VOUT – VEE
l
2
2.4
2.8
V
OUT Pin Pull-Up Resistance to AGND
0V ≤ (AGND – VOUT) ≤ 5V
l
300
500
700
kΩ
8
12
14
V
Output Voltage Sense
VPG
4274acfc
3
LTC4274A/LTC4274C
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V
unless otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Sense
VCUT
VLIM
VLIM
VLIM
Overcurrent Sense Voltage
VSENSE – VEE, hpen = 01h, cut[5:0] ≥ 4 (Note 12)
cutrng = 0
cutrng = 1
l
l
9
4.5
9.38
4.69
9.75
4.88
mV/LSB
mV/LSB
Overcurrent Sense in AUTO Pin Mode
Class 0, Class 3
Class 1
Class 2
Class 4
l
l
l
l
90
26
49
152
94
28
52
159
98
30
55
166
mV
mV
mV
mV
Active Current Limit in 802.3af
Compliant Mode
VSENSE – VEE, hpen = 01h, lim = 80h,
VEE = 55V (Note 12)
VEE < VOUT < AGND – 29V
AGND – VOUT = 0V
l
l
102
20
106
110
50
mV
mV
hpen = 01h, lim = C0h, VEE = 55V
VOUT – VEE = 0V to 10V
VEE + 23V < VOUT < AGND – 29V
AGND – VOUT = 0V
l
l
l
204
100
20
212
106
221
113
50
mV
mV
mV
VOUT – VEE = 0V to 10V, VEE = 55V
Class 0 to Class 3
Class 4
l
l
102
204
106
212
110
221
mV
mV
Active Current Limit in High Power Mode
Active Current Limit in AUTO Pin Mode
VMIN
DC Disconnect Sense Voltage
VSENSE – VEE, rdis = 0
VSENSE – VEE, rdis = 1
l
l
2.6
1.3
3.8
1.9
4.8
2.41
mV
mV
VSC
Short-Circuit Sense
VSENSE – VEE – VLIM, rdis = 0
VSENSE – VEE – VLIM, rdis = 1
l
l
160
75
200
100
255
135
mV
mV
Port Current ReadBack
Resolution
No Missing Codes, fast_iv = 0
LSB Weight
VSENSE – VEE
50Hz to 60Hz Noise Rejection
(Note 7)
14
Bits
30.5
μV/LSB
30
dB
Port Voltage ReadBack
Resolution
No Missing Codes, fast_iv = 0
LSB Weight
AGND – VOUT
50Hz to 60Hz Noise Rejection
(Note 7)
14
bits
5.835
mV/LSB
30
dB
Digital Interface
VILD
VIHD
Digital Input Low Voltage
ADn, SHDN, RESET, MSD, AUTO, MID
(Note 6)
l
0.8
V
I2C Input Low Voltage
SCL, SDAIN (Note 6)
l
0.8
V
Digital Input High Voltage
(Note 6)
l
Digital Output Low Voltage
ISDAOUT = 3mA, IINT = 3mA
ISDAOUT = 5mA, IINT = 5mA
l
l
Internal Pull-Up to VDD
ADn, SHDN, RESET, MSD
50
kΩ
Internal Pull-Down to DGND
AUTO, MID
50
kΩ
2.2
V
0.4
0.7
V
V
4274acfc
4
LTC4274A/LTC4274C
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V
unless otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
290
310
ms
470
ms
Timing Characteristics
tDET
Detection Time
Beginning to End of Detection (Note 7)
l
270
tDETDLY
Detection Delay
From PD Connected to Port to Detection
Complete (Note 7)
l
300
tCLE
Class Event Duration
(Note 7)
l
12
ms
tCLEON
Class Event Turn-On Duration
CPORT = 0.6μF (Note 7)
l
tME
Mark Event Duration
(Notes 7, 11)
l
tMEL
Last Mark Event Duration
(Notes 7, 11)
l
tPON
Power On Delay in AUTO Pin Mode
From End of Valid Detect to Application of Power
to Port (Note 7)
l
Turn On Rise Time
(AGND – VOUT): 10% to 90% of (AGND – VEE),
CPORT = 0.15μF (Note 7)
l
Turn On Ramp Rate
CPORT = 0.15μF (Note 7)
l
Fault Delay
From ICUT Fault to Next Detect
l
1.0
1.1
Midspan Mode Detection Backoff
Rport = 15.5kΩ (Note 7)
l
2.3
2.5
2.7
s
Power Removal Detection Delay
From Power Removal After tDIS to Next Detect
(Note 7)
l
1.0
1.3
2.5
s
tSTART
Maximum Current Limit Duration During
Port Start-Up
(Note 7)
l
52
62.5
66
ms
tLIM
Maximum Current Limit Duration After Port tLIM Enable = 1 (Notes 7, 12)
Start-Up
l
tCUT
Maximum Overcurrent Duration After Port
Start-Up
(Note 7)
l
52
62.5
66
ms
Maximum Overcurrent Duty Cycle
(Note 7)
l
5.8
6.3
6.7
%
tMPS
Maintain Power Signature (MPS) Pulse
Width Sensitivity
Current Pulse Width to Reset Disconnect Timer
(Notes 7, 8)
l
1.6
3.6
ms
tDIS
Maintain Power Signature (MPS) Dropout
Time
(Notes 5, 7)
l
320
380
ms
tMSD
Masked Shut Down Delay
(Note 7)
l
6.5
μs
tSHDN
Port Shut Down Delay
(Note 7)
l
6.5
μs
3
s
0.1
16
ms
22
ms
60
15
ms
8.6
24
μs
10
V/μs
s
11.9
350
ms
ms
I2C Watchdog Timer Duration
l
1.5
Minimum Pulse Width for Masked Shut
Down
(Note 7)
l
3
μs
Minimum Pulse Width for SHDN
(Note 7)
l
3
μs
(Note 7)
l
4.5
μs
Minimum Pulse Width for RESET
2
4274acfc
5
LTC4274A/LTC4274C
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Clock Frequency
(Note 7)
l
t1
Bus Free Time
Figure 5 (Notes 7, 9)
l
480
ns
t2
Start Hold Time
Figure 5 (Notes 7, 9)
l
240
ns
t3
SCL Low Time
Figure 5 (Notes 7, 9)
l
480
ns
t4
SCL High Time
Figure 5 (Notes 7, 9)
l
240
ns
t5
Data Hold Time
Figure 5 (Notes 7, 9) Data into Chip
Data Out of Chip
l
l
60
I2C Timing
1
120
MHz
ns
ns
t6
Data Set-Up Time
Figure 5 (Notes 7, 9)
l
80
ns
t7
Start Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
t8
Stop Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
tr
SCL, SDAIN Rise Time
Figure 5 (Notes 7, 9)
l
120
ns
tf
SCL, SDAIN Fall Time
Figure 5 (Notes 7, 9)
l
60
ns
Fault Present to INT Pin Low
(Notes 7, 9, 10)
l
150
ns
Stop Condition to INT Pin Low
(Notes 7, 9, 10)
l
1.5
μs
ARA to INT Pin High Time
(Notes 7, 9)
l
1.5
μs
(Notes 7, 9)
l
120
ns
SCL Fall to ACK Low
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4274A/LTC4274C operates with a negative supply voltage
(with respect to ground). To avoid confusion, voltages in this data sheet
are referred to in terms of absolute magnitude.
Note 5: tDIS is the same as tMPDO defined by IEEE 802.3at.
Note 6: The LTC4274A/LTC4274C digital interface operates with respect to
DGND. All logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
tMPS within any tMPDO time window.
Note 9: Values measured at VILD(MAX) and VIHD(MIN).
Note 10: If fault condition occurs during an I2C transaction, the INT pin
will not be pulled down until a stop condition is present on the I2C bus.
Note 11: Load Characteristic of the LTC4274A/LTC4274C during Mark:
7V < (AGND – VOUT) < 10V or IOUT < 50μA
Note 12: See the LTC4274A/LTC4274C Software Programming
documentation for information on serial bus usage and device
configuration and status registers.
4274acfc
6
LTC4274A/LTC4274C
TYPICAL PERFORMANCE CHARACTERISTICS
Power-On Sequence in
AUTO Pin Mode
10
GND
PORT VOLTAGE (V)
FORCED VOLTAGE
DETECTION
–30
–40
VDD = 3.3V
VEE = –54V
LOAD
FULLY
CHARGED
–18.4
VEE
PORT
CURRENT
200 mA/DIV
802.3af
CLASSIFICATION
POWER ON
–50
–60
VDD = 3.3V
VEE = –54V
PORT
VOLTAGE
20V/DIV
–10
–20
GND
GND
FORCED CURRENT DETECTION
0
802.3af Classification in
AUTO Pin Mode
Powering Up into a 180μF Load
FOLDBACK
0mA
GATE
VOLTAGE
10V/DIV VEE
VEE
VDD = 3.3V
VEE = –55V
PD IS CLASS 1
PORT
VOLTAGE
10V/DIV
425mA
CURRENT LIMIT
FET ON
VEE
–70
5ms/DIV
100ms/DIV
5ms/DIV
4274AC G02
4274AC G01
2-Event Classification in
AUTO Pin Mode
Classification Transient Response
to 40mA Load Step
Classification Current Compliance
0
40mA
PORT
CURRENT
20mA/DIV
–17.6
0mA
1ST CLASS EVENT
2ND CLASS EVENT
VDD = 3.3V
VEE = –55V
PD IS CLASS 4
VDD = 3.3V
–2 VEE = –54V
TA = 25°C
–4
VDD = 3.3V
VEE = –54V
CLASSIFICATION VOLTAGE (V)
GND
PORT
VOLTAGE
10V/DIV
4274AC G03
PORT
VOLTAGE
1V/DIV
–20V
–6
–8
–10
–12
–14
–16
–18
VEE
–20
0
50μs/DIV
10ms/DIV
4274AC G04
4274AC G05
VDD Supply Current vs Voltage
215
IEE SUPPLY CURRENT (mA)
1.5
1.4
1.3
1.2
1.1
1.0
214
2.3
2.2
2.1
85°C
25°C
–40°C
0.9
0.8
2.7
2.9
3.1 3.3 3.5 3.7 3.9
VDD SUPPLY VOLTAGE (V)
4.1
4.3
4274AC G07
2.0
–60 –55 –50 –45 –40 –35 –30 –25 –20
VEE SUPPLY VOLTAGE (V)
4274AC G08
860
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 48h = C0h
856
213
852
212
848
211
844
210
–40
0
40
–80
TEMPERATURE (°C)
ILIM (mA)
IDD SUPPLY CURRENT (mA)
1.6
802.3at ILIM Threshold
vs Temperature
2.4
85°C
25°C
–40°C
1.7
70
4274AC G06
VEE Supply Current vs Voltage
VLIM (mV)
1.8
10
20
30
40
50
60
CLASSIFICATION CURRENT (mA)
840
120
4274AC G09
4274acfc
7
LTC4274A/LTC4274C
TYPICAL PERFORMANCE CHARACTERISTICS
802.3af ILIM Threshold
vs Temperature
423
105.75
105.00
–40
0
161
644
160
640
159
636
158
–40
420
120
40
80
TEMPERATURE (°C)
648
80
40
TEMPERATURE (°C)
0
4274AC G10
DC Disconnect Threshold
vs Temperature
384
2.0000
381
1.9375
378
93.75
375
93.00
–40
0
7.75
1.8750
7.50
1.8125
7.25
1.7500
–40
372
120
80
40
TEMPERATURE (°C)
8.00
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 47h = E2h
0
80
40
TEMPERATURE (°C)
ADC Noise Histogram
Current Readback in Fast Mode
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 48h = C0h
800
400
200
350
175
300
150
500
125
400
100
300
75
200
50
100
25
50
0
0
0
–54
–45
–36
–18
–27
VOUTn (V)
–9
0
4274AC G14
BIN COUNT
600
VLIM (mV)
ILIM (mA)
700
225
ADC Integral Nonlinearity
Current Readback in Fast Mode
1.0
VSENSE – VEE = 110.4mV
ADC INTEGRAL NONLINEARITY (LSBs)
900
7.00
120
4274AC G13
4274AC G12
Current Limit Foldback
IMIN (mV)
94.50
VMIN (mV)
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 47h = D4h
ICUT (mA)
VCUT (mV)
95.25
630
120
4274AC G11
802.3af ICUT Threshold
vs Temperature
96.00
ICUT (mA)
426
ILIM (mA)
106.50
652
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 47h = E2h
162
429
VLIM (mV)
107.25
163
432
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 48h = 80h
VCUT (mV)
108.00
802.3at ICUT Threshold
vs Temperature
250
200
150
100
191
192
193
194
ADC OUTPUT
195
196
4274AC G15
0.5
0
–0.5
–1.0
0 50 100 150 200 250 300 350 400 450 500
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
4274AC G16
4274acfc
8
LTC4274A/LTC4274C
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Noise Histogram
Current Readback in Slow Mode
ADC INTEGRAL NONLINEARITY (LSBs)
250
200
BIN COUNT
600
1.0
VSENSE – VEE = 110.4mV
150
100
50
0
6139
6141
6143
ADC OUTPUT
6145
500
400
0
200
100
0
500
BIN COUNT
400
300
200
–0.5
100
50
60
0
8532
8533
8534
8535
ADC OUTPUT
8536
0.5
0
–0.5
–1.0
0
10
20
40
30
PORT VOLTAGE (V)
4274AC G21
4274AC G20
INT and SDAOUT Pull-Down Voltage
vs Load Current
60
4274AC G22
GND
VDD = 3.3V
VEE = –54V
PORT
VOLTAGE
20V/DIV
2
50
MOSFET Gate Drive with Fast
Pull-Down
3
2.5
265
1.0
AGND – VOUT = 48.3V
0.5
20
40
30
PORT VOLTAGE (V)
264
ADC Integral Nonlinearity
Voltage Readback in Slow Mode
ADC INTEGRAL NONLINEARITY (LSBs)
600
PULL-DOWN VOLTAGE (V)
ADC INTEGRAL NONLINEARITY (LSBs)
1.0
10
262
263
ADC OUTPUT
4274AC G19
ADC Noise Histogram Port
Voltage Readback in Slow Mode
0
261
260
0 50 100 150 200 250 300 350 400 450 500
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
4274AC G18
ADC Integral Nonlinearity
Voltage Readback in Fast Mode
0
300
–0.5
–1.0
6147
AGND – VOUT = 48.3V
0.5
4274AC G17
–1.0
ADC Noise Histogram Port
Voltage Readback in Fast Mode
BIN COUNT
300
ADC Integral Nonlinearity
Current Readback in Slow Mode
VEE
1.5
FAST PULL-DOWN
GATE
VOLTAGE
10V/DIV VEE
1
PORT
CURRENT
500mA/DIV 0mA
0.5
0
0
5
10 15 20 25 30
LOAD CURRENT (mA)
35
40
4274AC G23
50Ω
FAULT
APPLIED
CURRENT LIMIT
50Ω FAULT REMOVED
100μs/DIV
4274AC G24
4274acfc
9
LTC4274A/LTC4274C
TEST TIMING DIAGRAMS
tDET
FORCED-CURRENT
CLASSIFICATION
FORCEDVOLTAGE
tME
0V
VPORT
tMEL
VOC
VMARK
15.5V
VCLASS
20.5V
tCLE
tCLE
PD
CONNECTED
tCLEON
tPON
VEE
INT
4274AC F01
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes
VLIM
VCUT
VSENSE TO VEE
0V
tSTART, tICUT
INT
4274AC F02
Figure 2. Current Limit Timing
VSENSE
TO VEE
VMIN
INT
tMPS
tDIS
4274AC F03
Figure 3. DC Disconnect Timing
4274acfc
10
LTC4274A/LTC4274C
TEST TIMING DIAGRAMS
VGATE
tMSD
tSHDN
VEE
MSD or
SHDN
4274AC F04
Figure 4. Shut Down Delay Timing
t3
tr
t4
tf
SCL
t2
t5
t6
t7
t8
SDA
t1
4274AC F05
Figure 5. I2C Interface Timing
4274acfc
11
12
SDA
SCL
1
0
AD3 AD2 AD1 AD0 R/W ACK A7
A5
A4
A3
A2
A1
A4
A0 ACK
ACK BY
SLAVE
A3
A2
0
0
D5
D3
FRAME 3
DATA BYTE
D4
FRAME 1
SERIAL BUS ADDRESS BYTE
REPEATED
START BY
MASTER
1
D6
D2
D6
D5
D3
D1
D0 ACK
NO ACK BY
MASTER
D2
4274AC F06
STOP BY
MASTER
FRAME 2
DATA BYTE
D4
D0 ACK
ACK BY
SLAVE
D1
ACK BY
SLAVE
AD3 AD2 AD1 AD0 R/W ACK D7
A0 ACK D7
ACK BY
SLAVE
A1
Figure 7. Reading from a Register
FRAME 2
REGISTER ADDRESS BYTE
ACK BY
SLAVE
A6
A5
FRAME 2
REGISTER ADDRESS BYTE
ACK BY
SLAVE
A6
Figure 6. Writing to a Register
AD3 AD2 AD1 AD0 R/W ACK A7
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
0
1
START BY
MASTER
0
4274AC F07
STOP BY
MASTER
I2C TIMING DIAGRAMS
START BY
MASTER
0
SDA
SCL
LTC4274A/LTC4274C
4274acfc
LTC4274A/LTC4274C
I2C TIMING DIAGRAMS
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W ACK D7
START BY
MASTER
D6
D5
D4
D3
ACK BY
SLAVE
D2
D1
D0 ACK
STOP BY
MASTER
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
4274AC F08
Figure 8. Reading the Interrupt Register (Short Form)
SCL
SDA
0
0
0
1
1
0
0
R/W ACK
START BY
MASTER
0
1
ACK BY
SLAVE
FRAME 1
ALERT RESPONSE ADDRESS BYTE
0
AD3 AD2 AD1 AD0
1
NO ACK BY
MASTER
FRAME 2
SERIAL BUS ADDRESS BYTE
ACK
STOP BY
MASTER
4274AC F09
Figure 9. Reading from Alert Response Address
4274acfc
13
LTC4274A/LTC4274C
PIN FUNCTIONS
RESET: Chip Reset, Active Low. When the RESET pin is
low, the LTC4274A/LTC4274C is held inactive with the port
off and all internal registers reset to their power-up states.
When RESET is pulled high, the LTC4274A/LTC4274C
begins normal operation. RESET can be connected to
an external capacitor or RC network to provide a power
turn-on delay. Internal filtering of the RESET pin prevents
glitches less than 1μs wide from resetting the LTC4274A/
LTC4274C. Internally pulled up to VDD.
MID: Midspan Mode Input. When high, the LTC4274A/
LTC4274C acts as a midspan device. Internally pulled
down to DGND.
INT: Interrupt Output, Open Drain. INT will pull low when
any one of several events occur in the LTC4274A/LTC4274C.
It will return to a high impedance state when bits 6 or 7
are set in the Reset PB register (1Ah). The INT signal can
be used to generate an interrupt to the host processor,
eliminating the need for continuous software polling.
Individual INT events can be disabled using the Int Mask
register (01h). See the LTC4274A/LTC4274C Software
Programming documentation for more information. The
INT pin is only updated between I2C transactions.
SCL: Serial Clock Input. High impedance clock input for the
I2C serial interface bus. SCL must be tied high if not used.
SDAOUT: Serial Data Output, Open Drain Data Output for
the I2C Serial Interface Bus. The LTC4274A/LTC4274C
uses two pins to implement the bidirectional SDA function
to simplify optoisolation of the I2C bus. To implement a
standard bidirectional SDA pin, tie SDAOUT and SDAIN
together. SDAOUT should be grounded or left floating if
not used. See the Applications Information section for
more information.
SDAIN: Serial Data Input. High impedance data input for
the I2C serial interface bus. The LTC4274A/LTC4274C
uses two pins to implement the bidirectional SDA function
to simplify optoisolation of the I2C bus. To implement a
standard bidirectional SDA pin, tie SDAOUT and SDAIN
together. SDAIN must be tied high if not used. See the
Applications Information section for more information.
AD3: Address Bit 3. Tie the address pins high or low to set
the I2C serial address to which the LTC4274A/LTC4274C
responds. This address will be 010A3A2A1A0b. Internally
pulled up to VDD.
AD2: Address Bit 2. See AD3.
AD1: Address Bit 1. See AD3.
AD0: Address Bit 0. See AD3.
NC, DNC: All pins identified with “NC” or “DNC” must be
left unconnected.
DGND: Digital Ground. DGND is the return for the VDD
supply.
VDD: Logic Power Supply. Connect to a 3.3V power supply
relative to DGND. VDD must be bypassed to DGND near
the LTC4274A/LTC4274C with at least a 0.1μF capacitor.
SHDN: Shutdown, Active Low. When pulled low, SHDN
shuts down the port, regardless of the state of the internal
registers. Pulling SHDN low is equivalent to setting the
Reset Port bit in the Reset Pushbutton register (1Ah).
Internal filtering of the SHDN pin prevents glitches less
than 1μs wide from resetting the port. Internally pulled
up to VDD.
AGND: Analog Ground. AGND is the return for the VEE
supply.
SENSE: Current Sense Input. SENSE monitors the external MOSFET current via a 0.5Ω or 0.25Ω sense resistor
between SENSE and VEE. Whenever the voltage across
the sense resistor exceeds the overcurrent detection
threshold VCUT, the current limit fault timer counts up. If
the voltage across the sense resistor reaches the current
limit threshold VLIM, the GATE pin voltage is lowered to
maintain constant current in the external MOSFET. See
the Applications Information section for further details.
4274acfc
14
LTC4274A/LTC4274C
PIN FUNCTIONS
GATE: Gate Drive. GATE should be connected to the gate
of the external MOSFET for the port. When the MOSFET
is turned on, the gate voltage is driven to 12V (typ) above
VEE. During a current limit condition, the voltage at GATE
will be reduced to maintain constant current through the
external MOSFET. If the fault timer expires, GATE is pulled
down, turning the MOSFET off and recording a t CUT or
tSTART event.
OUT: Output Voltage Monitor. OUT should be connected
to the output port. A current limit foldback circuit limits
the power dissipation in the external MOSFET by reducing the current limit threshold when the drain-to-source
voltage exceeds 10V. The Power Good bit is set when the
voltage from OUT to VEE drops below 2.4V (typ). A 500k
resistor is connected internally from OUT to AGND when
the port is idle.
VEE: Main Supply Input. Connect to a –45V to –57V
supply, relative to AGND.
AUTO: AUTO Pin Mode Input. AUTO pin mode allows the
LTC4274A/LTC4274C to detect and power up a PD even
if there is no host controller present on the I2C bus. The
voltage of the AUTO pin determines the state of the internal
registers when the LTC4274A/LTC4274C is reset or comes
out of VDD UVLO (see the LTC4274A/LTC4274C Software
Programming documentation). The states of these register
bits can subsequently be changed via the I2C interface.
The real-time state of the AUTO pin is read at bit 0 in the
Pin Status register (11h). Internally pulled down to DGND.
Must be tied locally to either VDD or DGND.
MSD: Maskable Shutdown Input. Active low. When pulled
low, all ports that have their corresponding mask bit set
in the Misc Config register (17h) will be reset, equivalent
to pulling the SHDN pin low. Internal filtering of the MSD
pin prevents glitches less than 1μs wide from resetting
ports. Internally pulled up to VDD.
OPERATION
Overview
PoE++ Evolution
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE spec, known as 802.3af, allowed for 48V DC
power at up to 13W. This initial spec was widely popular,
but 13W was not adequate for some requirements. In
2009, the IEEE released a new standard, known as 802.3at
or PoE+, increasing the voltage and current requirements
to provide 25W of power.
Even during the process of creating the IEEE PoE+ 25.5W
specification, it became clear that there was a significant
and increasing need for more than 25.5W of delivered
power. The LTC4274A family responds to this market by
allowing a reliable means of providing up to 90W of delivered power to a LTPoE++ PD. The LTPoE++ specification
provides reliable detection and classification extensions to
the existing IEEE PoE technique that are backward compatible and interoperable with existing Type 1 and Type 2
PDs. Unlike other proprietary PoE++ solutions, Linear’s
LTPoE++ solution provides mutual identification between
the PSE and PD. This ensures that the LTPoE++ PD knows
it may use the requested power at start-up because it has
detected a LTPoE++ PSE. LTPoE++ PSEs can differentiate
between a LTPoE++ PD and all other types of IEEE compliant PDs allowing LTPoE++ PSEs to remain compliant and
interoperable with existing equipment.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE, or
power sourcing equipment, while a device that draws power
from the network is known as a PD, or powered device.
PSEs come in two types: Endpoints (typically network
switches or routers), which provide data and power; and
Midspans, which provide power but pass through data.
Midspans are typically used to add PoE capability to existing
non-PoE networks. PDs are typically IP phones, wireless
access points, security cameras, and similar devices.
4274acfc
15
LTC4274A/LTC4274C
OPERATION
LTC4274 Product Family
The LTC4274 is a third-generation single PSE controller
that implements four PSE ports in either an end-point
or midspan design. Virtually all necessary circuitry is
included to implement an IEEE 802.3at compliant PSE
design, requiring only an external power MOSFET and
sense resistor; these minimize power loss compared to
alternative designs with an on-board MOSFET.
The LTC4274 comes in three grades which support different PD power levels.
The A-grade LTC4274 extends PoE power delivery capabilities to LTPoE++ levels. LTPoE++ is a Linear Technology
proprietary specification allowing for the delivery of up to
90W to LTPoE++ compliant PDs. The LTPoE++ architecture
extends the IEEE physical power negotiation to include
38.7W, 52.7W, 70W and 90W power levels. The A-grade
LTC4274 also incorporates all B- and C-grade features.
The B-grade LTC4274 is a fully IEEE-compliant Type 2
PSE supporting autonomous detection, classification
and powering of Type 1 and Type 2 PDs. The B-grade
LTC4274 also incorporates all C-grade features. The
B-grade LTC4274 is marketed and numbered without the
B suffix for legacy reasons; the absence of power grade
suffix infers a B-grade part.
PSE
RJ45
4
The C-grade LTC4274 is a fully autonomous 802.3at Type 1
PSE solution. Intended for use only in AUTO pin mode,
the C-grade chipset autonomously supports detection,
classification and powering of Type 1 PDs. As a Type 1
PSE, 2-event classification is prohibited and Class 4 PDs
are automatically treated as Class 0 PDs.
PoE Basics
Common Ethernet data connections consist of two or four
twisted pairs of copper wire (commonly known as CAT-5
cable), transformer-coupled at each end to avoid ground
loops. PoE systems take advantage of this coupling arrangement by applying voltage between the center-taps
of the data transformers to transmit power from the PSE
to the PD without affecting data transmission. Figure 10
shows a high-level PoE system schematic.
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE spec defines a protocol
that determines when the PSE may apply and remove
power. Valid PDs are required to have a specific 25kΩ
common-mode resistance at their input. When such a PD
is connected to the cable, the PSE detects this signature
resistance and turns on the power. When the PD is later
disconnected, the PSE senses the open circuit and turns
power off. The PSE also turns off power in the event of a
current fault or short-circuit.
CAT 5
5
GND
3.3V
INTERRUPT
I2C
1μF
100V
X7R
–54V
5
1N4002
=4
SPARE PAIR
DGND
SMAJ58A
58V
PD
RJ45
4
AGND
VDD
INT
LTC4274A/
LTC4274C
SCL
SDAIN
SDAOUT
VEE
0.22μF
100V
X7R
1
1
2
2
Tx
DATA PAIR
3
3
Rx
SENSE GATE OUT
0.1μF
Tx
6
DATA PAIR
6
1N4002
=4
GND
100V
RCLASS
S1B
0.25Ω
5μF ≤ CIN
≤ 300μF
SMAJ58A
58V
Rx
PWRGD
LTC4265
S1B
7
7
8
8
VIN
VOUT
DC/DC
CONVERTER
+
VOUT
–
SPARE PAIR
4274AC F10
Figure 10. Power over Ethernet System Diagram
4274acfc
16
LTC4274A/LTC4274C
OPERATION
When a PD is detected, the PSE optionally looks for a
classification signature that tells the PSE the maximum
power the PD will draw. The PSE can use this information
to allocate power among several ports, police the current
consumption of the PD, or to reject a PD that will draw
more power that the PSE has available. For a 802.3af PSE,
the classification step is optional; if a PSE chooses not to
classify a PD, it must assume that the PD is a 13W (full
802.3af power) device.
Extended Power LTPoE++
New in 802.3at
The higher levels of LTPoE++ delivery impose additional
layout and component selection constraints. The LTC4274A
is offered in four power levels (-1, -2, -3, and -4) which
allows the AUTO pin mode LTC4274A to autonomously
power up to supported power levels. If the AUTO pin is
high, internal circuitry determines the maximum deliverable power. PDs requesting more than the available power
limits are not powered.
The newer 802.3at standard supersedes 802.3af and brings
several new features:
• A PD may draw as much as 25.5W. Such PDs (and the
PSEs that support them) are known as Type 2. Older
13W 802.3af equipment is classified as Type 1. Type 1
PDs will work with all PSEs; Type 2 PDs may require
Type 2 PSEs to work properly. The LTC4274A/LTC4274C
is designed to work in both Type 1 and Type 2 PSE designs, and also supports non-standard configurations
at higher power levels.
• The Classification protocol is expanded to allow Type 2
PSEs to detect Type 2 PDs, and to allow Type 2 PDs to
determine if they are connected to a Type 2 PSE. Two
versions of the new Classification protocol are available: an expanded version of the 802.3af Class Pulse
protocol, and an alternate method integrated with the
existing LLDP protocol (using the Ethernet data path).
The LTC4274A/LTC4274C fully supports the new Class
Pulse protocol and is also compatible with the LLDP
protocol (which is implemented in the data communications layer, not in the PoE circuitry).
The LTC4274A adds the capability to autonomously deliver
up to 90W of power to the PD. LTPoE++ PDs may forego
802.3 LLDP support and rely solely on the LTPoE++ Physical Classification to negotiate power with LTPoE++ PSEs;
this greatly simplifies high-power PD implementations.
LTPoE++ classification may be optionally enabled for the
LTC4274A by setting both the High Power Enable and
LTPoE++ Enable bits.
Table 1. LTPoE++ Auto Pin Mode Maximum Delivered
Power Capabilities
PART
PAIRS
PD POWER
LTC4274A-1
4
38.7W
LTC4274A-2
4
52.7W
LTC4274A-3
4
70W
LTC4274A-4
4
90W
• Fault protection current levels and timing are adjusted
to reduce peak power in the MOSFET during a fault;
this allows the new 25.5W power levels to be reached
using the same MOSFETs as older 13W designs.
4274acfc
17
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
Operating Modes
Reset and the AUTO/MID Pins
The LTC4274A/LTC4274C can operate in one of four modes:
manual, semi-auto, AUTO pin, or shutdown.
The initial LTC4274A/LTC4274C configuration depends on
the state of the AUTO and MID pins during reset. Reset
occurs at power-up, or whenever the RESET pin is pulled
low or the global Reset All bit is set. Changing the state
of AUTO or MID after power-up will not properly change
the port behavior of the LTC4274A/LTC4274C until a reset
occurs.
Table 2. Operating Modes
MODE
AUTO
PIN OPMD
DETECT/
CLASS
POWER-UP
Enabled at Automatically
Reset
AUTOMATIC
ICUT/ILIM
ASSIGNMENT
AUTO Pin
1
11b
Yes
Reserved
0
11b
N/A
N/A
N/A
Semi-auto
0
10b
Host
Enabled
Upon
Request
No
Manual
0
01b
Once Upon
Request
Upon
Request
No
Shutdown
0
00b
Disabled
Disabled
No
• In manual mode, the port waits for instructions from the
host system before taking any action. It runs a single
detection or classification cycle when commanded to
by the host, and reports the result in its Port Status
register. The host system can command the port to turn
on or off the power at any time. This mode should only
be used for diagnostic and test purposes.
• In semi-auto mode, the port repeatedly attempts to
detect and classify any PD attached to it. It reports the
status of these attempts back to the host, and waits for
a command from the host before turning on power to
the port. The host must enable detection (and optionally
classification) for the port before detection will start.
• AUTO pin mode operates the same as semi-auto mode
except that it will automatically turn on the power to the
port if detection is successful. In AUTO pin mode, ICUT
and ILIM values are set automatically by the LTC4274A/
LTC4274C. This operational mode is only valid if the
AUTO pin is high at reset or power-up and remains high
during operation.
Although typically used with a host controller, the
LTC4274A/LTC4274C can also be used in a standalone
mode with no connection to the serial interface. If there is
no host present, the AUTO pin must be tied high so that, at
reset, the port will be configured to operate automatically.
The port will detect and classify repeatedly until a PD is
discovered, set ICUT and ILIM according to the classification results, apply power after successful detection, and
remove power when a PD is disconnected.
Table 3 shows the ICUT and ILIM values that will be automatically set in standalone (AUTO pin) mode, based on
the discovered class.
Table 3. ICUT and ILIM Values in AUTO Pin Mode
CLASS
ICUT
ILIM
Class 1
112mA
425mA
Class 2
206mA
425mA
Class 3 or Class 0
375mA
425mA
Class 4
638mA
850mA
The automatic setting of the ICUT and ILIM values only
occurs if the LTC4274A/LTC4274C is reset with the AUTO
pin high.
If the standalone application is a midspan, the MID pin must
be tied high to enable correct midspan detection timing.
DETECTION
• In shutdown mode, the port is disabled and will not
detect or power a PD.
Detection Overview
Regardless of which mode it is in, the LTC4274A/LTC4274C
will remove power automatically from a port which generates a current limit fault. It will also automatically remove
power from any port that generates a disconnect event if
disconnect detection is enabled. The host controller may
also command the port to remove power at any time.
To avoid damaging network devices that were not designed
to tolerate DC voltage, a PSE must determine whether
the connected device is a real PD before applying power.
The IEEE specification requires that a valid PD have a
common-mode resistance of 25k ±5% at any port voltage below 10V. The PSE must accept resistances that fall
4274acfc
18
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
between 19k and 26.5k, and it must reject resistances
above 33k or below 15k (shaded regions in Figure 11).
The PSE may choose to accept or reject resistances in the
undefined areas between the must-accept and must-reject
ranges. In particular, the PSE must reject standard computer
network ports, many of which have 150Ω common-mode
termination resistors that will be damaged if power is applied to them (the black region at the left of Figure 11).
RESISTANCE 0Ω
10k
20k
150Ω (NIC)
PD
PSE
15k
30k
23.75k
26.25k
19k
26.5k
33k
4274AC F11
Figure 11. IEEE 802.3af Signature Resistance Ranges
4-Point Detection
The LTC4274A/LTC4274C uses a 4-point detection method
to discover PDs. False-positive detections are minimized by
checking for signature resistance with both forced-current
and forced-voltage measurements. Initially, two test currents are forced onto the port (via the OUT pin) and the
resulting voltages are measured. The detection circuitry
subtracts the two V-I points to determine the resistive slope
while removing offset caused by series diodes or leakage
at the port (see Figure 12). If the forced-current detection
yields a valid signature resistance, two test voltages are
then forced onto the port and the resulting currents are
measured and subtracted. Both methods must report
valid resistances for the port to report a valid detection.
PD signature resistances between 17k and 29k (typically)
are detected as valid and reported as Detect Good in the
CURRENT (μA)
275
25kΩ SLOPE
165
VALID PD
0V-2V
OFFSET
FIRST
DETECTION
POINT
SECOND
DETECTION
POINT
VOLTAGE
corresponding Port Status register. Values outside this
range, including open and short-circuits, are also reported.
If the port measures less than 1V at the first forced-current
test, the detection cycle will abort and Short Circuit will
be reported. Table 4 shows the possible detection results.
Table 4. Detection Status
MEASURED PD SIGNATURE
DETECTION RESULT
Incomplete or Not Yet Tested
Detect Status Unknown
<2.4k
Short Circuit
Capacitance > 2.7μF
CPD Too High
2.4k < RPD < 17k
RSIG Too Low
17k < RPD < 29k
Detect Good
>29k
RSIG Too High
>50k
Open Circuit
Voltage > 10V
Port Voltage Outside Detect Range
More On Operating Modes
The port’s operating mode determines when the LTC4274A/
LTC4274C runs a detection cycle. In manual mode, the
port will idle until the host orders a detect cycle. It will
then run detection, report the results, and return to idle
to wait for another command.
In semi-auto mode, the LTC4274A/LTC4274C autonomously polls a port for PDs, but it will not apply power
until commanded to do so by the host. The Port Status
register is updated at the end of each detection cycle. If a
valid signature resistance is detected and classification is
enabled, the port will classify the PD and report that result
as well. The port will then wait for at least 100ms (or 2
seconds if midspan mode is enabled), and will repeat the
detection cycle to ensure that the data in the Port Status
register is up-to-date.
If the port is in semi-auto mode and high power operation is enabled, the port will not turn on in response to
a power-on command unless the current detect result is
Detect Good. Any other detect result will generate a tSTART
fault if a power-on command is received. If the port is not
in high power mode, it will ignore the detection result and
apply power when commanded, maintaining backwards
compatibility with the LTC4259A.
4274AC F12
Figure 12. PD Detection
4274acfc
19
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
Behavior in AUTO pin mode is similar to semi-auto; however,
after Detect Good is reported and the port is classified (if
classification is enabled), it is automatically powered on
without further intervention. In standalone (AUTO pin)
mode, the ICUT and ILIM thresholds are automatically set;
see the Reset and the AUTO/MID Pin section for more
information.
60
PSE LOAD LINE
OVER
CURRENT
50
CURRENT (mA)
48mA
The signature detection circuitry is disabled when the port
is initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding Detect Enable bit is
cleared.
40
CLASS 4
30
CLASS 3
33mA
23mA
20
TYPICAL
CLASS 3
PD LOAD
LINE
10
0
0
5
CLASS 2
14.5mA
CLASS 1
CLASS 0
10
15
VOLTAGE (VCLASS)
6.5mA
25
20
4274AC F13
Detection of Legacy PDs
Proprietary PDs that predate the original IEEE 802.3af
standard are commonly referred to today as legacy devices. One type of legacy PD uses a large common mode
capacitance (>10μF) as the detection signature. Note that
PDs in this range of capacitance are defined as invalid, so
a PSE that detects legacy PDs is technically noncompliant
with the IEEE spec.
The LTC4274A/LTC4274C can be configured to detect this
type of legacy PD. Legacy detection is disabled by default,
but can be manually enabled. When enabled, the port will
report Detect Good when it sees either a valid IEEE PD or
a high-capacitance legacy PD. With legacy mode disabled,
only valid IEEE PDs will be recognized.
CLASSIFICATION
802.3af Classification
A PD can optionally present a classification signature to
the PSE to indicate the maximum power it will draw while
operating. The IEEE specification defines this signature as
a constant current draw when the PSE port voltage is in the
VCLASS range (between 15.5V and 20.5V), with the current
level indicating one of 5 possible PD classes. Figure 13
shows a typical PD load line, starting with the slope of the
25kΩ signature resistor below 10V, then transitioning to
the classification signature current (in this case, Class 3)
in the VCLASS range. Table 5 shows the possible classification values.
Figure 13. PD Classification
Table 5. Classification Values
CLASS
RESULT
Class 0
No Class Signature Present; Treat Like Class 3
Class 1
3W
Class 2
7W
Class 3
13W
Class 4
25.5W (Type 2)
If classification is enabled, the port will classify the PD
immediately after a successful detection cycle in semi-auto
or AUTO pin modes, or when commanded to in manual
mode. It measures the PD classification signature by applying 18V for 12ms (both values typical) to the port via
the OUT pin and measuring the resulting current; it then
reports the discovered class in the Port Status register.
If the LTC4274A/LTC4274C is in AUTO pin mode, it will
additionally use the classification result to set the ICUT
and ILIM thresholds. See the Reset and the AUTO/MID Pin
section for more information.
The classification circuitry is disabled when the port is
initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding Class Enable bit is
cleared.
4274acfc
20
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
802.3at 2-Event Classification
The 802.3at specification defines two methods of classifying a Type 2 PD. The LTC4274A supports 802.3at 2-event
classification. The LTC4274C does not support 2-event
classification.
One method adds extra fields to the Ethernet LLDP data
protocol; although the LTC4274A/LTC4274C is compatible
with this classification method, it cannot perform classification directly since it doesn’t have access to the data
path. LLDP classification requires the PSE to power the
PD as a standard 802.3af (Type 1) device. It then waits
for the host to perform LLDP communication with the PD
and update the PSE port data. The LTC4274A/LTC4274C
supports changing the ILIM and ICUT levels on the fly, allowing the host to complete LLDP classification.
The second 802.3at classification method, known as
2-event classification or ping-pong, is supported by the
LTC4274A. A Type 2 PD that is requesting more than 13W
will indicate Class 4 during normal 802.3af classification.
If the LTC4274A sees Class 4, it forces the port to a specified lower voltage (called the mark voltage, typically 9V),
pauses briefly, and then re-runs classification to verify the
Class 4 reading (Figure 1). It also sets a bit in the High
Power Status register to indicate that it ran the second
classification cycle. The second cycle alerts the PD that
it is connected to a Type 2 PSE which can supply Type 2
power levels.
2-event ping-pong classification is enabled by setting a bit
in the port’s High Power Mode register. Note that a pingpong enabled port only runs the second classification cycle
when it detects a Class 4 device; if the first cycle returns
Class 0 to 3, the port assumes it is connected to a Type 1
PD and does not run the second classification cycle.
Invalid Type 2 Class Combinations
The 802.3at specification defines a Type 2 PD class signature as two consecutive Class 4 results; a Class 4 followed by a Class 0-3 is not a valid signature. In AUTO pin
mode, the LTC4274A will power a detected PD regardless
of the classification results, with one exception: if the PD
presents an invalid Type 2 signature (Class 4 followed by
Class 0 to 3), the LTC4274A will not provide power and
will restart the detection process. To aid in diagnosis, the
Port Status register will always report the results of the
last class pulse, so, for example, an invalid Class 4–Class 2
combination would report a second class pulse was run
in the High Power Status register (which implies that the
first cycle found Class 4), and Class 2 in the Port Status
register.
POWER CONTROL
External MOSFET, Sense Resistor Summary
The primary function of the LTC4274A/LTC4274C is to
control the delivery of power to the PSE port. It does this
by controlling the gate drive voltage of an external power
MOSFET while monitoring the current via an external
sense resistor and the output voltage at the OUT pin. This
circuitry serves to couple the raw VEE input supply to the
port in a controlled manner that satisfies the PD’s power
needs while minimizing power dissipation in the MOSFET
and disturbances on the VEE backplane.
The LTC4274A/LTC4274C is designed to use 0.25Ω sense
resistors to minimize power dissipation. It also supports
0.5Ω sense resistors, which are the default when LTC4258/
LTC4259A compatibility is desired.
Inrush Control
Once the command has been given to turn on a port, the
LTC4274A/LTC4274C ramps up the GATE pin of the port’s
external MOSFET in a controlled manner. Under normal
power-up circumstances, the MOSFET gate will rise until
the port current reaches the inrush current limit level
(typically 450mA), at which point the GATE pin will be
servoed to maintain the specified IINRUSH current. During
this inrush period, a timer (tSTART) runs. When output
charging is complete, the port current will fall and the GATE
pin will be allowed to continue rising to fully enhance the
MOSFET and minimize its on-resistance. The final VGS is
nominally 12V. The inrush period is maintained until the
tSTART timer expires. At this time if the inrush current limit
level is still exceeded the port will be turned back off and
a tSTART fault reported.
4274acfc
21
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
Current Limit
The LTC4274A/LTC4274C port includes two current limiting thresholds (ICUT and ILIM), each with a corresponding
timer (tCUT and tLIM). Setting the ICUT and ILIM thresholds
depends on several factors: the class of the PD, the voltage of the main supply (VEE), the type of PSE (Type 1 or
Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of
the MOSFET, and whether or not the system is required
to implement class enforcement.
Per the IEEE specification, the LTC4274A/LTC4274C will
allow the port current to exceed ICUT for a limited period
of time before removing power from the port, whereas it
will actively control the MOSFET gate drive to keep the port
current below ILIM. The port does not take any action to
limit the current when only the ICUT threshold is exceeded,
but does start the tCUT timer. If the current drops below
the ICUT current threshold before its timer expires, the
tCUT timer counts back down, but at 1/16 the rate that it
counts up. If the tCUT timer reaches 60ms (typical) the
port is turned off and the port tCUT fault is set. This allows
the current limit circuitry to tolerate intermittent overload
signals with duty cycles below about 6%; longer duty cycle
overloads will turn the port off.
The ILIM current limiting circuit is always enabled and
actively limiting port current. The tLIM timer is enabled
only when the programmable tLIM field is non-zero. This
allows tLIM to be set to a shorter value than tCUT to provide
more aggressive MOSFET protection and turn off a port
before MOSFET damage can occur. The tLIM timer starts
when the ILIM threshold is exceeded. When the tLIM timer
reaches 1.7ms (typ) times the programmable tLIM field the
port is turned off and the port tLIM fault is set. When the
tLIM field is zero, tLIM behaviors are tracked by the tCUT
timer, which counts up during both ILIM and ICUT events.
ICUT is typically set to a lower value than ILIM to allow the
port to tolerate minor faults without current limiting.
Per the IEEE specification, the LTC4274A/LTC4274C will
automatically set ILIM to 425mA (shown in bold in Table 6)
during inrush at port turn-on, and then switch to the
programmed ILIM setting once inrush has completed.
To maintain IEEE compliance, ILIM should be kept at 425mA
for all Type 1 PDs, and 850mA if a Type 2 PD is detected.
ILIM is automatically reset to 425mA when a port turns off.
Table 6. Example Current Limit Settings
INTERNAL REGISTER SETTING (hex)
ILIM (mA)
RSENSE = 0.5Ω
53
88
106
08
159
89
213
80
266
8A
319
09
372
8B
425
00
478
8E
531
92
584
CB
638
10
90
744
D2
9A
RSENSE = 0.25Ω
88
08
89
80
8A
850
40
C0
956
4A
CA
1063
50
D0
1169
5A
DA
1275
60
E0
1488
52
49
1700
40
1913
4A
2125
50
2338
5A
2550
60
2975
52
ILIM Foldback
The LTC4274A/LTC4274C features a two-stage foldback
circuit that reduces the port current if the port voltage falls
below the normal operating voltage. This keeps MOSFET
power dissipation at safe levels for typical 802.3af MOSFETs, even at extended 802.3at power levels. Current limit
and foldback behavior are programmable. Table 6 gives
examples of recommended ILIM register settings.
4274acfc
22
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
The LTC4274A/LTC4274C will support current levels well
beyond the maximum values in the 802.3at specification.
The shaded areas in Table 6 indicate settings that may
require a larger external MOSFET, additional heat sinking,
or enabling tLIM .
MOSFET Fault Detection
The LTC4274A/LTC4274C PSE port is designed to tolerate significant levels of abuse, but in extreme cases it is
possible for the external MOSFET to be damaged. A failed
MOSFET may short source to drain, which will make the
port appear to be on when it should be off; this condition
may also cause the sense resistor to fuse open, turning
off the port but causing the LTC4274A/LTC4274C SENSE
pin to rise to an abnormally high voltage. A failed MOSFET
may also short from gate to drain, causing the LTC4274A/
LTC4274C GATE pin to rise to an abnormally high voltage.
The LTC4274A/LTC4274C OUT, SENSE and GATE pins are
designed to tolerate up to 80V faults without damage.
If the LTC4274A/LTC4274C sees any of these conditions for
more than 180μs, it disables all port functionality, reduces
the gate drive pull-down current for the port and reports
a FET Bad fault. This is typically a permanent fault, but
the host can attempt to recover by resetting the port, or
by resetting the entire chip if a port reset fails to clear the
fault. If the MOSFET is in fact bad, the fault will quickly
return, and the port will disable itself again.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a tSTART fault if the LTC4274A/LTC4274C
attempts to turn on the port.
Voltage and Current Readback
The LTC4274A/LTC4274C measures the output voltage
and current at the port with an internal A/D converter. Port
data is only valid when the port power is on. The converter
has two modes:
• Slow mode: 14 samples per second, 14.5 bits resolution
• Fast mode: 440 samples per second, 9.5 bits resolution
In fast mode, the least significant 5 bits of the lower byte
are zeroes so that bit scaling is the same in both modes.
Disconnect
The LTC4274A/LTC4274C monitors the port to make sure
that the PD continues to draw the minimum specified
current. A disconnect timer counts up whenever port
current is below 7.5mA (typ), indicating that the PD has
been disconnected. If the tDIS timer expires, the port will
be turned off and the disconnect bit in the fault event register will be set. If the current returns before the tDIS timer
runs out, the timer resets and will start counting from the
beginning if the undercurrent condition returns. As long
as the PD exceeds the minimum current level more often
than tDIS, it will stay powered.
Although not recommended, the DC disconnect feature
can be disabled by clearing the DC Disconnect Enable
bit. Note that this defeats the protection mechanisms
built into the IEEE spec, since a powered port will stay
powered after the PD is removed. If the still-powered port
is subsequently connected to a non-PoE data device, the
device may be damaged.
The LTC4274A/LTC4274C does not include AC disconnect circuitry, but includes an AC Disconnect Enable bit
to maintain compatibility with the LTC4259A. If the AC
Disconnect Enable bit is set, DC disconnect will be used.
Shutdown Pin
The LTC4274A/LTC4274C includes a hardware SHDN pin.
When the SHDN pin is pulled to DGND, the port will be
shut off immediately. The port remains shut down until
re-enabled via I2C or a device reset in AUTO pin mode.
Masked Shutdown
The LTC4274A/LTC4274C provides a low latency port
shedding feature to quickly reduce the system load when
required. By allowing a pre-determined set of ports to
be turned off, the current on an overloaded main power
supply can be reduced rapidly while keeping high priority
devices powered. Each port can be configured to high or
low priority; all low-priority ports will shut down within
6.5μs after the MSD pin is pulled low. If a port is turned off
via MSD, the corresponding Detection and Classification
Enable bits are cleared, so the port will remain off until
the host explicitly re-enables detection.
4274acfc
23
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
SERIAL DIGITAL INTERFACE
EXTERNAL COMPONENT SELECTION
Overview
Power Supplies and Bypassing
The LTC4274A/LTC4274C communicates with the host using a standard SMBus/I2C 2-wire interface. The LTC4274A/
LTC4274C is a slave-only device, and communicates with
the host master using the standard SMBus protocols.
Interrupts are signaled to the host via the INT pin. The
timing diagrams (Figures 5 through 9) show typical communication waveforms and their timing relationships. More
information about the SMBus data protocols can be found
at www.smbus.org.
The LTC4274A/LTC4274C requires two supply voltages to
operate. VDD requires 3.3V (nominally) relative to DGND.
VEE requires a negative voltage of between –45V and –57V
for Type 1 PSEs, –51V to –57V for Type 2 PSEs or –54.75V
to –57V for LTPoE++ PSEs, relative to AGND. The relationship between the two grounds is not fixed; AGND can be
referenced to any level from VDD to DGND, although it
should typically be tied to either VDD or DGND.
The LTC4274A/LTC4274C requires both the VDD and VEE
supply rails to be present for the serial interface to function.
Bus Addressing
The LTC4274A/LTC4274C’s primary serial bus address is
010xxxxb, with the lower four bits set by the AD3-AD0
pins; this allows up to 16 LTC4274A/LTC4274Cs on a
single bus. All LTC4274A/LTC4274Cs also respond to
the address 0110000b, allowing the host to write the
same command (typically configuration commands) to
multiple LTC4274A/LTC4274Cs in a single transaction. If
the LTC4274A/LTC4274C is asserting the INT pin, it will
also respond to the alert response address (0001100b)
per the SMBus spec.
Interrupts and SMBALERT
Most LTC4274A/LTC4274C port events can be configured
to trigger an interrupt, asserting the INT pin and alerting
the host to the event. This removes the need for the host
to poll the LTC4274A/LTC4274C, minimizing serial bus
traffic and conserving host CPU cycles. Multiple LTC4274A/
LTC4274Cs can share a common INT line, with the host
using the SMBALERT protocol (ARA) to determine which
LTC4274A/LTC4274C caused an interrupt.
VDD provides power for most of the internal LTC4274A/
LTC4274C circuitry, and draws a maximum of 3mA. A
ceramic decoupling cap of at least 0.1μF should be placed
from VDD to DGND, as close as practical to each LTC4274A/
LTC4274C chip.
Figure 14 shows a three component low dropout regulator for a negative supply to DGND generated from the
negative VEE supply. VDD is tied to AGND and DGND is
negative referenced to AGND. This regulator drives a single
LTC4274A/LTC4274C device. In Figure 15, DGND is tied
to AGND in this boost converter circuit for a positive VDD
supply of 3.3V above AGND. This circuit can drive multiple
LTC4274A/LTC4274C devices and opto couplers.
AGND
D1
CMHZ4687-4.3V
VDD
C1
0.1μF
AGND
LTC4274A/
LTC4274C
DGND
Q2
CMPTA92
R5
750k
VEE
VEE
4274AC F14
Figure 14. Negative LDO to DGND
Register Description
For information on serial bus usage and device configuration and status, refer to the LTC4274A/LTC4274C Software
Programming documentation.
4274acfc
24
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
L3
100μH
SUMIDA CDRH5D28-101NC
L4
10μH
SUMIDA CDRH4D28-100NC
D28
B1100
3.3V AT 400mA
C76
10μF
63V
+
R51
4.7k
1%
C78
0.22μF
100V
5
VCC
C77
0.22μF
100V
1
R58
10Ω
R60
10Ω
C74
100μF
6.3V
C75
10μF
16V
R53
4.7k
1%
R54
56k
C79
2200pF
ITH/RUN
C73
10μF
6.3V
R52
3.32k
1%
Q13
FMMT723
NGATE
6
Q14
FMMT723
Q15
FDC2512
LTC3803
3
VFB
SENSE
4
GND
2
R57
1k
R55
806Ω
1%
R59
0.100Ω
1%, 1W
R56
47.5k
1%
VEE
4274AC F15
Figure 15. Positive VDD Boost Converter
VEE is the main supply that provides power to the PD.
Because it supplies a relatively large amount of power and
is subject to significant current transients, it requires more
design care than a simple logic supply. For minimum IR
loss and best system efficiency, set VEE near maximum
amplitude (57V), leaving enough margin to account for
transient over- or undershoot, temperature drift, and the
line regulation specs of the particular power supply used.
Bypass capacitance between AGND and VEE is very important for reliable operation. If a short-circuit occurs at the
output port it can take as long as 1μs for the LTC4274A/
LTC4274C to begin regulating the current. During this
time the current is limited only by the small impedances
in the circuit and a high current spike typically occurs,
causing a voltage transient on the VEE supply and possibly
causing the LTC4274A/LTC4274C to reset due to a UVLO
fault. A 1μF, 100V X7R capacitor placed near the VEE pin
is recommended to minimize spurious resets.
Isolating the Serial Bus
The LTC4274A/LTC4274C includes a split SDA pin (SDAIN
and SDAOUT) to ease opto-isolation of the bidirectional
SDA line.
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be isolated
from each other, provided that the segments are connected
to devices residing within a single building on a single
power distribution system.
For simple devices such as small PoE switches, the isolation requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
standard I2C/SMBus SDA pin.
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to
protective ground for some other reason, the Power over
Ethernet subsystem (including all LTC4274A/LTC4274Cs)
must be electrically isolated from the rest of the system.
Figure 16 shows a typical isolated serial interface. The
SDAOUT pin of the LTC4274A/LTC4274C is designed to
drive the inputs of an opto-coupler directly. Standard I2C/
SMBus devices typically cannot drive opto-couplers, so U1
is used to buffer the signals from the host controller side.
4274acfc
25
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
0.1μF
2k
U2
2001
VDD CPU
U1
ISOLATED
3.3V
SCL
0.1μF
2001
2k
SDA
HCPL-063L
TO
CONTROLLER
+
10μF
U3
2001
ISOLATED
GND
VDD LTC4274A/
INT LTC4274C
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND
2001
SMBALERT
0.1μF
GND CPU
U1: FAIRCHILD NC7WZ17
U2, U3: AGILENT HCPL-063L
4274AC F16
HCPL-063L
Figure 16. Opto-Isolating the I2C Bus
4274acfc
26
LTC4274A/LTC4274C
APPLICATIONS INFORMATION
External MOSFET
ESD/Cable Discharge Protection
Careful selection of the power MOSFET is critical to system
reliability. LTC recommends either Fairchild IRFM120A,
FDT3612, FDMC3612 or Philips PHT6NQ10T for their
proven reliability in Type 1 and Type 2 PSE applications.
Non-standard applications that provide more current than
the 850mA IEEE maximum may require heat sinking and
other MOSFET design considerations. Contact LTC Applications before using a MOSFET other than one of these
recommended parts.
Ethernet ports can be subject to significant ESD events when
long data cables, each potentially charged to thousands
of volts, are plugged into the low impedance of the RJ45
jack. To protect against damage, the port requires a pair
of clamp diodes; one to AGND and one to VEE (Figure 10).
An additional surge suppressor is required for each
LTC4274A/LTC4274C chip from VEE to AGND. The diodes
at the port steer harmful surges into the supply rails,
where they are absorbed by the surge suppressor and the
VEE bypass capacitance. The surge suppressor has the
additional benefit of protecting the LTC4274A/LTC4274C
from transients on the VEE supply.
Sense Resistor
The LTC4274A/LTC4274C is designed to use either 0.5Ω or
0.25Ω current sense resistors. For new designs 0.25Ω is
recommended to reduce power dissipation; the 0.5Ω option is intended for existing systems where the LTC4274A/
LTC4274C is used as a drop-in replacement for the LTC4258
or LTC4259A. The lower sense resistor values reduce
heat dissipation. Four commonly available 1Ω resistors
(0402 or larger package size) can be used in parallel in
place of a single 0.25Ω resistor. In order to meet the ICUT
and ILIM accuracy required by the IEEE specification, the
sense resistors should have ±1% tolerance or better, and
no more than ±200ppm/°C temperature coefficient.
Port Output Cap
The port requires a 0.22μF cap across its output to keep
the LTC4274A/LTC4274C stable while in current limit
during startup or overload. Common ceramic capacitors
often have significant voltage coefficients; this means the
capacitance is reduced as the applied voltage increases.
To minimize this problem, X7R ceramic capacitors rated
for at least 100V are recommended.
S1B diodes work well as port clamp diodes, and an
SMAJ58A or equivalent is recommended for the VEE surge
suppressor.
LAYOUT GUIDELINES
Strict adherence to board layout, parts placement and
routing guidelines is critical for optimal current reading accuracy, IEEE compliance, system robustness, and
thermal dissipation.
Power delivery above 25.5W imposes additional component and layout restraints. Specifically MOSFET, sense
resistor and transformer selection is crucial to safe and
reliable system operation.
Contact LTC Applications to obtain a full set of layout
guidelines, example layouts and BOMs.
4274acfc
27
LTC4274A/LTC4274C
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 p 0.05
5.50 p 0.05
5.15 ± 0.05
4.10 p 0.05
3.00 REF
3.15 ± 0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
5.5 REF
6.10 p 0.05
7.50 p 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 p 0.10
0.75 p 0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 p0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
7.00 p 0.10
5.50 REF
3.15 ± 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 p 0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4274acfc
28
LTC4274A/LTC4274C
REVISION HISTORY
REV
DATE
DESCRIPTION
A
9/11
Changed GATE typ voltage to 12V.
B
C
1/12
8/12
PAGE NUMBER
3, 15, 21
Revised VILD text under Digital Interface.
4
Table 4 reference and caption changed to Table 5.
20
Revised power supply voltage figures under Power Supplies and Bypassing.
24
Text CUT/LIM changed to ICUT/ILIM in the Related Parts section.
30
Specified SMAJ58A for Zener diode.
30
Changed LTPoE++ power levels from 35W, 45W to 38.7W, 52.7W respectively.
1, 2, 16, 17
Revised Max value for VILD I2C Input Low Voltage.
4
Clarified AUTO Pin mode relationship to Reset pin.
Table 1: Changed twisted pair requirement from 2-pair to 4-pair for 38.7W and 52.7W
18
17
4274acfc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
29
LTC4274A/LTC4274C
TYPICAL APPLICATION
One Complete Isolated Powered Ethernet Port
ISOLATED
3.3V
ISOLATED
GND
0.1μF
DGND AGND
2k
U2
200Ω
LTC4274A/
LTC4274C
SCL
SDAIN
SDAOUT
INT
VDD CPU
U1
SCL
VEE
2k
200Ω
1μF
100V
X7R
TO
CONTROLLER
0.22μF
100V
X7R
VDD
FB1
SENSE GATE OUT
FB2
S1B
RSENSE
0.25Ω
SDA
Q1
HCPL-063L
U3
SMAJ58A
200Ω
ISOLATED
–54V
S1B
RJ45
CONNECTOR
T1
s
200Ω
SMBALERT
s
s
s
s
0.01μF
200V
75Ω
0.01μF
200V
75Ω
75Ω
75Ω
1
2
3
4
5
6
7
8
s
PHY
0.1μF
GND CPU
(NETWORK
PHYSICAL
LAYER
CHIP)
s
s
s
s
s
HCPL-063L
0.01μF
200V
0.01μF
200V
s
4274AC TA02
1000pF
2000V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC4270/LTC4271
12-Port PoE/PoE+/LTPoE++ PSE Controller
Transformer Isolation, Supports Type 1, Type 2 and LTPoE++ PDs
LTC4266
Quad IEEE 802.3at PoE PSE Controller
2-Event Classification, Programmable ICUT /ILIM
LTC4266A/LTC4266C
Quad IEEE 802.3at PoE PSE Controller
13W through 90W Support
LTC4274
Single IEEE 802.3at PoE PSE Controller
2-Event Classification, Programmable ICUT /ILIM
LTC4265
IEEE 802.3at PD Interface Controller
100V, 1A Internal Switch, 2-Event Classification Recognition
LTC4267
IEEE 802.3af PD Interface with Integrated Switching
Regulator
Internal 100V, 400mA Switch, Dual Inrush Current,
Programmable Class
LTC4269-1
IEEE 802.3at PD Interface with Integrated Flyback
Switching Regulator
2-Event Classification, Programmable Classification, Synchronous
No-Opto Flyback Controller, 50kHz to 250kHz, Auxiliary Support
LTC4269-2
IEEE 802.3at PD Interface with Integrated Forward
Switching Regulator
2-Event Classification, Programmable Classification, Synchronous
Forward Controller, 100kHz to 500kHz, Auxiliary Support
LTC4278
IEEE 802.3at PD Interface with Integrated Flyback
Switching Regulator
2-Event Classification, Programmable Classification, Synchronous
No-Opto Flyback Controller, 50kHz to 250kHz, 12V Auxiliary Support
4274acfc
30 Linear Technology Corporation
LT 0812 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
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© LINEAR TECHNOLOGY CORPORATION 2011