P1P8160A Low Jitter Clock Generator and Peak EMI Reduction IC Product Description P1P8160A is a versatile low jitter clock generator and spread spectrum frequency modulator designed to reduce electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The device allows significant system cost savings by reducing the number of circuit board layers ferrite beads, shielding and other passive components that are traditionally required to pass EMI regulations. P1P8160A modulates the output of a PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. P1P8160A accepts an input from either a 27 MHz fundamental Crystal or from an external reference clock and generates a 100 MHz Spread Spectrum clock. The device also features a 27MHz reference clock output. Two Tri−level logic pins, SS1% and SS2% enables selecting one of the eight different frequency deviations along with SSOFF. Refer to Frequency Deviation Selection table. P1P8160A operates over a supply voltage range of 3.3 V ± 10%. P1P8160A is available in a 10 Pin WDFN (3 mm x 3 mm) package, over temperature range −10°C to +85°C. Features http://onsemi.com MARKING DIAGRAM 1 WDFN10 CASE 511BK A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONFIGURATION CLKIN/XIN 1 VSS 2 10 XOUT 9 RefOUT SS2% 3 8 VDD2 VDD1 4 7 SS1% ModOUT 5 • LVCMOS Peak EMI Reduction • Input clock Frequency: 1P 8160A ALYWG G 6 VSS 27 MHz: External Crystal or Reference Clock • Output clock Frequencies: • • • • • • • 100 MHz Spread Spectrum Clock 27 MHz Refout Two Tri−level Logic Pins for Selecting Eight Different Frequency Deviations Along with SSOFF Modulation Rate at 100 MHz: 32 kHz Low Cycle−Cycle Jitter, LT Jitter Supply voltage: 3.3 V ± 10% Temperature Range: −10°C to +85°C 10 Pin WDFN, 3 mm x 3 mm Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Application • P1P8160A is targeted for use in a broad range of notebook, desktop and embedded digital applications. © Semiconductor Components Industries, LLC, 2010 October, 2010 − Rev. 2 1 Publication Order Number: P1P8160A/D P1P8160A VDD1 CLKIN/XIN VDD2 SS2% SS1% ModOUT Crystal PLL Oscillator XOUT RefOUT 2 VSS Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 CLKIN / XIN I Crystal connection or External Reference Clock Input. 2 VSS P Ground to entire chip 3 SS2% I Frequency Deviation Selection. Tri−level logic pin. Has an internal pull down resistor. Refer to Frequency Deviation Selection table 4 VDD1 5 ModOUT O Buffered 100MHz spread spectrum clock output 6 VSS P Ground to entire chip 7 SS1% I Frequency Deviation Selection. Tri−level logic pin. Has an internal pull down resistor. Refer to Frequency Deviation Selection table 8 VDD2 P Supply Voltage for 27 MHz RefOUT 9 RefOUT O Buffered reference clock output 10 XOUT O Crystal connection. If using an external reference, this pin must be left unconnected. Supply Voltage for 100 MHz ModOUT 3 Level Digital Logic SS1% and SS2% digital inputs are designed to sense 3 different logic levels designated as High “1”, Low “0” and Middle “M”. With this 3−Level digital inputs, 9 different logic states can be detected. Use 5k/5k resistor divider at SS1% and SS2% pins from VDD to VSS to obtain VDD/2, Middle “M” logic level as shown: Logic Control Pins 1 SS1%, SS2% to VDD VDD VDD 5k M SS1%, SS2% 5k 0 VSS SS1%, SS2% to VSS (UNCONNECTED) VSS http://onsemi.com 2 P1P8160A Table 2. FREQUENCY DEVIATION SELECTION TABLE SS2% (Pin#3) SS1% (Pin#7) Deviation at 100 MHz (%) (Pin#5) L L SSOFF L M −0.5 L H −2.5 M L −0.25 M M −0.75 M H −1 H L −1.5 H M −2 H H −3 ModRate (kHz) 32 Table 3. OPERATING CONDITIONS Symbol VDD Parameter Min Max Unit Voltage on any pin with respect to VSS 2.97 3.63 V TA Operating Temperature −10 +85 °C CL Load Capacitance 15 pF CIN Input Capacitance 7 pF Table 4. ABSOLUTE MAXIMUM RATINGS Symbol VDD, VIN TSTG Parameter Rating Unit Voltage on any pin with respect to Ground −0.5 to +4.6 V Storage Temperature −65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 kV TDV Static Discharge Voltage (As per JEDEC STD 22− A114−B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. DC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ± 10%, Ambient Temperature Range: −10°C to +85°C unless otherwise specified) Parameter Symbol VDD Supply Voltage Min Typ Max Unit 2.97 3.3 3.63 V VIL Input Low Voltage (CLKIN/XIN, SS1%, SS2% Inputs) 0 0.2 V VIM Input Middle Voltage (SS1%, SS2% Inputs) 0.4 x VDD 0.6 x VDD V VIH Input High Voltage (CLKIN/XIN, SS1%, SS2% Inputs) 0.9 x VDD VDD V VOL Output Low Voltage (ModOUT, RefOUT) IOL = 15 mA 0.4 V VOH Output High Voltage (ModOUT, RefOUT) IOH = −15 mA IDD Dynamic Supply Current (CL = 15 pF, VDD = 3.63 V, T = +85°C) CIN1 Input Capacitance (XIN and XOUT) CIN2 Input Capacitance (SS1%, SS2% Inputs) RPD Pull Down Resistor (SS1%, SS2% Inputs) NOTE: 2.4 V 22 6.0 100 The voltage on any input or I/O pin cannot exceed the power pin during power up. http://onsemi.com 3 200 mA pF 7.0 pF 250 kW P1P8160A Table 6. AC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ± 10%, Ambient Temperature Range: −10°C to +85°C unless otherwise specified) Parameter Symbol fIN fOUT Min Typ Max Unit Input Clock frequency (Tolerance: ±10ppm) 27 MHz ModOUT Clock frequency (SS1% & SS2% = 0) (Tolerance: ±30ppm) 100 MHz RefOUT Clock frequency (Tolerance: ±30ppm) 27 tLH, tHL (Note 2) RefOUT Rise and Fall time (Measured between 20% to 80%) CL = 5 pF 0.75 1.5 CL = 15 pF 1.25 2.0 tLH, tHL (Note 2) ModOUT Rise and Fall time (Measured between 20% to 80%) CL = 5 pF 0.75 1.0 CL = 15 pF 1.25 1.75 50 55 % 125 200 ps 27 MHz, RefOUT 150 300 100 MHz ModOUT (SSOFF) 350 600 45 ns ns TDCOUT (Notes 1, 2) Output Clock Duty Cycle TJC (Notes 1, 2) Cycle−Cycle Jitter (For ModOUT, RefOUT) TJL (Notes 1, 2) Long Term Jitter (10k cycles) tON (Notes 1, 2) Power Up Time (Stable power supply, valid input clock to valid Clock on ModOUT). 5 ms tSS% (Notes 1, 2) Spread Percentage Setting Time (Time from SS1%/SS2% change to stable ModOUT with change in spread %) 1 ms MF (Notes 1, 2) Modulation Frequency 33 kHz FMTSR (Notes 1, 2) Frequency Modulation Type and Slew Rate (Triangular Modulation Profile) 0.125 %/ms 31 1. Parameters are specified with 15 pF loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production R Crystal CL Rx CL Figure 2. Typical Crystal Interface Circuit CL = 2 * (CP – CS), Where CP = Load capacitance of crystal specified in a Crystal Datasheet CS = Stray capacitance due to CIN, PCB, Trace etc. CL = Load capacitance to be used Rx is used to reduce power dissipation in the Crystal http://onsemi.com 4 32 P1P8160A VDD Ferrite Bead 1.0 mF 4 8 VDD1 VDD2 1.0 mF ModOUT 5 1 CLKIN/XIN Y1 27 MHz CL Tri−level SS% Control 7 SS1% 27M (RefOUT) RefOUT 9 P1P8160A VDD 100M (ModOUT) Rs 10 XOUT CL Rs VDD Tri−level SS% Control SS2% 3 VSS 2,6 NOTE: Refer Pin Description table for Functionality details Figure 3. Typical Application Schematic ORDERING INFORMATION Part Number P1P8160AG−10CR Top Marking Temperature Package Shipping† 1P 8160A −10°C to +85°C 10 pin (3 mm x 3 mm) WDFN 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. http://onsemi.com 5 P1P8160A PACKAGE DIMENSIONS WDFN10 3x3, 0.5P CASE 511BK−01 ISSUE O D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L A B L1 PIN ONE REFERENCE 2X 0.10 C 2X ÍÍÍ ÍÍÍ ÍÍÍ 0.10 C DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS ÉÉ ÉÉ ÇÇ EXPOSED Cu TOP VIEW A3 DETAIL B 0.10 C A1 DETAIL B ALTERNATE CONSTRUCTIONS A 0.08 C ÉÉ ÉÉ ÇÇ A3 MOLD CMPD A1 NOTE 4 C SIDE VIEW DETAIL A 10X D2 1 SEATING PLANE MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 3.00 BSC 2.20 2.40 3.00 BSC 1.50 1.70 0.50 BSC 0.20 --0.35 0.45 --0.15 RECOMMENDED SOLDERING FOOTPRINT* 2.46 0.62 L DIM A A1 A3 b D D2 E E2 e K L L1 5 E2 1.76 3.30 PACKAGE OUTLINE K 10 1 6 10X e BOTTOM VIEW b 0.10 C A 0.05 C 0.50 PITCH B NOTE 3 10X 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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