March 12, 2012 LM3017 High Efficiency Low-Side Controller with True Shutdown General Description Features The LM3017 is a versatile low-side NFET controller incorporating true shutdown and input side current limiting. It is designed for simple implementation of boost conversions in Thunderbolt™ Technology. The LM3017 can also be configured for flyback or SEPIC designs. The input voltage range of 5V to 18V accommodates a two or three cell lithium ion battery or a 12V rail. The enable pin accepts a single input to drive three different modes of operation: boost, pass through, or shutdown mode. The LM3017 draws very low current in shutdown mode, typically 40nA from the input supply. The LM3017 provides an adjustable output from VIN to 20V in order to drive the Power Load Switch or Mux for the host Thunderbolt™ port. The ability to drive an external high-side NMOS provides for true isolation of the load from the input. Current limiting on the input ensures that inrush and shortcircuit currents are always under control. The LM3017 incorporates built in thermal shutdown, cycle-by-cycle current limit, short circuit protection, output overvoltage protection, and soft-start. It is available in a 10-pin QFN package. ■ Fully compliant to Thunderbolt™ Technology pass through, or shutdown ■ Built-in charge pump for high-side NFET disconnect ■ ■ ■ ■ ■ ■ switch 1A push-pull driver for low-side NFET Peak current mode control Simple slope compensation Protection features: thermal shutdown, cycle-by-cycle current limit, short circuit protection, output overvoltage protection, and latch-off Internal soft-start 2.4mm x 2.7mm x 0.8mm 10-pin QFN package Applications ■ Thunderbolt Technology™ Host Ports ■ Notebook and Desktop Computers, Tablets, and Other Key Specifications ■ ■ ■ ■ ■ specifications ■ True shutdown for short circuit protection ■ Single enable pin with three modes of operation: boost, Input voltage range of 5V to 18V 400 kHz fixed frequency operation ±1% reference voltage accuracy over temperature Low shutdown current (< 1µA), 40nA typical ±3% D.C. input current limit Portable Consumer Electronics ■ Hard Disc Drives, Solid State Drives ■ Offline Power Supplies ■ Set-Top Boxes Typical Application Circuit 30180901 Typical Boost Converter Application © 2012 Texas Instruments Incorporated 301809 SNOSC66 www.ti.com LM3017 High Efficiency Low-Side Controller with True Shutdown PRELIMINARY LM3017 Connection Diagram 30180903 Top View 10-pin QFN Pin Descriptions Pin Name 1 VCC Description Function Driver supply voltage pin Output of internal regulator powering low side NMOS driver. A minimum of 0.47µF must be connected from this pin to PGND for proper operation. 2 DR Low-side NMOS gate driver output Output gate drive to low side NMOS gate. 3 PGND Power Ground Ground for power section. External power circuit reference. Should be connected to AGND at a single point. 4 VG High side NMOS gate driver output Output gate drive to high side NMOS gate. 5 EN/MODE Multi-function input pin This input provides for chip enable, and mode selection. See functional description for details. 6 FB Feed-back input pin Negative input to error amplifier. Connect to feed-back resistor tap to regulate output. 7 COMP Compensation pin A resistor and capacitor combination connected to this pin provides frequency compensation for the regulator control loop. 8 AGND Analog Ground Ground for analog control circuitry. Reference point for all stated voltages. 9 ISEN Current sense input Current sense input, with respect to Vin, for all current limit functions. 10 VIN Power Supply input pin Input supply to regulator. See applications section for recommendations on bypass capacitors on this pin. www.ti.com 2 If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VIN to PGND, AGND FB, EN/MODE, COMP, VCC -0.3V to 20V 1.0A Operating Ratings -0.3V to 20V -0.3V to 6V (Note 1) VIN Junction Temperature Range (TJ) ESD Susceptibility (Note 2) 5V to 18V −40°C to +125°C ±2 kV Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: Vin = 12V. Symbol VFB Parameter Conditions Feedback Voltage Vcomp = 1.4V, 5V ≤ Vin ≤ 18V 0°C to +85°C Feedback Voltage Vcomp = 1.4V, Min (Note 3) Typ Max (Note Units (Note 3) 4) 1.2622 1.275 1.28775 5 V 1.2495 1.275 V 1.3005 5V ≤ Vin ≤ 18V -40°C to +125°C ΔVLINE Feedback Voltage Line Regulation 5V ≤ Vin ≤ 18V TBD %/V ΔVLOAD Output Voltage Load Regulation Vin = 12V TBD %/A Input Under Voltage Lock-Out reference Voltage Ramping up VUVLO Input Under Voltage Lock-Out reference Voltage Hysteresis Fnom RDS(ON) VDR (max) Dmax Tmin(on) Nominal Switching Frequency (Note 5) TBD 4.5 TBD V TBD 300 TBD mV 360 400 440 kHz Low side NMOS driver resistance; top switch Vin = 5V, IDR = 0.2A 4 Ω Low side NMOS driver resistance; bottom switch Vin = 5V, IDR = 0.2A 2 Ω Maximum Driver Voltage Supply Vin < 6V Vin V Vin ≥ 6V 6 Maximum Duty Cycle 85 Minimum On Time 250 Irun Supply Current in Boost Mode - No-load EN/MODE pin = 1.6V FEEDBACK pin = 1.4V IQ Supply Current in Shutdown Mode EN/MODE pin = 0.3V Istby Supply Current in Stand-by mode EN/MODE pin = 2.6V Stand-by Mode Threshold EN/MODE pin thresholds TBD Shut-down Mode Threshold EN/MODE pin thresholds Run Mode Window EN/MODE pin thresholds EN/MODE pin bias current Cycle-by-Cycle Current Limit Threshold during boost mode Ven-stby Ven-shutdown Ven-run Ien VSENSE VSL % 4 ns TBD mA 1 µA 1.2 TBD mA 2.6 TBD V TBD 0.4 TBD V 1.6 1.9 2.2 V EN/MODE = 1.6V TBD ±1.0 TBD µA EN/MODE = 1.6V FB = 0.5V 153 170 187 mV Internal Ramp Compensation Voltage 90 mV VLIM1 Input Current Limit Threshold Voltage in Stand-by mode EN/MODE = 2.6V (Note 7) 82 85 88 mV VLIM2 Input Current Limit Threshold Voltage in Stand-by Mode (during Start-up) EN/MODE = 2.6V(Note 7) TBD 102 TBD mV 3 www.ti.com LM3017 ISEN, DR, VG to PGND, AGND Peak low side driver output current Absolute Maximum Ratings (Note 1) LM3017 Symbol Min (Note 3) Typ Max (Note Units (Note 3) 4) Parameter Conditions VOVP Output-Over Voltage Protection Threshold Measured with respect to FB pin. VCOMP = 1.4V TBD 85 TBD mV VOVP(HYS) Output-Over Voltage Protection Threshold Hysteresis Measured with respect to FB pin. VCOMP = 1.4V TBD 70 TBD mV VSC Short Circuit Current Limit Threshold during boost mode 200 Gm Error Amplifier Transconductance VCOMP = 1.4V VG-max Maximum Drive voltage at VG pin Vin = 5V, Isense = 5V IG = 0A 10 V VG-min Minimum Drive voltage at VG pin Vin = 5V, Isense = Vin - 200mV IG = 0A 100 mV IG Maximum Drive current at VG pin Vin = 5V, Isense = 5V VG = Vin 500 µA AVOL Error Amplifier Open Loop Voltage Gain IEAO Error Amplifier Output Current Limits VEAO Tss Error Amplifier Output Voltage Limits 216 450 mV 690 µA/V 35 60 66 V/V SOURCING: VCOMP = 1.4V VFB = 1.1V 475 640 837 µA SINKING: VCOMP = 1.4V VFB = 1.4V 31 65 100 µA UPPER LIMIT: VFB = 0V 2.45 2.7 2.93 V LOWER LIMIT: VFB = 1.4V 0.32 0.6 0.9 V Internal Soft-Start Delay VFB = 1.2V 10 ms TLIM1 Current Limit time at VLIM1 (Note 7) TBD ms TLIM2 Current Limit time at VLIM2 (Note 7) TBD Tsc Short-Circuit Time in Boost (Note 7) TBD TDELAY Time delay to transition between stand-by and boost (Note 7) TBD TBLANK TBD ms Current Limit Latch-off Blank Time (Note 7) Tr Drive Pin Rise Time Cload = 3nF VDR = 0V to 3V 25 ns Tf Drive Pin Fall Time Cload = 3nF VDR = 3V to 0V 25 ns Thermal Shutdown Threshold 165 °C Thermal Shutdown Threshold Hysteresis 10 °C TSD TSD-hyst Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method is per JESD-22-114. Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National's Average Quality Level (AOQL). Note 4: Typical numbers are at 25°C and represent the most likely parametric norm. Note 5: Typical values are programmed by metal mask options. The following options are available: 100 kHz, 200 kHz, 340 kHz, 400 kHz, 500 kHz, 750 kHz, 1 MHz. Consult the factory for details. Note 6: The bias current flowing through this pin is compensated and can flow either in-to or out-of this pin. Note 7: See text for details of current limit operation. www.ti.com 4 LM3017 Functional Block Diagram 30180906 Under extremely light load or no-load conditions, the energy delivered to the output capacitor when the external MOSFET is on during the blank-out time is more than what is delivered to the load. An over-voltage comparator inside the LM3017 prevents the output voltage from rising under these conditions by sensing the feedback (FB pin) voltage and resetting the RS latch. The latch remains in a reset state until the output decays to the nominal value. Thus the operating frequency decreases at light loads, resulting in excellent efficiency. Functional Description The LM3017 uses a fixed frequency, Pulse Width Modulated (PWM), current mode control architecture. In a typical application circuit, the peak current through the external high side MOSFET is sensed through an external sense resistor. The voltage across this resistor is fed into the ISEN pin. This voltage is then level shifted and fed into the positive input of the PWM comparator. The output voltage is also sensed through an external feedback resistor divider network and fed into the error amplifier (EA) negative input (feedback pin, FB). The output of the error amplifier (COMP pin) is added to the slope compensation ramp and fed into the negative input of the PWM comparator. At the start of any switching cycle, the oscillator sets a high signal on the DR pin (gate of the external MOSFET) and the external MOSFET turns on. When the voltage on the positive input of the PWM comparator exceeds the negative input, the Drive Logic is reset and the external MOSFET turns off. The voltage sensed across the sense resistor generally contains spurious noise spikes, as shown in Figure 1. These spikes can force the PWM comparator to reset the RS latch prematurely. To prevent these spikes from resetting the latch, a blank-out circuit inside the IC prevents the PWM comparator from resetting the latch for a short duration after the latch is set. This duration, called the blank-out time, is typically 250 ns and is specified as Tmin (on) in the electrical characteristics section. 30180907 FIGURE 1. Basic Operation of the PWM comparator 5 www.ti.com LM3017 OPERATION OF THE EN/MODE PIN The EN/MODE pin drives the high side gate (VG pin) to enable or disable the output through the high side MOSFET (pass MOSFET), furthermore it defines the current limit for each operation mode (see next section). BOOST MODE The boost regulator can be turned on by bringing the EN/ MODE pin to greater than 1.6V, but less than 2.2V. This is the run mode for the boost regulator. Note that the LM3017 will always start in stand-by and transition to boost mode, after a delay of TDELAY=XXms (typ); see typical waveforms. If the EN/MODE pin is taken to a value >2.6V, the part will enter stand-by mode. 1) VEN/MODE < 0.4V Shutdown mode 2) 0.4V < VEN/MODE < 2.6V Boost mode 3) VEN/MODE > 2.6V Standby mode STANDBY MODE Pulling the EN/MODE pin to greater than 2.6V, for more than 50µS, during any mode of operation, will place the part in stand-by mode. The boost regulator will be off and the highside NMOS FET will be on. During this mode, the load is connected to the input supply through the inductor. SHUTDOWN MODE Pulling the EN/MODE pin to less than 0.4V, for more than 50µS, during any mode of operation, will place the part in full shutdown mode. The boost regulator and high-side NMOS FET will be off and the load will be disconnected from the input supply. In this mode, the regulator will draw a maximum of 1µA from the input supply. 30180951 30180917 30180996 30180993 www.ti.com 6 LM3017 CURRENT LIMIT AND SHORT CIRCUIT PROTECTION Boost Mode In boost mode the LM3017 features both cycle-by-cycle current limit and short circuit protection. Unlike most boost regulators, the LM3017 can protect itself from short circuits on the output by shutting off the pass FET. The boost current limit, defined by VCL=170mV in the electrical characteristics table, turns off the boost FET for normal overloads on a cycleby-cycle basis. The current is limited to VCL/RSEN until the overload is removed. Should the output be shorted, or otherwise pulled below VIN, the inductor current will have a tendency to "run-away". This is prevented by the short circuit protection feature, defined as VSC = 200mV in the electrical characteristics table. When this current limit is tripped, the current is limited to VSC/RSEN by controlling the pass FET. If the short persists for TSC > 450µs the pass FET will be latched off. In this way, the current is limited to VSC/Rsen until the short is removed or the time of TSC = 450µs is completed. Pulling the EN/MODE pin low (<0.4V, typ) is required to reset this short circuit latch-off mode. The delay of TSC = 450µs helps to prevent nuisance latch-off during a momentary short on the output. Standby Mode In stand-by mode the power path is protected from shorts and overloads by the current limit defined as VLIM1 = 85mV in the electrical characteristics table. When this current limit is tripped, the current is limited to VLIM1/RSEN by controlling the pass FET. If the short persists for TLIM1 > 900µs the pass FET will be latched off. In this way, the current is limited to VLIM1/ RSEN until the short is removed or the time of TLIM1 = 900µs is completed. Pulling the EN/MODE pin low (<0.4V, typ) is required to reset this latch-off mode. Start-up Stand-bye Mode During start-up in stand-by mode, the current limit is defined by VLIM2 = 100mV in the electrical characteristics table, for the first TLIM2 = 3.6ms. The current is limited to VLIM2/RSEN, for this period . Once the TLIM2 = 3.6ms timer has finished, the current limit is reduced to VLIM1 = 85mV . For the first TLIM2 = 3.6ms of the start-up, the latch-off feature is not enabled, however the current will always be limited to VLIM2/RSEN. This allows the part to start-up normally. If the current limit is still tripped at the end of TLIM2 = 3.6ms, the TLIM1 = 900µs timer is started. Once the TLIM1= 900µs time has expired, the pass FET is latched off. This gives a total current-limited time of TLIM1+ TLIM2 = 4.5ms, in cases where the LM3017 is started into a short circuit at the output. 30180944 FIGURE 2. Current Limit / Short Circuit protection OVER VOLTAGE PROTECTION The LM3017 has over voltage protection (OVP) for the output voltage. OVP is sensed at the feedback pin (FB). If at anytime the voltage at the feedback pin rises to VFB + VOVP, OVP is triggered. See the electrical characteristics section for limits on VFB and VOVP. OVP will cause the drive pin (DR) to go low, forcing the power MOSFET off. With the MOSFET off, the output voltage will drop. The LM3017 will begin switching again when the feedback voltage reaches VFB + (VOVP - VOVP(HYS)). See the electrical characteristics section for limits on VOVP(HYS). Start-up Boost Mode During start-up in boost mode, the current limit is defined by VLIM2 = 100mV (typ) in the electrical characteristics table, for the first TLIM2 = 3.6ms. The current is limited to VLIM2/RSEN, for this period . Once the TLIM2 = 3.6ms timer has finished, the current limit is increased to VSC = 200mV. For the first TLIM2 = 3.6ms of the start-up, the latch-off feature is not enabled, however the current will always be limited to VLIM2/RSEN. This allows the part to start-up normally. If the current limit is still tripped at the end of TLIM2 = 3.6ms, the TSC = 450µs timer is started. Once the TSC = 450µs time has expired, the pass FET is latched off. This gives a total current-limited time of TSC + TLIM2 = 4.05ms, in cases where the LM3017 is started into a short circuit at the output. SLOPE COMPENSATION RAMP The LM3017 uses a current mode control scheme. The main advantages of current mode control are inherent cycle-by-cycle current limit for the switch, simpler control loop characteristics and excellent line and load transient response. However there is a natural instability that will occur for duty cycles, D, 7 www.ti.com LM3017 greater than 50% if additional slope compensation is not addressed as described below. slope of the compensation ramp externally, if the need arises. Adding a single external resistor, RS (as shown in Figure 4) increases the amplitude of the compensation ramp as shown in Figure 3. MC > M2 / 2 For the boost topology: M1 = [VIN / L] x RSEN x A M2 = [(VOUT − VIN) / L] x RSEN x A Where: • MC is the slope of the compensation ramp. • M1 is the slope of the inductor current during the ON time. • M2 is the slope of the inductor current during the OFF time. • RSEN is the sensing resistor value. • VOUT represents the output voltage. • VIN represents the input voltage. • A is equal to 0.86 and it is the internal sensing amplification of the LM3017. The compensation ramp has been added internally in the LM3017. The slope of this compensation ramp has been selected to satisfy most applications, and its value depends on the switching frequency. This slope can be calculated using the formula: 301809a1 FIGURE 3. Additional Slope Compensation Added Using External Resistor RS Where, ΔVSL = K x RS K = 40 µA typically and changes slightly as the switching frequency changes. A more general equation for the slope compensation ramp, MC, is shown below to incluse ΔVSL cause by the resistor RS. MC = VSL x fS In the above equation, VSL is the amplitude of the internal compensation ramp and fS is the controller's switching frequency. Limits for VSL have been specified in the electrical characteristics section. In order to provide the user additional flexibility, a patented scheme has been implemented inside the IC to increase the MC = (VSL + ΔVSL) x fS 30180913 FIGURE 4. Increasing the Slope of the Compensation Ramp www.ti.com 8 LM3017 Application Circuits 30180943 FIGURE 5. Typical High Efficiency Step-Up (Boost) Converter Bill of Materials (BOM) Designation Description Size Manufacturer Part # Vendor CIN1 Cap 22µF 25V X5R 1206 GRM31CR61E226KE15L Murata CO1,CO2, CO3 Cap 22µF 25V X5R 1206 GRM31CR61E226KE15L Murata CCOMP Cap 0.022µF 0603 CCOMP2 Cap 1000pF 0603 CBYP Cap 0.1µF 25V X7R 0603 06033C104KAT2A AVX CVCC Cap 0.47µF 16V X7R 0805 C2012X7R1C474K TDK RCOMP RES, 10k ohm, 1%, 0.1W 0603 CRCW060310K0FKEA Vishay RFBT RES, 21.5k ohm, 1%, 0.1W 0603 CRCW060321K5FKEA Vishay RFBB RES, 2k ohm, 1%, 0.1W 0603 CRCW06032K00FKEA Vishay RS RES, 100 ohm, 1%, 0.1W 0603 CRCW0603100RFKEA Vishay RSEN RES, 0.03 ohm, 1%, 1W 1206 WSLP1206R0300FEA Vishay Q1 NexFET™ N-CH, 25V, 60A, RDS(on)= 4.4mohm 8-SON CSD16323Q3 TI Q2 NexFET™ N-CH, 25V, 60A, RDS(on)= 4.3mohm 8-SON CSD16340Q3 TI D1 Diode Schottky, 30V, 2A SMB 20BQ030TRPBF Vishay L1 Shielded Inductor, 2.2µH, 3.4A 4.45mm L x 4.06mm W x 1.85mm H MPI4040R3 Cooper U1 LM3017 TI 9 www.ti.com LM3017 Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead QFN Package NS Package Number LEK10A www.ti.com 10 LM3017 Notes 11 www.ti.com LM3017 High Efficiency Low-Side Controller with True Shutdown Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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