LM3481
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SNVS346E – NOVEMBER 2007 – REVISED APRIL 2012
LM3481/LM3481Q High Efficiency Low-Side N-Channel Controller for Switching
Regulators
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FEATURES
KEY SPECIFICATIONS
•
•
•
1
2
•
•
•
•
•
•
•
•
LM3481QMM in the VSSOP-10 Package are
Automotive Grade Products that are AEC-Q100
Grade 1 Qualified (-40°C to +125°C Operating
Junction Temperature)
10-Lead VSSOP Package
Internal Push-Pull Driver with 1A Peak Current
Capability
Current Limit and Thermal Shutdown
Frequency Compensation Optimized with a
Capacitor and a Resistor
Internal Softstart
Current Mode Operation
Adjustable Undervoltage Lockout with
Hysteresis
Pulse Skipping at Light Loads
•
•
DESCRIPTION
The LM3481 is a versatile Low-Side N-FET high
performance controller for switching regulators. It is
suitable for use in topologies requiring a low-side
FET, such as boost, flyback, SEPIC, etc. The
LM3481 can be operated at extremely high switching
frequencies in order to reduce the overall solution
size. The switching frequency of the LM3481 can be
adjusted to any value between 100 kHz and 1 MHz
by using a single external resistor or by synchronizing
it to an external clock. Current mode control provides
superior bandwidth and transient response in addition
to cycle-by-cycle current limiting. Current limit can be
programmed with a single external resistor.
APPLICATIONS
•
•
•
•
Wide Supply Voltage Range of 2.97V to 48V
100 kHz to 1 MHz Adjustable and
Synchronizable Clock Frequency
±1.5% (Over Temperature) Internal Reference
10 µA Shutdown Current (Over Temperature)
Distributed Power Systems
Notebook, PDA, Digital Camera, and other
Portable Applications
Offline Power Supplies
Set-Top Boxes
The LM3481 has built in protection features such as
thermal shutdown, short-circuit protection and over
voltage protection. Power saving shutdown mode
reduces the total supply current to 5µA and allows
power supply sequencing. Internal soft-start limits the
inrush current at start-up.
TYPICAL APPLICATION CIRCUIT
R7
VIN = 3.0V to 48V
+
CIN
R8
VIN
ISEN
UVLO
RC
FB
VOUT = 5V, 1A
VCC
CC
COMP
L1
LM3481
CBYP
DR
Q1
CS
D1
L2
+
COUT
PGND
RF2
AGND
FA/SYNC/SD
RFA
CSEN
RSEN
RF1
Figure 1. Typical SEPIC Converter
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2012, Texas Instruments Incorporated
LM3481
SNVS346E – NOVEMBER 2007 – REVISED APRIL 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
ISEN
UVLO
COMP
FB
AGND
1
10
2
9
3
8
LM3481
4
7
5
6
VIN
VCC
DR
PGND
FA/SYNC/SD
Figure 2. 10-Lead VSSOP Package
(DGS-10 Package)
PIN DESCRIPTIONS
2
Pin Name
Pin Number
ISEN
1
Current sense input pin. Voltage generated across an external sense resistor is fed into this pin.
Description
UVLO
2
Under voltage lockout pin. A resistor divider from VIN to ground is connected to the UVLO pin. The ratio of
these resistances determine the input voltage which allows switching and the hysteresis to disable
switching.
COMP
3
Compensation pin. A resistor and capacitor combination connected to this pin provides compensation for
the control loop.
FB
4
Feedback pin. Inverting input of the error amplifier.
AGND
5
Analog ground pin. Internal bias circuitry reference. Should be connected to PGND at a single point.
FA/SYNC/SD
6
Frequency adjust, synchronization, and shutdown pin. A resistor connected from this pin to ground sets the
oscillator frequency. An external clock signal at this pin will synchronize the controller to the frequency of
the clock. A high level on this pin for ≥ 30 µs will turn the device off and the device will then draw 5 µA
from the supply typically.
PGND
7
Power ground pin. External power circuitry reference. Should be connected to AGND at a single point.
DR
8
Drive pin of the IC. The gate of the external MOSFET should be connected to this pin.
VCC
9
Driver supply voltage pin. A bypass capacitor must be connected from this pin to PGND. See DRIVER
SUPPLY CAPACITOR SELECTION section.
VIN
10
Power supply input pin.
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ABSOLUTE MAXIMUM RATINGS
(1)
VIN pin Voltage
-0.4V to 50V
FB Pin Voltage
-0.4V to 6V
FA/SYNC/SD Pin Voltage
-0.4V to 6V
COMP Pin Voltage
-0.4V to 6V
UVLO Pin Voltage
-0.4V to 6V
VCC Pin Voltage
-0.4V to 6V
DR Pin Voltage
-0.4V to 6V
ISEN Pin Voltage
–0.4V to 600 mV
Peak Driver Output Current
1.0A
Power Dissipation
Internally Limited
Storage Temperature Range
−65°C to +150°C
Junction Temperature
ESD Susceptibility
+150°C
Human Body Model
(2)
2 kV
Lead Temperature
DGS Package
Vapor Phase (60 sec.)
Infared (15 sec.)
(1)
(2)
215°C
220°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings indicates conditions for which
the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
RECOMMENDED OPERATING CONDITIONS
(1)
Supply Voltage
2.97V to 48V
Junction Temperature Range
−40°C to +125°C
Switching Frequency Range
100 kHz to 1 MHz
(1)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings indicates conditions for which
the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions.
ELECTRICAL CHARACTERISTICS
VIN=12V, RFA=40 kΩ unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type
apply for TJ = 25°C. Limits appearing in boldfacetype apply over the full Operating Temperature Range (-40°C to 125°C).
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. (1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
1.256
1.275
1.294
Units
VFB
Feedback Voltage
VCOMP = 1.4V, 2.97 ≤ VIN ≤ 48V
ΔVLINE
Feedback Voltage Line Regulation
2.97 ≤ VIN ≤ 48V
0.003
%/V
ΔVLOAD
Output Voltage Load Regulation
IEAO Source/Sink
±0.5
%/A
VUVLOSEN
Undervoltage Lockout Reference
Voltage
VUVLO Ramping Down
IUVLO
UVLO Source Current
Enabled
VUVLOSD
UVLO Shutdown Voltage
ICOMP
COMP pin Current Sink
VCOMP
V
1.345
1.430
1.517
V
3
5
6
µA
VFB = 0V
VFB = 1.275V
0.7
V
640
µA
1
Nominal Switching Frequency
RFA = 40 kΩ
Vsync-HI
Threshold for Synchronization on
FA/SYNC/SD pin
Synchronization Voltage Rising
1.4
V
Vsync-LOW
Threshold for Synchronization on
FA/SYNC/SD pin
Synchronization Voltage Falling
0.7
V
(1)
(2)
406
475
V
fnom
550
kHz
All limits are guaranteed at room temperature (standard type face) and at temperature extremes (bold type face). All room
temperature limits are 100% tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality
Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely norm.
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ELECTRICAL CHARACTERISTICS (continued)
VIN=12V, RFA=40 kΩ unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type
apply for TJ = 25°C. Limits appearing in boldfacetype apply over the full Operating Temperature Range (-40°C to 125°C).
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. (1) (2)
Symbol
RDS1
RDS2
Parameter
Conditions
Min
Typ
Max
Units
(ON)
Driver Switch On Resistance (top)
IDR = 0.2A, VIN= 5V
4
Ω
(ON)
Driver Switch On Resistance (bottom)
IDR = 0.2A
2
Ω
VIN < 6V
VIN
VIN ≥ 6V
6
VDR (max)
Maximum Drive Voltage Swing (3)
Dmax
Maximum Duty Cycle
tmin (on)
Minimum On Time
ISUPPLY
Supply Current (switching)
IQ
Quiescent Current in Shutdown Mode
VSENSE
Current Sense Threshold Voltage
VSC
Over Load Current Limit Sense Voltage
VSL
Internal Compensation Ramp Voltage
VOVP
Output Over-voltage Protection (with
respect to feedback voltage) (6)
VCOMP = 1.4V
26
85
135
mV
VOVP(HYS)
Output Over-Voltage Protection
Hysteresis
VCOMP = 1.4V
28
70
106
mV
Gm
Error Amplifier Transconductance
VCOMP = 1.4V
216
450
690
µmho
AVOL
Error Amplifier Voltage Gain
VCOMP = 1.4V
IEAO = 100 µA (Source/Sink)
35
60
66
V/V
IEAO
Error Amplifier Output Current (Source/
Sink)
Source, VCOMP = 1.4V, VFB = 1.1V
475
640
837
µA
Sink, VCOMP = 1.4V, VFB = 1.4V
31
65
100
µA
Upper Limit, VFB = 0V, COMP Pin
Floating
2.45
2.70
2.93
V
Lower Limit, VFB = 1.4V
0.32
0.60
0.90
V
85
%
250
See
(4)
ns
3.7
5.0
VFA/SYNC/SD = 3V (5), VIN = 12V
9
15
VFA/SYNC/SD = 3V (5), VIN = 5V
5
10
100
160
190
mV
157
220
275
mV
90
mA
µA
mV
VEAO
Error Amplifier Output Voltage Swing
tSS
Internal Soft-Start Delay
VFB = 1.2V, COMP Pin Floating
15
ms
tr
Drive Pin Rise Time
Cgs = 3000 pf, VDR = 0V to 3V
25
ns
tf
Drive Pin Fall Time
VSD
Shutdown signal threshold
FA/SYNC/SD pin
ISD
Shutdown Pin Current FA/SYNC/SD pin
TSD
Thermal Shutdown
165
°C
Tsh
Thermal Shutdown Hysteresis
10
°C
θJA
Thermal Resistance
200
°C/W
(3)
(4)
(5)
(6)
(7)
4
Cgs = 3000 pf, VDR = 3V to 0V
(7)
25
Output = High (Shutdown)
Output = Low (Enable)
1.31
0.40
0.68
VSD = 5V
−1
VSD = 0V
20
DGS Package
V
ns
1.40
V
V
µA
The drive pin voltage, VDR, is equal to the input voltage when input voltage is less than 6V. VDR is equal to 6V when the input voltage is
greater than or equal to 6V.
For this test, the FA/SYNC/SD Pin is pulled to ground using a 40 kΩ resistor .
For this test, the FA/SYNC/SD Pin is pulled to 3V using a 40 kΩ resistor.
The over-voltage protection is specified with respect to the feedback voltage. This is because the over-voltage protection tracks the
feedback voltage. The over-voltage threshold can be calculated by adding the feedback voltage (VFB) to the over-voltage protection
specification.
The FA/SYNC/SD pin should be pulled to VIN through a resistor to turn the regulator off. The voltage on the FA/SYNC/SD pin must be
above the max limit for the Output = High longer than 30 µs to keep the regulator off and must be below the minimum limit for Output =
Low to keep the regulator on.
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, VIN = 12V, TJ = 25°C.
Comp Pin Voltage vs. Load Current
Switching Frequency vs. RFA
Figure 3.
Figure 4.
Efficiency vs. Load Current (3.3VIN and 12VOUT)
Efficiency vs. Load Current (5VIN and 12VOUT)
Figure 5.
Figure 6.
Efficiency vs. Load Current (9VIN and 12VOUT)
Frequency vs. Temperature
Figure 7.
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VIN = 12V, TJ = 25°C.
6
COMP Pin Source Current vs. Temperature
ISupply vs. Input Voltage (Non-Switching)
Figure 9.
Figure 10.
ISupply vs. Input Voltage (Switching)
Shutdown Threshold Hysteresis vs. Temperature
Figure 11.
Figure 12.
Drive Voltage vs. Input Voltage
Short Circuit Protection vs. VIN
Figure 13.
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VIN = 12V, TJ = 25°C.
Current Sense Threshold vs. Input Voltage
Compensation Ramp Amplitude vs. Input Voltage
Figure 15.
Figure 16.
Minimum On-Time vs. Temperature
Figure 17.
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FUNCTIONAL BLOCK DIAGRAM
Shutdown Detect
VIN
SYNC/Fixed
Frequency detect
FA/SYNC/SD
Oscillator
Set/Blankout
Slope
Compensation
6V
Soft-start
UVLO
Bias
Voltages
UVLO
Thermal
Shutdown
40 éA
1.275V
Reference
Ramp
Adjust
-
COMP
+
6
V-I
Converter
EA
Vfb + Vovp
Overvoltage
Comparator
Switch
Logic
+
+
FB
I-V
Converter
PWM
Comparator
R
-
S
Q
+
VCC
220 mV
ISEN
Short-circuit
Comparator
One Shot
+
Switch
Driver
DR
Level Shifter
AGND
PGND
FUNCTIONAL DESCRIPTION
The LM3481 uses a fixed frequency, Pulse Width Modulated (PWM), current mode control architecture. In a
typical application circuit, the peak current through the external MOSFET is sensed through an external sense
resistor. The voltage across this resistor is fed into the ISEN pin. This voltage is then level shifted and fed into the
positive input of the PWM comparator. The output voltage is also sensed through an external feedback resistor
divider network and fed into the error amplifier (EA) negative input (feedback pin, FB). The output of the error
amplifier (COMP pin) is added to the slope compensation ramp and fed into the negative input of the PWM
comparator.
At the start of any switching cycle, the oscillator sets the RS latch using the SET/Blank-out and switch logic
blocks. This forces a high signal on the DR pin (gate of the external MOSFET) and the external MOSFET turns
on. When the voltage on the positive input of the PWM comparator exceeds the negative input, the RS latch is
reset and the external MOSFET turns off.
The voltage sensed across the sense resistor generally contains spurious noise spikes, as shown in Figure 18.
These spikes can force the PWM comparator to reset the RS latch prematurely. To prevent these spikes from
resetting the latch, a blank-out circuit inside the IC prevents the PWM comparator from resetting the latch for a
short duration after the latch is set. This duration, called the blank-out time, is typically 250 ns and is specified as
tmin (on) in the electrical characteristics section.
Under extremely light load or no-load conditions, the energy delivered to the output capacitor when the external
MOSFET is on during the blank-out time is more than what is delivered to the load. An over-voltage comparator
inside the LM3481 prevents the output voltage from rising under these conditions by sensing the feedback (FB
pin) voltage and resetting the RS latch. The latch remains in a reset state until the output decays to the nominal
value. Thus the operating frequency decreases at light loads, resulting in excellent efficiency.
8
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Blank-Out prevents false
reset
PWM Comparator resets
the RS latch
VSL
_
+
PWM
Comparator
Oscillator Sets
the RS Latch
Tmin (on) Blank-Out time
Figure 18. Basic Operation of the PWM Comparator
OVER VOLTAGE PROTECTION
The LM3481 has over voltage protection (OVP) for the output voltage. OVP is sensed at the feedback pin (FB). If
at anytime the voltage at the feedback pin rises to VFB + VOVP, OVP is triggered. See the electrical characteristics
section for limits on VFB and VOVP.
OVP will cause the drive pin (DR) to go low, forcing the power MOSFET off. With the MOSFET off, the output
voltage will drop. The LM3481 will begin switching again when the feedback voltage reaches VFB + (VOVP VOVP(HYS)). See the electrical characteristics section for limits on VOVP(HYS).
The internal bias of the LM3481 comes from either the internal bias voltage generator as shown in the block
diagram or directly from the voltage at the VIN pin. At input voltages lower than 6V the internal IC bias is the
input voltage and at voltages above 6V the internal bias voltage generator of the LM3481 provides the bias.
SLOPE COMPENSATION RAMP
The LM3481 uses a current mode control scheme. The main advantages of current mode control are inherent
cycle-by-cycle current limit for the switch and simpler control loop characteristics. It is easy to parallel power
stages using current mode control since current sharing is automatic. However there is a natural instability that
will occur for duty cycles, D, greater than 50% if additional slope compensation is not addressed as described
below.
The current mode control scheme samples the inductor current, IL, and compares the sampled signal, Vsamp, to a
internally generated control signal, Vc. The current sense resistor, RSEN, as shown in Figure 22, converts the
sampled inductor current, IL, to the voltage signal, Vsamp, that is proportional to IL such that:
Vsamp = IL x RSEN
The rising and falling slopes, M1 and −M2 respectively, of Vsamp are also proportional to the inductor current rising
and falling slopes, Mon and −Moff respectively. Where Mon is the inductor slope during the switch on-time and
−Moff is the inductor slope during the switch off-time and are related to M1 and −M2 by:
M1 = Mon x RSEN
−M2 = −Moff x RSEN
For the boost topology:
Mon = VIN / L
−Moff = (VIN − VOUT) / L
M1 = [VIN / L] x RSEN
−M2 = [(VIN − VOUT) / L] x RSEN
M2 = [(VOUT − VIN) / L] x RSEN
Current mode control has an inherent instability for duty cycles greater than 50%, as shown in Figure 19, where
the control signal slope, MC, equals zero. In Figure 19, a small increase in the load current causes the sampled
signal to increase by ΔVsamp0. The effect of this load change, ΔVsamp1, at the end of the first switching cycle is :
M
D
'Vsamp1 = - 2 'Vsamp0 = 'Vsamp0
M1
1-D
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From the above equation, when D > 0.5, ΔVsamp1 will be greater than ΔVsamp0. In other words, the disturbance is
divergent. So a very small perturbation in the load will cause the disturbance to increase. To ensure that the
perturbed signal converges we must maintain:
-
M2 <
M1 1
Control Signal MC = 0
Perturbed Signal
-M2
_
M1
'Vsamp0
'Vsamp1
Steady State
Signal Vsamp
+
PWM
Comparator
(1-D)TS
DTS
Figure 19. Sub-Harmonic Oscillation for D>0.5
-MC
Control Signal
Compensation Ramp
VSL
Perturbed Signal
-M2
M1
'Vsamp0
_
Vsamp
+
'Vsamp1
Steady State
Signal Vsamp
DTS
Control
Signal
PWM
Comparator
(1-D)TS
Figure 20. Compensation Ramp Avoids Sub-Harmonic Oscillation
To prevent the sub-harmonic oscillations, a compensation ramp is added to the control signal, as shown in
Figure 20.
With the compensation ramp, ΔVsamp1 and the convergence criteria are expressed by,
M - MC
'Vsamp1 = - 2
'Vsamp0
M 1 + MC
-
M 2 - MC
<1
M1 + MC
The compensation ramp has been added internally in the LM3481. The slope of this compensation ramp has
been selected to satisfy most applications, and it's value depends on the switching frequency. This slope can be
calculated using the formula:
MC = VSL x fS
In the above equation, VSL is the amplitude of the internal compensation ramp and fS is the controller's switching
frequency. Limits for VSL have been specified in the electrical characteristics section.
In order to provide the user additional flexibility, a patented scheme has been implemented inside the IC to
increase the slope of the compensation ramp externally, if the need arises. Adding a single external resistor,
RSL(as shown in Figure 22) increases the amplitude of the compensation ramp as shown in Figure 21.
10
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Control Signal
Compensation Ramp
with RSL
Control Signal
Compensation Ramp
without RSL
'VSL
-MC
VSL
Figure 21. Additional Slope Compensation Added Using External Resistor RSL
Where,
ΔVSL = K x RSL
K = 40 µA typically and changes slightly as the switching frequency changes. Figure 23 shows the effect the
current K has on ΔVSLand different values of RSL as the switching frequency changes.
A more general equation for the slope compensation ramp, MC, is shown below to include ΔVSL caused by the
resistor RSL.
MC = (VSL + ΔVSL) x fS
It is good design practice to only add as much slope compensation as needed to avoid subharmonic oscillation.
Additional slope compensation minimizes the influence of the sensed current in the control loop. With very large
slope compensation the control loop characteristics are similar to a voltage mode regulator which compares the
error voltage to a saw tooth waveform rather than the inductor current.
VIN
L1
D1
VOUT
+
DR
COUT
Q1
LM3481
ISEN
RSL
RSEN
CSEN
Figure 22. Increasing the Slope of the Compensation Ramp
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Figure 23. ΔVSL vs RSL
FREQUENCY ADJUST/SYNCHRONIZATION/SHUTDOWN
The switching frequency of the LM3481 can be adjusted between 100 kHz and 1 MHz using a single external
resistor. This resistor must be connected between the FA/SYNC/SD pin and ground, as shown in Figure 24.
Please refer to the typical performance characteristics to determine the value of the resistor required for a
desired switching frequency.
The following equation can also be used to estimate the frequency adjust resistor.
Where fS is in kHz and RFA in kΩ.
RFA =
22 x 103
- 5.74
fS
The LM3481 can be synchronized to an external clock. The external clock must be connected between the
FA/SYNC/SD pin and ground, as shown in Figure 25. The frequency adjust resistor may remain connected while
synchronizing a signal, therefore if there is a loss of signal, the switching frequency will be set by the frequency
adjust resistor.
It is also necessary to have the width of the synchronization pulse narrower than the duty cycle of the converter
and to have the synchronization pulse width ≥ 300 ns.
The FA/SYNC/SD pin also functions as a shutdown pin. If a high signal (refer to the electrical characteristics
section for definition of high signal) appears on the FA/SYNC/SD pin, the LM3481 stops switching and goes into
a low current mode. The total supply current of the IC reduces to 5 µA, typically, under these conditions.
Figure 26 and Figure 27 shows an implementation of a shutdown function when operating in frequency adjust
mode and synchronization mode respectively. In frequency adjust mode, connecting the FA/SYNC/SD pin to
ground forces the clock to run at a certain frequency. Pulling this pin high shuts down the IC. In frequency adjust
or synchronization mode, a high signal for more than 30 µs shuts down the IC.
RFA
FA/SYNC/SD
LM3481
Figure 24. Frequency Adjust
12
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RFA
FA/SYNC/SD
LM3481
Freq. clock
100 kHz to 1 MHz
Figure 25. Frequency Synchronization
RFA
10 k:
>1.3V
FA/SYNC/SD
LM3481
MOSFET State
On-Normal Operation
OFF- Shutdown
Figure 26. Shutdown Operation in Frequency Adjust Mode
30 Ps
40 k:
FA/SYNC/SD
LM3481
DR
Figure 27. Shutdown Operation in Synchronization Mode
UNDER VOLTAGE LOCKOUT (UVLO) Pin
The UVLO pin provides user programmable enable and shutdown thresholds. The UVLO pin is compared to an
internal reference of 1.43V (typical), and a resistor divider programs the enable threshold, VEN. When the IC is
enabled, a 5 μA current is sourced out of the UVLO pin, which effectively causes a hysteresis, and the UVLO
shutdown threshold, VSH, is now lower than the enable threshold. Setting these thresholds requires two resistors
connected from the VIN pin to the UVLO pin and from the UVLO pin to GND (see Figure 28). Select the desired
enable, VEN, and UVLO shutdown, VSH, threshold voltages and use the following equations to determine the
resistance values:
1.43V ± VSH
1.43V §
x ¨1 +
R8 =
IUVLO ©
VEN ± 1.43V
§
¨
©
§ VEN
-1
R7 = R8 x ¨
© 1.43V
§
¨
©
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VIN
IUVLO
R7
2
+
UVLO
R8
VUVLOSEN
+
-
Figure 28. UVLO Pin Resistor Divider
If the UVLO pin function is not desired, select R8 and R7 of equal magnitude greater than 100 kΩ. This will allow
VIN to be in control of the UVLO thresholds. The UVLO pin may also be used to implement the enable/disable
function. If a signal pulls the UVLO pin below the 1.43V (typical) threshold, the converter will be disabled.
SHORT CIRCUIT PROTECTION
When the voltage across the sense resistor (measured on the ISEN Pin) exceeds 220 mV, short-circuit current
limit gets activated. A comparator inside the LM3481 reduces the switching frequency by a factor of 8 and
maintains this condition until the short is removed.
TYPICAL APPLICATIONS
The LM3481 may be operated in either continuous or discontinuous conduction mode. The following applications
are designed for continuous conduction operation. This mode of operation has higher efficiency and lower EMI
characteristics than the discontinuous mode.
Boost Converter
The most common topology for the LM3481 is the boost or step-up topology. The boost converter converts a low
input voltage into a higher output voltage. The basic configuration for a boost regulator is shown in Figure 29. In
continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator
operates in two cycles. In the first cycle of operation, MOSFET Q is turned on and energy is stored in the
inductor. During this cycle, diode D1 is reverse biased and load current is supplied by the output capacitor, COUT.
In the second cycle, MOSFET Q is off and the diode is forward biased. The energy stored in the inductor is
transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The
output voltage is defined as:
(ignoring the voltage drop across the MOSFET and the diode), or
VOUT + VD1 - VQ =
VIN - VQ
1-D
where D is the duty cycle of the switch, VD1 is the forward voltage drop of the diode, and VQ is the drop across
the MOSFET when it is on. The following sections describe selection of components for a boost converter.
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L
VIN
D1
+
VOUT
+
Q
PWM
L
COUT
L
D1
+ VOUT
+
+ VOUT
RLOAD
VIN
+
-
-
COUT
+
+
VIN
-
COUT
RLOAD
-
Figure 29. Simplified Boost Converter Diagram (a) First cycle of operation. (b) Second cycle of operation
POWER INDUCTOR SELECTION
The inductor is one of the two energy storage elements in a boost converter. Figure 30 shows how the inductor
current varies during a switching cycle. The current through an inductor is quantified as:
IL (A)
VIN
VIN - VOUT
L
L
'i L
IL_AVG
t (s)
D*Ts
Ts
(a)
ID (A)
VIN - VOUT
L
ID_AVG
= IOUT_AVG
t (s)
D*Ts
Ts
(b)
ISW (A)
VIN
L
ISW_AVG
t (s)
D*Ts
Ts
(c)
Figure 30. a. Inductor current b. Diode current c. Switch current
If VL(t) is constant, diL(t)/dt must be constant. Hence, for a given input voltage and output voltage, the current in
the inductor changes at a constant rate.
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The important quantities in determining a proper inductance value are IL (the average inductor current) and ΔiL
(the inductor current ripple difference between the peak inductor current and the average inductor current). If ΔiL
is larger than IL, the inductor current will drop to zero for a portion of the cycle and the converter will operate in
discontinuous conduction mode. If ΔiL is smaller than IL, the inductor current will stay above zero and the
converter will operate in continuous conduction mode. All the analysis in this datasheet assumes operation in
continuous conduction mode. To operate in continuous conduction mode, the following conditions must be met:
IL > ΔiL
Choose the minimum IOUT to determine the minimum L. A common choice is to set (2 x ΔiL) to 30% of IL.
Choosing an appropriate core size for the inductor involves calculating the average and peak currents expected
through the inductor. In a boost converter,
IL =
IOUT
1-D
IL_peak = IL(max) + ΔiL(max)
A core size with ratings higher than these values should be chosen. If the core is not properly rated, saturation
will dramatically reduce overall efficiency.
The LM3481 can be set to switch at very high frequencies. When the switching frequency is high, the converter
can operate with very small inductor values. With a small inductor value, the peak inductor current can be
extremely higher than the output currents, especially under light load conditions.
The LM3481 senses the peak current through the switch. The peak current through the switch is the same as the
peak current calculated above.
Programming the Output Voltage and Output Current
The output voltage can be programmed using a resistor divider between the output and the feedback pins, as
shown in Figure 31. The resistors are selected such that the voltage at the feedback pin is 1.275V. RF1 and RF2
can be selected using the equation,
R
VOUT = 1.275 (1+ F1 )
RF2
A 100 pF capacitor may be connected between the feedback and ground pins to reduce noise.
The maximum amount of current that can be delivered at the output can be controlled by the sense resistor,
RSEN. Current limit occurs when the voltage that is generated across the sense resistor equals the current sense
threshold voltage, VSENSE. Limits for VSENSE have been specified in the electrical characteristics section. This can
be expressed as:
Isw(peak) x RSEN = VSENSE- D x VSL
The peak current through the switch is equal to the peak inductor current.
Isw(peak) = IL(max) + ΔiL
Therefore for a boost converter
(D x VIN)
IOUT(max)
+
Isw(peak) =
(1-D)
(2 x fS x L)
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Combining the two equations yields an expression for RSEN
VSENSE - (D x VSL)
RSEN =
(D x VIN)
IOUT(max)
+
(1-D)
(2 x fS x L)
Evaluate RSEN at the maximum and minimum VIN values and choose the smallest RSEN calculated.
VIN
L
D1
DR
VOUT
Q
+
LM3481
COUT
ISEN
FB
RF1
RSEN
RF2
Figure 31. Adjusting the Output Voltage
Current Limit with Additional Slope Compensation
If an external slope compensation resistor is used (see Figure 22) the internal control signal will be modified and
this will have an effect on the current limit.
If RSL is used, then this will add to the existing slope compensation. The command voltage, VCS, will then be
given by:
VCS = VSENSE − D x (VSL + ΔVSL)
Where VSENSE is a defined parameter in the electrical characteristics section and ΔVSL is the additional slope
compensation generated as discussed in the Slope Compensation Ramp section. This changes the equation for
RSEN to:
VSENSE - D x (VSL+'VSL)
RSEN =
(D x VIN)
IOUT(max)
+
(1-D)
(2 x fS x L)
Note that since ΔVSL = RSL x K as defined earlier, RSLcan be used to provide an additional method for setting the
current limit. In some designs RSL can also be used to help filter noise to keep the ISEN pin quiet.
Power Diode Selection
Observation of the boost converter circuit shows that the average current through the diode is the average load
current, and the peak current through the diode is the peak current through the inductor. The diode should be
rated to handle more than the inductor peak current. The peak diode current can be calculated using the formula:
ID(Peak) = [IOUT/ (1−D)] + ΔiL
In the above equation, IOUT is the output current and ΔiL has been defined in Figure 30.
The peak reverse voltage for a boost converter is equal to the regulator output voltage. The diode must be
capable of handling this peak reverse voltage. To improve efficiency, a low forward drop Schottky diode is
recommended.
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Power MOSFET Selection
The drive pin, DR, of the LM3481 must be connected to the gate of an external MOSFET. In a boost topology,
the drain of the external N-Channel MOSFET is connected to the inductor and the source is connected to the
ground. The drive pin voltage, VDR, depends on the input voltage (see typical performance characteristics). In
most applications, a logic level MOSFET can be used. For very low input voltages, a sub-logic level MOSFET
should be used.
The selected MOSFET directly controls the efficiency. The critical parameters for selection of a MOSFET are:
1. Minimum threshold voltage, VTH(MIN)
2. On-resistance, RDS(ON)
3. Total gate charge, Qg
4. Reverse transfer capacitance, CRSS
5. Maximum drain to source voltage, VDS(MAX)
The off-state voltage of the MOSFET is approximately equal to the output voltage. VDS(MAX) of the MOSFET must
be greater than the output voltage. The power losses in the MOSFET can be categorized into conduction losses
and ac switching or transition losses. RDS(ON) is needed to estimate the conduction losses. The conduction loss,
PCOND, is the I2R loss across the MOSFET. The maximum conduction loss is given by:
IOUT(max) 2
PCOND(MAX) =
DMAXRDS(ON)
1 - DMAX
where DMAX is the maximum duty cycle.
VIN(MIN)
DMAX = 1VOUT
At high switching frequencies the switching losses may be the largest portion of the total losses.
The switching losses are very difficult to calculate due to changing parasitics of a given MOSFET in operation.
Often, the individual MOSFET datasheet does not give enough information to yield a useful result. The following
formulas give a rough idea how the switching losses are calculated:
ILmax x Vout
x fSW x (tLH + tHL)
PSW =
2
RGate
Qgs
x
tLH = Qgd +
VDR - Vgsth
2
Input Capacitor Selection
Due to the presence of an inductor at the input of a boost converter, the input current waveform is continuous
and triangular, as shown in Figure 30. The inductor ensures that the input capacitor sees fairly low ripple
currents. However, as the input capacitor gets smaller, the input ripple goes up. The rms current in the input
capacitor is given by:
(VOUT - VIN)VIN
ICIN(RMS) = 'iL / 3 =
12 VOUTLfS
The input capacitor should be capable of handling the rms current. Although the input capacitor is not as critical
in a boost application, low values can cause impedance interactions. Therefore a good quality capacitor should
be chosen in the range of 100 µF to 200 µF. If a value lower than 100 µF is used, then problems with impedance
interactions or switching noise can affect the LM3481. To improve performance, especially with VIN below 8V, it
is recommended to use a 20Ω resistor at the input to provide a RC filter. This resistor is placed in series with the
VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 32). A 0.1 µF or 1 µF ceramic
capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side
of the resistor with the input power supply.
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RIN
VIN
VIN
LM3481
CBYPASS
CIN
Figure 32. Reducing IC Input Noise
Output Capacitor Selection
The output capacitor in a boost converter provides all the output current when the inductor is charging. As a
result it sees very large ripple currents. The output capacitor should be capable of handling the maximum rms
current. The rms current in the output capacitor is:
Where
'iL =
DVIN
2LfS
and D, the duty cycle is equal to (VOUT − VIN)/VOUT.
The ESR and ESL of the output capacitor directly control the output ripple. Use capacitors with low ESR and ESL
at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer
electrolytic and polymer tantalum, Sanyo- OSCON, or multi-layer ceramic capacitors are recommended at the
output.
Driver Supply Capacitor Selection
A good quality ceramic bypass capacitor must be connected from the VCC pin to the PGND pin for proper
operation. This capacitor supplies the transient current required by the internal MOSFET driver, as well as
filtering the internal supply voltage for the controller. A value of between 0.47µF and 4.7µF is recommended.
Layout Guidelines
Good board layout is critical for switching controllers such as the LM3481. First the ground plane area must be
sufficient for thermal dissipation purposes and second, appropriate guidelines must be followed to reduce the
effects of switching noise. Switch mode converters are very fast switching devices. In such devices, the rapid
increase of input current combined with the parasitic trace inductance generates unwanted Ldi/dt noise spikes.
The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may
turn into electromagnetic interference (EMI), and can also cause problems in device performance. Therefore,
care must be taken in layout to minimize the effect of this switching noise. The current sensing circuit in current
mode devices can be easily effected by switching noise. This noise can cause duty cycle jitter which leads to
increased spectral noise. Although the LM3481 has 250 ns blanking time at the beginning of every cycle to
ignore this noise, some noise may remain after the blanking time.
The most important layout rule is to keep the AC current loops as small as possible. Figure 33 shows the current
flow of a boost converter. The top schematic shows a dotted line which represents the current flow during onstate and the middle schematic shows the current flow during off-state. The bottom schematic shows the currents
we refer to as AC currents. They are the most critical ones since current is changing in very short time periods.
The dotted lined traces of the bottom schematic are the once to make as short as possible.
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Figure 33. Current Flow In A Boost Application
The PGND and AGND pins have to be connected to the same ground very close to the IC. To avoid ground loop
currents attach all the grounds of the system only at one point.
A ceramic input capacitor should be connected as close as possible to the Vin pin and grounded close to the
GND pin.
For a layout example please see Application Note 1204 (SNVA042). For more information about layout in switch
mode power supplies please refer to Application Note 1229 (SNVA054).
Compensation
For detailed explanation on how to select the right compensation components to attach to the compensation pin
for a boost topology please see Application Note 1286 (SNVA067). When calculating the Error Amplifier DC gain,
AEA, ROUT = 152 kΩ for the LM3481.
DESIGNING SEPIC USING LM3481
Since the LM3481 controls a low-side N-Channel MOSFET, it can also be used in SEPIC (Single Ended Primary
Inductance Converter) applications. An example of SEPIC using the LM3481 is shown in Figure 34. As shown in
Figure 34, the output voltage can be higher or lower than the input voltage. The SEPIC uses two inductors to
step-up or step-down the input voltage. The inductors L1 and L2 can be two discrete inductors or two windings of
a coupled transformer since equal voltages are applied across the inductor throughout the switching cycle. Using
two discrete inductors allows use of catalog magnetics, as opposed to a custom transformer. The input ripple can
be reduced along with size by using the coupled windings of transformer for L1 and L2.
Due to the presence of the inductor L1 at the input, the SEPIC inherits all the benefits of a boost converter. One
main advantage of SEPIC over a boost converter is the inherent input to output isolation. The capacitor CS
isolates the input from the output and provides protection against shorted or malfunctioning load. Hence, the
SEPIC is useful for replacing boost circuits when true shutdown is required. This means that the output voltage
falls to 0V when the switch is turned off. In a boost converter, the output can only fall to the input voltage minus a
diode drop.
The duty cycle of a SEPIC is given by:
In the above equation, VQ is the on-state voltage of the MOSFET, Q1, and VDIODE is the forward voltage drop of
the diode.
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Power MOSFET Selection
As in a boost converter, the parameters governing the selection of the MOSFET are the minimum threshold
voltage, VTH(MIN), the on-resistance, RDS(ON), the total gate charge, Qg, the reverse transfer capacitance, CRSS,
and the maximum drain to source voltage, VDS(MAX). The peak switch voltage in a SEPIC is given by:
VSW(PEAK) = VIN + VOUT + VDIODE
The selected MOSFET should satisfy the condition:
VDS(MAX) > VSW(PEAK)
The peak switch current is given by:
'IL1 + 'IL2
ISWPEAK = IL1(AVG) + IOUT +
2
Where ΔIL1 and ΔIL2 are the peak-to-peak inductor ripple currents of inductors L1 and L2 respectively.
The rms current through the switch is given by:
Power Diode Selection
The Power diode must be selected to handle the peak current and the peak reverse voltage. In a SEPIC, the
diode peak current is the same as the switch peak current. The off-state voltage or peak reverse voltage of the
diode is VIN + VOUT. Similar to the boost converter, the average diode current is equal to the output current.
Schottky diodes are recommended.
R7
10 k:
VIN = 3.0V to 24V
D2
5.1V
L1
10 PH
VIN
ISEN
0.47 µF
RC
4.7 k:
CC
0.1 PF
UVLO
COMP
FB
RF2
20 k:
AGND
MBRS130LT3
VCC
LM3481
CS
Q1
IRF7807
DR
PGND
D1
L2
10 PH
VOUT = 5V, 1A
+ COUT
100 PF, 10V
FA/SYNC/SD
RFA
40 k:
RF1
60 k:
1 PF, ceramic
+ CIN
15 PF, 35V x2
CSEN
1 nF
RSEN
0.05:
Figure 34. Typical SEPIC Converter
Selection of Inductors L1 and L2
Proper selection of the inductors L1 and L2 to maintain constant current mode requires calculations of the
following parameters.
Average current in the inductors:
IL2AVE = IOUT
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Peak to peak ripple current, to calculate core loss if necessary:
Maintaining the condition IL > ΔIL/2 to ensure continuous conduction mode yields the following minimum values
for L1 and L2:
(VIN - VQ)(1-D)
L1 >
2IOUTfS
L2 >
(VIN - VQ)D
2IOUTfS
Peak current in the inductor, to ensure the inductor does not saturate:
IL1PK must be lower than the maximum current rating set by the current sense resistor.
The value of L1 can be increased above the minimum recommended value to reduce input ripple and output
ripple. However, once ΔIL1 is less than 20% of IL1AVE, the benefit to output ripple is minimal.
By increasing the value of L2 above the minimum recommendation, ΔIL2 can be reduced, which in turn will
reduce the output ripple voltage:
'VOUT =
(
IOUT
1-D
+
'IL2
2
)
ESR
where ESR is the effective series resistance of the output capacitor.
If L1 and L2 are wound on the same core, then L1 = L2 = L. All the equations above will hold true if the
inductance is replaced by 2L. A good choice for transformer with equal turns is Coiltronics CTX series Octopack.
Sense Resistor Selection
The peak current through the switch, ISWPEAK, can be adjusted using the current sense resistor, RSEN, to provide
a certain output current. Resistor RSEN can be selected using the formula:
VSENSE - D x (VSL+'VSL)
RSEN =
ISWPEAK
SEPIC CAPACITOR SELECTION
The selection of SEPIC capacitor, CS, depends on the rms current. The rms current of the SEPIC capacitor is
given by:
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The SEPIC capacitor must be rated for a large ACrms current relative to the output power. This property makes
the SEPIC much better suited to lower power applications where the rms current through the capacitor is small
(relative to capacitor technology). The voltage rating of the SEPIC capacitor must be greater than the maximum
input voltage. Tantalum capacitors are the best choice for SMT, having high rms current ratings relative to size.
Ceramic capacitors could be used, but the low C values will tend to cause larger changes in voltage across the
capacitor due to the large currents, and high C value ceramics are expensive. Electrolytics work well for through
hole applications where the size required to meet the rms current rating can be accommodated. There is an
energy balance between CS and L1, which can be used to determine the value of the capacitor. The basic
energy balance equation is:
1
1
2
C 'V 2 = (L1)'IL1
2 S S 2
Where
is the ripple voltage across the SEPIC capacitor, and
(VIN - VQ) D
'IL1 =
(L1)fS
is the ripple current through the inductor L1. The energy balance equation can be solved to provide a minimum
value for CS:
CS t L1
IOUT2
(VIN - VQ)2
INPUT CAPACITOR SELECTION
Similar to a boost converter, the SEPIC has an inductor at the input. Hence, the input current waveform is
continuous and triangular. The inductor ensures that the input capacitor sees fairly low ripple currents. However,
as the input capacitor gets smaller, the input ripple goes up. The rms current in the input capacitor is given by:
D
ICIN(RMS) = 'IL1 / 12 =
2 3
VIN - VQ
(L1)fS
The input capacitor should be capable of handling the rms current. Although the input capacitor is not as critical
in a SEPIC application, low values can cause impedance interactions. Therefore a good quality capacitor should
be chosen in the range of 100 µF to 200 µF. If a value lower than 100 µF is used, then problems with impedance
interactions or switching noise can affect the LM3481. To improve performance, especially with VIN below 8V, it
is recommended to use a 20Ω resistor at the input to provide a RC filter. This resistor is placed in series with the
VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 32). A 0.1 µF or 1 µF ceramic
capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side
of the resistor with the input power supply.
OUTPUT CAPACITOR SELECTION
The output capacitor of the SEPIC sees very large ripple currents similar to the output capacitor of a boost
converter. The rms current through the output capacitor is given by:
IRMS =
2
2
ISWPEAK2 - ISWPEAK ('IL1 + 'IL2) + ('IL1 + 'IL2) (1-D) - IOUT
3
The ESR and ESL of the output capacitor directly control the output ripple. Use capacitors with low ESR and ESL
at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer
electrolytic and polymer tantalum, Sanyo- OSCON, or multi-layer ceramic capacitors are recommended at the
output for low ripple.
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OTHER APPLICATION CIRCUITS
R7
121 k:
VIN = 5V
R8
121 k:
C8
390 pF
ISEN
VIN
UVLO
L1
6.8 PH
1 PF
VCC
C9
COMP
RC
22.6 k:
CC
82 nF
FB
RF2
20 k:
RF1
169 k:
LM3481
Q1
DR
D1
+ CIN1, CIN2
150 PF
VOUT = 12V
IOUT = 1.8A
+ COUT1, COUT2
150 PF
PGND
AGND
FA/SYNC/SD
RFA
90.9 k:
CSEN
1 nF
RSEN
20 m:
Figure 35. Typical High Efficiency Step-Up (Boost) Converter
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM3481MM/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SJPB
LM3481MMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SJPB
LM3481QMM/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SUAB
LM3481QMMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SUAB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF LM3481, LM3481-Q1 :
• Catalog: LM3481
• Automotive: LM3481-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM3481MM/NOPB
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3481MMX/NOPB
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3481QMM/NOPB
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3481QMMX/NOPB
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3481MM/NOPB
VSSOP
DGS
10
1000
210.0
185.0
35.0
LM3481MMX/NOPB
VSSOP
DGS
10
3500
367.0
367.0
35.0
LM3481QMM/NOPB
VSSOP
DGS
10
1000
210.0
185.0
35.0
LM3481QMMX/NOPB
VSSOP
DGS
10
3500
367.0
367.0
35.0
Pack Materials-Page 2
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