LM3487 High Efficiency High-Side N-Channel Controller for Switching Regulator General Description Features The LM3487 is a high-side N-channel MOSFET switching regulator controller. It can be used in topologies requiring a high side MOSFET such as buck, inverting (buck-boost) and zeta regulators. The LM3487's internal push pull driver allows compatibility with a wide range of MOSFETs. A wide input voltage range and an adjustable current limit allow the LM3487 to be optimized for a wide variety of applications. The LM3487 has an adjustable switching frequency which can also be synchronized to an external clock. Current-mode control requires only a single resistor and capacitor for frequency compensation. The current mode architecture also yields superior line and load regulation and cycle-by-cycle current limiting. A 7µA shutdown state can be used for power savings and for power supply sequencing. Other features include external soft-start to reduce inrush current and output over voltage protection. ■ Adjustable/synchronizable switching frequency from ■ ■ ■ ■ ■ ■ ■ ■ ■ 100kHz to 1.4MHz Adjustable cycle by cycle current limit Wide 3V-35V input voltage range Thermal shutdown Frequency compensation optimized with a single capacitor and resistor External softstart Current mode operation Undervoltage lockout with hysteresis 10-lead Mini-SO10 (MSOP-10) package Automotive grade including AEC-Q100 is available Applications ■ ■ ■ ■ ■ ■ ■ ■ ■ ADSL Modems Local Voltage Regulation Distributed Power Notebook and Palmtop Computers Internet Appliances Printers and Office Automation Battery operated Devices Cable Modems Battery Chargers Typical Application Circuit 20049233 Typical High Efficiency Step-Down (Buck) Converter © 2008 National Semiconductor Corporation 200492 www.national.com LM3487 High Efficiency High-Side N-Channel Controller for Switching Regulator February 19, 2008 LM3487 Connection Diagram 20049202 10-Lead Mini SO10 Package (MSOP-10 Package) Package Marking and Ordering Information Order Number Package Type Package Marking LM3487MM Supplied As: 1000 units on Tape and Reel LM3487MMX MSOP-10 LM3487QMM S38B LM3487QMMX 3500 units on Tape and Reel 1000 units on Tape and Reel 3500 units on Tape and Reel For automotive grade including AEC-Q100 use ‘Q’ versions. Pin Descriptions Pin Name Pin Number ISEN 1 Current sense input pin. Voltage generated across an external sense resistor is fed into this pin. Description SS/SD 2 Soft-Start and Shutdown pin. Connect a capacitor from this pin to ground to achieve soft-start. Pull this pin below 0.7V (typical) to shutdown the device. COMP 3 Compensation pin. A resistor-capacitor combination connected to this pin provides compensation for the control loop. FB 4 Feedback pin. The output voltage should be adjusted using a resistor divider to provide 1.260V (typical) at this pin. GND 5 Ground pin. FA/SYNC 6 Frequency adjust and synchronization pin. Connect a resistor from this pin to ground to set the switching frequency. Connect a high impedance clock signal to this pin to synchronize the switching frequency with the rising edge of the clock. SW 7 Switch Node. Source of the external MOSFET is connected to this node. DR 8 Drive pin. The gate of the external MOSFET should be connected to this pin. CB 9 Boot-strap pin. A capacitor must be connected between this pin and SW pin (pin 5) for proper operation. The voltage developed across this capacitor provides the gate drive for the external MOSFET. VIN 10 Power Supply Input pin. www.national.com 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN (Note 2) Peak Driver Output Current (<10ns) FA/SYNC SW FB CB ISEN Power Dissipation (Note 3) Storage Temperature Range 45V 1.0A 5.5V VIN 2.5V 7.2V + VSW (Vin-500mV) to Vin .5W −65°C to +150°C Electrical Characteristics Operating Ratings +150°C 2kV 200V 215°C 220°C (Note 1) 2.97V ≤ VIN ≤ 35V Supply Voltage Junction Temperature Range −40°C ≤ TJ ≤ +125°C (Note 5) Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature Range. Unless otherwise specified, VIN = 12V. Symbol VFB Parameter Feedback Voltage ΔVLINE Feedback Voltage Line Regulation ΔVLOAD VUVLO VUVLO(HYS) FS Conditions Vcomp = 0.7V 2.97V ≤ VIN ≤ 35V Typical Limit Units 1.210 1.290 V V(min) V(max) 1.260 0.001 %/V Output Voltage Load Regulation ±0.5 %/V (max) Input Undervoltage Lock-out 2.80 Input Undervoltage Lock-out Hysteresis Nominal Maximum Switching Frequency 2.97 V V(max) 100 235 mV mV (min) mV (max) 1.25 1.66 MHz MHz(min) MHz(max) 180 RFA = 9.76K 1.45 RDRIVE Driver Switch On Resistance (Source) IDR = 0.2A, VIN= 5V 7 Ω RDRIVE Driver Switch On Resistance (Sink) 9 Ω Dmax Maximum Duty Cycle (Note 6) 100 % Tmin (on) Minimum On Time 130 nsec ISUPPLY Supply Current (switching) IQ VCL(O) VCL(100) VSC IDR = 0.2A SS/SD=open DR=open Quiescent Current in Shutdown Mode VIN = 5V, SS/SD=0V Current Limit Voltage at 0% Duty Cycle VIN = 5V Current Limit Voltage at 100% Duty Cycle VIN = 5V Short-Circuit Current Limit Sense Voltage VIN = 5V 2.4 6 mA mA (max) 10 µA µA (max) 90 200 mV mV (min) mV (max) 60 120 mV mV (min) mV (max) 270 420 mV mV (min) mV (max) 7.3 155 118 350 VSL Internal Compensation Ramp Voltage VIN = 5V Height 65 VOVP Output Over-voltage Protection (with respect to feedback voltage) (Note 7) 50 VCOMP = 0.7V 3 mV 40 110 mV mV(min) mV(max) www.national.com LM3487 Junction Temperature ESD Susceptibility (Note 4) Human Body Model Machine Model Lead Temperature for MSOP Package Vapor Phase (60 sec.) Infrared (15 sec.) Absolute Maximum Ratings (Note 1) LM3487 Symbol VOVP(HYS) Gm IEAO Parameter Conditions Output Over-Voltage Protection Hysteresis(Note 7) VCOMP = 0.7V Error Amplifier Transconductance VCOMP = 0.7V Error Amplifier Output Current (Source/ Source, VCOMP = 0.7V, VFB = Sink) 0V VEAO Error Amplifier Output Voltage Swing Typical Limit Units 20 110 mV mV(min) mV(max) 500/300 1000/1300 µmho µmho (min) µmho (max) 60 750 103 µA Sink, VCOMP = 0.7V, VFB = 1.4V 138 µA Upper Limit VFB = 0V COMP Pin = Floating 1.5 V V(min) V(max) Lower Limit VFB = 1.4V 0.4 V V(min) V(max) VSD Shutdown Threshold (Note 8) 0.7 V VSYNC FA/SYNC Threshold Voltage 2.5 V ISS SS Source Current 2.4 µA TSD Thermal Shutdown 165 °C TSH Thermal Shutdown Hysteresis θJA Thermal Resistance VSD = 0V MM Package 10 °C 200 °C/W Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The Absolute Maximum VIN rating of 45V is for non-operational (storage) conditions only. The maximum operating voltage is 35V. Note 3: The maximum allowable power dissipation is calculated by using PDMAX= (TJMAX-TA)/θJA, where TJMAX is the maximum junction temperature, TA is the ambient temperature and θJA is the junction to ambient thermal resistance of the package. The 0.5W rating results from using 125°C, 25°C, and 200°C/W for TJMAX, TA, and θJA respectively. A θJA of 200°C/W represents the worst case condition of no heat sinking of the MSOP-10 package. Note 4: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is 200 pF capacitor discharged directly into each pin. Note 5: All limits are guaranteed at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature limits are 100% tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 6: 100% duty cycle can be achieved only for a limited number of cycles before the CB voltage collapses and the device shuts down. Note 7: The over-voltage protection is specified with respect to the feedback voltage. The overvoltage protection threshold is given by adding the feedback voltage, VFB to the over-voltage protection specification. Note 8: The SS/SD pin must be pulled below this limit to turn the regulator off. Typical Performance Characteristics Unless otherwise specified, VIN = 12V, TJ = 25°C. IQ (Shutdown) vs Temperature & Supply Voltage ISupply vs Temperature & Supply Voltage (Non-Switching) 20049213 www.national.com 20049214 4 LM3487 ISupply vs Temperature & Supply Voltage (Switching) Frequency vs Temperature 20049216 20049215 VCB−VSW vs Supply Voltage Error Amplifier Gain 20049220 20049208 Error Amplifier Phase Shift COMP Pin Source Current vs Temperature 20049219 20049209 5 www.national.com LM3487 Slope Compensation Ramp vs Slope Compensation Resistor Efficiency vs Load Current (VOUT = 2.5V, 500kHz) 20049212 200492n8 Efficiency vs Load Current (VOUT = 5V, 500kHz) Softstart Source Current vs Temperature 200492o1 200492n9 VFB vs Temperature Short Circuit Threshold Voltage vs Temperature 200492o2 200492o3 www.national.com 6 LM3487 Functional Description Functional Block Diagram 20049201 quency than in PWM mode (see OVER VOLTAGE PROTECTION section). GENERAL DESCRIPTION The LM3487 is a switching regulator controller for topologies incorporating a high side switch. The most common of these topologies is the step-down, or buck, converter. Other topologies such as the inverting (buck-boost) and inverse SEPIC (zeta) converters can also be realized. This datasheet will focus on buck converter applications. The LM3487 employs current mode control architecture. Among the many benefits of this architecture are superior line and load regulation, cycle-by-cycle current limiting, and simple loop compensation. A patented adjustable slope compensation scheme enables flexible inductor selection. The LM3487 has a combination of features that allow its use in a wide variety of applications. The input voltage can range from 2.97V to 35V, with the output voltage being positive or negative depending on the topology. The current limit can be scaled to safely drive a wide range of loads. An external softstart is used to limit initial in-rush current. Output over voltage and input under voltage protection ensure safe operation of the LM3487. 200492j2 REGIONS OF OPERATION Pulse width modulation (PWM) is the normal mode of operation. In PWM, the output voltage is well regulated and has a ripple frequency equal to the switching frequency. In low load conditions, the part operates in hysteretic mode. In this mode, the output voltage is regulated between a high and low value that results in a higher ripple magnitude and lower ripple fre- FIGURE 1. Operating Regions of the LM3487 Figure 1 shows the operating regions of the LM3487. The device will enter hysteretic mode below minimum duty cycle, or at low loads below the VHYS threshold. Above the VCL threshold, the device is in current limit. VSC is the current limit ceiling. 7 www.national.com LM3487 Above this ceiling, the device enters short circuit protection mode (see the SHORT CIRCUIT CURRENT LIMIT section). The voltages in Figure 1 can be referred to the switch current by dividing through by RSN. The LM3487 has a low hysteretic threshold voltage VHYS, and thus will operate in PWM mode for a large load range. Typically, VHYS = 11mV for the LM3487. OVER VOLTAGE PROTECTION The LM3487 has over voltage protection (OVP) for the output voltage. OVP is sensed at and is in respect to the feedback pin (pin 4). If at anytime the voltage at the feedback pin rises to VFB + VOVP, OVP is triggered. See ELECTRICAL CHARACTERISTICS section for limits on VFB and VOVP. OVP will cause the drive pin to go low, forcing the power MOSFET off. With the MOSFET off, the output voltage will drop. The LM3487 will begin switching again when the feedback voltage reaches VFB + (VOVP - VOVP(HYS)). See ELECTRICAL CHARACTERISTICS for limits on VOVP(HYS). OVP can be triggered by any event that causes the output voltage to rise out of regulation. There are several common circumstances in which this can happen, and it is beneficial for a designer to be aware of these for debugging purposes, since the mode of operation changes from the normal Pulse Width Modulation (PWM) mode to the hysteretic mode. In the hysteretic mode the output voltage is regulated within the OVP hysteresis window, which results in a higher ripple magnitude and lower ripple frequency than in the PWM mode, see Figure 4. It is useful to plot the operational boundaries in order to illustrate the point at which the device switches into hysteretic mode. In Figure 4, the limits shown are with respect to the peak voltage across the sense resistor RSEN, (VSENpk); they can be referred to the peak inductor current by dividing through by RSEN. In normal circumstances VSENpk is within the shaded region, and the LM3487 will operate in the PWM mode. If operating conditions are chosen such that VSENpk would not normally fall in the shaded regions (for example, under light load), then the mode of operation is changed so that VSENpk will be forced into the shaded region, and the part will operate in the hysteretic mode. The LM3487 will not allow VSENpk to be outside of the shaded regions, so the duty cycle is adjusted accordingly. FREQUENCY ADJUST/SYNCHRONIZATION The switching frequency of the LM3487 can be adjusted between 100kHz and 1.4MHz using a single external resistor. This resistor must be connected from FA/SYNC pin to ground as shown in Figure 2. See Figure 3 to determine the required resistance to set a switching frequency. To ensure stable operation, a 10nF capacitor should be placed in parallel with the resistor as shown. The LM3487's switching frequency can also be synchronized to an external signal. A switching period is initialized at every rising edge of the applied external signal. The synchronizing signal should transition between 0V and at least 2.5V, but no greater than 5.5V. The signal must have a pulse width of at least 100 ns. 200492m9 FIGURE 2. Programming the Switching Frequency 200492c1 FIGURE 4. The Feedback Voltage is related to the Output Voltage. See different Ripple Components in PWM and Hysteretic Modes If the load current becomes too low, and VSENpk falls below VHYS, the LM3487 will increase the duty cycle, causing the voltage to rise and trigger the OVP. Another way OVP can be tripped is if the input voltage rises higher than the LM3487 is able to regulate in pulse width modulation (PWM) mode. The output voltage is related to the input voltage by the duty cycle as: VOUT = VIN*D. Minimum 200492n7 FIGURE 3. Frequency vs RFA www.national.com 8 LM3487 duty cycle can be calculated as DMIN = TON(MIN)*fSW. Where TON(MIN) is the minimum on time of 130ns (typical). If the input voltage increases such that the duty cycle wants to be less than DMIN, the duty cycle will hold at DMIN and the output voltage will increase with the input voltage until it trips OVP. An output voltage transient response overshoot can also trigger OVP. As discussed in the OUTPUT CAPACITOR section, if the capacitance is too low or ESR too high, the output voltage overshoot can rise high enough to trigger OVP. However, as long as there is room for the duty cycle to adjust (the converter is not near DMIN or DMAX), the LM3487 will return to PWM mode after a few cycles of hysteretic mode operation. There is one last way that OVP can be triggered. If the unregulated input voltage crosses 7.2V, the output voltage will react as shown in Figure 5. The internal bias of the LM3487 switches on at 7.2V input. When this happens, a sudden small change in bias voltage is seen by all the internal blocks of the LM3487. The control voltage, VC, shifts because of the bias change, and the PWM comparator tries to keep regulation. To the PWM comparator, the scenario is identical to a step change in the load current, so the response at the output voltage is the same as would be observed in a step load change. Hence, the output voltage overshoot here can also trigger OVP. The LM3487 will regulate in hysteretic mode for several cycles, or may not recover and simply stay in hysteretic mode until the load current drops. Note that the output voltage is still regulated in hysteric mode. Predicting whether or not the LM3487 will come out of hysteretic mode in this scenario is a difficult task, however it is largely a function of the output current and the output capacitance. Triggering hysteretic mode in this way is only possible at higher load currents. To avoid this condition, increase the output capacitance. 200492c2 FIGURE 6. The Current Sensing Loop and Corresponding Waveforms As a brief explanation, consider Figure 6. The top portion shows a schematic of the current sensing loop. The bottom portion shows the pulse width modulation (PWM) comparator waveforms for two switching cycles. The two solid waveforms shown are the waveforms compared at the internal pulse width modulator, used to generate the MOSFET drive signal. The top waveform with the slope Se is the internally generated control waveform VC. The bottom waveform with slopes Sn and Sf is the sensed inductor current waveform VSEN. VSEN is fed back to the PWM comparator, where it is compared to VC. The output of the comparator in combination with the R/ S latch determine if the MOSFET is on or off, which effectively controls the amount of current the inductor receives. While VC is higher than VSEN, the PWM comparator outputs a high signal, driving the external power MOSFET on. When MOSFET is on, the inductor current rises at a constant slope, generating the sensed voltage VSEN. When VSEN equals VC, the PWM comparator turns the MOSFET off, and the sensed inductor current decreases with a slope Sf. The process begins again when RS latch is set by an internal oscillator. The subharmonic oscillation phenomenon occurs when a load excursion is experienced. It is analyzed by calculating how the inductor current settles after such an excursion. Take for example the case when the inductor current experiences a step increase in its average current, shown as the dotted line in Figure 6. In the switching period that the excursion occurs, the inductor current will change by ΔI0. In the following switching period, the inductor current will have a difference ΔI1 from its original starting value. Thus the original excursion is being propagated each switching cycle. Whether or not there are subharmonic oscillations depends on whether this propagation is converging or diverging. The difference in the inductor current from one cycle to the next (ΔIn) is a function of Sn, Sf, and Se, as follows: 200492j6 FIGURE 5. The Feedback Voltage Experiences an Oscillation if the Input Voltage Crosses the 7.2V Internal Bias Threshold DEFAULT/ADJUSTABLE SLOPE COMPENSATION The LM3487 uses a current mode control scheme. There are many advantages in a current mode architecture including inherent cycle-by-cycle current limiting and simple compensation of the control loop. However, there are consequences to using current mode control that one must be aware of while selecting circuit components. One of these consequences is the inherent possibility of subharmonic oscillations in the inductor current. This is a form of instability and should be avoided. Hence, if the quantity (Sf - Se)/(Sn + Se) is greater than 1, the inductor current diverges and subharmonic oscillations result. Notice that as Se increases, the factor decreases. Also, when 9 www.national.com LM3487 the duty cycle is greater than 50%, and as the inductance decreases, the factor increases. The LM3487 internally generates enough slope compensation Se to allow for the use of reasonable inductances. The height of the compensation slope ramp VSL can be found in the ELECTRICAL CHARACTERISTICS section. The LM3487 incorporates a patented scheme to increase Se if there is need to use a smaller inductor. With the use of a single resistor R SL, S e can be increased indefinitely. RSL increases the compensation slope by the amount: Therefore, 200492n1 When excursions of the inductor current are divergent, the current sensing control loop is unstable and produces a subharmonic oscillation in the inductor current. This oscillation is viewed as a resonance in the outer voltage control loop at half the switching frequency. In the inductor design section, calculations for minimum inductance and necessary slope resistance RSL are carried out based on this resonant peaking. FIGURE 7. Soft Start Thresholds INPUT UNDER VOLTAGE LOCKOUT (UVLO) The input under voltage lockout, which is sensed at VIN, is set at 2.80V (typical). If the input voltage falls below this threshold, the FET will be turned off and the soft-start capacitor will be discharged. As the input voltage rises above 3.0V (typical) the LM3487 will restart from the soft-start phase. SOFT-START/SHUTDOWN The softstart time of the LM3487 is programmed by an external capacitor connected from the SS/SD pin to ground, as shown in Figure 7. When the input voltage is applied to the device, a 2µA current source charges the capacitor at a constant rate. When the capacitor develops 0.75V (typical), the LM3487 begins switching the power MOSFET at low duty cycles. The softstart period continues until the softstart capacitor reaches 2V. Therefore, the turn-on delay period between 0 - 0.75V is: CURRENT LIMIT PROTECTION Current limit is sensed as the voltage across the sense resistor. When this voltage exceeds the VCL threshold, current limit is activated and the LM3487 will immediately shut off the FET until the next cycle. This will cause the duty cycle and output voltage to drop. The current limit threshold can be adjusted using the sense resistor (see the SETTING CURRENT LIMIT section). In current limit operation, the FET will turn on each cycle and will remain on during the leading edge minimum on time (130nsec typical). During this minimum on time, inductor current may become excessive under short circuit conditions. In this case, a secondary current limit, Short Circuit Protection, is enabled. and the softstart period between 0.75V - 2V is: SHORT CIRCUIT PROTECTION When the voltage across the sense resistor (measured as the VIN − ISEN differential voltage) exceeds VSC, short-circuit current limit gets activated. In the short-circuit protection mode, the external MOSFET is turned off. When the short is removed, the external MOSFET is held off for up to four cycles before resuming normal operation. The short circuit protection voltage VSC is specified in the ELECTRICAL CHARACTERISTICS section. The time from when voltage is applied to the LM3487 to when the output voltage reaches its target can be approximated as tDELAY + tSS. A minimum value of 2.2nF is recommended for Css. During softstart, both current limit and OVP are enabled. However, since the feedback reference voltage ramps up with softstart voltage, the OVP threshold will ramp up along with it. The LM3487 will not start up if the output voltage is held above 200mV. If the slope resistor (Rsl) is used, the hysteretic threshold will be lowered and up to 100mA of pre-load may be required for startup. The LM3487 may be disabled by pulling the voltage at the SS/ SD pin below 0.7V (typical). In this shutdown mode, the device consumes only 15µA (max). This is typically accomplished by presenting a low impedance path from the SS/ SD pin to ground using a transistor as shown in Figure 7. Driving this impedance high will engage the softstart procedure and enable the device. www.national.com Design Section GENERAL Power supply design involves making tradeoffs. The LM3487 provides many degrees of flexibility in choosing external components to accommodate various performance/component selection optimizations. For example, the internal slope compensation can be externally increased to allow smaller inductances to be used. The design procedures that follow provide instruction on how to select the external components in a typical LM3487 buck circuit in continuous conduction mode, as well as aid in the optimization of performance and/or compo- 10 DMIN = TMIN* fs This will not limit how high the input voltage can rise, since the LM3487 will operate in hysteretic mode once the operating duty cycle decreases to the minimum duty cycle. SETTING CURRENT LIMIT AND HYSTERETIC THRESHOLD The current limit is the point at which the LM3487 begins to limit the peak switch current. The adjustable current limit of the LM3487 is set by the sense resistor RSN. The voltage across RSN is compared to an internal control voltage VC. The onset of current limiting is when VSEN(PEAK) equals VC(MAX), or VCL (current limit voltage). VSEN is defined here as the differential voltage from the VIN pin to the ISEN pin. VCL decreases as the duty cycle increases, as shown in Figure 9. Therefore, it is important to know both VSEN(PEAK) and VCL(MIN) at the maximum operating duty cycle, or lowest VIN condition. 200492m8 FIGURE 8. LM3487 Buck Converter Reference Schematic PROGRAMMING THE OUTPUT VOLTAGE The output voltage can be programmed using a resistor divider between the output and the feedback pins, as shown in Figure 8. The resistors are selected such that the voltage at the feedback pin is 1.26V. RFB1 and RFB2 can be selected using the equation: VOUT = 1.26*(1+ RFB1/RFB2) CALCULATING THE DUTY CYCLE In buck converter applications, the duty cycle of the LM3487 may be calculated as: 200492k3 FIGURE 9. Current Limit and Hysteretic Threshold vs Duty Cycle Where VD = forward drop of the power diode ≊ 0.5V VQ = VDS of the MOSFET when it is conducting ≊ IOUT*RDSON VSEN = Voltage across the sense resistor = IOUT x RSEN This is the fraction of the switching period that the switch is on. The switch is off for the remainder of the period. This fraction is expressed as: VCL(MIN) = VCL(0)(MIN) − D(MAX) (VCL(0)(MIN) − VCL(100)(MIN)) D' = 1 − D where DMAX is the duty cycle at the lowest VIN condition. To avoid current limit, The LM3487 has limits for the maximum and minimum duty cycle (see ELECTRICAL CHARACTERISTICS). The LM3487 can operate at 100% duty cycle, but only for a few periods (during transients). The gate voltage of the N channel MOSFET must be higher than VIN in order for it to be on. The LM3487 provides this drive voltage through the voltage developed across CBOOT, which is charged when the SW pin goes low (i.e. when the MOSFET is off and the diode is conducting). In this configuration, the drive voltage can not be maintained with a continuous 100% duty cycle. If the off time is too short to allow Cboot to recharge, the device will automatically shut down and enter softstart mode when VCBOOT falls below approximately 1.5V. There is also a second level VSEN(PEAK) < VCL(MIN) Therefore, 11 www.national.com LM3487 of protection, whereby if the FET stays on for more than typically 450µs, the LM3487 will restart regardless of the Cboot voltage. To avoid this condition, either decrease the duty cycle or lower the operating frequency. The minimum duty cycle of the LM3487 corresponds to the minimum on time, or blank out time (see ELECTRICAL CHARACTERISTICS). nent selection. See Figure 8 for component reference and typical circuit. The LM3487 may also be designed to operate in discontinuous conduction mode. LM3487 Example: VIN(MIN) = 4.5V, VOUT = 2.5V, IOUT(MAX) = 3A, L = 3.3µH, fs = 500kHz where MAX(VHYS − 50x10-6 x RSL x DMAX, 0) is the larger of the two values in the parenthesis. RSL can be used creatively to intentionally lower the hysteretic threshold, allowing for better performance at lower loads. However, when RSL is used, there may be a minimum load requirement (see START-UP/SOFT-START section). Hysteretic threshold is the switch current at which the LM3487 enters the hysteretic mode of operation (see OVER VOLTAGE PROTECTION section). Hysteretic threshold is derived in a similar manner to current limit threshold, the only difference being that VSEN(PEAK) is compared VC(MIN) (VHYS). Notice that VHYS does not vary with the duty cycle. The hysteretic threshold is predetermined by the selection of RSN above. The hysteretic threshold is: POWER INDUCTOR SECTION 1. Select Inductor Value The LM3487 operates at high switching frequencies up to 1.4 MHz, which allows the use of small inductors. As the switching frequency (fs) increases, the inductance required for a given output voltage ripple decreases. This is made apparent in the following set of equations used to calculate the output voltage ripple. ΔVOUT(Pk-Pk) ≊ ΔiL(Pk-Pk) x RESR (V) Continuing with the example above, Use the equations above for ΔVOUT and ΔiL to select an inductance value. The maximum voltage ripple in steady-state, PWM operation can be controlled by limiting ΔiL which in turn is set by the inductance value. Alternatively, one can simply choose ΔiL as a percentage of the maximum output current. Clearly, the size of the output capacitor ESR, RESR, will have an affect on which criteria is used to choose the inductance. When the ESR is relatively low (less than 100mΩ), such as in ceramic, OSCON, and some low ESR tantalum capacitors, it is convenient to choose the inductance based on setting ΔiL to 30% of Iout (max). If the ESR is high, then it may be necessary to restrict ΔiL to a lower value so that the output voltage ripple is not too high. Generally speaking, the former suggestion of setting ΔiL to 30% of IOUT(MAX) is recommended. 2. Verify Stability The inductance also affects the stability of the converter. The slopes Sn and Sf in Figure 6 are functions of the inductance, while the compensation ramp, Se, is fixed by default. Therefore if the inductance is too small, the converter may experience sub-harmonic oscillations. The LM3487 provides sufficient internal slope compensation to allow for inductances chosen according to the ΔiL = 0.3 x IOUT guideline in most cases. Still, one should check to make sure the inductance is not too low before continuing the design process. If it is found that the selected inductance is too low, a patented scheme to increase the compensation ramp, Se, is provided in the LM3487 (see DEFAULT/ADJUSTABLE SLOPE COMPENSATION section). In the calculations that follow, if it is found that the chosen inductance is too small, RSL can be used to increase so that the inductance can be used. In a current mode control architecture, there is an inherent resonance at half the switching frequency (see DEFAULT/ ADJUSTABLE SLOPE COMPENSATION section). A convenient indicator of how much resonance exists is the quality factor Q. If Q is too high, subharmonic oscillations could occur, if Q is too low, the current mode architecture begins to act like a voltage mode architecture and the necessary compensation becomes more complex. This is discussed in more detail in the COMPENSATION section, but here it is important to calculate Q to be sure the selected inductance will not If the peak switch current decreases below this threshold, the LM3487 will operate in hysteretic mode (see OVER VOLTAGE PROTECTION section). In some designs, it will be desired to use RSL so that lower valued inductors can be used (see DEFAULT/ADJUSTABLE SLOPE COMPENSATION section and Inductor section). Using RSL will lower the current limit and the hysteretic threshold. See Figure 10. RSL effectively adds an additional slope to the existing slope of the VC waveform. 200492k4 FIGURE 10. Current Limit and Hysteretic Threshold vs Duty Cycle with RSL When RSL is used, the following equations apply: www.national.com 12 Output Capacitor Considerations Skip to the "Calculations for the output capacitor" subsection if a quick design is desired. While it is generally desired to use as little output capacitance as possible to keep costs down, the output capacitor should be chosen with care as it directly affects the ripple component of the output voltage as well as other components in the design. The output voltage ripple is directly proportional to the ESR of the output capacitor (see POWER INDUCTOR section). Therefore, designs requiring low output voltage ripple should have an output capacitor with low ESR. Choosing a capacitor with low ESR has the additional benefit of requiring one less component in the compensation network, as discussed in the Compensation section. In addition to the output voltage ripple, the output capacitor directly affects the output voltage overshoot in a load transient. Two transients are possible: an unloading transient and a loading transient. An unloading transient occurs when the load current transitions to a higher current, and charge is unloaded from the output capacitor. A loading transient is when the load transitions to a lower current, and charge is loaded to the output capacitor. How the output voltage reacts during these transitions is known as the transient response. Both the capacitance and the ESR of the output capacitor will affect the transient response. Where, D' = 1−D VQ = VDS of the MOSFET when it is conducting IOUT*RDS(ON). VSEN = Voltage across the sense resistor ≊ IOUT x RSN Back solving for L gives a range for acceptable inductances based on a range for Q: 200492b9 It is recommended that: Q(max) = 2, and Q(min) = 0.15 Values for VSL can be found in the ELECTRICAL CHARACTERISTICS section. Note: Adding slope compensation with RSL will decrease the current limit. An iterative process may be needed to meet current limit and stability requirements, see PROGRAMMING CURRENT LIMIT/HYSTERETIC THRESHOLD section. FIGURE 11. A Loading Transient The control loop of the LM3487 can be made fast enough to saturate the duty cycle when the worst case lode transient occurs. This means the duty cycle jumps to DMIN or DMAX, depending on the type of load transient. In a loading transient, as shown in Figure 11, the duty cycle drops to DMIN while the inductor current falls to match the load current. During this time, the regulator is heavily dependent on the output capacitors to handle the load transient. The initial overshoot is caused by the ESR of the output capacitors. How the output voltage recovers after that initial excursion depends on how fast the inductor current falls and how large the output capacitance is. See Figure 12. OUTPUT CAPACITANCE SELECTION A capacitance between 47µF - 100µF is typically used. Skip to "Calculations for the Output Capacitance" for minimum capacitance calculations. Type of output capacitors Different type of capacitors often have different combinations of capacitance, equivalent series resistance (ESR), and voltage ratings. High-capacitance multi-layer ceramic capacitors (MLCCs) have a very low ESR, typically 12mΩ, but also relatively low capacitance and low voltage ratings. Tantalum capacitors can have fairly low ESR, such as 18mΩ, and high capacitance (up to 1mF) at higher voltage ratings than MLCCs. Aluminum capacitors offer high capacitance and relatively low ESR and are available in high voltage ratings. OSCON capacitors can achieve ESR values that are even lower than those of MLCCs and with higher capacitance, but the voltage ratings are low. Other tradeoffs in capacitor technology include temperature stability, surge current capability, and capacitance density (physical size vs. capacitance). 200492b5 FIGURE 12. Output Voltage Overshoot Violation The ESR and the capacitance of the output capacitor must be carefully chosen so that the output voltage overshoot is within 13 www.national.com LM3487 cause problems to the stability of the converter. The calculations below call for an inductance that results in Q between 0.15 and 2. See the COMPENSATION section if the chosen inductance enforces Q to be out of this range. By default, no extra slope compensation is needed, so RSL = 0. In general, a Q between 0.5 and 1 is optimal. LM3487 the design's specification VOS(MAX). If the total combined ESR of the output capacitors is not low enough, the initial output voltage excursion will violate the specification, see ΔVC1. If the ESR is low enough, but there is not enough output capacitance, the output voltage will travel outside the specification window due to the extra charge being dumped into the capacitor, see ΔVC2. The LM3487 has output over voltage protection (OVP) which could trigger if the transient overshoot is high enough. If this happens, the controller will operate in hysteretic mode (see OVER VOLTAGE PROTECTION section) for a few cycles before the output voltage settles to its steady state. If this behavior is not desired, substitute VOVP (referred to the output) for VOS(MAX) (VOVP is found in the ELECTRICAL CHARACTERISTICS table) to find the minimum capacitance and maximum ESR of the output capacitor. 200492b6 FIGURE 13. Output Voltage Overshoot Peak The intention is to find the capacitance value that will yield, at tpeak, a ΔVC that equals VOS(max). Substituting tpeak for t and equating ΔVC to VOS(max) gives the following solution for COUT (MIN): Calculations for the Output Capacitor During a loading transient, the delta output voltage ΔVc has two changing components. One is the voltage difference across the ESR (ΔVr), the other is the voltage difference caused by the gained charge (ΔVq). This gives: ΔVc = ΔVr + ΔVq The chosen output capacitance should not be less than 47µF, even if the solution for COUT(MIN) is less than 47µF. Notice it is already assumed that the total ESR is no greater than RESR (MAX), otherwise the term under the square root will be a negative number. The design objective is to keep ΔVc lower than some maximum overshoot (VOS(MAX)). VOS(MAX) is chosen based on the output load requirements. Both voltages ΔVr and ΔVqwill change with time. For ΔVr the equation is: POWER MOSFET SELECTION The drive pin of LM3487 must be connected to the gate of an external MOSFET. In a buck topology, the drain of the external N-Channel MOSFET is connected to the input and the source is connected to the inductor. The CB pin voltage provides the gate drive needed for an external N-Channel MOSFET. The gate drive voltage depends on the input voltage (see TYPICAL PERFORMANCE CHARACTERISTICS). In most applications, a logic level MOSFET can be used. For very low input voltages, a sub-logic level MOSFET should be used. The selected MOSFET directly controls the efficiency. The critical parameters for selection of a MOSFET are: 1. Minimum threshold voltage, VTH(MIN) 2. On-resistance, RDS(ON) 3. Total gate charge, Qg 4. Reverse transfer capacitance, CRSS 5. Maximum drain to source voltage, VDS(MAX) 6. Maximum drain current, ID(MAX) The off-state voltage of the MOSFET is approximately equal to the input voltage. VDS(MAX) of the MOSFET must be greater than the input voltage. Also, the ID rating must be greater than the maximum peak load current. The power losses in the MOSFET can be categorized into conduction losses and ac switching or transition losses. RDS (ON) is needed to estimate the conduction losses. The conduction loss, PCOND, is the I2R loss across the MOSFET. The maximum conduction loss is given by: where, RESR = the output capacitor ESR ΔIOUT = the difference between the load current change IOUT (MAX) − IOUT(MIN) DMIN = Minimum duty cycle of device (TMIN • fs) Evaluating this equation at t = 0 gives ΔVr(max). Substituting VOS(MAX) for ΔVr(MAX) and solving for RESR gives: The expression for ΔVq is: From Figure 13 it can be seen that ΔVC will reach its peak value at some point in time and then decrease. The larger the output capacitance is, the earlier the peak will occur. To find the peak position, let the derivative of ΔVC go to zero, and the result is: where DMAX is the maximum operating duty cycle: www.national.com 14 must be able to dissipate the power. PD(CIN) must be lower than the rated power dissipation of the selected input capacitor. In many cases, several capacitors have to be paralleled to handle the rms current. In that case, the power dissipated in each capacitor is given by: PD(CIN) = (I2RMS_CINRESR_CIN)/n2, where n is the total number of capacitors paralleled at the input. A 0.1µF or 1µF ceramic bypass capacitor is also recommended on the VIN pin of the IC. This capacitor must be connected very close to the pin. IG = Qg.FS The required gate drive power to turn the MOSFET on is equal to the switching frequency times the energy required to deliver the charge to bring the gate charge voltage to VDR (see ELECTRICAL CHARACTERISTICS and TYPICAL PERFORMANCE CHARACTERISTICS for the drive voltage specification). COMPENSATION PDrive = FS.Qg.VDR It is sometimes helpful or necessary to slow down the turn on transition of the FET so that less switching noise appears at the ISEN pin. This can be done by inserting a drive resistor RDR in series with the boot-strap capacitor (see Figure 8). This can help reduce sensing noise that may be preventing designs from operating at or near the LM3487's minimum duty cycle limit. Gate drive resistors from 2.2Ω to 51Ω are recommended. 20049291 CALCULATING POWER DISSIPATION Although most of the power loss in a switching regulator is dissipated in the FETs, it can also be useful to know the power used by the IC. The electrical characteristics table shows a typical value for Iq, however this does not include the FET drive current. The following equation gives an accurate estimate of power lost in the device during switching: Where IG is the average drive current defined above, and VDR is the FET drive voltage, typically 6.1V. FIGURE 14. Control Block Diagram of a Current Mode Controlled Buck Converter The LM3487 is a current mode controller, therefore the control block diagram representation involves 2 feedback loops (see Figure 14). The inner feedback loop derives its feedback from the sensed inductor current, while the outer loop monitors the output voltage. This section will not give a rigorous analysis of current mode control, but rather a simplified but accurate method to determine the compensation network. The first part reveals the results of the model, giving expressions for solving for component values in the compensation network. The compensation network is designed around the power components, or the power stage. An isolated schematic of the error amplifier and the various compensation components is shown in Figure 15. The error amplifier in conjunction with the compensation network makes up the compensator block in Figure 14. The purpose of the compensator block is to stabilize the control loop and achieve high performance in terms of the transient response, audio susceptibility and output impedance. PD = VinIq + (Vin - VDR) IG POWER DIODE SELECTION The output current commutates through the diode when the external MOSFET turns off. The three most important parameters for the diode are the peak current, peak inverse voltage, and average power dissipation. Exceeding these ratings can cause damage to the diode. The average current through the diode is given by: ID(AVG) = IOUT x (1-D) where D is the duty cycle and IOUT is the output current. The diode must be rated to handle this current. The off-state voltage across the diode in a buck converter is approximately equal to the input voltage. The peak inverse voltage rating of the diode must be greater than the off-state voltage of the diode. To improve efficiency, a low forward drop schottky diode is recommended. INPUT CAPACITOR SELECTION In a buck converter, the high side switch draws large ripple currents from the input capacitor. The input capacitor must be rated to handle this RMS current. The power dissipated in the input capacitor is given by: PD(CIN)=IRMS_CIN2RESR_CIN, where RESR_CIN is the ESR of the input capacitor. The input capacitor must be selected to handle the rms current and 15 www.national.com LM3487 The turn-on and turn-off transition times of a MOSFET from the MOSFET specifications require tens of nano-seconds. CRSS and Qg are needed from the MOSFET specifications to estimate the large instantaneous power loss that occurs during these transitions. The average amount of gate current required to turn the MOSFET on can be calculated using the formula: LM3487 Se = fS(VSL + 50x10−6 RSL) 20049290 FIGURE 15. LM3487 Compensation Components Figure 16 shows a bode plot of a typical current mode buck regulator. It is an estimate of the actual plot using the asymptotic approach. The three plots shown are of the compensator, powerstage, and loop gain, which is the product of the power stage, compensator, and feedback gain. The loop gain determines both static and dynamic performance of the converter. The power stage response is fixed by the selection of the power components, therefore the compensator is designed around the powerstage response to achieve a good loop response. Specifically, the compensator is added to increase low frequency magnitude, extend the 0dB frequency (crossover frequency), and improve the phase characteristic. With the power stage known, a compensator can be designed to achieve improved performance and stability. The LM3487 will typically require only a single resistor and capacitor for compensation, but depending on the power stage it could require three or four external components. It is a good idea to check that Q is between 0.15 and 2, if it was not already done when selecting the inductor. If Q is less than 0.15 or greater than 2, skip to the SAMPLING POLE QUALITY FACTOR section below before continuing with the compensator design. First, a target crossover frequency (fc) for the loop gain must be selected. The crossover frequency is the bandwidth of the converter. A higher bandwidth generally corresponds to faster response times and lower overshoots to load transients. However, the bandwidth should not be much higher than 1/10 the switching frequency. The schematic of the LM3487 compensator is shown in Figure 15. The default design uses Rc and CC1 to form a lag (type 2) compensator. The CC2 capacitor can be added to form an additional pole that is typically used to cancel out the ESR zero of the output capacitor. Finally, if extra phase margin is needed, the Cff capacitor can be added (this does not help at low output voltages, see below). The strategy taken here for choosing Rc and CC1 is to set the crossover frequency with Rc, and set the compensator zero with CC1. Using the selected target crossover frequency, fC, set RC to: 200492j4 FIGURE 16. Typical Loop, Compensator, and Power Stage Bode Plots for LM3487 Buck Circuits. Poles, Zeros and Important Measurements are Labeled There are several different types of compensation that can be used to improve the frequency response of the control loop. To determine which compensation scheme to use, some information about the power stage is needed. Use VIN = VIN(MIN) and R = RMIN (IOUT(MAX)) when calculating compensation components. www.national.com fC = Crossover frequency in Hertz (fS/20 - fS/10 is recommended) 16 LM3487 RGM = 50x103Ω GM = 1000x10−6 A/V The compensator zero, fZ1, is set with CC1. When fast transient responses are desired, fZ1 should be placed as high as possible, however it should not be higher than the selected crossover frequency fC. The guideline proposed here is to choose CC1 such that fZ1 falls somewhere between the power pole fP1 and ½ decade before the selected crossover frequency: One can plot the magnitude and phase of the open loop response to analyze the frequency response. Example: Compensation Design 4.5V ≤ VIN ≤ 5.5V VOUT = 2.5V IOUT = 3A (R = 0.83Ω) RSEN = 0.02Ω L = 3.3µH RSL = 0Ω COUT = 100µF RESR = 0.01Ω fs = 500kHz First, calculate the power stage parameters using VIN(MIN) and R(MIN): In this compensation scheme, the pole created by CC2 is used to cancel out the zero created by the ESR of the output capacitor. In other schemes such as the methods discussed in the SAMPLING POLE QUALITY FACTOR subsection, the ESR zero is used. For the typical case, use CC2 if: PLOTTING THE OPEN LOOP RESPONSE The open loop response is expressed as: T = ADC x ACM x H x Fp(s) x Fc(s) Where ADC and H are given above and ACM = GM x RGM In this example, a crossover frequency of 20kHz is chosen, so: fC = 20000. RC is now calculated using the power stage information and the target crossover frequency fC: Selecting RC = 910Ω sets the high frequency gain of the compensator such that a crossover frequency of fC is obtained. The capacitor CC1 sets the compensator zero, fZ2. Set fZ2 between the power pole fP1 and ½ decade before the target crossover frequency fC: Choosing CC1 = 70nF will set fZ2 = fP1, canceling out the power pole and insuring a −20dB/decade slope in the low frequency 17 www.national.com LM3487 18 shows how the power stage bode plot is affected as Q is varied from 0.01 to 10. The resonance is caused by two complex poles at half the switching frequency. If mc is too low, the resonant peaking could become severe coinciding with subharmonic oscillations in the inductor current. If mc is too high, the two complex poles split and the converter begins to act like a voltage mode converter and the compensation scheme used above should be changed. magnitude response. In other words, the phase margin below the crossover frequency will always be higher than the phase margin at the crossover frequency. If better transient response times are desired, set fz2 closer to 1/2 decade before fc (smaller capacitor). This trades more low frequency gain for less phase margin, which translates to faster but more oscillatory step responses. We pick CC1 = 47nF. If the esr zero of the output capacitor (fESR) is too low or if more phase margin is required, additional components may be added to increase the flexibility of the compensator. Use CC2 if fESR < ½ fS, that is if: For this example, fESR = 159 kHz, so use CC2. In general, Cc2 should be kept as small as possible to prevent the gain and phase margins from dropping too low. The equations used here for RC, CC1, and CC2 are approximations valid when CC2 << CC1. For exact equations, see Plotting Open Loop Response earlier in this section. In some cases, the desired inductance is several times higher than the optimal inductance set by the internal slope compensation. This results in a Q lower than 0.15, in which case additional methods of compensating are presented (see SAMPLING POLE QUALITY FACTOR section). 200492j5 FIGURE 18. The Quality Factor Q of the Two Complex Poles is used to qualify how much resonant peaking is observed in the Power Stage Bode Plot If Q>2, the sampling poles are imaginary and are approaching the right half of the imaginary plane (the system is becoming unstable). In this case, Q must be decreased by either increasing the inductance, or more preferably, adding more slope compensation through the RSL resistor (see DEFAULT/ ADJUSTABLE SLOPE COMPENSATION section). If Q<0.15, it means that one of the sampling poles is decreasing in frequency towards the dominant power pole, fp1. There are three ways to compensate for this. Decrease the crossover frequency, add a phase lead network, or use the output capacitor's ESR to cancel out the low frequency sampling pole. One option is to decrease the crossover frequency so that the phase margin is not as severely decreased by the sampling pole. Decreasing the crossover frequency to between 1kHz to 10kHz is advisable here. As a result, there will be a decrease in transient response performance. Another option is the use of the feed-forward capacitor, Cff (see Figure 15. This will provide a positive phase shift (lead) which can be used to increase phase margin. However, it is important to note that the effectiveness of Cff decreases with output voltage. This is due to the fact that the frequencies of the zero fzff and pole fpff get closer together as the output voltage is reduced. The frequency of the feed-forward zero and pole are: 200492j3 FIGURE 17. Open Loop Frequency Response for LM3487 Compensation Design Example SAMPLING POLE QUALITY FACTOR In a current mode control architecture, there is an inherent resonance at half the switching frequency. The LM3487 internally compensates for this by adding a negative slope to the PWM control waveform (see DEFAULT/ADJUSTABLE SLOPE COMPENSATION section). The factor in the power stage equations above, Q, describes how much resonance will be observed. Q is a function of duty cycle and mc. Figure www.national.com 18 LM3487 A third option is to strategically place the ESR zero fESR of the output capacitor to cancel out the sampling pole. In this case, the capacitor CC2 will not be used to cancel out fESR. fESR should be placed around the crossover frequency fc, but this will depend on how low Q is. CURRENT SENSE FILTERING AND LAYOUT High side current sensing like that used in the LM3487 buck circuit is subject to high frequency noise at the turn on of the MOSFET. The noise will appear in the current sense signal and could cause duty cycle jittering. This will produce undesirable spectrum noise. The LM3487 uses a 130 ns blanking time at the beginning of every cycle to ignore this noise, but the noise may be prevalent after the blanking time. Because the noise spike increases with input voltage and load current, duty cycle jitter occurs more commonly at input voltages above 15V and loads above 2A. Current sense filtering is necessary to reduce the noise at the ISEN pin and stabilize the jitter. The schematic in Figure 19 shows the current sense circuit with the recommended RC filter. The layout of the filter components is very important. Grounding should be very good for the input bypass capacitor, and the components at the Vin node should be kept very close together. An example layout is shown in Figure 19. The better the layout, the less delay necessary in the RC filter. The RC time constant of the filter should be in the range of 10ns to 300ns. The resistor in the RC filter should be less than 100 ohm to avoid adding appreciable slope compensation. It is important to keep the RC time constant at a minimum because the delay of the filter has a side effect of increasing the hysteretic threshold current (see PROGRAMMING THE CURRENT LIMIT/HYSTERETIC THRESHOLD section). When creating a PCB layout, a few important guidelines should be followed. First, the switch node should be kept as small as possible. Also, the catch diode, input capacitors, and output capacitors should be grounded to a large ground plane, with the input cap grounded at a point close to the catch diode anode. Keeping the feedback trace short and away from the inductor is also important. See Application Note AN-1229 for more specific information regarding PCB layout. 200492n5 FIGURE 19. Current Sense Filter Schematic and Local Layout Recommendation 19 www.national.com LM3487 Physical Dimensions inches (millimeters) unless otherwise noted 10 Lead Mini SO-10 Package NS Package Number MUB10A www.national.com 20 LM3487 Notes 21 www.national.com LM3487 High Efficiency High-Side N-Channel Controller for Switching Regulator Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2008 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Technical Support Center Email: [email protected] German Tel: +49 (0) 180 5010 771 English Tel: +44 (0) 870 850 4288 National Semiconductor Asia Pacific Technical Support Center Email: [email protected] National Semiconductor Japan Technical Support Center Email: [email protected]