MOTOROLA Order this document by MCM72CF32/D SEMICONDUCTOR TECHNICAL DATA Advance Information 256KB and 512KB BurstRAM Secondary Cache Module for Pentium MCM72CF32 MCM72CF64 160–LEAD CARD EDGE CASE 1113A–01 TOP VIEW 1 The MCM72CF32SG and MCM72CF64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor. The modules are configured as 32K x 72 and 64K x 72 bits in a 160 pin card edge memory module. The module uses four of Motorola’s MCM67C518 or MCM67C618 BiCMOS BurstRAMs. Bursts can be initiated with either address status processor (ADSP) or address status controller (ADSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control. The cache family is designed to interface with popular Pentium cache controllers with on board tag. PD0 – PD2 are reserved for density identification. • Pentium–style Burst Counter on Board 42 43 • Pipelined Data Out • 160 Pin Card Edge Module • Single 5 V ± 5% Power Supply • All Inputs and Outputs are TTL Compatible • Three State Outputs • Byte Parity • Byte Write Capability 80 • Fast Module Clock Rates: 66 MHz • Decoupling Capacitors for each Fast Static RAM • High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes • I/Os are 3.3 V Compatible • Burndy Connector, Part Number: CELP2X80SC3Z48 • Series 20Ω Resistors for Noise Immunity BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp. This document contains information on a new product. Specifications and information herein are subject to change without notice. 5/95 Motorola, Inc. 1995 MOTOROLA FAST SRAM MCM72CF32•MCM72CF64 1 PIN ASSIGNMENT 68–LEAD CARD EDGE MODULE TOP VIEW PD2 PD1 PD0 Cache Size Module VSS VSS NC 256KB 72CF32SG VSS VSS VSS 512KB 72CF64SG PIN NAMES A3 – A18 . . . . . . . . . . . . . . . . . . . . . . Address Inputs K0, K1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock W0 – W7 . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Write E0, E1 . . . . . . . . . . . . . . . . . . . . . . . . Module Enable G0, G1 . . . . . . . . . . . . . . . . . Module Output Enable DQ0 – DQ63 . . . . . . . . . . Cache Data Input/Output DQP0 – DQP7 . . . . . . . . . Data Parity Input/Output ADSC0, ADSC1 . . . . . . Controller Address Status ADSP0, ADSP1 . . . . . . Processor Address Status ADV0, ADV1 . . . . . . . . . . . . . . . . . . . Burst Advance PD0 – PD2 . . . . . . . . . . . . . . . . . . Presence Detect VCC5 . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground * No Connect for MCM72CF32/MCM72CF64 ** No Connect for MCM72CF32 MCM72CF32•MCM72CF64 2 VSS DQ63 VCC5 DQ61 VCC5 DQ59 DQ57 VSS DQP7 DQ55 DQ53 DQ51 VSS DQ49 DQ47 DQ45 DQ43 VSS DQ41 DQP5 DQ39 DQ37 DQ35 VSS DQ33 DQ31 DQ29 DQ27 DQ25 VSS DQP3 DQ23 DQ21 VCC5 DQ19 VSS DQ17 VCC5 DQ15 DQ13 VSS DQ11 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 VSS DQ62 VCC3* DQ60 VCC3* DQ58 DQ56 VSS DQP6 DQ54 DQ52 DQ50 VSS DQ48 DQ46 DQ44 DQ42 VSS DQ40 DQP4 DQ38 DQ36 DQ34 VSS DQ32 DQ30 DQ28 DQ26 DQ24 VSS DQP2 DQ22 DQ20 VCC3* DQ18 VSS DQ16 VCC3* DQ14 DQ12 VSS DQ10 VCC5 DQ9 DQP1 VCC5 DQ7 DQ5 DQ3 DQ1 VSS A3B A4B A5B A6B A7 VSS A9 A11 A13 A15 A17 VSS *A19 PD1 K0 *K2 VSS WE7 WE5 WE3 WE1 VSS ADSC1 E1 ADV1 G1 VCC5 ADSP1 VSS 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VCC3* DQ8 DQP0 VCC3* DQ6 DQ4 DQ2 DQ0 VSS A3A A4A A5A A6A A8 VSS A10 A12 A14 A16 A18** VSS PD0 PD2 K1 K3* VSS WE6 WE4 WE2 WE0 VSS ADSC0 E0 ADV0 G0 VCC3* ADSP0 VSS MOTOROLA FAST SRAM 64K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM MCM67C618 A7 – A18 A3A – A6A 12 4 LW A4 – A15 A0 – A3 W0 8 ADSP0 ADSP DQ0 – DQ7 ADSC0 ADSC DQ8 ADV0 ADV UW K0 K DQ9 – DQ16 G0 G DQ17 E0 E DQ0 – DQ7 DQP0 8 DQ8 – DQ15 DQP1 MCM67C618 LW A4 – A15 A0 – A3 W1 W2 8 ADSP DQ0 – DQ7 ADSC DQ8 UW ADV K DQ9 – DQ16 G DQ17 DQ16 – DQ23 DQP2 8 W3 DQ24 – DQ31 DQP3 E MCM67C618 LW A4 – A15 A3B – A6B 4 A0 – A3 W4 8 ADSP1 ADSP DQ0 – DQ7 ADSC1 ADSC DQ8 ADV1 ADV UW K1 K DQ9 – DQ16 G1 G DQ17 E1 E DQ32 – DQ39 DQP4 8 DQ40 – DQ47 DQP5 MCM67C618 LW A4 – A15 A0 – A3 W5 W6 8 ADSP DQ0 – DQ7 ADSC DQ8 ADV UW K DQ9 – DQ16 G DQ17 DQ48 – DQ55 DQP6 8 W7 DQ56 – DQ63 DQP7 E DQ 0–63 and DQP 0–7 are series terminated with 20Ω resistors. MOTOROLA FAST SRAM MCM72CF32•MCM72CF64 3 32K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM A18 A7 – A17 A3A – A6A NC 11 4 MCM67C518 W0 LW A4 – A14 A0 – A3 8 ADSP0 ADSP DQ0 – DQ7 ADSC0 ADSC DQ8 ADV0 ADV UW K0 K DQ9 – DQ16 G0 G DQ17 E0 E DQ0 – DQ7 DQP0 8 DQ8 – DQ15 DQP1 MCM67C518 LW A4 – A14 A0 – A3 W1 W2 8 ADSP DQ0 – DQ7 ADSC DQ8 UW ADV K DQ9 – DQ16 G DQ17 DQ16 – DQ23 DQP2 8 W3 DQ24 – DQ31 DQP3 E MCM67C518 A4 – A14 A3B – A6B 4 LW A0 – A3 W4 8 ADSP1 ADSP DQ0 – DQ7 ADSC1 ADSC DQ8 ADV1 ADV UW K1 K DQ9 – DQ16 G1 G DQ17 E1 E DQ32 – DQ39 DQP4 8 DQ40 – DQ47 DQP5 MCM67C518 LW A4 – A14 A0 – A3 W5 W6 8 ADSP DQ0 – DQ7 ADSC DQ8 ADV UW K DQ9 – DQ16 G DQ17 DQ48 – DQ55 DQP6 8 W7 DQ56 – DQ63 DQP7 E DQ0–63 and DQP0–7 are series terminated with 20Ω resistors. MCM72CF32•MCM72CF64 4 MOTOROLA FAST SRAM MCM67C618 BLOCK DIAGRAM (See Note) ADV BURST LOGIC INTERNAL ADDRESS Q0 BINARY COUNTER K A0′ A0 Q1 A1′ CLR ADSC ADSP 64K × 18 MEMORY ARRAY 16 A1 2 A1 – A0 ADDRESS REGISTER A0 – A15 A2 – A15 18 16 WRITE REGISTER UW LW 9 DQ9 – DQ17 9 DATA–OUT REGISTERS OUTPUT BUFFER G DQ0 – DQ8 9 DATA–IN REGISTERS ENABLE REGISTER E 9 9 9 NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by asserting ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW). BURST SEQUENCE TABLE (See Note) External Address A15 – A2 A1 A0 1st Burst Address A15 – A2 A1 A0 2nd Burst Address A15 – A2 A1 A0 3rd Burst Address A15 – A2 A1 A0 NOTE: The burst wraps around to its initial state upon completion. MOTOROLA FAST SRAM MCM72CF32•MCM72CF64 5 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3) E ADSP ADSC ADV UW or LW K Address Used Operation H L X X X L–H N/A Deselected H X L X X L–H N/A Deselected L L X X X L–H External Address Read Cycle, Begin Burst L H L X L L–H External Address Write Cycle, Begin Burst L H L X H L–H External Address Read Cycle, Begin Burst X H H L L L–H Next Address Write Cycle, Continue Burst X H H L H L–H Next Address Read Cycle, Continue Burst X H H H L L–H Current Address Write Cycle, Suspend Burst X H H H H L–H Current Address Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K). 3. Wait states are inserted by suspending burst. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) Operation G I/O Status Read L Data Out Read H High–Z Write X High–Z — Data In Deselected X High–Z NOTES: 1. X means Don’t Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 30 mA Power Dissipation PD 6.4 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to +70 °C Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This device contains circuitry that will ensure the output devices are in High–Z at power up. Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Storage Temperature MCM72CF32•MCM72CF64 6 MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC Input High Voltage VIH 4.75 5.25 V 2.2 VCC + 0.3** V Input Low Voltage VIL – 0.5* 0.8 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS AND SUPPLY CURRENTS Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Parameter Ilkg(I) — ± 1.0 µA Output Leakage Current (G = VIH) Ilkg(O) — ± 1.0 µA AC Supply Current (G = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) ICCA66 — 1100 mA AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) ISB1 — 300 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 3.3 V NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible Pentium bus cycles. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Max Unit Input Capacitance (A7 – A18) Cin 20 pF Input Capacitance (A3 – A6, ADSPx, ADSCx, ADVx, Kx, Gx, Ex, Wx) Cin 10 pF Input/Output Capacitance (DQ0 – DQ63, DQP0 – DQP7) CI/O 8 pF MOTOROLA FAST SRAM MCM72CF32•MCM72CF64 7 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) MCM72CF64SG66 Parameter Symbol Min Max Unit Cycle Time tKHKH 15 — ns Clock Access Time tKHQV — 9 ns Output Enable to Output Valid tGLQV — 6 ns Clock High to Output Active tKHQX1 2 — ns Clock High to Output Change tKHQX2 2 — ns Output Enable to Output Active tGLQX 1 — ns Output Disable to Q High–Z tGHQZ 2 6 ns Clock High to Q High–Z tKHQZ — 6 ns Clock High Pulse Width tKHKL 5 — ns Clock Low Pulse Width tKLKH 5 — ns Notes 5 6 Setup Times: Address Address Status Data In Write Address Advance Chip Enable tAVKH tADSVKH tDVKH tWVKH tADVVKH tEVKH 2.5 — ns 7 Hold Times: Address Address Status Data In Write Address Advance Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX 0.5 — ns 7 NOTES: 1. In setup and hold time W (write) refers to either one or both byte write enables LW and UW. 2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP high for the setup and hold times. 3. All read and write cycle timings are referenced from K or G. 4. G is a don’t care when UW or LW is sampled low. 5. Maximum access times are guaranteed for all possible Pentium external bus cycles. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is enabled.Chip enable must be valid at each rising edge of clock for the device (when ADSP or ADSC is low) to remain enabled. AC TEST LOADS +5V 480 Ω OUTPUT OUTPUT Z0 = 50 Ω RL = 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MCM72CF32•MCM72CF64 8 Figure 1B MOTOROLA FAST SRAM MOTOROLA FAST SRAM MCM72CF32•MCM72CF64 9 Q G ADV E LW, UW A ADSC ADSP K t KHQX1 t KHEX t EVKH t KHAX t AVKH t KHADSX A1 t KHQV t ADSVKH t KHKH SINGLE READ Q(A1) t GLQX t GLQV t KHADVX t ADVVKH t WVKH t KHWX A2 t KHADSX t ADSVKH t GHQZ t KHKL t KLKH Q(A2) Q(A2 +1) t KHQX2 t KHQV BURST READ Q(A2 + 2) A3 Q(A2 + 3) Q(A2) Q(A2 +1) (BURST WRAPS AROUND TO ITS INITIAL STATE) ADSP STARTS NEW READ (ADV SUSPENDS BURST) READ CYCLES Q(A3) t KHQZ A4 CHIP DESELECT MCM72CF32•MCM72CF64 10 MOTOROLA FAST SRAM DATA OUT DATA IN G ADV E LW, UW ADDRESS ADSC ADSP K BURST READ Q(An – 1) t EVKH t AVKH t ADSVKH Q(An) A1 A2 t KLKH t KHADSX SINGLE WRITE t GHQZ D(A1) t KHEX D(A2) D(A2 + 1) D(A2 + 3) ADSC STARTS NEW BURST D(A2 + 2) BURST WRITE (WITH A SUSPENDED CYCLE) D(A2 + 1) ADV SUSPENDS BURST W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST t KHAX t ADSVKH t KHKL t KHADSX t KHKH WRITE CYCLES D(A3) t DVKH t ADVVKH t WVKH A3 D(A3 + 2) NEW BURST WRITE D(A3 + 1) t KHDX t KHADVX t KHWX MOTOROLA FAST SRAM MCM72CF32•MCM72CF64 11 Q D G ADV LW, UW A ADSP K t KHQX1 t AVKH t KHAX t ADVSKH t KHADSX A1 READ t KHQV Q(A1) t KHKL A2 D(A2) WRITE t GHQZ t KHDX t DVKH t ADVKH t KHADVX t WVKH t KHWX t KHKH t KLKH t GLQX A3 COMBINATION READ/WRITE CYCLES (E low, ADSC high) Q(A3 + 1) t KHQX2 BURST READ Q(A3) t KHQV Q(A3 + 2) APPLICATION EXAMPLE DATA BUS DATA ADDRESS BUS ADDRESS CLOCK Pentium ADDR CLK ADDR DATA K0 K1 ADSC W MCM67C618FN9 G0 G1 ADSP ADV K CACHE CONTROL LOGIC MCM72CF64SG66 ADS CONTROL 512K Byte Burstable, Secondary Cache Using MCM72CF64SG66 with a 66 MHz Pentium Figure 2 ORDERING INFORMATION (Order by Full Part Number) 72CF32 MCM 72CF64 XX XX Motorola Memory Prefix Speed (66 = 66 MHz) Part Number Package (SG = Gold Pad SIMM) Full Part Numbers — MCM72CF32SG66 MCM72CF64SG66 MCM72CF32•MCM72CF64 12 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 160–LEAD CARD EDGE MODULE CASE 1113A–01 A C NOTE 4 E ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉ COMPONENT AREA FULL R B 80 –Y– VIEW AA 43 2X 42 AC –X– M AB NOTE 5 J –T– FRONT VIEW ÉÉÉ É ÉÉÉ É ÉÉÉ É ÉÉÉ É ÉÉÉ É 160X R W D 0.004 (0.1) 160X 156X L T Y X S 0.012 (0.3) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND V DEFINE A DOUBLE–SIDED MODULE. 5. DIMENSION AB DEFINES OPTIONAL SINGLE–SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. H 160X K G ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ VIEW AA 123 NOTE 6 SIDE VIEW (N) 160 NOTE 4 F L R V P 1 122 COMPONENT AREA BACK VIEW 81 DIM A B C D E F G H J K L M N P R V W AB AC INCHES MIN MAX 4.330 4.350 1.270 1.310 ––– 0.454 0.033 0.037 2.265 2.275 0.075 BSC 0.050 BSC ––– 0.030 0.055 0.069 0.210 ––– 1.955 1.965 2.155 2.165 0.110 REF 0.125 ––– 0.285 0.305 0.157 ––– 0.040 0.060 ––– 0.262 0.072 0.076 MILLIMETERS MIN MAX 109.98 110.49 32.26 33.27 ––– 11.53 0.84 0.94 57.53 57.79 1.91 BSC 1.27 BSC ––– 0.51 1.40 1.75 5.33 ––– 49.66 49.91 54.74 54.99 2.79 REF 3.18 ––– 7.24 7.75 3.99 ––– 1.02 1.52 ––– 6.66 1.83 1.93 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA FAST SRAM MCM72CF32•MCM72CF64 13 Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM72CF32•MCM72CF64 14 ◊ *MCM72CF32/D* MCM72CF32/D MOTOROLA FAST SRAM