MOTOROLA Order this document by MCM62486B/D SEMICONDUCTOR TECHNICAL DATA MCM62486B 32K x 9 Bit BurstRAM Synchronous Static RAM With Burst Counter and Self–Timed Write • Single 5 V ± 10% Power Supply (± 5% for MCM62486BFN11) • Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility • Fast Access Times:11/12/14/19 ns Max and Cycle Times:15/20/25 ns Min • Internal Input Registers (Address, Data, Control) • Internally Self–Timed Write Cycle • ADSP, ADSC, and ADV Burst Control Pins • Asynchronous Output Enable Controlled Three–State Outputs • Common Data Inputs and Data Outputs • High Output Drive Capability: 85 pF per I/O • High Board Density PLCC Package • Fully TTL–Compatible • Active High and Low Chip Select Inputs for Easy Depth Expansion FN PACKAGE 44–LEAD PLCC CASE 777–01 A1 A0 ADV ADSC ADSP K V CC A7 A8 A9 A10 PIN ASSIGNMENT A11 A12 A13 A14 VSS DQ7 DQ6 VSSQ VCCQ DQ5 DQ4 S1 DQ8 V SSQ 6 5 4 3 2 1 44 43 42 41 40 39 7 38 8 37 9 36 10 11 35 12 34 33 13 32 14 15 31 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 W V CC V SS G S0 A2 A3 A4 A5 A6 VSS DQ0 DQ1 VSSQ VCCQ DQ2 DQ3 V SSQ V SS The MCM62486B is a 294,912 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486 and Pentium microprocessors. It is organized as 32,768 words of 9 bits, fabricated with Motorola’s high–performance silicon–gate CMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 – A14), data inputs (D0 – D8), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. Bursts can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM62486B (burst sequence imitates that of the i486 and Pentium) and controlled by the burst address advance (ADV) input pin. The following pages provide more detailed information on burst controls. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased flexibility for incoming signals. The MCM62486B will be available in a 44–pin plastic leaded chip carrier (PLCC). Multiple power and ground pins have been utilized to minimize effects induced by output noise. Separate power and ground pins have been employed for DQ0 – DQ8 to allow user–controlled output levels of 5 volts or 3.3 volts. PIN NAMES A0 – A14 . . . . . . . . . . . . . . . . Address Inputs K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable S0, S1 . . . . . . . . . . . . . . . . . . . . Chip Selects ADV . . . . . . . . . . . . Burst Address Advance ADSP, ADSC . . . . . . . . . . . . Address Status DQ0 – DQ8 . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VCCQ . . . . . . . Output Buffer Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground VSSQ . . . . . . . . . . . . Output Buffer Ground All power supply and ground pins must be connected for proper operation of the device. VCC ≥ VCCQ at all times including power up. BurstRAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp. REV 2 5/95 Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM62486B 1 BLOCK DIAGRAM (See Note) ADV BURST LOGIC INTERNAL A0′ ADDRESS Q0 BINARY COUNTER K A0 A1′ Q1 A1 CLR ADSC ADSP 32K x 9 MEMORY ARRAY 15 2 A0 – A14 15 ADDRESS REGISTER A1 – A0 A2 – A14 WRITE REGISTER W S0 S1 9 9 DATA–IN REGISTERS ENABLE REGISTER OUTPUT BUFFER G DQ0 – DQ8 9 NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip selects (S0, S1) are sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. BURST SEQUENCE TABLE (See Note) External Address A14 – A2 A1 A0 1st Burst Address A14 – A2 A1 A0 2nd Burst Address A14 – A2 A1 A0 3rd Burst Address A14 – A2 A1 A0 NOTE: The burst wraps around to its initial state upon completion. MCM62486B 2 MOTOROLA FAST SRAM SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4) S ADSP ADSC ADV W K Address Used Operation F L X X X L–H N/A Deselected F X L X X L–H N/A Deselected T L X X X L–H External Address Read Cycle, Begin Burst T H L X L L–H External Address Write Cycle, Begin Burst T H L X H L–H External Address Read Cycle, Begin Burst X H H L L L–H Next Address Write Cycle, Continue Burst X H H L H L–H Next Address Read Cycle, Continue Burst X H H H L L–H Current Address Write Cycle, Suspend Burst X H H H H L–H Current Address Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K). 3. S represents S0 and S1. T implies S1 = L and S0 = H; F implies S1 = H or S0 = L. 4. Wait states are inserted by suspending burst. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) Operation G I/O Status Read L Data Out (DQ0 – DQ8) Read H High–Z Write X High–Z — Data In (DQ0 – DQ8) Deselected X High–Z NOTES: 1. X means Don’t Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0) Rating Power Supply Voltage Output Power Supply Voltage Symbol Value Unit VCC – 0.5 to 7.0 V VCCQ – 0.5 to VCC V Voltage Relative to VSS Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 20 mA Power Dissipation PD 1.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. Storage Temperature Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MOTOROLA FAST SRAM MCM62486B 3 DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC, VCCQ = 5.0 V ± 5%, TA = 0 to + 70°C, for device MCM62486B–11) (VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, for all other devices) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Parameter Supply Voltage (Operating Voltage Range) Output Buffer Supply Voltage (5.0 V TTL Compatible) (3.3 V 50 Ω Compatible) Symbol Min Max Unit VCC 4.5 5.5 V 4.5 3.0 5.5 3.6 VCCQ V Input High Voltage VIH 2.2 VCC + 0.3 V Input Low Voltage VIL – 0.5* 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ± 1.0 µA Output Leakage Current (G, S1 = VIH, S0 = VIL, Vout = 0 to VCCQ) Ilkg(O) — ± 1.0 µA AC Supply Current (G, S1 = VIL, S0 = VIH, All Inputs = VIL = 0.0 V and VIH ≥ 3.0 V, Iout = 0 mA, Cycle Time ≥ tKHKH min) ICCA — 160 mA Standby Current (S1 = VIH, S0 = VIL, All Inputs = VIL and VIH, Cycle Time ≥ tKHKH min) ISB1 — 50 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V * VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium bus cycles. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic Symbol Typ Max Unit Input Capacitance (All Pins Except DQ0 – DQ8) Cin 2 3 pF Input/Output Capacitance (DQ0 – DQ8) CI/O 7 8 pF MCM62486B 4 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC, VCCQ = 5.0 V ± 5%, TA = 0 to + 70°C, for device MCM62486B–11) (VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, for all other devices) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) 62486B–11 62486B–12 62486B–14 62486B–19 Symbol Min Max Min Max Min Max Min Max Unit Cycle Time tKHKH 15 — 20 — 20 — 25 — ns Clock Access Time tKHQV — 11 — 12 — 14 — 19 ns Output Enable Access tGLQV — 5 — 5 — 6 — 7 ns Clock High to Output Active tKHQX1 6 — 6 — 6 — 6 — ns Clock High to Q Change tKHQX2 3 — 3 — 4 — 4 — ns Output Enable to Q Active tGLQX 0 — 0 — 0 — 0 — ns Output Disable to Q High–Z tGHQZ — 6 — 6 — 6 — 7 ns Clock High to Q High–Z tKHQZ — 6 — 6 — 6 — 6 ns Clock High Pulse Width tKHKL 5.5 — 7 — 8 — 6 — ns Parameter Clock Low Pulse Width Notes 4 tKLKH 5.5 — 7 — 8 — 6 — ns Setup Times: Address Address Status Data In Write Address Advance Chip Select tAVKH tADSVKH tDVKH tWVKH tADVVKH tS0VKH tS1VKH 2 — 2 — 3 — 3 — ns 5 Hold Times: Address Address Status Data In Write Address Advance Chip Select tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHS0X tKHS1X 2 — 2 — 2 — 2 — ns 5 NOTES: 1. A read cycle is defined by W high or ADSP low for the setup and hold times. A write cycle is defined by W low and ADSP high for the setup and hold times. 2. All read and write cycle timings are referenced from K or G. 3. G is a don’t care when W is sampled low. 4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of clock (K) whenever ADSP and ADSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is selected.Chip select must be true (S1 low and S0 high) at each rising edge of clock for the device (when ADSP or ADSC is low) to remain enabled. Timings for S1 and S0 are similar. AC TEST LOADS +5V RL = 50 Ω OUTPUT 480 Ω OUTPUT Z0 = 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MOTOROLA FAST SRAM Figure 1B MCM62486B 5 MCM62486B 6 MOTOROLA FAST SRAM t S1VKH t AVKH t ADSVKH t GLQX A1 SINGLE READ Q(A1) t KHQV t GLQV t KHS1X t KHAX t KHKL t KHKH t GHQZ Q(A2) t KHQX2 t ADVVKH t WVKH A2 t ADSVKH t KLKH Q(A2+1) t KHQV t KHADVX t KHWX t KHADSX BURST READ Q(A2+2) Q(A2+3) Q(A2) (BURST WRAPS AROUND TO ITS INITIAL STATE) (ADV SUSPENDS BURST) NOTE: Q(A2) represents the first output data from the base address A2; Q(A2+1) represents the next output data in the burst sequence with A2 as the base address. DATA OUT G ADV S1 (S0 = VIH) W ADDRESS ADSC ADSP K t KHADSX READ CYCLES Q(A2+1) Q(A2+2) t KHQZ MOTOROLA FAST SRAM MCM62486B 7 DATA OUT DATA IN G ADV S0 (S1 = VIL ) W ADDRESS ADSC ADSP K BURST READ Q(An–1) t SOVKH t AVKH t ADSVKH Q(An) A1 A2 t KHADSX t KLKH SINGLE WRITE t GHQZ D(A) t KHSOX D(A2) BURST WRITE D(A2+1) (WITH A SUSPENDED CYCLE) D(A2+1) ADV SUSPENDS BURST W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST t KHAX t ADSVKH t KHKL t KHADSX t KHKH WRITE CYCLES D(A2+2) D(A2+3) ADSC STARTS NEW BURST D(A3) t DVKH t ADVVKH t WVKH A3 D(A3+2) NEW BURST WRITE D(A3+1) t KHDX t KHADVX t KHWX MCM62486B 8 MOTOROLA FAST SRAM DATA OUT DATA IN G ADV W ADDRESS ADSP K t KHQX1 t KHQV t AVKH t ADSVKH A1 t KHAX Q(A1) READ t KHADSX t KHKL t WVKH t GHQZ t DVKH t ADVVKH A2 t KHKH WRITE D(A2) t KLKH t GLQX t KHDX t KHADVX t KHWX A3 t GLQV Q(A3) COMBINATION READ/WRITE CYCLE (E low, ADSC high) BURST READ Q(A3+1) t KHQX2 Q(A3+2) APPLICATION EXAMPLE DATA BUS DATA ADDRESS BUS ADDRESS 15 36 CLOCK i486DX4 CLK ADDR ADDR K CACHE CONTROL LOGIC ADSC K DATA MCM62486B W G ADV ADSP ADS CONTROL 128K Byte Burstable, Secondary Cache Using 4 MCM62486BFN19s With a 100 MHz i486DX4 MOTOROLA FAST SRAM MCM62486B 9 ORDERING INFORMATION (Order by Full Part Number) MCM 62486B XX XX Motorola Memory Prefix Speed (11 = 11 ns, 12 = 12 ns, 14 = 14 ns, 19 = 19 ns) Part Number Package (FN = PLCC) Full Part Numbers — MCM62486BFN11 MCM62486BFN12 MCM62486BFN14 MCM62486BFN19 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MCM62486B 10 MOTOROLA FAST SRAM PACKAGE DIMENSIONS FN PACKAGE 44–LEAD PLCC CASE 777–02 B Y BRK -N- 0.18 (0.007) D -L- T L –M 0.18 (0.007) M N S T L –M S S N S -M- 44 LEADS ACTUAL Z W D 1 44 U M V A 0.18 (0.007) M T L –M S N S R 0.18 (0.007) M T L –M S N S G1 0.25 (0.010) X VIEW D-D S T L –M N S S Z H C 0.18 (0.007) M T L –M S N S E 0.10 (0.004) G -T- J SEATING PLANE K1 K VIEW S G1 0.25 (0.010) S T L –M MOTOROLA FAST SRAM S N S NOTES: 1. DUE TO SPACE LIMITATION, CASE 777-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 44 LEADS. 2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.25 (0.010) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO .012 (.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 8. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN .037 (.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN .025 (.635). 9. 777-01 IS OBSOLETE, NEW STANDARD 777-02. F 0.18 (0.007) M T L –M S N S VIEW S DIM A B C E F G H J K R U V W X Y Z G1 K1 MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 15.50 16.00 1.02 — INCHES MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.610 0.630 0.040 — MCM62486B 11 Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM62486B 12 ◊ *MCM62486B/D* MCM62486B/D MOTOROLA FAST SRAM