SN54HC684, SN74HC684 8-BIT MAGNITUDE COMPARATORS SCLS340B – MARCH 1996 – REVISED MARCH 2003 D D D D D D D Wide Operating Voltage Range of 2 V to 6 V High-Current Outputs Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 22 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Compare Two 8-Bit Words SN54HC684 . . . FK PACKAGE (TOP VIEW) 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4 P1 Q1 P2 Q2 P3 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Q7 P7 Q6 P6 Q5 Q3 GND P4 Q4 P5 P>Q P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND Q0 P0 P>Q VCC P=Q SN54HC684 . . . J OR W PACKAGE SN74HC684 . . . DW OR N PACKAGE (TOP VIEW) description/ordering information These magnitude comparators perform comparisons of two 8-bit binary or BCD words. These devices provide P = Q and P > Q outputs. ORDERING INFORMATION PDIP – N –40°C to 85°C –55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING Tube SN74HC684N Tube SN74HC684DW Tape and reel SN74HC684DWR CDIP – J Tube SNJ54HC684J SNJ54HC684J CFP – W Tube SNJ54HC684W SNJ54HC684W LCCC – FK Tube SNJ54HC684FK SNJ54HC684FK SOIC – DW SN74HC684N HC684 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE DATA INPUTS P, Q OUTPUTS P=Q P>Q P=Q L H P>Q H L P<Q H H The P < Q function can be generated by applying P = Q and P > Q to a 2-input NAND gate. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC684, SN74HC684 8-BIT MAGNITUDE COMPARATORS SCLS340B – MARCH 1996 – REVISED MARCH 2003 logic diagram (positive logic) 19 P0 Q0 P1 Q1 P2 Q2 P3 Q3 P4 Q4 P5 Q5 P6 Q6 P7 Q7 2 P=Q 2 3 4 5 6 7 8 9 11 12 1 13 14 15 16 17 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P>Q SN54HC684, SN74HC684 8-BIT MAGNITUDE COMPARATORS SCLS340B – MARCH 1996 – REVISED MARCH 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC684 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tt Low-level input voltage MAX 2 5 6 MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 0 Output voltage Input transition (rise and fall) times NOM VCC = 4.5 V VCC = 6 V Input voltage SN74HC684 MIN 0 VCC = 2 V VCC = 4.5 V VCC = 6 V 0.5 1.35 1.35 1.8 1.8 0 0 V V 0.5 VCC VCC UNIT VCC VCC 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HC684, SN74HC684 8-BIT MAGNITUDE COMPARATORS SCLS340B – MARCH 1996 – REVISED MARCH 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –20 µA VOH VI = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA IIH IIL VI = VCC VI = 0 ICC Ci VI = VCC or 0, IO = 0 MIN TA = 25°C TYP MAX SN54HC684 MIN MAX SN74HC684 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.30 3.7 3.84 6V 5.48 5.80 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 6V –0.1 –100 –1000 –1000 nA 8 160 80 µA 10 10 10 pF 6V 2 V to 6 V 3 V nA switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN TYP MAX 2V 130 275 413 344 tpd P or Q Any 4.5 V 26 55 88 69 6V 22 47 70 58 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 tt Any SN54HC684 MIN MAX SN74HC684 MIN MAX UNIT ns ns operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TEST CONDITIONS TYP UNIT No load 40 pF SN54HC684, SN74HC684 8-BIT MAGNITUDE COMPARATORS SCLS340B – MARCH 1996 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr tPHL VCC 50% 10% 0 V Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74HC684DW ACTIVE SOIC DW 20 SN74HC684DWR ACTIVE SOIC DW SN74HC684DWRE4 ACTIVE SOIC SN74HC684N ACTIVE SN74HC684NE4 ACTIVE 25 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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