SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
•
•
•
•
•
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
S1
SL
QH′
H/QH
F/QF
D/QD
B/QB
CLK
SR
SN54ALS323 . . . FK PACKAGE
(TOP VIEW)
description
These 8-bit universal shift /storage registers
feature multiplexed input/output (I/O) ports to
achieve full 8-bit data handling in a 20-pin
package. Two function-select (S0, S1) inputs and
two output-enable (OE1, OE2) inputs can be used
to choose the modes of operation listed in the
function table.
G/QG
E/QE
C/QC
A/QA
QA′
S1
•
S0
OE1
OE2
G/QG
E/QE
C/QC
A/QA
QA′
CLR
GND
OE2
OE1
S0
VCC
•
SN54ALS323 . . . J PACKAGE
SN74ALS323 . . . DW OR N PACKAGE
(TOP VIEW)
Multiplexed I/O Ports Provide Improved Bit
Density
Four Modes of Operation:
− Hold (Store)
− Shift Right
− Shift Left
− Load Data
Operate With Outputs Enabled or at High
Impedance
3-State Outputs Drive Bus Lines Directly
Can Be Cascaded for n-Bit Word Lengths
Synchronous Clear
Applications:
− Stacked or Push-Down Registers
− Buffer Storage
− Accumulator Registers
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
SL
QH′
H/QH
F/QF
D/QD
CLR
GND
SR
CLK
B/Q B
•
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs
in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading
out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs
synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but has
no effect on clearing, shifting, or storing data.
The SN54ALS323 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ALS323 is characterized for operation from 0°C to 70°C.
Copyright 1994, Texas Instruments Incorporated
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
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1
SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
FUNCTION TABLE
INPUTS
MODE
I/O PORTS
OE2†
OUTPUTS
CLR
S1
S0
OE1†
CLK
SL
SR
A/QA
B/QB
C/QC
D/QD
QA′
QH′
Clear
L
X
H
L
L
X
L
L
X
↑
↑
↑
X
X
X
X
X
X
L
L
X
L
L
X
L
L
X
L
L
X
F/QF
L
L
X
H/QH
X
L
H
E/QE
L
L
X
G/QG
L
L
L
L
L
X
L
L
X
L
L
L
L
L
L
Hold
H
H
L
X
L
X
L
L
L
L
X
L
X
X
X
X
QA0
QA0
QB0
QB0
QC0
QC0
QD0
QD0
QE0
QE0
QF0
QF0
QG0
QG0
QH0
QH0
QA0
QA0
QH0
QH0
Shift
Right
H
H
L
L
H
H
L
L
L
L
↑
↑
X
X
H
L
H
L
QAn
QAn
QBn
QBn
QCn
QCn
QDn
QDn
QEn
QEn
QFn
QFn
QGn
QGn
H
L
QGn
QGn
Shift
Left
H
H
H
H
L
L
L
L
L
L
↑
↑
H
L
X
X
QBn
QBn
QCn
QCn
QDn
QDn
QEn
QEn
QFn
QFn
QGn
QGn
QHn
QHn
H
L
QBn
QBn
H
L
Load
H
H
H
X
X
↑
X
X
a
b
c
d
e
f
g
h
a
h
NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs
are isolated from the I/O terminals.
† When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
logic symbol‡
9
CLR
OE1
2
SRG8
4R
&
3
3EN13
OE2
S0
S1
CLK
SR
1
19
0
1
M
0
3
12
C4/1→/2←
11
7
A /QA
8
1,4D
Z5
5, 13
B/QB
13
3, 4D
Z6
6, 13
C/QC
D/QD
E/QE
F/QF
G/QG
H/QH
SL
6
14
5
15
4
16
18
3, 4D
Z12
12, 13
17
QH′
2, 4D
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
QA′
3,4D
•
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•
SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
logic diagram (positive logic)
CLR
S0
S1
SR
(shift right
serial input)
CLK
9
1
19
18
11
Six
Identical
Channels
Not
Shown†
12
1D
1D
C1
QA′
OE1
OE2
SL
(shift left
serial input)
C1
17
8
QH′
2
3
7
16
A/QA
H/QH
† I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA: SN54ALS323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
SN74ALS323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
•
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•
3
SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
recommended operating conditions
SN54ALS323
VCC
VIH
Supply voltage
VIL
Low-level input voltage
High-level input voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
SN74ALS323
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
2
2
0.7
0.8
−0.4
QA thru QH
−1
−2.6
QA′ or QH′
QA thru QH
4
8
12
24
−55
125
V
V
−0.4
QA′ or QH′
UNIT
0
70
V
mA
mA
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V
VCC = 4.5 V
IOL = 4 mA
IOL = 8 mA
0.25
QA′
A or QH′
H
0.25
VCC = 4.5 V
IOL = 12 mA
IOL = 24 mA
VCC = 5.5 V
VI = 5.5 V
VI = 7 V
VCC = 5.5 V,
VI = 2.7 V
Any others
IIH‡
ICC
−1.5
QA thru QH
A thru H
IOS§
−1.5
IOH = − 1 mA
IOH = − 2.6 mA
QA thru QH
IIL‡
SN74ALS323
MIN TYP†
MAX
II = − 18 mA
IOH = − 0.4 mA
VOL
II
SN54ALS323
MIN TYP†
MAX
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
Any output
VOH
TEST CONDITIONS
VCC − 2
2.4
QA′ or QH′
QA thru QH
VCC = 5.5 V,
VI = 0.4 V
VCC = 5.5 V,
VO = 2.25 V
VCC = 5.5 V
V
VCC − 2
3.3
V
2.4
S0, S1, SR, SL
Any others
UNIT
0.4
0.4
3.2
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
0.1
0.1
0.1
0.1
20
20
−0.2
−0.2
−0.1
−0.1
−15
−70
−15
−70
−20
−112
−30
−112
Outputs high
15
28
15
28
Outputs low
22
38
22
38
V
mA
µA
mA
mA
mA
Outputs disabled
23
40
23
40
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54ALS323
fclock
tw
tsu
Clock frequency (at 50% duty cycle)
Pulse duration
Inactive-state setup time before CLK↑†
th
Hold time after CLK↑
MAX
0
17
SN74ALS323
MIN
MAX
0
17
CLK high or low
22
16.5
S0 or S1
25
20
High
18
16
Low
15
6
CLR active
25
20
CLR
18
16
S0 or S1
0
0
Serial or parallel data
0
0
Serial or parallel data
Setup time before CLK↑
MIN
UNIT
MHz
ns
ns
ns
† Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX‡
SN54ALS323
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
SN74ALS323
MAX
17
CLK
QA thru QH
CLK
QA
A′ or QH
H′
OE1, OE2
QA thru QH
S0, S1
QA thru QH
OE1, OE2
QA thru QH
•
•
MIN
MAX
17
MHz
2
19
4
13
4
25
7
19
2
21
5
15
4
25
8
18
5
22
6
16
6
27
8
22
5
27
7
17
6
27
8
22
1
15
1
8
4
38
5
15
1
12
8
25
1
16
S0, S1
QA thru QH
tPLZ
4
34
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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UNIT
ns
ns
ns
ns
ns
ns
5
SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
From Output
Under Test
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
3.5 V
Input
tPZH
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
VOL
0.3 V
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
1.3 V
1.3 V
[3.5 V
1.3 V
tPHZ
Waveform 2
S1 Open
(see Note B)
1.3 V
VOH
Out-of-Phase
Output
(see Note C)
0.3 V
[0 V
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
•
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•
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
83021022A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
83021022A
SNJ54ALS
323FK
8302102RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8302102RA
SNJ54ALS323J
8302102SA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
8302102SA
SNJ54ALS323W
SN74ALS323N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74ALS323N
SN74ALS323N3
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
0 to 70
SN74ALS323NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SNJ54ALS323FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
83021022A
SNJ54ALS
323FK
SNJ54ALS323J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8302102RA
SNJ54ALS323J
SNJ54ALS323W
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
8302102SA
SNJ54ALS323W
SN74ALS323N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS323, SN74ALS323 :
• Catalog: SN74ALS323
• Military: SN54ALS323
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
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