SCBS303C − DECEMBER 1993 − REVISED JANUARY 1996
D State-of-the-Art Advanced BiCMOS
D
D
D
D
D
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
SN54LVTZ245 . . . FK PACKAGE
(TOP VIEW)
A3
A4
A5
A6
A7
description
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
B1
B2
B3
B4
B5
A8
GND
B8
B7
B6
These octal bus transceivers are designed
specifically for low-voltage (3.3-V) VCC operation,
but with the capability to provide a TTL interface
to a 5-V system environment.
OE
D
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
High-Impedance State During Power Up
and Power Down
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs
A2
A1
DIR
VCC
D
SN54LVTZ245 . . . J PACKAGE
SN74LVTZ245 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the devices so the buses are effectively
isolated.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVTZ245 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVTZ245 is characterized for operation over the full military temperature range of − 55°C to 125°C.
The SN74LVTZ245 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#'
+&%#$ %! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$
$#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+'
#'$#0 "** (""!'#'$
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1
SCBS303C − DECEMBER 1993 − REVISED JANUARY 1996
logic symbol†
OE
DIR
A1
19
1
2
logic diagram (positive logic)
G3
DIR
1
3EN1[BA]
3EN2[AB]
19
18
1
B1
A1
OE
2
2
A2
A3
A4
A5
A6
A7
A8
3
17
4
16
5
15
6
14
7
13
8
12
9
11
B2
18
B3
B1
B4
B5
B6
B7
To Seven Other Channels
B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, PW, and J packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . −0.5 V to 7 V
Current into any output in the low state, IO: SN54LVTZ245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTZ245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVTZ245 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTZ245 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
2
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•
SCBS303C − DECEMBER 1993 − REVISED JANUARY 1996
recommended operating conditions (see Note 4)
SN54LVTZ245
SN74LVTZ245
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
0.8
Input voltage
5.5
5.5
V
IOH
IOL
High-level output current
−24
−32
mA
48
64
mA
∆t /∆v
Input transition rise or fall rate
10
10
ns / V
∆t /∆VCC
Power-up ramp rate
High-level input voltage
2
Low-level output current
Outputs enabled
2
200
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
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•
−55
V
−40
V
µs / V
200
125
V
85
°C
3
SCBS303C − DECEMBER 1993 − REVISED JANUARY 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
SN54LVTZ245
TYP†
MAX
TEST CONDITIONS
VCC = 2.7 V,
VCC = MIN to MAX‡,
II = −18 mA
IOH = −100 µA
VCC = 2.7 V,
IOH = − 8 mA
IOH = − 24 mA
VCC = 3 V
VCC = 2.7 V
VOL
VCC = 3 V
VCC = 3.6 V,
VCC = 0 or MAX‡,
II
MIN
−1.2
VCC −0.2
2.4
2
0.2
0.2
IOL = 24 mA
IOL = 16 mA
0.5
0.5
0.4
0.4
IOL = 32 mA
IOL = 48 mA
0.5
0.5
IOL = 64 mA
VI = VCC or GND
VI = 5.5 V
VI = 5.5 V
0.55
Control inputs
A or B ports§
VCC = 0,
VCC = 0 to 1.5 V,
VI or VO = 0 to 4.5 V
VO = 0.5 V to 3 V, OE = X
VCC = 1.5 V to 0,
II(hold)
VCC = 3 V
VO = 0.5 V to 3 V,
VI = 0.8 V
IOZH
IOZL
VCC = 3.6 V,
VCC = 3.6 V,
±1
10
100
20
5
5
A or B ports
75
75
−75
−75
µA
± 50
µA
± 50
µA
−1
1
µA
−1
µA
Outputs high
0.13
0.5
0.13
0.225
Outputs low
8.8
17
8.8
15
0.13
0.5
0.13
0.225
VCC = 3 V to 3.6 V,
One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
0.3
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•
0.2
mA
mA
4
4
pF
10
10
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ Unused terminals at VCC or GND
¶ This parameter is specified by characterization but is not production tested.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
4
± 100
µA
A
1
Outputs
disabled
µA
−10
OE = X
∆ICC#
Cio
±1
10
−10
VO = 0.5 V
IO = 0,
V
0.55
Ioff
IOZPU¶
IOZPD¶
VI = 2 V
VO = 3 V
V
V
IOH = − 32 mA
IOL = 100 µA
VI = VCC
VI = 0
VCC = 3.6 V,
VI = VCC or GND
−1.2
UNIT
VCC −0.2
2.4
2
VCC = 3.6 V
ICC
SN74LVTZ245
TYP†
MAX
MIN
SCBS303C − DECEMBER 1993 − REVISED JANUARY 1996
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTZ245
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
SN74LVTZ245
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
MAX
MIN
1
1
VCC = 3.3 V
± 0.3 V
TYP†
VCC = 2.7 V
MAX
MIN
MAX
MIN
4.6
5.3
1
2.5
4
5.2
4.1
5.7
1
2.5
4
5.5
1.1
6.1
7.2
1.1
3.3
5.9
7.1
1.5
6.6
8
1.5
3.8
6.5
7.9
2.2
6.2
7
2.2
4.3
5.9
6.5
2
5.7
5.9
2
3.9
5.5
5.6
UNIT
MAX
ns
ns
ns
† All typical values are at VCC = 3.3 V, TA = 25°C.
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5
SCBS303C − DECEMBER 1993 − REVISED JANUARY 1996
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
500 Ω
2.7 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
0V
tw
tsu
2.7 V
Input
1.5 V
th
2.7 V
1.5 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
Input
0V
1.5 V
1.5 V
VOL
tPLH
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
Output
1.5 V
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 6 V
(see Note B)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
2.7 V
Output
Control
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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•
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
SN74LVTZ245DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
SN74LVTZ245DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74LVTZ245DWR
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74LVTZ245PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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