19-5669; Rev 2; 12/11 73S8014BN Smart Card Interface DS_8014BN_057 DESCRIPTION APPLICATIONS The 73S8014BN is a single smart card (ICC) interface circuit designed to provide full electrical compliance with ISO 7816-3, EMV® 4.2, and NDS specifications. It is derived from the 73S8024RN industry-standard electrical interface, but adds support for 1.8V smart card applications. The 73S8014BN has been optimized to match set-top box/A/V conditional access applications. The optimization adds functionality while creating a device with a smaller pin count. For NDS applications requiring an on-chip adjustable POR, see the Maxim 73S8024RN series of interface ICs. • • The 73S8014BN interfaces with the host processor through the same bus (digital I/Os) as the 73S8024RN and most other 8024 type devices. As a result, the 73S8014BN is a very attractive cost-reduction path from traditional 8024 ICs. Interfacing with the system controller is done through a control bus, composed of digital inputs to control the 73S8014BN, and one interrupt output to inform the system controller of the card presence, device readiness and faults. The card clock can be generated by an on-chip oscillator using an external crystal or by connection to an externally supplied clock signal. In addition, the clock divider provides divisor values of divide by 1, 2, 4, and 8 that are controlled through a single pin. The 73S8014BN incorporates an ISO 7816-3 activation/deactivation sequencer that controls the card signals. Level-shifters drive the card signals with the selected card voltage (1.8V, 3V, or 5V), coming from an internal low dropout (LDO) voltage regulator. This LDO regulator is powered by a dedicated power-supply input, VPC. Digital circuitry is powered separately by a digital power supply, VDD. With its embedded LDO regulator, the 73S8014BN is a costeffective solution for any application where a 5V (typically -5% +10%) power supply is available. Emergency card deactivation is initiated upon card extraction or upon any fault detected by the protection circuitry. The fault can be a card overcurrent, VCC undervoltage, or power-supply fault (VDD). The card overcurrent circuitry is a true currentdetection function, as opposed to VCC voltage drop detection, as usually implemented in non-Maxim 8024 interface ICs. The 73S8014BN contains a power-down mode with typical power consumption of 1µA on each of the VDD and VPC supplies. The power-down mode is controlled through existing control pins without the need for a dedicated control pin. Set-Top Box Conditional Access and Pay-per-View General-Purpose Smart Card Readers ADVANTAGES • • • • • • NDS Compliant Same Advantages as the Maxim 73S80xxR Family: Card VCC Generated by an LDO Regulator Very Low Power Dissipation (Saves Up to 1/2W) Fewer External Components Are Required Better Noise Performance True Card Overcurrent Detection Firmware Compatibility with 8024 ICs Small-Format 20-Pin SO Package Capable of Fully Supporting NDS Applications Power-Down Mode FEATURES • Card Interface Complies with ISO 7816-3, EMV 4.2, and NDS Supports 3V/5V Cards Up to 65mA and 1.8V Cards Up to 40mA ISO 7816-3 Activation/Deactivation Sequencer Automated Deactivation Upon Hardware Fault (i.e., Upon Drop on VDD Power Supply or Card Overcurrent) Overcurrent Detection 145mA max Card CLK Clock Frequency Up to 20MHz • System Controller Interface Three Digital Inputs Control the Card Activation/Deactivation, Card Reset, Power-Down, and Card Voltage One Digital Input Controls the Card Clock Frequency One Digital Output, Interrupt to the System Controller, Reports to the Host the Card Presence, Device Readiness, and Faults Crystal Oscillator or Host Clock, Up to 27MHz • Regulator Power Supply 4.75V to 5.5V (EMV 4.2) 4.85V to 5.5V (NDS) • Digital Interfacing: 2.7V to 3.6V • • • ±6kV ESD Protection on the Card Interface 20-Pin SO Package RoHS-Compliant (6/6)/Lead(Pb)-Free Package EMV is a registered trademark of EMVCo LLC. Rev. 2 1 73S8014BN Data Sheet DS_8014BN_057 FUNCTIONAL DIAGRAM VDD VPC vdd circuits VOLTAGE and CURRENT REFERENCES VDD FAULT vref bias currents POWER DOWN CMDVCC LDO REGULATOR VCC CONTROL CONTROLLER AND FAULT LOGIC RSTIN 5V#V GND VCC FAULT VCC RESET BUFFER RST CLOCK BUFFER CLK OFF R-C OSC. CKDIV XTALIN/ CLKIN XTAL OSC CLOCK GENERATION 1.5MHz SC SEQUENCER VDD CKT PRES CLOCK XTALOUT vdd circuits I/OUC C4UC SMART CARD SIGNAL CONTROL and LEVEL SHIFTERS I/O C4 C8 C8UC vcc circuits Figure 1: 73S8014BN Block Diagram 2 Rev. 2 DS_8014BN_057 73S8014BN Data Sheet Table of Contents 1 2 Pinout.............................................................................................................................................................. 5 Electrical Specifications................................................................................................................................. 8 2.1 Absolute Maximum Ratings ...................................................................................................................... 8 2.2 Recommended Operating Conditions ....................................................................................................... 8 2.3 Smart Card Interface Requirements ......................................................................................................... 9 2.4 Digital Signals Characteristics ................................................................................................................ 11 2.5 DC Characteristics ................................................................................................................................. 12 2.6 Voltage Fault-Detection Circuits ............................................................................................................. 12 3 Applications Information.............................................................................................................................. 13 3.1 Example 73S8014BN Schematics .......................................................................................................... 13 3.2 System Controller Interface .................................................................................................................... 15 3.3 Power-Down Mode ................................................................................................................................. 15 3.4 Power Supply and Voltage Supervision .................................................................................................. 16 3.5 Card Power Supply ................................................................................................................................ 16 3.6 On-Chip Oscillator and Card Clock ......................................................................................................... 17 3.7 Activation Sequence............................................................................................................................... 18 3.8 Deactivation Sequence........................................................................................................................... 19 3.9 Fault Detection and OFF......................................................................................................................... 20 3.10 I/O, C4, and C8 Circuitry and Timing ...................................................................................................... 20 4 Equivalent Circuits ....................................................................................................................................... 22 5 Mechanical Drawing ..................................................................................................................................... 27 6 Ordering Information .................................................................................................................................... 28 7 Contact Information ..................................................................................................................................... 28 Revision History .................................................................................................................................................. 29 Rev. 2 3 73S8014BN Data Sheet DS_8014BN_057 Figures Figure 1: 73S8014BN Block Diagram ....................................................................................................................2 Figure 2: 73S8014BN 20-SO Pinout ......................................................................................................................5 Figure 3: 73S8014BN—Typical Application Schematic ........................................................................................ 14 Figure 4: Power-Down Mode and PRES Debounce .............................................................................................16 Figure 5: CLKDIV Usage .....................................................................................................................................17 Figure 6: Activation Sequence—RSTIN Low When CMDVCC Goes Low ............................................................. 18 Figure 7: Activation Sequence—RSTIN High When CMDVCC Goes Low ............................................................ 19 Figure 8: Deactivation Sequence .........................................................................................................................19 Figure 9: Timing Diagram—Management of the Interrupt Line OFF ...................................................................... 20 Figure 10: I/O and I/OUC State Diagram..............................................................................................................21 Figure 11: Timing Diagram—I/O to I/OUC Delays ................................................................................................21 Figure 12: Open-Drain Type—OFF ......................................................................................................................22 Figure 13: Power Input/Output Circuit—VDD, VPC, VCC ..........................................................................................22 Figure 14: Smart Card CLK Driver Circuit ............................................................................................................23 Figure 15: Smart Card RST Driver Circuit ............................................................................................................23 Figure 16: Smart Card I/O, C4, and C8 Interface Circuit....................................................................................... 24 Figure 17: Smart Card I/OUC Interface Circuit .....................................................................................................24 Figure 18: General Input Circuit ...........................................................................................................................25 Figure 19: Oscillator Circuit..................................................................................................................................25 Figure 20: CLKDIV ..............................................................................................................................................26 Figure 21: Mechanical Drawing 20-Pin SO Package ............................................................................................27 Tables Table 1: 73S8014BN 20-Pin SO Pin Definitions .....................................................................................................6 Table 2: Absolute Maximum Device Ratings ..........................................................................................................8 Table 3: Recommended Operating Conditions .......................................................................................................8 Table 4: DC Smart Card Interface Requirements ...................................................................................................9 Table 5: Digital Signals Characteristics ................................................................................................................11 Table 6: DC Characteristics .................................................................................................................................12 Table 7: Voltage and Current Fault-Detection Circuits..........................................................................................12 Table 8: VCC Voltage Logic Table.........................................................................................................................15 Table 9: Order Numbers and Packaging Marks....................................................................................................28 4 Rev. 2 DS_8014BN_057 73S8014BN Data Sheet 1 Pinout The 73S8014BN is offered in a 20-pin SO package. RSTIN 1 20 OFF C8UC 2 19 PRES I/OUC 3 18 VCC VPC 4 17 CLK C4UC 5 16 GND CLKDIV 6 15 RST 7 14 C8 CMDVCC 8 13 I/O 5V/#V 9 12 C4 10 11 XTALOUT VDD XTALIN/CLKIN 73S8014BN Figure 2: 73S8014BN 20-SO Pinout Rev. 2 5 73S8014BN Data Sheet DS_8014BN_057 Table 1 provides the 73S8014BN pin names, pin numbers, type, equivalent circuits, and descriptions. Table 1: 73S8014BN 20-Pin SO Pin Definitions NAME PIN TYPE EQUIVALENT CIRCUIT FIGURE # DESCRIPTION CARD INTERFACE I/O 13 IO Figure 16 C4 12 IO Figure 16 C8 14 IO Figure 16 RST 15 O Figure 15 Card I/O: Data Signal to/from Card. Includes an 11kΩ pullup resistor to VCC. Card C4: Data Signal to/from Card. Includes an 11kΩ pullup resistor to VCC. Card C8: Data Signal to/from Card. Includes an 11kΩ pullup resistor to VCC. Card Reset. Provides reset (RST) signal to card. CLK 17 O Figure 14 Card Clock: Provides clock signal (CLK) to card. The rate of this clock is determined by the external crystal frequency or frequency of the external clock signal applied on XTALIN and CLKDIV selections. PRES 19 I Figure 18 Card Presence Switch. Active high indicates the card is present. Includes a high-impedance pulldown current source. The PRES input includes a 5ms debounce for card insertion. VCC 18 PSO Figure 13 Card Power Supply. Logically controlled by sequencer, output of LDO regulator. Requires an external filter capacitor to the card GND. GND 16 GND — Card and Digital Ground HOST PROCESSOR INTERFACE CMDVCC 5V/3V CLKDIV 8 9 6 I I I Figure 18 Command VCC (Negative Assertion). Logic-low on this pin causes the LDO regulator to ramp the VCC supply to the card and initiates a card activation sequence, only when a card is present. Figure 18 5V/3V/1.8V Card Selection. Logic-high selects 5V for VCC and card interface. Logic-low selects 3V operation. Logic going from high to low within ±400ns of CMDVCC falling selects 1.8V. When the device is to be used with a single card voltage (3V or 5V only), this pin should be connected to either GND or VDD. However, it includes a high-impedance pullup resistor to default this pin high (selection of 5V card) when not connected. Do not change the level of this pin when CMDVCC is low. Figure 20 Sets the Divide Ratio from the XTAL Oscillator (or External Clock Input) to Card Clock. This is a multilevel input that uses a ratio of the VDD voltage to select the clock divider as shown: CLKDIV CLOCK RATE GND XTALIN/4 VDD/3 XTALIN VDD x 2/3 XTALIN/8 VDD XTALIN/2 Note: This input has no internal pullup or pulldown so it must not be left unconnected. OFF 6 20 O Figure 12 Active-Low Interrupt Signal to the Processor. Active-low multifunction indicating fault conditions, device readiness, and card presence. Open-drain output configuration. It includes an internal 20kΩ pullup to VDD. Rev. 2 DS_8014BN_057 73S8014BN Data Sheet NAME PIN TYPE EQUIVALENT CIRCUIT FIGURE # RSTIN 1 I Figure 18 Reset Input. Within a card session, this signal is the reset command to the card. Outside a card session, this signal is used to place the device in power-down. C8UC 2 IO Figure 17 System Controller Data C8 to/from the Card. Includes an 11kΩ pullup resistor to VDD. I/OUC 3 IO Figure 17 System Controller Data I/O to/from the Card. Includes an 11kΩ pullup resistor to VDD. C4UC 5 IO Figure 17 System Controller Data C4 to/from the Card. Includes an 11kΩ pullup resistor to VDD. DESCRIPTION MISCELLANEOUS INPUTS AND OUTPUTS XTALIN/ CLKIN 10 I Figure 19 Crystal Oscillator Input. This pin can either be connected to crystal or driven as a source for the card clock. XTALOUT 11 O Figure 19 Crystal Oscillator Output. Connected to crystal. This pin can be left open if XTALIN is being used as external clock input. POWER SUPPLY AND GROUND VDD 7 PSO Figure 13 System Interface Supply Voltage and Supply Voltage for Internal Circuitry VPC 4 PSO Figure 13 LDO Regulator Power Supply Source Rev. 2 7 73S8014BN Data Sheet DS_8014BN_057 2 Electrical Specifications This section provides the following: Absolute Maximum Ratings Recommended Operating Conditions Smart Card Interface Requirements Digital Signals Characteristics DC Characteristics Voltage Fault-Detection Circuits 2.1 Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8014BN. Permanent device damage can occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. The smart card interface pins are protected against short circuits to VCC, ground, and each other. Table 2: Absolute Maximum Device Ratings PARAMETER RATING Supply Voltage Range, VDD -0.5V to 4.0V DC Supply Voltage Range, VPC -0.5V to 6.0V DC Input Voltage for Digital Inputs -0.3V to (VDD + 0.5V) DC Storage Temperature Range -60°C to +150°C Pin Voltage Range (except Card Interface) -0.3V to (VDD + 0.5V) DC Pin Voltage Range (Card Interface) -0.3V to (VCC + 0.5V) DC ESD Tolerance (Card Interface Pins)* ±6kV ESD Tolerance (Other Pins) ±2kV *ESD testing on smart card pins is Human Body Model (HBM) condition, three pulses, each polarity referenced to ground. Note: Smart card pins are protected against shorts between any combinations of smart card pins. 2.2 Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions PARAMETER 8 RATING Supply Voltage Range, VDD 2.7V to 3.6V DC Supply Voltage Range, VPC 4.75V to 5.5V DC Ambient Operating Temperature Range -40°C to +85°C Input Voltage for Digital Inputs 0 to (VDD + 0.3V) Rev. 2 DS_8014BN_057 2.3 73S8014BN Data Sheet Smart Card Interface Requirements Table 4 lists the 73S8014BN smart card interface requirements. Table 4: DC Smart Card Interface Requirements PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CARD POWER SUPPLY (VCC) REGULATOR (General conditions: 4.75V < VPC < 5.5V, 2.7V < VDD < 5.5V; -40°C < TA < +85°C, unless otherwise noted.) (NDS conditions: 4.85V < VPC < 5.5V, unless otherwise noted.) Inactive mode -0.1 +0.1 Card Supply Voltage Including Ripple and Noise VCC VCC Ripple VCCRIP Card Supply Output Current ICCMAX Inactive mode, ICC = 1mA -0.1 +0.4 Active mode; ICC < 65mA; 5V 4.65 5.25 Active mode; ICC < 65mA; 5V, NDS condition 4.75 5.25 Active mode; ICC < 65mA; 3V 2.85 3.15 Active mode; single pulse of 100mA for 2µs; 5V, fixed load = 25mA (Note 1) 4.6 5.25 Active mode; ICC < 40mA; 1.8V 1.68 1.92 Active mode; single pulse of 100mA for 2µs; 3V, fixed load = 25mA (Note 1) 2.76 3.15 Active mode; current pulses of 40nAs with peak |ICC | < 200mA, t < 400ns; 5V (Note 1) 4.6 5.25 Active mode; current pulses of 40nAs with peak |ICC | <200mA, t < 400ns; 5V, NDS condition (Note 1) 4.65 5.25 Active mode; current pulses of 40nAs with peak |ICC | <200mA, t < 400ns; 3V (Note 1) 2.7 3.15 1.62 1.92 Active mode; current pulses of 20nAs with peak |ICC | <100mA, t < 400ns; 1.8V (Note 1) fRIPPLE = 20kHz – 200MHz (Note 1) 350 Static load current, VCC > 4.6V or 2.7V as selected 65 Static load current, VCC>1.65 40 145 mA VCC = 1.8V 50 110 mA 0.150 0.30 V/µs 0.075 0.150 0.60 V/µs 0.5 1.0 1.5 µF VCC Slew Rate, Rise VSR CF = 1.0µF on VCC 0.06 VCC Slew Rate, Fall VSF CF = 1.0µF on VCC Rev. 2 mA 70 ICCF CFNDS mV VCC = 3V or 5V ICC Fault Current External Filter Cap (VCC to GND) V NDS applications, CF should be ceramic with low ESR (< 100mΩ) (Note 1) 9 73S8014BN Data Sheet PARAMETER DS_8014BN_057 SYMBOL CONDITIONS MIN TYP MAX UNITS INTERFACE REQUIREMENTS DATA SIGNALS: I/O, C4, C8 HOST INTERFACES: I/OUC, C4UC, C8UC (ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, C4UC, and C8UC.) Output Level High (I/OUC, C4UC, C8UC) Output Level High (I/O, C4, C8) Output Level Low (I/OUC, C4UC, C8UC) Output Level Low (I/O, C4, C8) Input Level High (I/OUC, C4UC, C8UC) Input Level High (I/O, C4, C8) Input Level Low (I/OUC, C4UC, C8UC) Input Level Low (I/O, C4, C8) Output Voltage When Outside of Session Input Leakage Input Current Low VOH IOH = -40µA 0.9 x VDD VDD + 0.1 IOH = 0mA 0.75 x VDD VDD + 0.1 IOH = -40µA (VCC = 3V/5V), -20µA (VCC = 1.8V) 0.9 x VCC VCC + 0.1 IOL = 1mA 0.75 VCC VCC+0.1 0.15 x VDD IOL = 1mA VOL 0.15 x VCC 0.6 x VDD VDD + 0.30 0.6 x VCC VCC + 0.30 -0.15 0.20 x VDD -0.15 0.20 x VCC VIH VIL IOL = 0mA VINACT ILEAK IIL V V V V IOL = 1mA 0.1 VIH = VCC 0.3 VIL = 0V 10 µA 0.65 mA For output low, shorted to VCC through 33Ω V Short-Circuit Output Current ISHORTL For output high, shorted to ground through 33Ω 15 mA Short-Circuit Output Current ISHORTH CL = 80pF, 10% to 90% 15 mA 100 ns Output Rise Time, Fall Times tR, tF Input Rise, Fall Times tIR, tIF Internal Pullup Resistor Maximum Data Rate Delay, I/O to I/OUC, I/OUC to I/O, C4 to C4UC, C4UC to C4, C8 to C8UC, C8UC to C8 (Respectively Falling Edge to Falling Edge and Rising Edge to Rising Edge) Input Capacitance 10 Output stable for > 400ns (Note 1) RPU FDMAX 8 11 Edge from master to slave, measured at 50% 60 tFDIO 100 1 µs 15 kΩ 1 MHz 200 ns tRDIO CIN 15 (Note 1) 10 pF Rev. 2 DS_8014BN_057 PARAMETER 73S8014BN Data Sheet SYMBOL CONDITIONS MIN TYP MAX UNITS 0.9 x VCC VCC V 0 0.15 x VCC V RESET AND CLOCK FOR CARD INTERFACE: RST, CLK Output Level High VOH IOH =-200µA Output Level Low VOL IOL=200µA IOL = 0mA 0.1 IOL = 1mA 0.3 Output Voltage When Outside of Session VINACT Output Current Limit, RST IRST_LIM 30 mA Output Current Limit, CLK ICLK_LIM 70 mA Output Rise Time, Fall Time Duty Cycle for CLK tR, tF δ CL = 35pF for CLK, 10% to 90% 8 CL = 200pF for RST, 10% to 90% CL =35pF, fCLK ≤ 20MHz 100 45 V ns 55 % MAX UNITS -0.3 +0.8 V 1.8 VDD + 0.3 V 0.45 V Note 1: Guaranteed by design; not production tested. 2.4 Digital Signals Characteristics Table 5 lists the 73S8014BN digital signals characteristics. Table 5: Digital Signals Characteristics PARAMETER Input Low Voltage SYMBOL CONDITIONS VIL Input High Voltage VIH Output Low Voltage VOL IOL = 2mA Output High Voltage VOH IOH = -1mA Pullup Resistor, OFF ROUT Input Leakage Current |IIL1| Input Level, CLKDIV MIN VDD - 0.45 13.5 VGND < VIN < VDD TYP V 20 26.5 kΩ -5 +5 µA VINCD1 Level Range 1 -0.3 +0.400 VINCD2 Level Range 2 0.26 x VDD 0.40 x VDD VINCD3 Level Range 3 0.6 x VDD 0.80 x VDD VINCD4 Level Range 4 VDD - 0.400 VDD + 0.3 V Input Low Voltage, XTALIN VILXTAL -0.3 0.3 x VDD V Input High Voltage, XTALIN VIHXTAL 0.7 x VDD VDD + 0.3 V Input Current, XTALIN IILXTAL -30 +30 µA 27 MHz 52 % Max Frequency Oscillator or External Clock fMAX External Input DutyCycle Limit δin VGND < VIN < VDD tR/tF < 10% fIN, 45% < δCLK < 55% (Note 1) 48 Note 1: Guaranteed by design; not production tested. Rev. 2 11 73S8014BN Data Sheet 2.5 DS_8014BN_057 DC Characteristics Table 6 lists the 73S8014BN DC characteristics. Table 6: DC Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.0 4 mA VDD Supply Current IDD VDD = 2.7V to 3.6V VDD Supply Current IPD Power-down 1 5 µA VPC Supply Current IPC VCC on, ICC = 0mA, CLK = 2.0MHz, external load < 10pF, I/O, C4, C8 = high 1 2 mA VPC Supply Current IPCPD CMDVCC = 1 1 2 µA TYP MAX UNITS V 2.6 Voltage Fault-Detection Circuits Table 7 lists the 73S8014BN voltage and current fault-detection circuits. Table 7: Voltage and Current Fault-Detection Circuits PARAMETER VDD Fault ICC Fault Current VCC Fault (VCC Voltage Supervisor Threshold) SYMBOL VDDF ICCF VCCF CONDITIONS VDD falling MIN 2.15 2.4 VCC = 3V or 5V 70 145 VCC = 1.8V 50 110 VCC = 5V 4.6 VCC = 3V 2.7 VCC = 1.8V (Note 1) 1.65 mA V Note 1: Guaranteed by design; not production tested. 12 Rev. 2 DS_8014BN_057 3 73S8014BN Data Sheet Applications Information This section provides general usage information for the design and implementation of the 73S8014BN. 3.1 Example 73S8014BN Schematics Figure 3 shows a typical application schematic for the implementation of the 73S8014BN. Note that minor changes can occur to the reference material from time to time and the reader is encouraged to contact Maxim for the latest information. Rev. 2 13 73S8014BN Data Sheet DS_8014BN_057 OFF_interrupt_to_uC RSTIN_from_uC C8UC_to/from_uC I/OUC_to/from_uC C4UC_to/from_uC CLKDIV2_from_uC 10uF C5 See NOTE 1 100nF C6 5V/#V_select_from_uC External_clock_from uC - OR - Y1 73S8014BN C3 See NOTE 4 R2 See NOTE 3 NOTES: 1) VDD = 2.7V to 3.6V DC.* 2) VPC = 4.75V(ISO)/4.85V(NDS) to 5.5V DC* 3) Required if external clock from uP is used. 4) Required if crystal is used. Y1, C2 and C3 must be removed if external clock is used. 5) Since the internal PRES pull down is weak, it is recommended that an external pull down is included 6) Pull down resistor R5 must be installed when using VCC = 1.8V, optional otherwise 47K See NOTE 5 20K R5 VDD R4 1K Card detection switch is normally open * Do not begin a NDS card session until VPC > 4.85V and VDD > VTH (VDD fault threshold) 8 7 6 5 4 3 2 1 22pF 20 19 18 17 16 15 14 13 12 11 C2 CRYSTAL CMDVCC_from_uC OFF PRES VCC CLK GND RST C8 I/O C4 XTALOUT C8 I/O VPP GND C4 CLK RST VCC 22pF RSTIN C8UC I/OUC VPC C4UC CLKDIV VDD CMDVCC 5V3V XTALIN 10 9 100nF C4 VDD 1 2 3 4 5 6 7 8 9 10 See NOTE 2 SW-2 SW-1 VPC See NOTE 6 C1 NDS, EMV & ISO7816= 1.0uF Low ESR (<100mohms) C1 should be placed near the SC connector contact CLK track should be routed far from RST, I/O, C4 and C8. Smart Card Connector Figure 3: 73S8014BN—Typical Application Schematic 14 Rev. 2 DS_8014BN_057 3.2 73S8014BN Data Sheet System Controller Interface Three digital inputs allow direct control of the card interface by the host. The 73S8014BN is controlled as follows: Pin CMDVCC: When asserted low, starts an activation sequence. When deasserted high, starts deactivation sequence. Pin RSTIN: Controls the card RST signal (when enabled by the sequencer) while the card is activated and the power-down mode when the card is not activated. Pin 5V/3V: Defines the card VDD voltage according to Table 8. Table 8: VCC Voltage Logic Table CONTROL PINS VCC VOLTAGE (V) NOTES CMDVCC 5V/3V 1 x 0 Off 1 5 5V/3V must be stable for at least 1µs before assertion of CMDVCC and held high until deassertion of CMDVCC. 0 3 5V/3V must be stable for at least 1µs before assertion of CMDVCC and held low until deassertion of CMDVCC. 1.8 Must be asserted low within 400ns of each other to generate 1.8V and held low until assertion of CMDVCC. The OFF digital output reports status back to the host. See the Fault Detection and OFF section for details on the operation of the OFF output. Note: 5V/3V should not change during a card session. Doing so does not change the voltage on VCC during that session, but if it is changed, the 5V/3V must be taken high outside the current card session and before beginning the next card session. Otherwise, the next card session may not power up to the selected VCC voltage. 3.3 Power-Down Mode The 73S8014BN includes a power-down mode to greatly reduce the power consumption on the VDD and VPC supplies when the smart card interface is deactivated. The power-down mode shuts down the crystal oscillator and other internal circuits to save power. When the power-down mode is released, the oscillator is restarted. It requires some time to start up and stabilize. During this time, the OFF output goes low (if a card is inserted) and is held low until the oscillator stabilizes, and then the OFF output goes high to indicate that the device is ready to activate the card. The power-down mode is initiated when RSTIN, CMDVCC, and 5V/3V are all logic-high for more than 2ms. The power-down mode is released immediately by bringing RSTIN low. This action forces the OFF output low for approximately 5ms to 7ms to allow the oscillator to start up and stabilize. This action informs the host that the 73S8014BN is busy and should not be activated while the OFF output is low. This ensures a proper activation sequence after coming out of power-down. The card-detection logic on the PRES input remains active in power-down mode. The card status is reported on OFF. Note: The CMDVCC and 5V/3V inputs have no effect when exiting power-down. Bringing RSTIN low is the only way to exit power-down. Figure 4 shows the power-down mode control timing with PRES debounce. See Section 3.9 for a full description of the PRES debounce behavior. Rev. 2 15 73S8014BN Data Sheet DS_8014BN_057 CMDVCC 5V/#V RSTIN PRES OFF PWR_DOWN 2ms 5ms 5ms 5 - 7ms When Power Down is de-asserted (RSTIN=Low), OFFB will go low indicating circuit is not ready, and then go high after 5ms (if PRES is high) This is a sequence of PRES events during the time when the host is requesting Power Down by setting CMDVCC = 5V/#V = RSTIN = High. In such a sequence, the circuit has to sense PRES and de-assert Power Down and time (de-bounce) the PRES signal, or assert the Power Down as appropriate. Figure 4: Power-Down Mode and PRES Debounce 3.4 Power Supply and Voltage Supervision The 73S8014BN smart card interface IC incorporates a low dropout (LDO) voltage regulator for VCC. The voltage output is controlled by the digital input 5V/3V of the 73S8014BN. This regulator can provide 1.8V, 3V, or 5V card voltage from the power supply applied on the VPC pin. The voltage regulator can provide a current of at least 65mA on VCC for both 3V and 5V or 40mA for 1.8V that complies with EMV 4.0 and NDS specifications. An overcurrent supervisor triggers a fault if the current on VCC exceeds the threshold at the given VCC voltage. Digital circuitry is powered by the power supply applied on the VDD pin. VDD is sourced by 2.7 to 3.6V so the system controller must operate with this supply level. A card deactivation sequence is forced upon fault of any voltage or overcurrent supervisor. One supervisor monitors the VCC output voltage at the selected VCC voltage level. The maximum VCC voltage-fault threshold does not exceed the minimum VCC voltage spec according to ISO 7816. See VCCF specification for the VCC voltage thresholds. Another voltage supervisor constantly monitors the VDD voltage. This fixed threshold supervisor is used to initialize the ISO 7816-3 sequencer at power-on and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD voltage supervisor is internally set to 2.26V typical (VDDF). If an adjustable VDD threshold (>2.26V) is required on the device, then the 73S8024RN should be considered or an external circuit configured for the desired VDD threshold should be added to the circuit to control either the CMDVCC or PRES input for an immediate VCC deactivation. Note: Since the VDD and the VPC power supplies are separate, special care must be taken to ensure that the VPC voltage is greater than 4.85V before beginning activating the card. In addition, VDD must be greater than the threshold for VDD fault before card activation. When turning off power to the VDD and the VPC power supplies, the card should be deactivated before shutdown or the VPC power supply must remain higher than 4.85V when the VDD fault is detected and the emergency deactivation sequence is completed. 3.5 Card Power Supply The 73S8014BN smart card interface IC incorporates an LDO voltage regulator for VCC. The voltage output is controlled by the digital inputs 5V/3V and CMDVCC of the 73S8014BN. This regulator can provide 1.8V, 3V, or 5V card voltage from the power supply applied on the VPC pin. The voltage regulator can provide a current of at least 65mA on VCC for both 3V and 5V and 40mA for 1.8V that complies with EMV 4.2 and NDS specifications. Note: When using VCC = 1.8V, a minimum load is required on VCC to ensure proper output regulator stability. A 20kΩ resistor is required between VCC and GND to meet this minimum load requirement. If VCC = 1.8V is never used in a given application, the resistor is not required. 16 Rev. 2 DS_8014BN_057 3.6 73S8014BN Data Sheet On-Chip Oscillator and Card Clock The 73S8014BN device has an on-chip oscillator that can generate the smart card clock using an external crystal (connected between XTALIN and XTALOUT) to set the oscillator frequency. When the clock signal is available from another source it can be connected to XTALIN, and XTALOUT should be left unconnected. For this device the card clock frequency can be chosen among four different division rates, defined by multiplestate input CLKDIV, as per the following table: CLKDIV CLK MAX XTALIN/CLKIN (MHz) GND 1/4 XTALIN 27 VDD/3 XTALIN 20 VDD x 2/3 1/8 XTALIN 27 VDD 1/2 XTALIN 27 Note: The clock-divider ratio must be configured prior to activation and must not change during the card session. Note: Special care should be taken when configuring the CLKDIV input when using the power-down mode. The CLKDIV input does not contain an internal pullup or pulldown so it must not be allowed to be left unconnected. In addition, the CLKDIV input should be set in such a manner as to set the voltage level to GND or VDD to keep the current consumption to an absolute minimum. There are numerous simple methods available to control CLKDIV as shown in Figure 5. 1. Selecting between Divide by 2 (I/O HIGH) or divide by 4 (I/O LOW) CLKDIV PIN HOST I/O PIN 2. Selecting between Divide by 2 (IO HIGH) or divide by 8 (IO LOW) VDD R HOST I/O PIN CLKDIV PIN 2R 3. Selecting any of the four Divide ratios CLKDIV PIN HOST I/O PIN 1 R HOST I/O PIN 2 2R Figure 5: CLKDIV Usage Rev. 2 17 73S8014BN Data Sheet 3.7 DS_8014BN_057 Activation Sequence The 73S8014BN smart card interface IC has an internal 1ms delay on the application of VDD where VDD > VDDF. No activation is allowed during this 1ms period. The CMDVCC (edge triggered) signal must then be set low to activate the card. To initiate activation, the card must be present and there can be no VDD fault. The following steps show the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low while the RSTIN is low: • • • • • CMDVCC is set low at t0. VCC rises to the selected level and then the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid at t1, OFF goes low to report a fault to the system controller, and VCC to the card is shut off. Turn I/O to reception mode at t2. CLK is applied to the card at t3. RST is a copy of RSTIN after t3. CMDVCC VCC I/O CLK RSTIN RST t0 t1 t2 t3 t1 = 0.2ms (timing by 1.5MHz internal oscillator) t2 = 1.5µs, I/O goes to reception state t3 = > 0.5µs, CLK starts, RST to become the copy of RSTIN Figure 6: Activation Sequence—RSTIN Low When CMDVCC Goes Low The startup of the CLK output can be delayed in the activation sequence by setting the RSTIN input high before beginning activation by bringing CMDVCC low. The CLK output is delayed until RSTIN is taken low. Special care must be taken when performing this type of activation. The power-down mode is initiated by setting the RSTIN and 5V/3V inputs high while CMDVCC is high (outside a card session). If this state is held for more than 2ms, the power mode is initiated. As a result, to use this activation mode, the CMDVCC falling edge must occur within 1ms of the RSTIN input being set high. The following steps show the activation sequence and the timing of the card control signals when the system controller pulls the CMDVCC low while the RSTIN is high: • • • • 18 CMDVCC is set low at t0. VCC rises to the selected level and then the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid at t1, OFF goes low to report a fault to the system controller, and VCC to the card is shut off. At the fall of RSTIN (under host control) at t2, CLK is applied to the card. RST is a copy of RSTIN after t2. Rev. 2 DS_8014BN_057 73S8014BN Data Sheet CMDVCC VCC I/O CLK RSTIN RST t1 t0 t2 t1 = 0.2 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state) t2 = RSTIN goes low and CLK becomes active t3 = > 0.5µs, CLK active, RST to become the copy of RSTIN Figure 7: Activation Sequence—RSTIN High When CMDVCC Goes Low 3.8 Deactivation Sequence Deactivation is initiated either by the system controller by setting the CMDVCC high or automatically in the event of hardware faults. Hardware faults are overcurrent, VDD fault, VCC fault, and card extraction during the session. The following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal: • • • • RST goes low at the end of t1. CLK is set low at the end of t2. I/O goes low at the end of t3. Out of reception mode. VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low. CMDVCC -- OR -- OFF RST CLK I/O VCC t1 t2 t3 t4 t5 t1 = > 0.5µs, timing by 1.5MHz internal oscillator t2 = > 7.5µs t3 = > 0.5µs t4 = > 0.5µs t5 = depends on VCC filter capacitor For NDS application, CF=1µF makes t1 + t2 + t3 + t4 + t5 < 100µs Figure 8: Deactivation Sequence Rev. 2 19 73S8014BN Data Sheet 3.9 DS_8014BN_057 Fault Detection and OFF There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence and device readiness outside card sessions, or for fault detection during card sessions. The OFF interrupt output operates as follows: As long as the card is not activated (CMDVCC is always high), OFF informs the host about the card presence or device readiness. When no card is inserted, the OFF output is low. When a card is inserted, the OFF output is set high after a 5ms debounce period. Upon card removal, there is no debounce on the PRES input as the emergency deactivation must occur as soon as possible to prevent any potential card errors or data corruption. The OFF output goes low immediately upon detection of a logic-low on the PRES input, but the OFF output does not bounce and remains low for at least 5ms. In addition, when a card is present and the power-down mode is released, the OFF output is taken low for about 5ms to indicate that the device is not ready. This time allows the crystal oscillator to start up and stabilize. When CMDVCC is asserted low (card activation sequence requested from the host), low level on OFF means a fault has been detected (e.g., card removal during card session, voltage fault, or overcurrent fault) that automatically initiates a deactivation sequence. Figure 9 shows the timing diagram for the signals CMDVCC, PRES, and OFF while the card is activated and deactivated: OFF is low by card extracted OFF is low by any fault PRES OFF CMDVCC VCC outside card session within card session within card session Figure 9: Timing Diagram—Management of the Interrupt Line OFF 3.10 I/O, C4, and C8 Circuitry and Timing The I/O, C4, and C8 are smart card data signals that operate identically, and I/OUC, C4UC, and C8UC are the corresponding microcontroller interface signals. The I/O and I/OUC data signals are described henceforth. The state of the I/O and I/OUC pins are low after power-on reset and goes high when the activation sequencer turns on the I/O reception state. See the Activation Sequence section for details on when the I/O reception is enabled. The state of I/OUC is high after power-on reset. When the card is activated and the I/O reception state is turned on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, both I/O lines return to their neutral state. Note: In certain situations and conditions, the I/O logic can get confused if the host and the card attempt to drive the I/OUC and the I/O signal low at the same time. It should be noted that this is an illegal condition as all card communication is initiated by the host with a command/response protocol. The next host command should not be sent until a valid response has been completely received from the card. However, if this condition should occur, the 73S8014BN could set both I/OUC and I/O as outputs where they are both driven low at the same time. When either side drives their respective signal high, this mode should be released. However, if there is a series resistance between the host and the 73S8014BN, there may not be enough drive to release this mode. If the series resistance is greater than approximately 100Ω, this can cause this mode to become locked for the duration of the card session. If the host detects this condition (I/OUC held low for more than 1 byte time), the card session must be terminated and restarted. 20 Rev. 2 DS_8014BN_057 73S8014BN Data Sheet Figure 10 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The delay between the I/O signals is shown in Figure 11. Neutral State No I/O reception Yes I/O & not I/OUC No Yes I/OUC & not I/O No Yes I/OICC in I/OUC in No No I/OUC I/O yes yes Figure 10: I/O and I/OUC State Diagram I/O I/OUC tI/O_HL Delay from I/O to I/OUC: Delay from I/OUC to I/O: tI/O_LH tI/O_HL = 100ns tI/OUC_HL = 100ns tI/OUC_HL tI/OUC_LH tI/O_LH = 25ns tI/OUC_LH = 25ns Figure 11: Timing Diagram—I/O to I/OUC Delays Rev. 2 21 73S8014BN Data Sheet DS_8014BN_057 4 Equivalent Circuits This section provides illustrations of circuits equivalent to those described in the pinout section. VDD Output Disable 20K PIN Data From circuit ESD STRONG NFET Figure 12: Open-Drain Type—OFF To Internal circuits PIN ESD Figure 13: Power Input/Output Circuit—VDD, VPC, VCC 22 Rev. 2 DS_8014BN_057 73S8014BN Data Sheet VCC VERY STRONG PFET ESD From circuit CLK PIN VERY STRONG NFET ESD Figure 14: Smart Card CLK Driver Circuit VCC STRONG PFET ESD From circuit RST PIN ESD STRONG NFET Figure 15: Smart Card RST Driver Circuit Rev. 2 23 73S8014BN Data Sheet DS_8014BN_057 VCC ESD STRONG PFET RL=11K 400ns DELAY From circuit I/O, C4, AND C8 PIN STRONG NFET To circuit CMOS ESD Figure 16: Smart Card I/O, C4, and C8 Interface Circuit VDD ESD STRONG PFET RL=11K 400ns DELAY From circuit I/OUC PIN To circuit CMOS STRONG NFET ESD Figure 17: Smart Card I/OUC Interface Circuit 24 Rev. 2 DS_8014BN_057 73S8014BN Data Sheet VDD VERY WEAK PFET Pull-up Disable ESD PIN TTL To circuit ESD VERY WEAK NFET Pull-down Enable Note: 5V/3V has the pullup enabled. PRES has the pulldown enabled. CMDVCC and RSTIN have pullup and pulldown disabled. Figure 18: General Input Circuit VDD VERY WEAK FETs ENABLEB ESD STRONG PFET ESD STRONG PFET XTALIN/ CLKIN XTALOUT PIN PIN STRONG NFET ESD ENABLE ESD STRONG NFET Figure 19: Oscillator Circuit Rev. 2 25 73S8014BN Data Sheet DS_8014BN_057 VDD Vin>Vhigh Vin>Vmid Vin>Vlow + - ESD Vhigh + - Vmid + - Vlow CLKDIV PIN ESD Figure 20: CLKDIV 26 Rev. 2 DS_8014BN_057 73S8014BN Data Sheet 5 Mechanical Drawing 0.505(12.83) + .003(.07) 0.296(7.52) - .004(.10) ± .005(.127) 0.092 (2.34) 0.505(12.83) 0.009 + .0025(.07) - .004(.093) (.22) ± .002(.05) 0.406(10.31) - .006(.15) + .004(.10) Inches (mm) ± .005(.127) BASE PLANE 0.016(.41) + .003(.07) - .002(.06) SEATING PLANE 0.050(1.27) TYP 0.01(.25) + .0025(.007) - .0009(.002) 0°- 8° Detail A .032 (.81) ± .008(.20) Detail “A” Figure 21: Mechanical Drawing 20-Pin SO Package Rev. 2 27 73S8014BN Data Sheet DS_8014BN_057 6 Ordering Information Table 9 lists the order numbers and packaging marks used to identify 73S8014BN products. Table 9: Order Numbers and Packaging Marks PART PIN-PACKAGE TOP MARK 73S8014BN-IL/F 20 SO 73S8014BN 73S8014BN-ILR/F 20 SO 73S8014BN F = Lead(Pb)-free/RoHS-compliant package. R = Tape and reel. 7 Contact Information For more information about Maxim products or to check the availability of the 73S8014BN, contact technical support at www.maxim-ic.com/support. 28 Rev. 2 DS_8014BN_057 73S8014BN Data Sheet Revision History REVISION NUMBER REVISION DATE 1.0 12/10 2 12/11 DESCRIPTION PAGES CHANGED Initial release — Deleted “Certification Pending” from the NDS logo. Added “designed to provide full electrical compliance with ISO 7816-3, EMV® 4.2, and NDS specifications” to the first sentence. Added “For NDS applications requiring an on-chip adjustable POR, see the Maxim 73S8024RN series of interface ICs.” to the first paragraph. 1 Provided additional description to Section 3.4. 16 Rev. 2 29 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.