TERIDIAN 73S8014RT

73S8014RT
Smart Card Interface
Simplifying System Integration™
DATA SHEET
December 2008
DESCRIPTION
APPLICATIONS
The Teridian 73S8014RT is a single smart card (ICC)
interface circuit. It is derived from the 73S8024RN
industry-standard electrical interface but adds support
for 1.8V smart card applications. The 73S8014RT has
been optimized to match most of the typical Set-Top
Box / A/V Conditional Access applications.
Optimization essentially involved a smaller pin-count
and support for single I/O.
• Set-Top Box Conditional Access and Pay-perView
• General purpose smart card readers
The 73S8014RT has been designed to provide full
electrical compliance with ISO 7816-3, EMV 4.0.
Interfacing with the system controller is done through a
control bus, composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults.
The card clock can be generated by an on-chip
oscillator using an external crystal or by connection to
an externally supplied clock signal. In addition, the
clock divider provides divisor values of divide by 1, 2, 4
and 6.
The 73S8014RT incorporates an ISO 7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the
selected card voltage (1.8V, 3V or 5V), coming from an
internal Low Drop-Out (LDO) voltage regulator. This
LDO regulator is powered by a dedicated power supply
input VPC. Digital circuitry is powered separately by a
digital power supply VDD. With its embedded LDO
regulator, the 73S8014RT is a cost-effective solution for
any application where a 5V (typically -5% +10%) power
supply is available.
Emergency card deactivation is initiated upon card
extraction or upon any fault detected by the protection
circuitry. The fault can be a card over-current, VCC
undervoltage or power supply fault (VDD). The card
over-current circuitry is a true current detection function,
as opposed to VCC voltage drop detection, as usually
implemented in non-Teridian 8024 interface ICs.
The VDD voltage fault has a threshold voltage that can
be adjusted with an external resistor network. It allows
automated card deactivation at a customized VDD
voltage threshold value. It can be used, for instance, to
match the system controller operating voltage range.
Rev. 1.0
ADVANTAGES
• Same advantages as the Teridian 73S80xxR
family:
ƒ Card VCC generated by an LDO regulator
ƒ Very low power dissipation (saves up to 1/2W)
ƒ Fewer external components are required
ƒ Better noise performance
• True card over-current detection
• Small format 20SO package
FEATURES
• Card Interface:
ƒ Complies with ISO 7816-3, EMV 4.0
ƒ 73S801RT device supports 3V / 5V cards up to
65mA and 1.8V up to 40mA
ƒ ISO 7816-3 Activation / Deactivation sequencer
ƒ Automated deactivation upon hardware fault (i.e.
upon drop on VDD power supply or card
overcurrent)
ƒ The VDD voltage supervisor threshold value (fault)
can be externally adjusted
ƒ Over-current detection 130mA max
ƒ Card CLK clock frequency up to 20MHz
• System Controller Interface:
ƒ 3 Digital inputs control the card activation /
deactivation, card reset and card voltage
ƒ 2 Digital inputs control the card clock frequency
ƒ 1 Digital output, interrupt to the system controller,
reports to the host the card presence and faults
ƒ Crystal oscillator or host clock, up to 27MHz
• Regulator Power Supply:
ƒ 4.75V to 5.5V (EMV 4.0)
• Digital Interfacing: 2.7V to 5.5V
• 6kV ESD protection on the card interface
• Package: SO 20-pin
• RoHS compliant (6/6) lead-free package
© 2008 Teridian Semiconductor Corporation
1
73S8014RT Data Sheet
DS_8014RT_015
FUNCTIONAL DIAGRAM
VDD
VPC
vdd circuits
VCC FAULT
VDDF_ADJ
INTERNAL POWER SUPPLY
VOLTAGE REFERENCE
VDD FAULT
vref
LDO
REGULATOR
bias currents
VPD - internal supply
CMDVCC%
CONTROLLER
AND
REGISTERS
RSTIN
CMDVCC#
1.5MHz
R-C
OSC.
VCC
FAULT LOGIC
TEST
GND
RESET
BUFFER
RST
CLOCK
BUFFER
CLK
OFF
SC
SEQUENCER
CKDIV1
CKDIV2
CLOCK
XTALIN
XTAL
OSC
CLOCK
GENERATION
VDD CKT
PRES
XTALOUT
vdd circuits
I/O
SMART CARD I/O BUFFER
IOUC
vcc circuits
73S8014RT
GND
Figure 1: 73S8014RT Block Diagram
2
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
Table of Contents
1 2 Pinout ................................................................................................................................................................ 5 Electrical Specifications .................................................................................................................................. 8 2.1 Absolute Maximum Ratings ........................................................................................................................ 8 2.2 Recommended Operating Conditions ......................................................................................................... 8 2.3 Package Thermal Parameters .................................................................................................................... 8 2.4 Smart Card Interface Requirements ........................................................................................................... 9 2.5 Characteristics: Digital Signals.................................................................................................................. 11 2.6 DC Characteristics .................................................................................................................................... 12 2.7 Voltage Fault Detection Circuits ................................................................................................................ 13 3 Applications Information ............................................................................................................................... 14 3.1 Example 73S8014RT Schematics ............................................................................................................ 14 3.2 System Controller Interface....................................................................................................................... 16 3.3 Power Supply and Voltage Supervision .................................................................................................... 16 3.4 Card Power Supply ................................................................................................................................... 16 3.5 On-Chip Oscillator and Card Clock ........................................................................................................... 17 3.6 Activation Sequence ................................................................................................................................. 17 3.7 Deactivation Sequence ............................................................................................................................. 19 3.8 Fault Detection and OFF ........................................................................................................................... 20 3.9 I/O Circuitry and Timing ............................................................................................................................ 20 4 Equivalent Circuits ......................................................................................................................................... 22 5 Mechanical Drawing ....................................................................................................................................... 27 6 Ordering Information ..................................................................................................................................... 28 7 Related Documentation ................................................................................................................................. 28 8 Contact Information ....................................................................................................................................... 28 Rev. 1.0
3
73S8014RT Data Sheet
DS_8014RT_015
Figures
Figure 1: 73S8014RT Block Diagram ........................................................................................................................ 2 Figure 2: 73S8014RT 20-SOP Pin Out ..................................................................................................................... 5 Figure 3: 73S8014RT – Typical Application Schematic .......................................................................................... 15 Figure 4: Activation Sequence – RSTIN Low When CMDVCC% or CMDVCC# Goes Low .................................... 18 Figure 5: Activation Sequence – RSTIN High When CMDVCC% or CMDVCC# Goes Low ................................... 18 Figure 6: Deactivation Sequence ............................................................................................................................ 19 Figure 7: Timing Diagram – Management of the Interrupt Line OFF ...................................................................... 20 Figure 8: I/O and I/OUC State Diagram................................................................................................................... 21 Figure 9: I/O – I/OUC Delays – Timing Diagram ..................................................................................................... 21 Figure 10: Open Drain type – OFF .......................................................................................................................... 22 Figure 11: Power Input/Output Circuit, VDD, VPC, VCC .............................................................................................. 22 Figure 12: Type 5 – Smart Card CLK Driver Circuit ................................................................................................ 23 Figure 13: Type 6 – Smart Card RST Driver Circuit ................................................................................................ 23 Figure 14: Type 7A – Smart Card IO Interface Circuit ............................................................................................ 24 Figure 15: Type 7B – Smart Card IOUC Interface Circuit ....................................................................................... 24 Figure 16: Type 8 – General Input Circuit ............................................................................................................... 25 Figure 17: Oscillator Circuit ..................................................................................................................................... 25 Figure 18: VDDFLT_ADJ .............................................................................................................................................. 26 Figure 19: Mechanical Drawing 20-Pin SO Package .............................................................................................. 27 Tables
Table 1: 73S8014RT 20-Pin SOP Pin Definitions ..................................................................................................... 6 Table 2: Absolute Maximum Device Ratings ............................................................................................................. 8 Table 3: Recommended Operating Conditions ......................................................................................................... 8 Table 4: Package Thermal Parameters ..................................................................................................................... 8 Table 5: DC Smart Card Interface Requirements ..................................................................................................... 9 Table 6: Digital Signals Characteristics ................................................................................................................... 11 Table 7: DC Characteristics ..................................................................................................................................... 12 Table 8: Voltage Fault Detection Circuits ................................................................................................................ 13 Table 9: VCC Voltage Logic Table ............................................................................................................................ 16 Table 10: Order Numbers and Packaging Marks .................................................................................................... 28 4
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
1 Pinout
The 73S8014RT is supplied as a 20-pin SO package.
Figure 2: 73S8014RT 20-SOP Pin Out
Rev. 1.0
5
73S8014RT Data Sheet
DS_8014RT_015
Table 1 provides the 73S8014RT pin names, pin numbers, type, equivalent circuits and descriptions.
Table 1: 73S8014RT 20-Pin SOP Pin Definitions
Pin Name
Pin
Number Type
Equivalent
Circuit
Description
Card Interface
I/O
14
IO
Figure 14
Card I/O: Data signal to/from card. Includes an 11K pull-up
resistor to VCC.
RST
15
O
Figure 13
Card reset: provides reset (RST) signal to card.
CLK
17
O
Figure 12
Card clock: provides clock signal (CLK) to card. The rate of this
clock is determined by the external crystal frequency or
frequency of the external clock signal applied on XTALIN and
CLKDIV selections.
PRES
19
I
Figure 16
Card Presence switch: active high indicates card is present.
Includes a high-impedance pull-down current source.
VCC
18
PSO
Figure 11
Card power supply – logically controlled by sequencer, output of
LDO regulator. Requires an external filter capacitor to the card
GND.
GND
16
GND
–
Card ground.
Host Processor Interface
CMDVCC%
6
I
Figure 16
CMDVCC#
7
I
Figure 16
Logic low on one or both of these pins will cause the LDO
regulator to ramp the Vcc supply to the smart card and smart
card interface to the value described in the following table:
CMDVCC#
Vcc Output Voltage
CMDVCC%
0
0
1.8V
0
1
5.0V
1
0
3.0V
1
1
Vcc Off
Note: See Section 3.2 for more details.
20
5
I
Figure 16
Sets the divide ratio from the XTAL oscillator (or external clock
input) to the card clock. These pins include a pull-up resistor for
CLKDIV1 and CLKLDIV2 to provide a default rate of divide by
two.
CLKDIV1
CLKDIV2
CLOCK RATE
0
0
XTALIN/6
0
1
XTALIN/4
1
1
XTALIN/2
1
0
XTALIN
OFF
1
O
Figure 10
Interrupt signal to the processor. Active Low – Multi-function
indicating fault conditions and card presence. Open drain output
configuration. It includes an internal 20kΩ pull-up to VDD.
RSTIN
2
I
Figure 16
Reset Input: This signal is the reset command to the card.
I/OUC
3
IO
Figure 15
System controller data I/O to/from the card. Includes an 11K
pull-up resistor to VDD.
CLKDIV1
CLKDIV2
6
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
Miscellaneous Inputs and Outputs
XTALIN
9
Figure 17
Crystal oscillator input: can either be connected to crystal or
driven as a source for the card clock.
XTALOUT
10
Figure 17
Crystal oscillator output: connected to crystal. Left open if
XTALIN is being used as external clock input.
VDDF_ADJ
12
Figure 18
VDD fault threshold adjustment input: this pin can be used to
adjust the VDDF value (that controls deactivation of the card).
Must be left open if unused.
Power Supply and Ground
VDD
13
PSO
Figure 11
System interface supply voltage and supply voltage for internal
circuitry.
VPC
4
PSO
Figure 11
LDO regulator power supply source.
GND
8, 11
GND
–
Rev. 1.0
Digital ground.
7
73S8014RT Data Sheet
DS_8014RT_015
2 Electrical Specifications
This section provides the following:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
2.1
Absolute maximum ratings
Recommended operating conditions
Package thermal parameters
Smart card interface requirements
Digital signals characteristics
DC Characteristics
Voltage Fault Detection Circuits
Absolute Maximum Ratings
Table 2 lists the maximum operating conditions for the 73S8014RT. Permanent device damage may occur if
absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended
periods may affect device reliability. The smart card interface pins are protected against short circuits to VCC,
ground, and each other.
Table 2: Absolute Maximum Device Ratings
Parameter
Rating
Supply Voltage VDD
-0.5 to 6.0 VDC
Supply Voltage VPC
-0.5 to 6.0 VDC
Input Voltage for Digital Inputs
-0.3 to (VDD +0.5) VDC
Storage Temperature
-60 to 150°C
Pin Voltage (except card interface)
-0.3 to (VDD +0.5) VDC
Pin Voltage (card interface)
-0.3 to (VCC + 0.5) VDC
ESD Tolerance – Card interface pins
+/- 6kV
ESD Tolerance – Other pins
+/- 2kV
* Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground.
Note: Smart Card pins are protected against shorts between any combinations of Smart Card pins.
2.2
Recommended Operating Conditions
Function operation should be restricted to the recommended operating conditions specified in Table 3.
Table 3: Recommended Operating Conditions
2.3
Parameter
Rating
Supply Voltage VDD
2.7 to 5.5 VDC
Supply Voltage VPC
4.75 to 5.5 VDC
Ambient Operating Temperature
-40°C to +85°C
Input Voltage for Digital Inputs
0V to VDD + 0.3V
Package Thermal Parameters
Table 4 lists the 73S8014RT Smart Card package thermal parameters.
Table 4: Package Thermal Parameters
8
Parameter
Rating
20 SO
50°C / W
Rev. 1.0
DS_8014RT_015
2.4
73S8014RT Data Sheet
Smart Card Interface Requirements
Table 5 lists the 73S8014RT Smart Card interface requirements.
Table 5: DC Smart Card Interface Requirements
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Card Power Supply (VCC) Regulator
General conditions, -40°C < T < 85°C, 4.75V < VPC < 5.5V, 2.7V < VDD < 5.5V
VCC
Card supply voltage
including ripple and
noise
VCCrip
VCC Ripple
ICCmax
Card supply output
current
Inactive mode
-0.1
0.1
V
Inactive mode, ICC = 1mA
-0.1
0.4
V
Active mode; ICC <65mA; 5V
4.65
5.25
V
Active mode; ICC <65mA; 3V
2.85
3.15
V
Active mode; ICC <40mA; 1.8V
1.68
1.92
V
Active mode; single pulse of 100mA for
2μs; 5V, fixed load = 25mA
4.6
5.25
V
Active mode; single pulse of 100mA for
2μs; 3V, fixed load = 25mA
2.76
3.2
V
Active mode; current pulses of 40nAs
with peak |ICC | <200mA,
t <400ns; 5V
4.6
5.25
V
Active mode; current pulses of 40nAs
with peak |ICC | <200mA,
t <400ns; 3V
2.76
3.15
V
Active mode; current pulses of 20nAs
with peak |ICC | <100mA,
(1)
t <400ns; 1.8V
1.62
1.92
V
350
mV
fRIPPLE = 20K – 200MHz
Static load current, VCC>4.6 or 2.7 volts
as selected
65
mA
Static load current, VCC>1.62
40
mA
ICCF
ICC fault current
VSR
VCC slew rate, rise
CF = 1.0μF on VCC
0.06
VSF
VCC slew rate, fall
CF = 1.0μF on VCC
CF
External filter cap
(VCC to GND)
CF should be ceramic with low ESR
(<100mΩ).
Rev. 1.0
70
130
mA
0.150
0.30
V/μs
0.075
0.150
0.60
V/μs
0.5
1.0
1.5
μF
9
73S8014RT Data Sheet
Symbol
Parameter
DS_8014RT_015
Condition
Min
Nom
Max
Unit
Interface Requirements – Data Signals: I/O and Host Interfaces: I/OUC.
ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC.
Output level, high (I/OUC)
VOH
Output level, high (I/O)
Output level, low (I/OUC)
VOL
VIH
Output level, low (I/O)
IOH =0
0.9 VDD
VDD+0.1
V
IOH = -40μA
0.75 VDD
VDD+0.1
V
IOH =0
0.9 VCC
VCC+0.1
V
IOH = -40μA (VCC =
3/5V), IOH = -20μA
(VCC = 1.8V)
0.75 VCC
VCC+0.1
V
IOL=1mA
0.3
V
Vcc = 5V
0.45
V
Vcc = 3V
0.2
V
Vcc = 1.8V
0.15 VCC
V
1.8
VDD + 0.3
V
0.6 VCC
VCC+0.30
V
-0.3
0.8
V
Vcc = 5V, 3V
-0.3
0.8
V
Vcc = 1.8V
-0.3
0.2 VCC
V
Input level, high
Input level, high (I/O)
Input level, low
VIL
Input level, low (I/O)
VINACT
Output voltage when outside
of session
IOL = 0
0.1
V
IOL = 1mA
0.3
V
ILEAK
Input leakage
VIH = VCC
10
μA
IIL
Input current, low
VIL = 0
0.65
mA
ISHORTL
Short circuit output current
For output low,
shorted to VCC
through 33 Ω
15
mA
ISHORTH
Short circuit output current
For output high,
shorted to ground
through 33 Ω
15
mA
tR, tF
Output rise time, fall times
100
ns
tIR, tIF
Input rise, fall times
1
μs
RPU
Internal pull-up resistor
14
kΩ
FDMAX
Maximum data rate
1
MHz
200
ns
TRDIO
Delay, I/O to I/OUC, I/OUC to
I/O, (respectively falling edge
to falling edge and rising
edge to rising edge)
CIN
Input capacitance
TFDIO
10
CL = 80pF, 10% to
90%.
Output stable for
>400ns
Edge from master to
slave, measured at
50%
8
60
11
100
15
ns
10
pF
Rev. 1.0
DS_8014RT_015
Symbol
73S8014RT Data Sheet
Parameter
Condition
Min
Nom
Max
Unit
Reset and Clock for Card Interface, RST, CLK
VOH
VOL
Output level, high
IOH =-200μA
0.9 VCC
VCC
V
0
0.45
V
Output level, low
IOL=200μA, VCC = 5V
IOL=200μA, VCC = 3V
0
0.2
V
IOL=200μA, VCC = 1.8V
0
0.15 VCC
V
IOL = 0
0.1
V
IOL = 1mA
0.3
V
VINACT
Output voltage when
outside of session
IRST_LIM
Output current limit, RST
30
mA
ICLK_LIM
Output current limit, CLK
70
mA
CLKSR3V
CLK slew rate
<
0.3
V/ns
CLKSR5V
CLK slew rate
Vcc = 5V
0.5
V/ns
tR, tF
Output rise time, fall time
δ
2.5
CL = 35pF for CLK,
10% to 90%
8
ns
CL = 200pF for RST,
10% to 90%
100
ns
55
%
Max
Unit
CL =35pF,
FCLK ≤ 20MHz
CL =35pF,
FCLK < 10MHz
Vcc = 1.8V
Duty cycle for CLK
45
Characteristics: Digital Signals
Table 6 lists the 73S8014RT digital signals characteristics.
Table 6: Digital Signals Characteristics
Symbol
Parameter
Condition
Min
Nom
Digital I/O Except for XTALIN and XTALOUT
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
1.8
VDD + 0.3
V
VOL
Output Low Voltage
IOL = 2mA
0.45
V
VOH
Output High Voltage
IOH = -1mA
ROUT
Pull-up resistor, OFF
|IIL1|
Input Leakage Current
GND < VIN < VDD
|IIL2|
Input Leakage Current
GND < VIN < VDD
CLKDIV2 only
Rev. 1.0
VDD - 0.45
16
V
20
24
kΩ
-5
5
μA
-15
15
μA
11
73S8014RT Data Sheet
DS_8014RT_015
Oscillator (XTALIN) I/O Parameters
VILXTAL
Input Low Voltage - XTALIN
-0.3
0.3 VDD
V
VIHXTAL
Input High Voltage - XTALIN
0.7 VDD
VDD+0.3
V
IILXTAL
Input Current XTALIN
-30
30
μA
fMAX
Max freq. Osc or external
clock
27
MHz
δin
External input duty cycle limit
52
%
Nom
Max
Unit
12 MHz XTAL
2.7
7.0
mA
Ext CLK,
VDD = 2.7 – 3.6V, VCC
Off
1.7
mA
Ext CLK,
VDD = 2.7 – 3.6V, VCC
On
2.2
mA
Ext CLK,
VDD = 4.5 – 5.5V, VCC
Off
2.7
mA
Ext CLK,
VDD = 4.5 – 5.5V, VCC
On
3
mA
VCC on, ICC=0
I/O, AUX1,
AUX2=high,
Clock not toggling
450
700
μA
CMDVCC% or
CMDVCC# High
345
650
μA
2.6
GND < VIN < VDD
tR/F < 10% fIN,
45% < δCLK < 55%
48
DC Characteristics
Table 7 lists the 73S8014RT DC characteristics.
Table 7: DC Characteristics
Symbol
IDD
Parameter
Supply Current
IPC
Supply Current
IPCOFF
VPC supply current when
VCC = 0
12
Condition
Min
Rev. 1.0
DS_8014RT_015
2.7
73S8014RT Data Sheet
Voltage Fault Detection Circuits
Table 8 lists the 73S8014RT Voltage Fault Detection Circuits.
Table 8: Voltage Fault Detection Circuits
Symbol
Parameter
VDDF
VDD fault
(VDD Voltage supervisor
threshold)
VCCF
VCC fault
(VCC Voltage supervisor
threshold)
Rev. 1.0
Condition
Min
No external resistor
on VDDF_ADJ pin
2.15
Nom
Max
Unit
2.4
V
VCC = 5v
4.6
V
VCC= 3v
2.7
V
13
73S8014RT Data Sheet
DS_8014RT_015
3 Applications Information
This section provides general usage information for the design and implementation of the 73S8014RT. The
documents listed in Related Documentation provide more detailed information.
3.1
Example 73S8014RT Schematics
Figure 3 shows a typical application schematic for the implementation of the 73S8014RT.
14
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
CLKDIV1_from_uC
OFF_interrupt_to_uC
RSTIN_from_uC
See
note 5
I/OUC_to/from_uC
VDD
CLKDIV2_from_uC
VPC
100nF
See NOTE 2
C4
1
2
3
4
5
6
7
8
9
10
10uF
C5
22pF
C2
CRYSTAL
Y1
CMDVCC%_from_uC
22pF
CMDVCC#_from_uC
OFF
RSTIN
I/OUC
VPC
CLKDIV2
CMDVCC5
CMDVCC3
GND
XTALIN
XTALOUT
CLKDIV1
PRES
VCC
CLK
GND
RST
I/O
VDD
VDDF_ADJ
TEST
R3
Rext2
20
19
18
17
16
15
14
13
12
11
VDD
See NOTE 1
C6
R1
Rext1
73S8014RT
C3
100nF
See NOTE 4
See NOTE 3
- OR -
External_clock_from uC
R2
47K
5) R1 and R3 are external resistors that adjust the VDD
fault voltage. Can be left open.
10
9
EMV & ISO7816=1uF
Low ESR (<100mohms) C1
should be placed near the SC
connecter contact
8
7
6
5
4
3
2
1
C8
I/O
VPP
GND
C4
CLK
RST
VCC
normally open
C1
SW-2
SW-1
NOTES:
1) VDD = 2.7V to 5.5V DC.
VDD
2) VPC = 4.75V(ISO) to 5.5V DC
R4
3) Required if external clock from uP is used.
1K
4) Required if crystal is used.
Card detection
Y1, C2 and C3 must be removed if external clock is used. switch is
CLK track should be routed
far from RST, I/O, C4 and
C8.
Smart Card Connector
Figure 3: 73S8014RT – Typical Application Schematic
Rev. 1.0
15
73S8014RT Data Sheet
3.2
DS_8014RT_015
System Controller Interface
Three digital inputs allow direct control of the card interface by the host.
The 73S8014RT is controlled as follows:
ƒ
ƒ
Pins CMDVCC% and/or CMDVCC#: When low, starts an activation sequence at the voltage specified in Table 9.
Pin RSTIN: controls the card RST signal (when enabled by the sequencer)
Table 9: VCC Voltage Logic Table
Control Pins
CMDVCC%
CMDVCC#
VCC
Voltage
1
1
0V
0
1
5V
1
0
3V
0
0
1.8V
Notes
Off
Must be asserted within 400ns of each other to generate 1.8V
Card clock frequency can be controlled by 2 digital inputs:
ƒ
CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input clock frequency (crystal
or external clock)
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card
presence only (Low = No card in the reader). When CMDVCC% or CMDVCC# is asserted low (Card activation
sequence requested from the host), low level on OFF means a fault has been detected (e.g. card removal during
card session, voltage fault, or over-current fault) that automatically initiates a deactivation sequence.
3.3
Power Supply and Voltage Supervision
The Teridian 73S8014RT smart card interface ICs incorporate an LDO voltage regulator. The voltage output is
controlled by both the CMDVCC% and CMDVCC# pins. This regulator is able to provide either 3V or 5V or 1.8V
card voltage from the power supply applied on the VPC pin. The voltage regulator can provide a current of at
least 65mA on VCC for both 3V and 5V that complies with EMV 4.0.
Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to
interface with the system controller. A card deactivation sequence is forced upon fault of any of this voltage
supervisor. One voltage supervisor constantly monitors the VDD voltage. It is used to initialize the ISO-7816-3
sequencer at power-on, and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD
voltage supervisor is internally set by default to 2.26V nominal. However, it may be desirable, in some
applications, to modify this threshold value.
The method of adjusting the VDD fault voltage is to use a resistive network of R3 from the VDDF_ADJ pin to VDD
supply and R1 from the VDDF_ADJ pin to ground (see application schematics). In order to set the new threshold
voltage, the equivalent voltage divider ratio must be determined. This ratio value will be designated Kx. Kx is
defined as R1/(R1+R3). Kx is calculated as:
Kx = (2.71 / VTH) - 0.595 where VTH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas (the parallel resistance of R1 and R3 is
selected to be 24000 ohms)
R3 = 24000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.6V is desired, solving for Kx gives:
Æ Kx = (2.71 / 2.6) - 0.595 = 0.4473.
Solving for R3 gives:
Æ R3 = 24000 / 0.4473 = 53654.
Solving for R1 gives:
Æ R1 = 58752 *(0.4473 / (1 – 0.4473)) = 43422.
Using standard 1 % resistor values gives R3 = 53.6KΩ and R1 = 43.2KΩ.
16
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
Using 1% external resistors and a parallel resistance of 24K ohms will result in a +/- 6% tolerance in the value of
VDD Fault. The sources of variation due to integrated circuit process variations and mismatches include the
internal reference voltage (less than +/- 1%), the internal comparator hysteresis and offset (less than +/- 1.7% for
part-to-part, processing and environment), the internal resistor value mismatch and value variations (less than
1.8%), and the external resistor values (1%).
If the 2.26V default threshold is used, this pin must be left unconnected.
3.4
Card Power Supply
The card power supply is internally provided by the LDO regulator and controlled by the digital ISO-7816-3
sequencer. Card voltage selection on the 73S8014RT is carried out by the digital inputs CMDVCC% and
CMDVCC#.
3.5
On-Chip Oscillator and Card Clock
The 73S8014RT devices have an on-chip oscillator that can generate the smart card clock using an external
crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the clock
signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be
left unconnected.
The card clock frequency may be chosen between 4 different division rates, defined by digital inputs CLKDIV 1
and CLKDIV 2, as per the following table:
3.6
CLKDIV1
CLKDIV2
CLK
Max XTALIN
0
0
1/6 XTALIN
27MHz
0
1
¼ XTALIN
27MHz
1
0
XTALIN
20MHz
1
1
½ XTALIN
27MHz
Activation Sequence
The 73S8014RT smart card interface ICs have an internal 10ms delay on the application of VDD where VDD >
VDDF. No activation is allowed during this 10ms period. The CMDVCC% or CMDVCC# (edge triggered) signals
must then be set low to activate the card. In order to initiate activation, the card must be present; there can be no
VDD fault.
The following steps show the activation sequence and the timing of the card control signals when the system
controller sets CMDVCC% or CMDVCC# low while the RSTIN is low:
-
-
CMDVCC% or CMDVCC# is set low at t0.
VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at
the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid
at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off.
Turn I/O to reception mode at t2.
CLK is applied to the card at t3.
RST is a copy of RSTIN after t3.
Rev. 1.0
17
73S8014RT Data Sheet
DS_8014RT_015
t1 = 0.510 ms (timing by 1.5MHz internal oscillator)
t2 = 1.5μs, I/O goes to reception state
t3 = >0.5μs, CLK starts, RST to become the copy of RSTIN
Figure 4: Activation Sequence – RSTIN Low When CMDVCC% or CMDVCC# Goes Low
The following steps show the activation sequence and the timing of the card control signals when the system
controller pulls CMDVCC% or CMDVCC# low while the RSTIN is high:
-
-
CMDVCC% or CMDVCC# is set low at t0.
VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at
the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid
at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off.
At the fall of RSTIN at t2, CLK is applied to the card
RST is a copy of RSTIN after t2.
t1 = 0.510 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state)
t2 = RSTIN goes low and CLK becomes active
t3 = > 0.5μs, CLK active, RST to become the copy of RSTIN
Figure 5: Activation Sequence – RSTIN High When CMDVCC% or CMDVCC# Goes Low
18
Rev. 1.0
DS_8014RT_015
3.7
73S8014RT Data Sheet
Deactivation Sequence
Deactivation is initiated either by the system controller by setting CMDVCC% and CMDVCC# high, or automatically
in the event of hardware faults. Hardware faults are over-current, VDD fault, VCC fault, and card extraction during the
session.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets CMDVCC% and CMDVCC# high or OFF goes low due to a fault or card removal:
-
RST goes low at the end of t1.
CLK is set low at the end of t2.
I/O goes low at the end of t3. Out of reception mode.
VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
t1 =
t2 =
t3 =
t4 =
t5 =
> 0.5μs, timing by 1.5MHz internal Oscillator
> 7.5μs
> 0.5μs
> 0.5μs
depends on VCC filter capacitor.
Figure 6: Deactivation Sequence
Rev. 1.0
19
73S8014RT Data Sheet
3.8
DS_8014RT_015
Fault Detection and OFF
There are two different cases that the system controller can monitor the OFF signal: to query regarding the card
presence outside card sessions, or for fault detection during card sessions.
Outside a card session: In this condition, CMDVCC% and CMDVCC# are always high, OFF is low if the card is not
present, and high if the card is present. Because it is outside a card session, any fault detection will not act upon
the OFF signal. No deactivation is required during this time.
During a card session: CMDVCC% or CMDVCC# is/are always low, and OFF falls low if the card is extracted or if
any fault detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation
process.
Figure 7 shows the timing diagram for the signals CMDVCC% or CMDVCC#, PRES, and OFF during a card
session and outside the card session:
Figure 7: Timing Diagram – Management of the Interrupt Line OFF
3.9
I/O Circuitry and Timing
The state of the I/O pin is low after power on reset and it goes high when the activation sequencer turns on the
I/O reception state. See the Activation Sequence section for details on when the I/O reception is enabled. The
state of I/OUC is high after power on reset.
Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling edge is
detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising
edge is detected then both I/O lines return to their neutral state.
Figure 8 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The
delay between the I/O signals is shown in Figure 9.
20
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
Neutral
State
No
I/O
reception
Yes
I/O
&
not I/OUC
No
Yes
No
I/OUC
&
not I/O
Yes
I/OUC
in
I/OICC
in
No
No
I/OUC
I/O
yes
yes
Figure 8: I/O and I/OUC State Diagram
I/O
I/OUC
tI/O_HL
Delay from I/O to I/OUC:
Delay from I/OUC to I/O:
tI/O_LH
tI/O_HL = 100ns
tI/OUC_HL = 100ns
tI/OUC_HL
tI/OUC_LH
tI/O_LH = 25ns
tI/OUC_LH = 25ns
Figure 9: I/O – I/OUC Delays – Timing Diagram
Rev. 1.0
21
73S8014RT Data Sheet
DS_8014RT_015
4 Equivalent Circuits
This section provides illustrations of circuits equivalent to those described in the pinout section.
Figure 10: Open Drain type – OFF
To
Internal
circuits
PIN
ESD
Figure 11: Power Input/Output Circuit, VDD, VPC, VCC
22
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
VCC
VERY
STRONG
PFET
ESD
From
circuit
CLK
PIN
VERY
STRONG
NFET
ESD
Figure 12: Type 5 – Smart Card CLK Driver Circuit
VCC
STRONG
PFET
ESD
From
circuit
RST
PIN
ESD
STRONG
NFET
Figure 13: Type 6 – Smart Card RST Driver Circuit
Rev. 1.0
23
73S8014RT Data Sheet
DS_8014RT_015
VCC
ESD
STRONG
PFET
RL=11K
400ns
DELAY
From
circuit
IO
PIN
STRONG
NFET
CMOS
To
circuit
ESD
Figure 14: Type 7A – Smart Card IO Interface Circuit
VDD
ESD
STRONG
PFET
RL=11K
400ns
DELAY
From
circuit
UC
PIN
To
circuit
CMOS
STRONG
NFET
ESD
Figure 15: Type 7B – Smart Card IOUC Interface Circuit
24
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
VDD
VERY
WEAK
PFET
Pull-up
Disable
ESD
TTL
To
circuit
PIN
VERY
WEAK
NFET
Pull-down
Enable
Note:
ESD
Pins CMDVCC%, CMDVCC#, CLKDIV1 and CLKDIV2 have the pull-up enabled.
Pins RSTIN, CLKIN, PRES have the pull-down enabled.
Figure 16: Type 8 – General Input Circuit
VDD
ENABLEB
VERY
WEAK
FETs
STRONG
PFET
ESD
ESD
STRONG
PFET
XTALIN
XTALOUT
PIN
PIN
STRONG
NFET
ESD
ENABLE
ESD
STRONG
NFET
Figure 17: Oscillator Circuit
Rev. 1.0
25
73S8014RT Data Sheet
DS_8014RT_015
VDD
PIN
ESD
R = 40k
VREF = 1.400v +
VDD FAULT
DETECTION
-
VDDF_
ADJ
ESD
PIN
R = 60k
R = 0.4k
(approx.)
ESD
Figure 18: VDDFLT_ADJ
26
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
5 Mechanical Drawing
+ .005(.127)
0.5050(12.82) - .009(.228)
+ .003(.076)
0.2960(7.51) - .004(.101)
0.4065(10.32)
± .0125(.318)
Inches (mm)
+ .005(.127)
- .009(.228)
BASE PLANE
+ .004(.101)
- .003(.076)
0.016(.406)
0.050(1.27)
TYP
SEATING PLANE
0.0082
(.208)
0.1000 + .004(.101)
- .007(.178)
(2.54)
0.5050(12.82)
+ .0025(.0634)
0.01(.254) - .0010(.0254)
0°- 8°
± .017(.431)
Detail A
.033
(.838)
Detail “A”
Figure 19: Mechanical Drawing 20-Pin SO Package
Rev. 1.0
27
73S8014RT Data Sheet
DS_8014RT_015
6 Ordering Information
Table 10 lists the order numbers and packaging marks used to identify 73S8014RT products.
Table 10: Order Numbers and Packaging Marks
Part Description
Order Number
Packaging Mark
73S8014RT 20-pin Lead-Free
73S8014RT-IL/F
73S8014RT
73S8014RT 20-pin Lead-Free Tape / Reel
73S8014RT-ILR/F
73S8014RT
7 Related Documentation
The following 73S8014RT document is available from Teridian Semiconductor Corporation:
73S8014R/RN/RT 20SO Demo Board User Manual
8 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73S8014RT,
contact us at:
6440 Oak Canyon Road
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: [email protected]
For a complete list of worldwide sales offices, go to http://www.teridian.com.
28
Rev. 1.0
DS_8014RT_015
73S8014RT Data Sheet
Revision History
Revision
1.0
Date
12/12/2008
Description
First publication.
© 2008 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms and
Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves
the right to change devices or specifications detailed herein at any time without notice and does not make any
commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this
document is current by comparing it to the latest version on http://www.teridian.com or by checking with your
sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com
Rev. 1.0
29