TI ADS1293CISQE/NOPB

ADS1293
www.ti.com
SNAS602A – AUGUST 2012 – REVISED NOVEMBER 2012
Low Power, 3-Channel, 24-Bit Analog Front End for Biopotential Measurements
Check for Samples: ADS1293
FEATURES
DESCRIPTION
•
The ADS1293 incorporates all features commonly
required in portable, low-power medical, sports and
fitness electrocardiogram (ECG) applications. With
high levels of integration and exceptional
performance, the ADS1293 enables the creation of
scalable medical instrumentation systems at
significantly reduced size, power, and overall cost.
1
The ADS1293 features three high-resolution channels
capable of operating up to 25.6ksps. Each channel
can be independently programmed for a specific
sample rate and bandwidth allowing users to optimize
the configuration for performance and power. All input
pins incorporate an EMI filter and can be routed to
any channel via a flexible routing switch. Flexible
routing also allows independent lead-off detection,
right leg drive, and Wilson/Goldberger reference
terminal generation without the need to reconnect
leads externally. A fourth channel allows external
analog pace detection for applications that do not
utilize digital pace detection.
The ADS1293 incorporates a self-diagnostics alarm
system to detect when the system is out of the
operating conditions range. Such events are reported
to error flags. The overall status of the error flags is
available as a signal on a dedicated ALARMB pin.
APPLICATIONS
Batt.
Mon
Lead off
detect
Test
Ref
VDDIO
RSTB
XTAL1
The device is packaged in a 5-mm × 5-mm × 0.8-mm,
28-pin LLP. Operating temperature ranges from
–20°C to 85°C.
CVREF
VDD
•
•
Portable 1/2/3/5/6/7/8/12-Lead ECG
Patient vital sign monitoring: holter, event,
stress, and telemedicine
Automated External Defibrillator
Sports and fitness (heart rate and ECG)
VSS
•
•
XTAL2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3 High Resolution Digital ECG Channels with
Simultaneous Pace Output
EMI Hardened Inputs
Low Power: 0.3mW/channel
Input-Referred Noise: 7µVpp (40Hz BW)
Input Bias Current: 175pA
Data Rate: Up to 25.6ksps
Differential Input Voltage Range: ±400mV
Analog Supply Voltage: 2.7V to 5.5V
Digital I/O Supply Voltage: 1.65V to 3.6V
Right Leg Drive Amplifier
AC and DC Lead-Off Detection
Wilson and Goldberger Terminals
ALARM Pin for Interrupt Driven Diagnostics
Battery Voltage Monitoring
Built-In Oscillator and Reference
Flexible Power-Down and Standby Modes
REF
CLK
OSC
POR
LOD_EN
CH2-Pace
+
CH3 InA
-
Σ∆
Modulator
Digital
Filter
CH3-ECG
CH3-Pace
WILSON_CN
CH4
PACE2WCT
SELRLD
WCT
+
InA
-
CMDET_EN
Wilson
ref.
CM
Detect
CMOUT
WILSON_EN
SDO
SDI
CH2-ECG
SCLK
CSB
DIGITAL
CONTROL AND
POWER
MANAGEMENT
CH4- Analog Pace
RLD
Amp.
ALARMB
REF for
CM & RLD
PACE2
RLDIN
VSSIO
EMI
filter
Digital
Filter
DRDYB
SYNCB
IN6
Σ∆
Modulator
RLDREF
EMI
filter
+
InA
-
EMI
filter
IN5
Flexible
Routing
Switch
CH2
RLDIN
EMI
filter
Digital
Filter
EMI
filter
IN4
Σ∆
Modulator
RLDINV
EMI
filter
+
InA
-
RLDOUT
IN3
CH1-ECG
CH1-Pace
CH1
-
EMI
filter
EMI
filter
+
IN1
IN2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
ADS1293
SNAS602A – AUGUST 2012 – REVISED NOVEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Batt.
Mon
Lead off
detect
Test
Ref
VDDIO
XTAL1
XTAL2
RSTB
CVREF
VSS
VDD
BLOCK DIAGRAM
REF
CLK
OSC
POR
LOD_EN
Digital
Filter
CH2-ECG
CH2-Pace
CH3
+
InA
-
Σ∆
Modulator
Digital
Filter
CH3-ECG
CH3-Pace
CH4
+
InA
-
Flexible
Routing
Switch
WILSON_CN
PACE2WCT
SELRLD
ALARMB
REF for
CM & RLD
PACE2
RLDIN
VSSIO
CM
Detect
RLD
Amp.
RLDOUT
Wilson
ref.
CMOUT
CMDET_EN
CH4- Analog Pace
+
WILSON_EN
CSB
DIGITAL
CONTROL AND
POWER
MANAGEMENT
SYNCB
WCT
SDI
SCLK
RLDREF
IN6
EMI
filter
Σ∆
Modulator
EMI
filter
IN5
EMI
filter
+
InA
-
CH2
DRDYB
SDO
RLDIN
IN4
EMI
filter
Digital
Filter
EMI
filter
IN3
EMI
filter
Σ∆
Modulator
RLDINV
IN2
EMI
filter
CH1-ECG
CH1-Pace
+
InA
-
CH1
-
IN1
EMI
filter
SPACER
SPACER
Table 1. ORDERING INFORMATION
PACKAGE
28–Pin LLP
PART NUMBER
PACKAGE MARKING
ADS1293CISQ
U2XYTT
ADS1293CISQx
TRANSPORT MEDIA
TI DRAWING
1k Units Tape and Reel
SQA28A
4.5k Units Tape and Reel
2
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SNAS602A – AUGUST 2012 – REVISED NOVEMBER 2012
CONNECTION DIAGRAM
28-PIN LLP
(TOP VIEW)
Table 2. PIN DESCRIPTIONS
PIN
TYPE
NO.
NAME
1-6
IN1 - IN6
Analog Input
7
WCT
Analog Output
FUNCTION
Electrode input signals
Wilson reference output or analog pace channel output
8
CMOUT
Output
Common-mode detector output
9
RLDOUT
Analog Output
Right leg drive amplifier output
10
RLDINV
Analog Input
Right leg drive amplifier negative input
11
RLDIN
Analog I/O
12
RLDREF
Analog Output
Right leg drive amplifier positive input or analog pace channel output
13
SYNCB
Digital I/O
14
VSSIO
Digital Supply
Digital input/output supply ground
15
ALARMB
Digital Output
Alarm bar
16
CSB
Digital Input
Chip select bar
17
SCLK
Digital Input
Serial clock
Serial data input
Internal right leg drive reference
Sync bar; multiple-chip synchronization signal input or output
18
SDI
Digital Input
19
SDO
Digital Output
Serial data output
20
DRDYB
Digital Output
Data ready bar
21
CLK
Digital I/O
22
VDDIO
Digital Supply
23
XTAL1
Digital Input
External crystal for clock oscillator
24
XTAL2
Digital Input
External crystal for clock oscillator
25
RSTB
Digital Input
Reset bar
26
CVREF
Analog I/O
External cap for internal reference voltage
27
VSS
Analog Supply
Power supply ground
28
VDD
Analog Supply
Positive power supply
DAP
Internal clock output or external clock input
Digital input/output supply
No connect
3
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SNAS602A – AUGUST 2012 – REVISED NOVEMBER 2012
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ABSOLUTE MAXIMUM RATINGS (1)
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for
availability and specifications.
VALUES
MIN
ESD Tolerance
(2)
UNITS
MAX
Human Body Model (HBM) For input pins only
1000
V
Charge Device Model (CDM)
500
V
Analog Supply Voltage, VDD
–0.3
6.0
V
Digital Supply Voltage, VDDIO
–0.3
6.0
V
Voltage on any Input Pin
–0.3 to (VDD + 0.3)
Input Current at Any Pin
Storage Temperature Range
Max Junction Temperature
(1)
(2)
(3)
–60
(3)
V
±10
mA
150
°C
150
°C
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be beyond such conditions. All voltages are
measured with respect to the ground pin, unless otherwise specified.
Human Body Model per MIL-STD-883, Method 3015.7. Machine Model, per JESD22-A115-A. Field-Induced Charge-Device Model, per
JESD22-C101-C.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) – TA)/ θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Units
2.7
5.5
V
VDD > 3.6V
1.65
3.6
V
VDD ≤ 3.6V
1.65
VDD
V
Analog Supply Voltage, VDD
Digital I/O Supply Voltage
Supply Ground
VSS = VSSIO
Full Scale Differential Input Voltage Range, DIVR
Temperature Range
±400
(1)
–20
Typical Package Thermal Resistance (1) , 28-Pin LLP (θJA)
(1)
85
29
mV
°C
°C/W
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) – TA)/ θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
4
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SNAS602A – AUGUST 2012 – REVISED NOVEMBER 2012
ELECTRICAL CHARACTERISTICS (1)
Unless otherwise noted, all limits are specified at TA = +25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65V ≤ VDDIO ≤ MIN(+3.6V, VDD),
VREF = +2.4V, fOSC = 409.6kHz, 1µF low ESR capacitor between CVREF and GND, 0.1µF capacitor between RLDREF and
GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
TYP (3)
MAX (2)
5.5
V
80
125
µA
Stand-by mode
120
175
µA
1 chan, WILSON OFF, RLD OFF, CMDET OFF, LOD OFF,
low power
205
290
1 chan, WILSON OFF, RLD OFF, CMDET OFF, LOD OFF,
high-res
335
490
3 chan, WILSON OFF, RLD OFF, CMDET OFF, LOD OFF,
low power
350
520
3 chan, WILSON ON, RLD ON, CMDET ON, LOD ON, low
power, low cap-drive
440
595
3 chan, WILSON ON, RLD ON, CMDET ON, LOD ON,
high-res, low cap-drive
835
1120
3 chan, WILSON ON, RLD ON, CMDET ON, LOD ON,
high-res, high cap-drive
960
1300
PARAMETER
TEST CONDITIONS
MIN (2)
UNIT
POWER SUPPLY (VDD, VDDIO)
VDD
Analog Supply Voltage
2.7
Power-down mode
IVDD
VDDIO
IVDDIO
Analog Supply Current
IO Supply Voltage
µA
VDD > 3.6V
1.65
3.6
VDD ≤ 3.6V
1.65
VDD
Quiescent Current IO Supply
0.6
V
V
µA
ANALOG INPUTS (IN1-IN6)
IB
Input Bias Current
RIN
Differential Input Resistance
(1)
(2)
(3)
TA = 25°C, LOD OFF
±175
TA = 85°C, LOD OFF
±13
500
pA
nA
MΩ
The Electrical Characteristics table lists specify specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
guaranteed.
Datasheet min/max specification limits are specified by test, unless otherwise noted.
Typical values represent the most likely parameter norms at TA = 25°C and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
5
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ELECTRICAL CHARACTERISTICS(1) (continued)
Unless otherwise noted, all limits are specified at TA = +25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65V ≤ VDDIO ≤ MIN(+3.6V, VDD),
VREF = +2.4V, fOSC = 409.6kHz, 1µF low ESR capacitor between CVREF and GND, 0.1µF capacitor between RLDREF and
GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
PARAMETER
MIN (2)
TEST CONDITIONS
TYP (3)
MAX (2)
UNIT
ANALOG FRONT END
DIVR
Differential Input Voltage Range
CMVR
Common-Mode Voltage Range for full
DIVR
VOS
Input-Referred Offset Voltage
CMRR
Common-Mode Rejection Ratio
-400
400
0.95
VDD0.95
V
±87
µV
±16
50 / 60Hz, VCMDC = RLDREF, VCMAC = 1.2VPP
100
23
30.5
0.1 - 215Hz, high resolution mode
15
23.95
0.1 - 40Hz, low power mode
10
23.1
7
10.3
Input-Referred Voltage Noise for
ECG (4)
Ve-PACE
Input-Referred Voltage Noise for Pace 1 - 1280Hz, high resolution mode, double pace data rate
0.1 - 40Hz, high resolution mode
315
0.1 - 215Hz, high resolution mode
155
250
PSRR
Power Supply Rejection Ratio
50 / 60Hz
XTLK
Crosstalk between channels
Crosstalk from driven channel to zero input channel
ENOBPACE
Effective Number of Bits for Pace
RS-ECG
Sample Rate ECG Channel
RS-PACE
Sample Rate PACE Channel
TSKEW
Sample Time Skew Between
Channels
µVPP
mVPP
240
Input-Referred Noise Density
Effective Number of Bits for ECG
0.4
0.1 - 215Hz, low power mode
Ne
ENOB-ECG
dB
0.1 - 215Hz, low power mode
Ve-ECG
mV
94
nV/√Hz
dB
-105
dB
215Hz bandwidth, low power mode
17.4
17.8
bits
215Hz bandwidth, high resolution mode
17.8
18.4
bits
13.7
bits
1280Hz bandwidth, high resolution mode, double pace data
rate
See Table 5, Table 6, Table 7 and Table 8
Multichip simultaneous sampling architecture
25
6400
sps
3.2
25.6
ksps
0
µs
INTERNAL REFERENCE (REF)
Internal Reference Voltage
VREF
2.4
V
Internal Reference Accuracy
±0.5
%
Internal Reference Drift
±11
ppm/°C
Internal Reference Start-up Time
5
ms
(VDD-VREF)/factor
3.246
V/V
Division Accuracy
±0.25
%
BATTERY MONITOR
Division
TEST REFERENCE
(VREF-VSS)/factor
12
Division Accuracy
±0.1
%
3.5
μA
Current Consumption
(4)
V/V
At least 1000 consecutive readings are used to calculate the peak-to-peak noise in production.
6
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SNAS602A – AUGUST 2012 – REVISED NOVEMBER 2012
ELECTRICAL CHARACTERISTICS(1) (continued)
Unless otherwise noted, all limits are specified at TA = +25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65V ≤ VDDIO ≤ MIN(+3.6V, VDD),
VREF = +2.4V, fOSC = 409.6kHz, 1µF low ESR capacitor between CVREF and GND, 0.1µF capacitor between RLDREF and
GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
UNIT
RIGHT LEG DRIVE AMPLIFIER (RLD Amp)
VOS
Input-Referred Offset Voltage
CMVR
Common-Mode Voltage Range
GBW
Programmable Gain Bandwidth
SR
Slew Rate
ClMAX
Programmable Capacitive Load
Driving Capability
IVDD
Quiescent Power Consumption
±5
mV
VDD0.5
0.5
V
Low bandwidth mode
50
High bandwidth mode
200
kHz
Low bandwidth mode
25
mV/μs
High bandwidth mode
kHz
90
mV/μs
High bandwidth, Low cap-drive mode (see Table 11)
400
pF
Low bandwidth, High cap-drive mode (see Table 11)
8
nF
Low bandwidth, Low cap-drive mode
20
36
μA
High bandwidth, High cap-drive mode
60
91
μA
RIGHT LEG DRIVE REFERENCE
RLDREF
Output Voltage
(VDDVSS)/2.2
Unloaded
V
COMMON-MODE DETECTOR AMPLIFIER (CMDET Amp)
CMVR
Common-Mode Voltage Range
BW
Programmable Bandwidth
SR
ClMAX
IVDD
Slew Rate
Programmable Capacitive Load
Driving Capability
Power Consumption (Selected Leads)
VDD0.5
0.5
V
Low bandwidth mode
50
High bandwidth mode
150
kHz
Low bandwidth mode
25
mV/μs
90
mV/μs
400
pF
High bandwidth mode
High bandwidth mode, Low capdrive mode (see Table 10)
Low bandwidth mode, High cap- drive mode (see Table 10)
kHz
8
nF
N leads, low bandwidth mode, low cap-drive mode
21+3*N
μA
N leads, high bandwidth mode, high cap-drive mode
61+3*N
μA
WILSON REFERENCE CIRCUIT
VDD0.5
IVR
Input Voltage Range
0.5
V
BW
Bandwidth
3 buffers ON
50
kHz
SR
Slew Rate
3 buffers ON
45
mV/μs
Ne
Noise Density
At 10Hz
60
nV/√Hz
Ve
Input-Referred Noise for Wilson
Reference Amp
0.1 - 200Hz, 3 buffers ON
5.5
μVPP
IVDD
Power Consumption (Selected Leads)
N leads, low power mode
7*N
μA
Programmable: Min. code 0x01
(See LEAD-OFF DETECTION (LOD))
8
nA
Programmable: Max. code 0xFF
(See LEAD-OFF DETECTION (LOD))
2040
nA
LEAD OFF DETECTION
IEXC
IEXCTOL
FEXC
Excitation Current
Excitation Current Accuracy
Excitation Frequency
25
%
AC LOD mode, programmable, minimum
(see Analog AC Lead-Off Detect )
6.1
Hz
AC LOD mode, programmable, maximum
(see Analog AC Lead-Off Detect)
12.5
kHz
VDD 0.5
VTHDC
DC Lead Off Comparator Threshold
V
VHYST
Comparator Hysteresis
DC lead off mode
55
mV
IVDD
Current Consumption
Programmed excl. excitation current
25
μA
7
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ELECTRICAL CHARACTERISTICS(1) (continued)
Unless otherwise noted, all limits are specified at TA = +25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65V ≤ VDDIO ≤ MIN(+3.6V, VDD),
VREF = +2.4V, fOSC = 409.6kHz, 1µF low ESR capacitor between CVREF and GND, 0.1µF capacitor between RLDREF and
GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
UNIT
ANALOG PACE CHANNEL
BW
Gain
3.5
V/V
-3dB Bandwidth
50
kHz
Output Reference
RLDREF
V
VOS
Input-Referred Offset Voltage
±1.3
DIVR
Differential Input Voltage Range
CMVR
Common-Mode Voltage Range for full
DIVR
CMRR
Common-Mode Rejection Ratio
0.5V ≤ VCM ≤ VDD-1.5V
85
PSRR
Power Supply Rejection Ratio
3V ≤ VDD ≤ 5V, VCM=RLDREF
80
dB
SR
Slew Rate
35
mV/µs
2.7V ≤ VDD < 3.3V
-330
330
mV
3.3V ≤ VDD
-400
400
mV
0.95
VDD 1.1
Overload Recovery
Ve-APACE
Input-Referred Noise for Analog Pace
IVDD
Current Consumption
mV
VCM = RLDREF, 0.1kHz - 20kHz
V
dB
100
µs
105
µVPP
29
µA
409.6
kHz
CLOCK
fOSC
Internal Clock Frequency
fCRYSTAL = 4.096MHz
Internal Clock Duty Cycle
fCRYSTAL = 4.096MHz
50
%
15
ms
TSTART
Internal Clock Start up Time
IVDD
Internal Clock Power Consumption
fEXT
External Clock Frequency (5)
370
409.6
450
External Clock Duty Cycle (5)
40%
50%
60%
83
µA
kHz
DIGITAL INPUT/OUTPUT CHARACTERISTICS
VIH
Logical “1” Input Voltage
VIL
Logical “0” Input Voltage
VOH
Logical “1” Output Voltage
VOL
Logical “0” Output Voltage
IIOHL
Digital IO Leakage Current
0.8x
VDDIO
0.2x
VDDIO
ISOURCE = 400 µA, Digital output high drive mode
VDDIO0.075
ISOURCE = 400 µA, Digital output low drive mode
VDDIO0.15
V
V
ISINK = 400 µA Digital output high drive mode
VSSIO
+ 0.075
V
ISINK = 400 µA Digital output low drive mode
VSSIO
+ 0.15
V
SYNCB and RESETB pins, with 1 MΩ internal pull-up
resistor
Other digital I/O pins
(5)
V
±1
µA
±500
nA
Specified by design; not production tested.
8
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TIMING DIAGRAMS
Unless otherwise noted, all limits specified at TA = 25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65 ≤ VDDIO ≤ MIN(+3.6V,
VDD), VREF = +2.4V, fOSC = 409.6kHz and a 10pF capacitive load in parallel with a 10kΩ load on SDO.
Figure 1. Write Timing Diagram
PARAMETER
CONDITIONS
MIN
TYP
MAX
20
UNITS
FSCLK
Serial Clock Frequency
MHz
tPH
SCLK Pulse Width - High
FSCLK = 20MHz
0.4/FSCLK
tPL
SCLK Pulse Width - Low
FSCLK = 20MHz
0.4/FSCLK
s
tSU
SDI Setup Time
5
ns
tH
SDI Hold Time
5
ns
s
Figure 2. Read Timing Diagram
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tODZ
SDO Driven-to-Tristate Time
Measured at 10% / 90% point
15
ns
tOZD
SDO Tristate-to-Driven Time
Measured at 10% / 90% point
15
ns
tOD
SDO Output Delay Time
10
ns
tCSS
CSB Setup Time
5
ns
tCSH
CSB Hold Time
5
ns
tIAG
Inter-Access Gap
10
ns
tDRDYB
Data Ready Bar at every 1/ODR second, see
Figure 25
4/fOSC
s
9
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TYPICAL CHARACTERISTICS
All plots at TA = +25°C, VDD = +3.3V, VDDIO = +1.8V, VSS = VSSIO = 0V, internal VREF = +2.4V, VCM = RLDREF, internal
fOSC = 409.6kHz, data rate = 1067sps, and High-Resolution mode, unless otherwise noted.
VOS vs VDD
VOS vs VCM
30
Input-Referred Offset Voltage (µV)
Input-Referred Offset Voltage (µV)
30
25
20
15
10
5
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
TA = +25°C
TA = -20°C
20
15
10
TA = +85°C
5
0
0.25
5.5
Analog Supply Voltage (V)
25
0.65
1.05
1.45
1.85
2.25
2.65
Common-Mode Voltage (V)
C00
Figure 3.
3.05
C01
Figure 4.
VOS DISTRIBUTION
VREF vs VDD
1800
2.396
Data from 1325 devices, three lots
2.3955
VDD = +5.5V
VDDIO = +3.3V
Internal Reference (V)
Occurrences
1500
1200
900
600
300
2.395
TA = -20°C
TA = +25°C
2.3945
2.394
2.3935
2.393
TA = +85°C
2.3925
2.392
50
41
32
23
14
5
-4
-13
-22
-40
0
-31
VCM = +0.5V
2.7
3.1
3.5
Input-Referred Offset Voltage (µV)
3.9
4.3
4.7
5.1
Analog Supply Voltage (V)
5.5
C01
C01
Figure 5.
Figure 6.
IBIAS vs VIN DIFF
1.00
100
0.95
Input Bias Current (nA)
Input Bias Current (pA)
IBIAS vs VIN DIFF
150
50
TA = 25°C
0
-50
TA = -20°C
-100
0.90
0.85
0.80
0.75
0.70
TA = +85°C
-150
0.65
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
Differential Input Voltage (V)
0.3
0.4
-0.4
C01
Figure 7.
-0.3
-0.2
-0.1
0
0.1
0.2
Differential Input Voltage (V)
0.3
0.4
C01
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
All plots at TA = +25°C, VDD = +3.3V, VDDIO = +1.8V, VSS = VSSIO = 0V, internal VREF = +2.4V, VCM = RLDREF, internal
fOSC = 409.6kHz, data rate = 1067sps, and High-Resolution mode, unless otherwise noted.
IBIAS vs VCM
IBIAS vs VCM
140
1.00
TA = +25°C
0.95
Input Bias Current (nA)
100
TA = -20°C
80
60
40
0.90
0.85
0.80
0.75
20
0.70
TA = +85°C
VIN DIFF = ±400mV
VIN DIFF = ±400mV
0
0.95
1.15
1.35
1.55
1.75
1.95
2.15
Common-Mode Voltage (V)
0.65
0.95
2.35
1.15
1.35
Figure 9.
PSRR vs FREQUENCY
1.95
2.15
2.35
C01
CMRR vs FREQUENCY
120
Common-Mode Rejection Ratio (dB)
VDD = +5.0V
110
100
90
VDD = +3.3V
80
Data Rate = 6.4ksps
VCM = +0.5V
70
110
+85°C
100
+25°C
90
VDDIO = +3.3V
Data Rate = 6.4ksps
VCMDC = +1.65V
VCMAC = +2.75VPP
80
-20°C
70
10
100
1k
Frequency (Hz)
10
100
1k
Frequency (Hz)
C00
Figure 11.
C00
Figure 12.
INPUT-REFERRED NOISE
NOISE HISTOGRAM
3500
15
VDDIO = +3.3V
VDDIO = +3.3V
3000
10
2500
Occurrences
5
0
-5
2000
1500
1000
-10
Time (s)
7
8
9
10
C00
12
6
10.2
5
8.4
4
6.6
3
4.8
2
-0.6
1
-2.4
0
-4.2
0
-15
-6
500
3
Power-Supply Rejection Ratio (dB)
1.75
Figure 10.
120
Input-Referred Noise (µV)
1.55
Common-Mode Voltage (V)
C01
1.2
Input Bias Current (pA)
120
Input-Referred Noise (µV)
C00
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
All plots at TA = +25°C, VDD = +3.3V, VDDIO = +1.8V, VSS = VSSIO = 0V, internal VREF = +2.4V, VCM = RLDREF, internal
fOSC = 409.6kHz, data rate = 1067sps, and High-Resolution mode, unless otherwise noted.
FFT PLOT ECG CHANNEL
(50Hz Signal)
FFT PLOT PACE CHANNEL
(50Hz Signal)
0
0
Data Rate = 1067SPS
ECG BW = 215Hz
VDDIO = +3.3V
-20
-40
Amplitude (dBFS)
Amplitude (dBFS)
-40
Data Rate = 25.6kSPS
PACE BW = 2550Hz
VDDIO = +3.3V
-20
-60
-80
-100
-120
-60
-80
-100
-120
-140
-140
-160
-160
-180
-180
0
40
80
120
Frequency (Hz)
160
200
240
0
C00
Figure 15.
400
800
1200
1600
Frequency (Hz)
2000
2400
C00
Figure 16.
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FUNCTIONAL DESCRIPTION
The ADS1293 is a fully integrated signal chain for ECG applications. It features three low-power, 24-bit resolution
channels for ECG and pace monitoring and an auxiliary fourth channel for analog pace detection. In addition, the
ADS1293 features AC and DC lead-off detection, right leg drive capability, and Wilson and Goldberger terminals.
Each of the three channels is synchronized and provides digital filtering with a cut-off frequency that is
programmable from 5Hz to 1280Hz. Each channel filter can be set independently while maintaining
synchronization. In addition, a lower resolution output is provided for each signal channel with a cut-off frequency
programmable between 650Hz to 2.6kHz. These output signals are ideal for sensing a pace-maker signal. Each
channel provides enough dynamic range to handle electrode offset and motion artifacts without sacrificing
resolution. Each input has built-in EMI rejection that eliminates noise from RF transmitters.
FLEXIBLE ROUTING SWITCH
The flexible routing switch can connect the inputs of the three analog front end channels as well as the inputs of
the analog pace channel to any of the 6 input pins. This allows system flexibility and even on-the-fly
reconfiguration of the ECG monitoring system. For test purposes, the flexible routing switch can short the
differential input pins of a channel or connect a differential reference signal to the input of a channel. This
reference voltage can be applied with both positive and negative polarity. This feature allows to measure relative
mismatches between channels, such as offset and gain mismatches. Additionally, there is an option to route a
fraction of the battery voltage (the voltage source connected to the VDD pin) to an input channel. This allows the
ADS1293 to monitor the state of charge of the battery.
The switch path inside the flexible routing switch is illustrated in Figure 17. The figure shows the switch path for a
single channel. All channels are completely identical. The switches are controlled by the registers
FLEX_CH1_CN, FLEX_CH2_CN, FLEX_CH3_CN, and FLEX_VBAT_CN, which are described in the Input
Channel Selection Registers.
POSx
IN1
IN2
IN3
INP_CHx
IN4
IN5
IN6
TSTx=01
VREFP
VDD
CALx=11
VBAT_MONI_CHx
NEGx
CVREF
VREFN
TSTx=10
INN_CHx
Figure 17. Flexible Routing Switch for Channel 1
It should be noted that the switches that control the input selection for the analog front end channels have a
certain priority. If the battery voltage monitoring mode is enabled by programming the VBAT_MONI_CHx bit in
the FLEX_VBAT_CN register, then the POSx and NEGx bits programmed in the FLEX_CHx_CN register no
longer have any effect. The battery voltage monitoring mode thus takes priority; this is shown in the first row of
Table 3. Furthermore, the test features take second priority over the input pin selection. If the TSTx bit of the
FLEX_CHx_CN register are not zero, then the POSx and NEGx bits are essentially ignored, and the test features
will take priority as seen in Table 3. The TSTx, POSx, and NEGx bits are described in the Input Channel
Selection Registers.
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Table 3. Channel 1 Switch Configuration
VBAT_MONI_
CHx
CALx
POSx
NEGx
1
X
X
X
CHx is in battery voltage monitoring mode
0
11
X
X
CHx input shorted
0
01
X
X
CHx input connected to positive reference
0
10
X
X
CHx input connected to negative reference
0
00
INx
INy
Mode
CHx positive input connected to pin INx and negative input connected to pin INy
Battery Monitoring
The battery voltage monitoring mode is enabled by setting bit VBAT_MONI_CHx = 1 in the FLEX_VBAT_CN
register. Also, the instrumentation amplifier of the selected channel must be shut down by setting
SHDN_INA_CHx = 1 in the AFE_SHDN_CN register. In this mode, the positive input, POSx, of the sigma delta
modulator will sample the voltage supplied on the VDD pin. At the same time, the negative input, NEGx, of the
sigma delta modulator will sample the reference voltage, VREF, generated on or provided to the CVREF pin. As a
result, the output signal of the sigma delta modulator is a measure for (VBAT-VREF). In this operation, the sigma
delta modulator works with a modified gain factor, and the battery voltage,VBAT, can be calculated as follows:
8»ºÍ L 8˾¿ ds E uätvx l
#&%ÈÎÍ s
F ph
#&%ÆºÑ t
(1)
In this equation, VREF equals 2.4V if the internal reference voltage generator is used, and ADCMAX represents the
maximum output code of the ADC, which would correspond to a theoretical 2.4V signal at the input of the sigma
delta modulator. The value of ADCMAX is dependent on the configuration of the digital filters, and the
corresponding ADCMAX values are listed in Table 5 through Table 8.
The battery monitoring mode is targeted for battery operated systems within a voltage range of 2.4V to 4.8V. The
battery monitoring mode cannot be used when the ADS1293 is powered from a regulated 5V supply because it
risks saturating the sigma delta modulator. There is a also a low battery alarm that is implemented independently
from the battery monitoring mode, which will trigger a battery alarm when the supply voltage is below 2.7V (see
the BATLOW description in ALARM FUNCTIONS).
Test Mode
If the battery voltage monitoring function is not enabled, and if bit TSTx = 01 (see the Input Channel Selection
Registers section), then a positive DC test signal is provided to the input of the instrumentation amplifier. If TSTx
= 10, then that same test signal is provided but with negative polarity. The expected ADC output code can be
calculated as follows:
é 3.5 VTEST 1 ù
+ ú ADCMAX
ADCOUT = ê ±
2 VREF
2û
ë
(2)
In Equation 2, the positive or negative DC test signal VTEST = VREF/12. Note that this test mode is not a gain
calibration since VTEST and VREF are generated by the same reference; however, it can be used as a self-test or
to measure gain mismatches between channels.
When TSTx = 11, the inputs of the instrumentation amplifier in the channel can be shorted to provide a zero test
signal. The expected ADC output code equation can be simplified to:
1
ADCOUT =
ADCMAX
(3)
2
For both equations, the value of ADCMAX corresponding to a given decimation configuration can be obtained from
Table 5 through Table 8.
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ANALOG FRONT END
The ADS1293 contains three analog front ends that convert a differential analog voltage into a digital signal.
Each analog front end consists of an instrumentation amplifier (INA), a sigma-delta modulator (SDM), and a
digital filter.
Instrumentation Amplifier (INA)
The instrumentation amplifier provides a high input impedance to interface with signal sources that may have
relatively high output impedance, such as ECG electrodes. The maximum differential input voltage range of the
Sigma-Delta Modulator (SDM) behind the INA is ±1.4V, and the gain of the INA is 3.5x. Therefore, the maximum
differential input voltage of the INA is ±400mV.
The input common-mode voltage range (CMVR) of the INA is 0.95V to VDD-0.95V. If the input differential voltage
range is limited to smaller values, then the CMVR can be somewhat extended. If the differential input signal is
limited to VINMAX, the CMVR range can be defined as:
:säyw Û 8+0ÆºÑ E rätw; Q %/84 Q :8&& F rätw F säyw Û 8+0ÆºÑ ;
(4)
The INA can be configured to operate in a low-power mode or in a high-resolution mode. The low-power mode
consumes about 3 times less power than the high-resolution mode. However, the high-resolution mode has less
noise than the low-power mode. Switching between these two modes is controlled by the EN_HIRES_CHx bits in
the AFE_RES register.
When a channel is not in use, its INA can be shut down by programming the SHDN_INA_CHx bit in the
AFE_SHDN_CN register, and its SDM can also be shut down by programming the SHDN_SDM_CHx bit in the
AFE_SHDN_CN register.
Instrumentation Amplifier Fault Detection
The output signal of the instrumentation amplifier can be monitored to ensure its output signal is within an
appropriate range. The out-of-range error flags for the INAs can be observed in the ERROR_RANGE1,
ERROR_RANGE2 and ERROR_RANGE3 registers.
The output signal is present at two points: OUTP and OUTN. If the input common-mode voltage or differential
voltage is such that the instrumentation amplifier would have to drive the voltages at these points above the
positive or below the negative supply rail, then the signal accuracy would be lost. These two points are monitored
and a warning flag is raised if the voltage on these pins approaches the supply rails. If the OUTP_HIGH flag is
raised, then the voltage at OUTP is close to the positive rail. This indicates the differential input signal is too
large or the input common-mode voltage is too high. If the OUTP_LOW flag is raised, then the voltage at OUTP
is close to the negative rail. This happens at low input common-mode voltages and large negative differential
input voltages. Similar reasoning holds for the OUTN_HIGH and OUTN_LOW flags.
The differential output voltage of the INA is monitored and reported to the DIF_HIGH bit. This error flag indicates
that the differential signal is out-of-range and is no longer an accurate representation of the input signal. The
DIF_HIGH error flag is raised if the differential output voltage of the INA exceeds ±1.4V, which is the input range
of the Delta-Sigma Modulator. When this happens, the SDM will no longer sample the output of the INA, but
instead will sample 0V. The sign of the input signal can still be observed in the SIGN bit of the ERROR_RANGEx
registers.
The fault detection circuitry for OUTP_HIGH, OUTP_LOW, OUTN_HIGH and OUTN_LOW can be shut down by
programming the SHDN_FAULTDET_CHx bits in the AFE_FAULT_CN register. These shutdown bits do not
affect the operation of DIF_HIGH and SIGN because the instrumentation amplifier should always provide these
signals to the sigma delta modulator. The circuitry that generates DIF_HIGH and SIGN only gets shut down
when the corresponding INA is shut down.
Sigma Delta Modulator (SDM)
The Sigma Delta Modulator (SDM) takes the output signal of the INA and converts this signal into a high
resolution bit stream that is further processed by the digital filters.
The SDM can operate at clock frequencies of 102.4kHz or 204.8kHz; these frequencies are generated internally.
Running the SDM at 204.8kHz results in a larger oversampling ratio, which improves the resolution of the signal
recovered by the digital filters behind the SDM. However, running the SDM at a higher clock frequency will
increase its power consumption, resulting in a trade-off between resolution and power consumption.
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The 102.4kHz or 204.8kHz clock frequency can be selected for each channel individually by programming the
FS_HIGH_CHx bits in the AFE_RES register.
The SDM also features dithering to reduce tones in the system, a known by-product of Sigma Delta converters.
The dithering circuit is active by default and is automatically turned OFF when the input signal is larger than
40mV.
Sigma Delta Modulator Fault Detection
The state of the integrators in the Sigma Delta Modulator (SDM) are monitored to detect over-range signals that
cause the SDM to become unstable. When an over-range event is detected in the SDM, the state of its
integrators is reset, and the over-range error is reported to the SDM_OR_CHx bits of the ERROR_RANGE1,
ERROR_RANGE2 and ERROR_RANGE3 registers.
Programmable Digital Filters
A programmable digital filter behind the Sigma Delta Modulator (SDM) reconstructs the signal from the SDM
output bit stream. The filter consist of three programmable SINC filters as shown in Figure 18. Each stage is a
fifth order SINC filter.
Figure 18. SINC Filters
The decimation rates (R1, R2, and R3) of the SINC filters are programmable as described in Table 4. Each of
the three stages further filters and decimates the bit stream so that the output data rate (ODR) and bandwidth
(BW) of the signal is reduced, and at the same time, the resolution is enhanced. A 16-bit digital signal with
relatively high ODR and BW, but with somewhat limited resolution, is available after the second stage; this signal
can be used for PACE pulse detection. That signal is further decimated by the third stage and results in a very
high resolution filtered 24-bit digital signal that is an accurate representation of the ECG signal.
Table 4. Programmable Digital Filter Coefficients
Stage 1 (R1)
Stage 2 (R2)
Stage 3 (R3)
4 (Standard PACE Data Rate), 2 (Double PACE Data Rate)
4,5,6,8
4,6,8,12,16,32,64,128
The first stage sets the Standard PACE Data Rate (where the decimation rate R1 = 4) or the Double PACE Data
Rate (where R1 = 2). Operating the device in the Double PACE Data Rate will double the ODR for the first stage
(and therefore also for the subsequent stages). However, the BW of the first stage does not change in this mode;
only the ODR is affected. By operating the device in the Double PACE Data Rate, the ODR of the PACE data is
doubled, and thus, more accurate PACE pulse detection is possible. However, operating the device in the
Double PACE Data Rate will increase its power consumption. The R1 decimation rate can be programmed for
each of the three channels separately by using the R1_RATE register.
Programming the second stage (R2) to a low decimation rate sets a relatively high ODR and BW, but doing so
will also increase the noise level. For digital PACE pulse detection, smalle values for R2 are recommended. The
R2 decimation rate can be programmed using the R2_RATE register.
As the third stage decimation (R3) increases, the ODR and BW of the ECG decreases. When detecting an ECG
signal, higher values of R3 are recommended. The R3 decimation rate for each channel can be individually
programmed using the R3_RATE_CH1, R3_RATE_CH2, and R3_RATE_CH3 registers.
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Table 5, Table 6, Table 7, and Table 8 illustrate how these decimation rates R1, R2, and R3 affect the ODR, BW,
and RMS Noise of the PACE and ECG signals. In addition, the ODR and BW also depend on whether the SDM
is running at a low (102.4kHz) or high (204.8kHz) clock frequency (set by the FS_HIGH_CHx bits in the
AFE_RES register). The RMS Noise of the PACE and ECG channels also depend on whether the
instrumentation amplifier is running in low power or high resolution mode (set by the EN_HIRES bits in the
AFE_RES register).
In summary, the output data rate of an ECG channel can be calculated as follows:
fS
ODRECG =
R1 R2 R3
(5)
And the output data rate of a PACE channel can be calculated as follows:
fS
ODRPACE =
R1 R2
(6)
Where fS is the clock frequency of the modulator: 102.4kHz, or 204.8kHz.
Filter Settling Time
The low-pass filter frequency responses of the ECG and Pace SINC filters result in a settling time associated
with their outputs as a response to a step input signal. This settling time is determined by the order of the filter,
N, its differential delay, M, and the channel output data rate, ODR:
ts = N × M / ODR
(7)
The ODR of the filter is a function of the sigma-delta's sampling frequency, fS, and the filter decimation rates. The
value of the ODR can be calculated using Equation 5 and Equation 6. For an ECG channel, the value of NxM =
5. For a Pace channel NxM = 5 when operated in the Standard Pace Data Rate (R1 = 4), and NxM = 10 when
operated in the Double Pace Data Rate (R1 = 2).
As a result, an unclamped pace signal applied to the filter input results in an ECG channel minimum settling time
of:
tS-ECG = 5 × R1 × R2 × R3 / fS
(8)
A Standard Pace Data Rate operated Pace channel will go through a minimum settling time of:
tS-PACE = 5 × R1 × R2 /fS
(9)
And a Double Pace Data Rate operated Pace channel will go through a minimum settling time of:
tS-PACE = 10 × R1 × R2 / fS
(10)
Ouput Code (ADCOUT)
The ADCOUT of the ADS1293 is due to a differential voltage applied between the positive and negative input
terminals of the instrumentation amplifier and can be calculated with Equation 11:
é 3.5 VINP - VINM 1 ù
+ ú ADCMAX
ADCOUT = ê
2 VREF
2û
ë
(11)
The reference voltage VREF, equals to 2.4V if the on-chip voltage reference is used. ADCMAX represents the
maximum output code of the ADC, which corresponds to a theoretical 2.4V signal at the input of the SDM. The
value of ADCMAX changes with the configuration of the digital filters, and the corresponding value can be found in
Table 5, Table 6, Table 7, and Table 8. Note that ADCOUT equals ADCMAX/2 for a 0V differential input.
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Output Data Rate, Bandiwdth and Noise Tables
Table 5. Channel Parameters with SDM running at 102.4kHz and at Standard PACE Data Rate (R1 = 4) (1)
PACE CHANNEL
R2
4
5
6
8
(1)
R3
BW
[Hz]
RMS
Noise
[mV]
ADCMAX
ODR
[Hz]
BW
[Hz]
4
0x800000
1600
6
0xF30000
1067
8
0x800000
ADCMAX
ODR
[Hz]
ECG CHANNEL
RMS noise
Low Pwr
[µV]
High Res
[µV]
325
4.47
4.16
215
3.42
3.05
800
160
2.92
2.57
0xF30000
533
105
2.37
2.07
0x800000
400
80
2.06
1.81
32
0x800000
200
40
1.50
1.29
12
16
0x8000
6400
1300
1.612
64
0x800000
100
20
1.12
0.94
128
0x800000
50
10
0.85
0.70
4
0xC35000
1280
260
3.82
3.42
6
0xB964F0
853
175
3.02
2.67
8
0xC35000
640
130
2.60
2.29
12
0xB964F0
427
85
2.13
1.86
0xC35000
320
65
1.86
1.62
32
0xC35000
160
32
1.36
1.16
64
0xC35000
80
16
1.02
0.85
128
0xC35000
40
8
0.79
0.64
4
0xF30000
1067
215
3.41
3.04
6
0xE6A900
711
145
2.74
2.42
8
0xF30000
533
110
2.38
2.07
0xE6A900
356
70
1.96
1.70
0xF30000
267
55
1.71
1.48
32
0xF30000
133
27
1.25
1.07
64
0xF30000
67
13
0.94
0.79
128
0xF30000
33
7
0.74
0.60
4
0x800000
800
160
2.91
2.58
6
0xF30000
533
110
2.37
2.08
8
0x800000
400
80
2.08
1.79
12
0xF30000
267
55
1.71
1.48
0x800000
200
40
1.50
1.29
32
0x800000
100
20
1.12
0.94
64
0x800000
50
10
0.85
0.70
128
0x800000
25
5
0.68
0.54
16
12
16
16
0xC350
0xF300
0x8000
5120
4267
3200
1040
870
650
0.572
0.238
0.060
10000 consecutive readings were used to calculat the RMS noise values in this table.
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Table 6. Channel Parameters with SDM running at 102.4kHz and at Double PACE Data Rate (R1 = 2) (1)
PACE CHANNEL
R2
4
5
6
8
(1)
R3
ODR
[Hz]
BW
[Hz]
4
0x800000
3200
6
0xF30000
8
0x800000
12
16
0x8000
12800
BW
[Hz]
RMS
noise
[mV]
ADCMAX
ADCMAX
ODR
[Hz]
ECG CHANNEL
1280
1.479
RMS noise
Low Pwr
[µV]
High Res
[µV]
640
38.17
37.92
2133
430
7.04
6.72
1600
320
4.35
3.93
0xF30000
1067
215
3.40
3.02
0x800000
800
160
2.92
2.57
32
0x800000
400
80
2.08
1.79
64
0x800000
200
40
1.49
1.29
128
0x800000
100
20
1.11
0.93
4
0xC35000
2560
510
12.64
12.38
6
0xB964F0
1707
340
4.53
4.12
8
0xC35000
1280
255
3.74
3.35
0xB964F0
853
170
3.01
2.65
0xC35000
640
130
2.59
2.28
32
0xC35000
320
65
1.86
1.62
12
16
0xC350
10240
1030
0.540
64
0xC35000
160
32
1.36
1.16
128
0xC35000
80
16
1.02
0.85
4
0xF30000
2133
420
6.20
5.88
6
0xE6A900
1422
285
3.94
3.57
8
0xF30000
1067
210
3.38
3.02
12
0xE6A900
711
140
2.74
2.42
0xF30000
533
105
2.37
2.07
32
0xF30000
267
55
1.70
1.47
64
0xF30000
133
26
1.26
1.07
128
0xF30000
67
13
0.95
0.78
4
0x800000
1600
320
4.14
3.73
6
0xF30000
1067
215
3.35
2.96
8
0x800000
800
160
2.89
2.54
12
0xF30000
533
110
2.37
2.07
16
16
0xF300
0x8000
8533
6400
860
650
0.228
0.058
0x800000
400
80
2.06
1.79
32
0x800000
200
40
1.50
1.29
64
0x800000
100
20
1.11
0.94
128
0x800000
50
10
0.85
0.70
10000 consecutive readings were used to calculat the RMS noise values in this table.
19
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Table 7. Channel Parameters with SDM running at 204.8kHz and at Standard PACE Data Rate (R1 = 4) (1)
PACE CHANNEL
R2
4
5
6
8
(1)
R3
ODR
[Hz]
BW
[Hz]
4
0x800000
3200
6
0xF30000
8
0x800000
12
16
0x8000
12800
BW
[Hz]
RMS
noise
[mV]
ADCMAX
ADCMAX
ODR
[Hz]
ECG CHANNEL
2600
1.738
RMS noise
Low Pwr
[µV]
High Res
[µV]
640
5.20
4.59
2133
430
3.92
3.38
1600
325
3.32
2.86
0xF30000
1067
215
2.69
2.31
0x800000
800
160
2.34
1.99
32
0x800000
400
80
1.68
1.43
64
0x800000
200
40
1.25
1.04
128
0x800000
100
20
0.95
0.78
4
0xC35000
2560
520
4.36
3.81
6
0xB964F0
1707
350
3.44
2.96
8
0xC35000
1280
260
2.95
2.54
0xB964F0
853
170
2.41
2.06
0xC35000
640
130
2.10
1.79
32
0xC35000
320
65
1.53
1.29
12
16
0xC350
10240
2080
0.613
64
0xC35000
160
32
1.14
0.95
128
0xC35000
80
15
0.88
0.72
4
0xF30000
2133
430
3.91
3.38
6
0xE6A900
1422
290
3.12
2.68
8
0xF30000
1067
215
2.68
2.30
12
0xE6A900
711
140
2.21
1.88
0xF30000
533
110
1.93
1.64
32
0xF30000
267
55
1.41
1.18
64
0xF30000
133
27
1.06
0.88
128
0xF30000
67
13
0.83
0.68
4
0x800000
1600
325
3.32
2.86
6
0xF30000
1067
215
2.69
2.31
8
0x800000
800
160
2.34
2.00
12
0xF30000
533
105
1.93
1.64
16
16
0xF300
0x8000
8533
6400
1740
1300
0.256
0.064
0x800000
400
80
1.69
1.44
32
0x800000
200
40
1.25
1.04
64
0x800000
100
20
0.96
0.78
128
0x800000
50
10
0.76
0.61
10000 consecutive readings were used to calculat the RMS noise values in this table.
20
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Table 8. Channel Parameters with SDM running at 204.8kHz and at Double PACE Data Rate (R1 = 2) (1)
PACE CHANNEL
R2
4
5
6
8
(1)
R3
ODR
[Hz]
BW
[Hz]
4
0x800000
6400
6
0xF30000
8
0x800000
12
16
0x8000
25600
BW
[Hz]
RMS
noise
[mV]
ADCMAX
ADCMAX
ODR
[Hz]
ECG CHANNEL
2550
1.592
RMS noise
Low Pwr
[µV]
High Res
[µV]
1280
41.27
40.81
4267
850
7.79
7.32
3200
640
4.97
4.35
0xF30000
2133
430
3.88
3.36
0x800000
1600
325
3.32
2.85
32
0x800000
800
160
2.34
1.98
64
0x800000
400
80
1.69
1.43
128
0x800000
200
40
1.25
1.04
4
0xC35000
5120
1020
13.57
13.38
6
0xB964F0
3413
680
5.18
4.56
8
0xC35000
2560
510
4.30
3.73
0xB964F0
1707
340
3.41
2.94
0xC35000
1280
260
2.94
2.53
32
0xC35000
640
130
2.10
1.79
12
16
0xC350
20480
2050
0.580
64
0xC35000
320
65
1.53
1.29
128
0xC35000
160
32
1.14
0.95
4
0xF30000
4267
850
6.99
6.43
6
0xE6A900
2844
570
4.53
3.94
8
0xF30000
2133
420
3.86
3.33
12
0xE6A900
1422
285
3.11
2.67
0xF30000
1067
215
2.69
2.29
32
0xF30000
533
110
1.93
1.64
64
0xF30000
267
55
1.41
1.18
128
0xF30000
133
26
1.06
0.88
4
0x800000
3200
640
4.74
4.15
6
0xF30000
2133
425
3.82
3.28
8
0x800000
1600
320
3.29
2.83
12
0xF30000
1067
215
2.68
2.30
16
16
0xF300
0x8000
17067
12800
1720
1300
0.245
0.062
0x800000
800
160
2.34
2.00
32
0x800000
400
80
1.69
1.42
64
0x800000
200
40
1.25
1.05
128
0x800000
100
20
0.95
0.79
10000 consecutive readings were used to calculat the RMS noise values in this table.
21
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ANALOG PACE CHANNEL
The ADS1293 features an additional analog pace channel to process pulses from a pace maker. The analog
pace channel is suitable for low power applications where the device can be configured for low data rates in ECG
mode only, while an analog channel detects PACE pulses. This channel consists of a traditional three opamp
instrumentation amplifier and is designed to amplify an ECG signal in a typical bandwidth, as specified in the
ELECTRICAL CHARACTERISTICS table, allowing for external circuitry to detect the PACE pulses. The analog
pace implementation inside the ADS1293 is depicted in Figure 19. The analog pace channel is not limited to
PACE detection; it is a full analog channel that could be used to pre-amplify signals, for instance, from a
respiration sensor.
The output voltage of the analog pace channel is:
Vpaceout = 3.5 × (Vinp – Vinm) + RLDREF
(12)
Where Vinp and Vinm are the positive and negative inputs of the analog pace channel. The input pins of this
channel can be selected in the FLEX_PACE_CN register and can connect to any of the IN1 through IN6 pins.
Note there is no battery monitoring option available through this channel. There is, however, the reference
voltage test mode available as described in Test Mode.
Figure 19. Analog Pace Channel Instrumentation Amplifier
The output of the analog pace channel can be multiplexed to the WCT or RLDIN pin using the AFE_PACE_CN
register. When PACE2RLDIN = 1, the output is routed to the RLDIN terminal, while internally the positive input of
the Right Leg Drive amplifier is connected to the RLDREF pin. When PACE2WCT = 1, the output is routed to the
WCT terminal, and the WCT terminal is disconnected from the Wilson output. In this case, the Wilson output can
still be connected internally to the IN6 pin using the WILSON_CN register. The analog pace channel is disabled
when SHDN_PACE = 1 to save power when it is not used.
The analog pace channel is designed to drive a high pass filter and can directly drive a capacitive load of 100pF.
For analog pace detection, it is recommended to have a band pass filter at the output of the analog pace
channel, amplify the resulting signal with a relatively high bandwidth amplifier, and compare the amplified pulses
with a relatively high speed window comparator. The bandwidth of the band pass filter, gain of the amplification,
and the thresholds of the window comparator should be tuned so the comparators trigger on pacemaker pulses,
but not to other signals present in the ECG environment.
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WILSON REFERENCE
The ADS1293 features a Wilson reference block consisting of three buffer amplifiers and resistors that can
generate the voltages for the Wilson Central Terminal or Goldberger terminals. Each of the three buffer amplifiers
can be connected to any input pin, IN1 through IN6, by programming the WILSON_EN1, WILSON_EN2, and
WILSON_EN3 registers. A buffer that is not connected to an input pin is automatically disabled. When disabled,
the buffers have a high output impedance.
SELWILSON1
001
010
011
100
101
110
000
enable
200kΩ
PACE2WCT
WCT
BUF1
SELWILSON2
IN1
IN2
IN3
IN4
IN5
IN6
001
010
011
100
101
110
000
enable
200kΩ
WCTOUT
BUF2
SELWILSON3
001
010
011
100
101
110
000
enable
200kΩ
BUF3
200kΩ
200kΩ
200kΩ
200kΩ
200kΩ
200kΩ
WILSONINT
GOLDINT
G1
G2
G3
Figure 20. Wilson Reference Generator Circuit
The output of the Wilson Reference can be routed internally to IN6, and the outputs of the Goldberger reference
can be routed internally to IN4, IN5 and IN6. This is configured in the WILSON_CN register. If routed externally,
it is strongly recommended to shield these connections, which due to their high output impedance, are prone to
pick up external interference.
Wilson Central Terminal
There are three main ECG leads that are measured differentially:
• Lead I: I = LA - RA
• Lead II: II = LL - RA
• Lead III: III = LL - LA
Where LA is the left arm electrode, LL is the left leg electrode, and RA is the right arm electrode.
In a standard 5-lead or 12-lead ECG, the Wilson Central Terminal is used as the reference voltage for the chest
electrodes, which are measured differentially against this reference. The Wilson Central Terminal is defined as
the average of the three limb electrodes, RA, LA and LL:
Wilson Central Terminal = (RA + LA + LL)/3
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The output of Wilson Central Terminal generated by the ADS1293, as seen in Figure 20, is defined as:
WCTOUT = (BUF1 + BUF2 + BUF3)/3
The user could program the WILSON_EN1 register to connect the RA electrode to BUF1, program the
WILSON_EN2 register to connect the LA electrode to BUF2, and program the WILSON_EN3 register to connect
the LL electrode to BUF3.
When the Wilson reference is enabled, its output is present at the WCT pin, except when the analog pace
channel is routed to the WCT pin (see ANALOG PACE CHANNEL). In such a configuration, the Wilson terminal
can still be made available at an external pin by programming the WILSONINT bit to 1. Setting this bit connects
the output of the Wilson reference internally to the IN6 pin.
Goldberger Terminals
Augmented leads in 3-lead, 5-lead or 12-lead ECG are typically calculated digitally based on the measurement
results of Lead I and Lead II. The augmented leads are defined as:
• aVR = -(I + II)/2 = RA - (LA + LL)/2 = RA - G1
• aVL = I - II/2 = LA - (RA + LL)/2 = LA - G2
• aVF = II - I/2 = LL - (RA + LA)/2 = LL - G3
Augmented leads can also be measured directly with the Goldberger terminals to give the best SNR. The
Goldberger terminals generated by the ADS1293, as seen in Figure 20, are defined as:
• G1 = (BUF2 + BUF3)/2
• G2 = (BUF1 + BUF3)/2
• G3 = (BUF1 + BUF2)/2
In this case, the user must program the WILSON_EN1 register to connect the RA electrode to BUF1, program
the WILSON_EN2 register to connect the LA electrode to BUF2, and program the WILSON_EN3 register to
connect the LL electrode to BUF3.
The Goldberger output terminals, G1, G2 and G3 can be made available on external pins programming the
GOLDINT bit to 1. Setting this bit connects the Goldberger terminals internally to the IN4, IN5 and IN6 pins.
• IN4 = G1
• IN5 = G2
• IN6 = G3
Note that multiple ADS1293 chips are required if both the augmented leads and the three basic leads need to be
converted directly.
The WILSONINT and GOLDINT bits must not be programmed to 1 simultaneously because it will short-circuit the
Wilson output terminal and the third Goldberger output terminal. The options described in these sections are
summarized in Table 9.
Table 9. Wilson and Goldberger Reference control
TERMINAL OUTPUTS
GOLDINT
WILSONINT
PACE2WCT
WCT PIN
IN4 PIN
IN5 PIN
IN6 PIN
0
0
0
WCTOUT
General input
General input
General input
0
1
0
WCTOUT
General input
General input
WCTOUT
1
0
0
WCTOUT
(BUF2+BUF3)/2
(BUF1+BUF3)/2
(BUF1+BUF2)/2
1
1
X
Illegal
Illegal
Illegal
Illegal
0
0
1
Vpaceout
General input
General input
General input
0
1
1
Vpaceout
General input
General input
WCTOUT
1
0
1
Vpaceout
(BUF2+BUF3)/2
(BUF1+BUF3)/2
(BUF1+BUF2)/2
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COMMON-MODE (CM) DETECTOR
The Common-Mode Detector averages the voltage of up to six input pins. Its output can be used in a right leg
drive feedback circuit. The selection of the input pins that contribute to the average is configured in the
CMDET_EN register. The Common-Mode Detector is automatically disabled when no input pin is selected.
Figure 21. Common-Mode Detector Circuit
Cable Shield Driving
The Common-Mode Detector also has a programmable capacitive load driving capability of up to 8nF that allows
it to drive a cable shield to reduce the common-mode signal current through a cable. This effectively increases
the bandwidth of the filter formed by the electrode impedance and the cable capacitance, reducing the amount of
common-mode to differential mode crosstalk. As a result, the CMRR of the overall ECG system is improved.
The bandwidth and capacitive load driving capability of the Common-Mode Detector can be configured in the
CMDET_CN register to achieve an optimal tradeoff with power consumption. Table 10 lists the power
consumption corresponding to different configuration scenarios given that all inputs are enabled by setting the
CMDET_EN register = 0x3F.
The lowest current consumption setting can be used when the Common-Mode Detector is only used to drive the
Right Leg Driver, and no cable shield is driven. If a cable shield needs to be driven, the power can be increased
to drive the cable capacitance depending on the number and type of the driven cable shields. Note that the
capacitive driving capability is reduced in the higher bandwidth mode.
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Table 10. Typical Common-Mode Detector Bandwidth, Capacitive Drive and
Power Consumption
CMDET_BW
CMDET_CAPDRIVE
BW
(kHz)
CLOAD
(nF)
CMDET ISUPPLY
(µA)
0: Low BW mode
00: Low Cap Drive
50
2
39
0: Low BW mode
01: Medium Low Cap Drive
50
3.3
45
0: Low BW mode
10: Medium High Cap Drive
50
4.5
56
0: Low BW mode
11: High Cap Drive
50
8
75
1: High BW mode
00: Low Cap Drive
150
0.4
43
1: High BW mode
01: Medium Low Cap Drive
150
0.65
49
1: High BW mode
10: Medium High Cap Drive
150
1
60
1: High BW mode
11: High Cap Drive
150
1.6
79
Common-Mode Output Range (CMOR)
The Common-Mode Detector incorporates an out-of-range alarm to sense if the common-mode voltage is outside
of the common-mode voltage range of the ADS1293. A Common-Mode Out-of-Range Alarm is created in the
CMOR bit of the ERROR_STATUS register when the common-mode drops below 0.75V or exceeds VDD-0.75V.
System alarms are filtered by the digital circuitry (see ERROR FILTERING), and for this reason, the master clock
must be active in order to capture an alarm.
RIGHT LEG DRIVE (RLD)
The RLD is a programmable operational amplifier that is intended to control the common-mode level of the
patient connected through electrodes to the ADS1293 and thereby improving the AC CMRR of the overall ECG
system. In a typical ADS1293 application, the common-mode level of the patient's body is measured by the
Common-Mode Detector described in the previous section. The CMOUT is compared by the RLD to the
reference voltage present on the RLDREF pin. When used in an inverting amplifier topology, the right leg
electrode is driven by the RLD to counter any differences between the reference voltage and the detected
common-mode level. This reduces the amount of power-line common-mode interference.
Figure 22. Right Leg-Drive Circuit
The negative input terminal of the RLD op-amp is always connected to the RLDINV pin. By default, the positive
input terminal of the RLD op-amp is routed to the RLDIN pin. However, when bit PACE2RLDIN = 1 in the
AFE_PACE_CN register, the positive input terminal is routed to the internally to the RLD reference. This will
allow connecting the output of the analog pace instrumentation amplifier to the RLDIN pin. The output of the RLD
op-amp is always connected to the RLDOUT pin, and in addition, can be connected to one of the IN1-IN6
terminals by programming the SELRLD bit in the RLD_CN register. The RLD circuit can be shut down in the
same register by setting bit SHDN_RLD = 1.
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Capacitive Load Driving
The bandwidth and capacitive load driving capability of the RLD can be configured in the RLD_CN register to
achieve an optimal tradeoff of power consumption. Table 11 lists the power consumption corresponding to
different configuration scenarios.
Table 11. Typical Right Leg Drive Bandwidth, Capacitive Drive and Power Consumption
RLD_BW
RLD_CAPDRIVE
GBW
(kHz)
CLOAD
(nF)
RLD ISUPPLY
(µA)
0: Low BW mode
00: Low Cap Drive
50
2
20
0: Low BW mode
01: Medium Low Cap Drive
50
3.3
25
0: Low BW mode
10: Medium High Cap Drive
50
4.5
36
0: Low BW mode
11: High Cap Drive
50
8
55
1: High BW mode
00: Low Cap Drive
200
0.4
23
1: High BW mode
01: Medium Low Cap Drive
200
0.65
29
1: High BW mode
10: Medium High Cap Drive
200
1
39
1: High BW mode
11: High Cap Drive
200
1.6
60
Error Status: RLD Rail
The RLD amplifier incorporates a near to rail alarm function that is triggered when the output of the op-amp is
below 0.2V or above VDD-0.2V. The alarm is reported to the RLDRAIL bit in the ERROR_STATUS register and
indicates that the RLD's feedback loop has difficulty maintaining a constant voltage on the patient’s body. In this
case, the common-mode on the patient’s body may drift away from its target value, but it may still be within the
proper input common-mode voltage range of the ADS1293, and the ECG signal data acquisition can continue.
When the common-mode on the patient’s body is outside the operation range of the ADS1293, the CMOR error
will be raised, as described in the previous section. System alarms are filtered by the digital circuitry (see
ERROR FILTERING) , and for this reason, the master clock must be active in order to capture an alarm.
LEAD-OFF DETECTION (LOD)
The lead-off detect (LOD) block of the ADS1293 can be used to monitor the connectivity of the 6 input pins to
electrodes. The LOD block injects a programmable DC or AC excitation current into selected input pins and
detects the voltages that appear on the input pins in response to that current. If a lead is not making a proper
contact, then the electrode impedance will be high, and as a result, the voltage in response to a small test
current will be relatively large, while the voltage for a well-connected lead will be small.
The LOD block can work in one of the three following modes: 1) DC lead-off detect, 2) analog AC lead-off detect
or 3) digital AC lead-off detect. All three LOD modes use a common DAC that provides a programmable
reference current. This reference current is used to set the magnitude of the test current for lead-off detection.
The amplitude of the excitation current used for lead-off detection can be programmed in the LOD_CURRENT
register, where codes 0 to 255 result in currents ranging from 0 to 2.040µA in steps of 8nA.
The complete LOD block can be shut down by programming the SHDN_LOD bit to 1 in the LOD_CN register.
DC Lead-Off Detect
The LOD block can be configured for DC LOD mode by programming a 0 in the SELAC_LOD bit of the LOD_CN
register. In the DC LOD mode, a DC test current can be injected into any of the six input pins by setting the
corresponding bit EN_LOD[x] of the LOD_EN register. Programming a bit to 1 in this register enables a switch
that allows a copy of the current programmed into the DAC to be injected into the desired input pins, as shown in
the simplified block diagram of Figure 23.
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Figure 23. Simplified DC Lead-off Detect Block Diagram
For the selected input pins, a Schmitt-trigger comparator then compares the voltage that appears on the pin to
(VDD-0.5V). The result of this comparison can be accessed through the corresponding OUT_LOD[x] bit of the
ERROR_LOD register. If a lead is off, then the injected current has no return path to ground, and as a result, the
voltage on the associated input pin will rise towards VDD. This is detected by the comparator and is used as a
signal to indicates the lead is not properly connected.
It is important to note that the lead-off detection circuit requires a low impedance return path from the right leg
electrode to ground, such as a voltage reference or the RLD amplifier output. Without a proper low impedance
return path for the LOD currents, all enabled LOD pins will report a lead disconnected.
Analog AC Lead-Off Detect
DC lead-off detection cannot be used when using capacitively coupled electrodes, such as dry electrodes,
because they have a high DC impedance that will block DC test currents. In this case, the analog AC LOD block
can be used. Contrary to the DC LOD, the AC LOD injects AC excitation currents with programmable amplitudes
and frequencies into the desired lead.
To operate the LOD in analog AC LOD mode, the SELAC_LOD and the ACAD_LOD bits of the LOD_CN register
must be set to 1.
A simplified block diagram of the analog AC LOD block is shown in Figure 25. The AC excitation frequency can
be programmed by a 7-bit number, ACDIV_LOD, and a division factor, ACDIV_FACTOR, in the LOD_AC_CN
register. The register sets the output frequency of the divider to a rate of:
Φ = 50/(4 × K × (ACDIV_LOD + 1)) kHz
(13)
Where K is 1 if the ACDIV_FACTOR bit equals 0, and K is 16 if the ACDIV_FACTOR bit equals 1. For instance,
ACDIV_LOD = 0 and ACDIV_FACTOR = 0 result in an excitation frequency of 12.5kHz, which is the maximum
excitation frequency.
Complimentary driven switches, enabled by the EN_LOD[x] bits of the LOD_EN register, sink and source the AC
excitation currents into the desired input pins. The resulting AC current has a frequency Φ and a peak-to-peak
amplitude equal to the current programmed into the DAC. An AC coupled synchronous detector detects the
amplitude of the AC voltage appearing on the lead. The detected amplitude is compared to a reference voltage
by means of a Schmitt-trigger comparator. The comparator’s reference voltage level, as shown in Figure 24, is
determined by a 2-bit reference DAC configured in the ACLVL_LOD bits of the LOD_CN register.
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1
Threshold Voltage (V)
Level 4
Level 3
Level 2
0.1
Level 1
0.01
500
1k
2k
3k 4k 5k
Excitation Frequency (Hz)
10k
C01
Figure 24. Analog AC Lead-Off reference levels
The comparator outputs can be accessed at the OUT_LOD[x] bit of the ERROR_LOD register. A high
comparator output signal indicates that the AC voltage at the excitation frequency is larger than the programmed
threshold, which indicates that the lead is not well connected.
The lead-off detection circuit requires a low impedance return path from the right leg electrode to ground, such
as a voltage reference or the RLD amplifier output. Without a proper low impedance return path for the LOD
currents, all enabled LOD pins will report a lead disconnected.
Figure 25. Simplified Analog AC Lead-off Detect Block Diagram
Digital AC Lead-Off Detect
The digital AC lead-off detect (LOD) allows for measurement of the impedance of the two electrodes connected
to an AFE channel by measuring a signal through the AFE. In this mode, the lead-off detect current is injected in
a balanced manner at the inputs of the AFE behind the flex routing switch. The AC test current is injected into
the positive input of the AFE behind the flex routing switch; while at the same time, a similar test current with
opposite sign is injected into the negative input of the AFE. Since the AFE has a very high input impedance, the
current injected into the positive input pin cannot flow into the AFE. Instead, it will flow through the flex routing
switch, via the positive input electrode into the patient, and then back through the negative input electrode and
via another path in the flex routing switch towards the negative input of the AFE, where it is cancelled by the
current injected at that point. As a result of this test current, an additional AC voltage input will occur at the input
of the AFE with a frequency equal to the frequency of the AC LOD test signal frequency. The magnitude of this
voltage equals the magnitude of the AC LOD test current (programmed into the CUR_LOD bit in the
LOD_CURRENT register) multiplied by the impedances of the two electrodes routed to the AFE input in series.
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This AC voltage will be digitized by the AFE, and the result is available in the digital AFE output signals. The lead
connectivity can be determined in the digital domain by applying an FFT to the digital data and by measuring the
amplitude of the tone at the AC LOD excitation frequency. It should be noted that the digital AC LOD can only
determine the series connectivity of the two leads attached to the inputs of a differential channel, and hence the
connectivity of the individual input pins can only be determined by the DC or the analog AC LOD.
Figure 26. Simplified Digital Analog AC Lead-off Detect Block Diagram
Figure 26 shows a simplified block diagram of the digital AC LOD. Follow the procedures below to activate the
Digital AC LOD:
1. Select the Digital AC lead-off mode by setting bit SELAC_LOD = 1 and ACAD_LOD = 0 in the LOD_CN
register.
2. Program the excitation frequency Φ by using the ACDIV_LOD and ACDIV_FACTOR bits in the LOD_AC_CN
register. See equation in Analog AC Lead-Off Detect
3. Enable which channel the digital AC LOD will be applied to by selecting the EN_LOD[2:0] bits in the
LOD_EN register . These bits correspond to the AFE channels CH3 to CH1 from MSB to LSB, respectively.
4. Determine the phase of the injected current to the AFE channels by programming the EN_LOD[5:3] bits in
the LOD_EN register.
The EN_LOD[5:3] bits determine the phase of the injected current to the AFE channels CH3 to CH1 from MSB to
LSB, respectively. A bit set to 1 means that the corresponding channel will receive an anti-phase excitation
current in respect to the frequency divider's phase. In some applications, it may be necessary to invert the sign of
the digital AC lead-off test current on a channel. Consider an example where the first AFE is configured through
the flexible routing switch to measure the voltage between IN1 and IN2, and the second AFE is configured
through the flexible routing switch to measure the voltage between IN2 and IN3.
In this configuration, if digital AC LOD test currents are applied to the inputs of both AFEs, the test current that is
applied to the negative input of the first AFE and the test current that is applied to the positive input of the
second AFE are both flowing through IN2. Depending on the sign of the test current in the second AFE, these
currents can add up or cancel each other. If the currents add up, the system will correctly measure the
differential input impedance on both AFE channels. If the currents on IN2 cancel, the test current will only flow
through IN1 and IN3, and the impedance of the electrode connected to IN2 cannot be measured. To apply the
digital AC LOD to CH3 and CH2, set EN_LOD[2] = 1 and EN_LOD[1] = 1. Then, by programming EN_LOD[5] = 0
and EN_LOD[4] = 1, CH3 and CH2 will receive excitation currents in-phase and anti-phase, respectively.
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CLOCK OSCILLATOR
The ADS1293 is designed to operate from a 409.6kHz clock. This clock can be generated by an on-chip crystal
oscillator or provided externally on the bidirectional CLK. The high-accuracy low-power on-chip crystal oscillator
will work with an external 4.096MHz crystal connected between the XTAL1 and XTAL2 pins, each of which must
be loaded with a 20pF capacitor to get an accurate oscillation frequency. The output frequency of the on-chip
crystal oscillator is divided by 10 to generate the required 409.6kHz clock frequency as shown in Figure 27.
VDD
VDD
22 pF
22 pF
4.096 MHz
XTAL2
crystal
oscillator
XTAL1
SHDN_OSC
÷10
enable
STRTCLK
CLK 409.6 kHz
enable
to internal clock
EN_CLKOUT
generators
SHDN_OSC
Figure 27. Block Diagram of the CLOCK
Even though the required oscillation frequency of the external crystal is rated at 4.096MHz, both the oscillator
and the chip can tolerate a wider crystal oscillation frequency (3.7MHz to 4.5MHz). Note though that the output
data rate and bandwidth of the SINC filters given in Table 5 through Table 8 will scale according to the crystal
oscillation frequency.
When the internal clock is used, the generated clock can be brought off chip through the CLK pin. Its output
driver is enabled by configuring bit EN_CLKOUT = 1 in the OSC_CN register, allowing a multi-chip system to
operate synchronously from a single crystal oscillator. Setting bit STRTCLK = 1 allows the internal 409.6kHz
clock to propagate to the digital circuitry and to the output driver of the CLK pin.
The internal crystal oscillator can be shut down to save power or when the clock of the device is provided
externally. Configuring bit SHDN_OSC = 1 powers down the internal crystal oscillator and enables the input
driver of the CLK pin. The external clock should have a frequency of 409.6kHz with a duty cycle of 50% to get
the SINC filter bandwidth given in Table 5 through Table 8. The chip can tolerate a wider frequency range and
clock duty cycle on this pin (see the External Clock Frequency and the External Clock Duty Cycle parameters in
the Clock section of the ELECTRICAL CHARACTERISTICS table) in exchange of scaling up or down the
bandwidth of the SINC filters. Setting bit STRTCLK = 1 allows the external 409.6kHz clock to propagate to the
digital circuitry.
The STRTCLK bit is designed to ensure all critical blocks of the chip get a clean clock start. The clock source
should first be configured and allowed to start up using the SHDN_OSC and EN_CLKOUT bits, and
subsequently, the STRTCLK bit can be set high.
The oscillator control register bits are summarized in Table 12. In a multi-chip system, the CLK pins of the master
and slaves should be connected together. The master should be configured to generate a clock on the CLK pin
while the slaves should use the CLK pin as a clock input source.
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Table 12. Clock Oscillator Configuration Bits
STRTCLK
SHDN_OSC
EN_CLKOUT
0
X
X
No clock
CLOCK PROPAGATION
1
0
0
Internal clock to digital circuitry
1
0
1
Internal clock to digital circuitry and CLK pin
1
1
X
External clock to digital circuitry
SERIAL DIGITAL INTERFACE
A serial peripheral interface (SPI) allows access to the control registers of the ADS1293. The serial interface is a
generic 4-wire synchronous interface compatible with SPI type interfaces used on many microcontrollers and
DSP controllers.
Digital Output Drive Strength
The strength of the transistors driving the serial data out pin (SDO) can be programmed to four levels in the
DIGO_STRENGTH register. The drive strength will affect the slope of the digital output signal edges, and the
optimal drive strength will depend on the capacitive loading on the SDO pin, where larger capacitive loads
require larger drive strength. The output drive strength configurability may help reduce interference from the SPI
communication into the AFE signal path. In this sense, it is advised to use the lowest drive strength that works
for a particular system.
SPI Protocol
A typical serial interface access cycle is exactly 16 bits long, which includes an 8-bit command field (R/WB + 7bit address) to provide for a maximum of 128 direct access addresses, and an 8-bit data field. Figure 28 shows
the access protocol used by this interface. Extended access cycles are possible and they are described in the
Auto-incrementing Address and Streaming sections.
Figure 28. Serial Interface Protocol
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Each assertion of chip select bar (CSB) starts a new register access. The R/Wb bit in the command field
configures the direction of the access operation; a value of 0 indicates a write operation and a value of 1
indicates a read operation. All output data is driven on the falling edge of the serial clock (SCLK), and for the 16bit protocol, SDO read data is driven on the falling edge of clocks 8 through 15. All input data on the serial data
in (SDI) pin is sampled on the rising edge of SCLK and is written into the register on the rising edge of the 16th
clock. The user is required to deassert CSB after the 16th clock; if CSB is deasserted before the 16th clock, no
data write will occur.
Random Register Access Protocol
The 16-bit protocol is useful for random address access. CSB must be asserted during 16 clock cycles of SCLK.
Auto-incrementing Address
An access cycle may be extended to multiple registers by simply keeping the CSB asserted beyond the stated
16 clocks of the standard 16-bit protocol. In this mode, CSB must be asserted during 8*(1+N) clock cycles of
SCLK, where N is the amount of bytes to write or read during the access cycle. The auto-incrementing address
mode is useful to access a block of registers of incrementing addresses.
For example, to read the pace and ECG data registers located from address 0x30 to address 0x3F and worth 16
bytes of data, follow the next steps:
1. Execute a read command to address 0x30.
2. Extend the CSB assertion during 136 clock cycles (8+8*16).
During an auto-incrementing read access, SDO outputs the register contents every 8 clock cycles after the initial
8 clocks of the command field. During an auto-incrementing write access, the data is written to the registers
every 8 clock cycles after the initial 8 clocks of the command field.
Automatic address increment stops at address 0x4F for both write and read operations.
Streaming
A read access cycle can operate in streaming mode, also referred to as loop read back mode, by performing a
read operation from the DATA_LOOP register and extending the CSB assertion beyond the standard 16 clocks.
The streaming mode is supported for the DATA_STATUS, DATA_CH1_PACE, DATA_CH2_PACE,
DATA_CH3_PACE, DATA_CH1_ECG, DATA_CH2_ECG and DATA_CH3_ECG registers described in Pace and
ECG Data Read Back Registers. The streaming mode is useful to access the block of pace and ECG data
registers when not all data needs to be read. The channels to read in this mode are selected in the CH_CNFG
register. In this mode, CSB must be asserted during 8*(1+N) clock cycles, where N is the number source bytes
enabled in CH_CNFG . The source for pace data is 2 bytes long; the source for ECG data is 3 bytes long, and
the source for data status is 1 byte long.
For example, to read the DATA_STATUS, DATA_CH3_PACE and DATA_CH3_ECG registers located at address
0x30, 0x35 and 0x3D and worth 6 bytes of data, follow the next steps:
1. Write a value of 0x49 to the CH_CNFG register (address 0x2F).
2. Read from the DATA_LOOP register (address 0x50).
3. Extend the CSB assertion for 56 clock cycles (8+8*6).
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DRDYB DATA READY BAR
Data ready bar (DRDYB) is an active low output signal and is asserted when new data is ready to be read. After
DRDYB is asserted and an SPI read of ECG or PACE data occurs, DRDYB will be deasserted at the 14th rising
edge of SCLK.
Figure 29. DRDYB Behavior for a Complete Read Operation
New data is available regardless of the serial interface being ready to read the data or not, and therefore, the
data is lost if it is not read before the next DRDYB assertion. If DRDYB is asserted and the data is not read,
DRDYB is automatically deasserted at least tDRDYB seconds before the next DRDYB assertion. The value for
tDRDYB can be found in the TIMING DIAGRAMS.
Figure 30. DRDYB Behavior for an Incomplete Read Operation
The source channel driving the assertion of the DRDYB signal can be configured in the DRDYB_SRC register. In
order to see the DRDYB output pin asserted, one bit of this register must be set to 1 to select the digital channel
to drive it. Multiple channels should not be selected to drive the DRDYB output pin, otherwise, it will result in
unexpected behavior. The selected channel should not be shut down in the AFE_SHDN_CN register, and if the
source is an ECG channel, its filter should not be disabled in the DIS_EFILTER register. It is strongly
recommended to select the channel with the fastest data rate as the source for the DRDYB signal to avoid loss
of data.
By default, the DRDYB signal is masked during the first few data samples after the start of a conversion or when
a synchronization error is detected. If any ECG channel is enabled, DRDYB is masked during the first six data
samples of the slowest enabled ECG channel. If all ECG channels are disabled, DRDYB is masked for the first
six data samples of the slowest enabled pace channel when the data rate is 1xODR, and for the first eleven data
samples of the slowest enabled pace channel when the data rate is 2xODR. Masking can be disabled in the
MASK_DRDYB register.
SYNCHRONIZATION
There are three filter timing generators implemented to support independent filter settings. Under normal
conditions, the filters always start synchronized when the START_CON bit in the CONFIG register is set to 1,
and will remain synchronized. Synchronization can also be continually enforced for the eventuality of a channel
losing synchronization, and it can be used in single-chip and multiple-chip systems.
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Single-chip Multi-Channel Synchronization
The filter channels are synchronized when DRDYB assertion is at a fixed frequency and new data from each
source is available at some integer multiple of DRDYB. This synchronization mode requires that the fastest
output data source is selected to drive DRDYB in the DRDYB_SRC register.
The filter channels will start synchronized if the output data rates in all channels are the same or integer multiples
of each other. Synchronization between channels will be continuously enforced as long as the slowest output
source is selected as the synchronization source in the SYNCB_CN register. The SYNCB pin output driver can
be disabled in a single-chip system, regardless of the synchronization source selected, and synchronization will
continue to be enforced between channels. The SYNCB output driver is disabled programming bit
DIS_SYNCBOUT=1 in the SYNCB_CN register.
Multi-chip Synchronization
Synchronization in a multiple ADS1293 system is achieved when all the devices share a common clock and
synchronization source. The common clock source, fOSC , can be driven from the CLK pin of an ADS1293 when
its CLK pin output driver is enabled in the OSC_CN register. The common synchronization source can be driven
from the SYNCB pin of the device with the slowest data rate in the system. An ADS1293 is configured as a
synchronization source by enabling its SYNCB output driver and selecting the slowest data rate channel to drive
the line in the SYNCB_CN register. The SYNCB_CN register of the other devices should be programmed to 0x40
to configure their SYNCB pins as inputs. When configured as an output, SYNCB is driven on the falling edge of
fOSC and when configured as an input, SYNCB is sampled on the rising edge of fOSC.
Synchronization Errors
Detected synchronization events are reported to the ERROR_SYNC register. A phase error is generated when
the phase of divided clocks of the timing generator has been adjusted to comply with the SYNCB input signal. A
timing error is generated when the timing of the indicated channel has been updated to comply with the timing of
the synchronization source, internal or external. By default, a synchronization error will propagate to the
ALARMB output pin. Reporting of a synchronization error can be disabled in the MASK_ERR register.
ALARM FUNCTIONS
The ADS1293 has multiple warning flags to diagnose possible fault conditions in the ECG monitoring application.
The warning flags can be read in the Error Status Registers . The system errors are filtered by the digital circuitry
(see ERROR FILTERING), and for this reason, the master clock must be active for the alarms to be reflected in
the error registers.
1. ERROR_LOD: Indicates which input has a lead-off error. The lead-off detection was described in LEAD-OFF
DETECTION (LOD) .
2. ERROR_STATUS: Contains the following error flags:
– SYNCEDGEERR: This flag is raised when a synchronization error occurs, as described in
Synchronization Errors.
– CH3ERR: This flag is raised when one of the 5 LSBs or bit 6 of the ERROR_RANGE3 register is a logic
1. It indicates an out-of-range condition at the AFE in channel 3. These error conditions are described in
Instrumentation Amplifier Fault Detection and in Sigma Delta Modulator Fault Detection .
– CH2ERR: See above, but for channel 2.
– CH1ERR: See above, but for channel 1.
– LEADOFF: This error flag is raised when one of the OUT_LOD bits in the ERROR_LOD register is a
logic 1.
– BATLOW: This error flag is raised when the supply voltage of the ADS1293 drops below 2.7V. This can
be used as a warning sign to the microcontroller that the state of charge of a supply battery is almost
below levels of operation. The ADS1293 is designed to function within specification for supplies larger
than 2.7V but communication the digital communication interface will work down to 2.4V so that this alarm
condition can still be communicated to the microcontroller. A low battery error propagates to the ALARMB
pin unless the MASK_BATLOW bit in the MASK_ERR register is set to 1. System alarms are filtered by
the digital circuitry (see ERROR FILTERING), and for this reason, the master clock must be active in
order to capture an alarm.There is also a battery voltage monitoring feature that can be used to monitor
the state of charge of the battery during normal operation described in Battery Monitoring.
– RLDRAIL: This error flag is raised when the output voltage of the right leg drive amplifier is approaching
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the supply rails. The flag goes high when the output voltage of the common-mode detector is 200mV
away from either supply rail. This condition would occur if the common-mode on the patient’s body is far
away from the target value and as a result the right leg drive amplifier needs to deliver a lot of charge to
the patient’s body to restore the common-mode voltage. In this scenario, the common-mode may still be
inside the range of the instrumentation amplifier and the ECG signal may still be accurately acquired.
– CMOR: The CMOR error flag is raised when the output voltage of the common-mode detector is 750mV
away from either supply rail. In this case, the common-mode voltage detected on the patient’s body is
outside of the input CMVR where the instrumentation amplifier can process the full differential input signal
(see Instrumentation Amplifier (INA)). When this flag is raised, the ECG signal accuracy may be lost.
3. ERROR_RANGE1, ERROR_RANGE2, ERROR_RANGE3: These registers contain the out-of-range error
signals of the AFEs in the three channels. The flags in these registers are described in Instrumentation
Amplifier Fault Detection and in Sigma Delta Modulator Fault Detection.
4. ERROR_SYNC: This register contains flags that indicate certain synchronization errors have been detected.
These errors have been described in Synchronization Errors .
5. ERROR_MISC: This register contains status flags for common-mode out-of-range, right leg drive near rail
and low battery errors.
ERROR FILTERING
The alarms that are generated by the analog circuitry inside the ADS1293 are filtered by digital logic. Alarms will
only be accepted if they are active for a number of consecutive digital clock cycles, which toggle on the falling
edge of the 409.6kHz oscillator clock. The number of digital clock cycles that an alarm will have to be active
before it is accepted is programmable between 1 and 16 counts using the ALARM_FILTER register. This register
contains two separate filter parameters. The 4 LSBs in this register program the filtering of the lead-off detect
error bits. The 4 MSBs program the filtering of the instrumentation amplifier signal out-of-range errors, the sigmadelta input over range errors, and the CMOR, RLDRAIL and BATLOW errors.
ALARMB PIN AND ERROR MASKING
The ADS1293 has an ALARMB output pin. This open drain output will go low when a new alarm condition occurs
in the ERROR_STATUS register. The ALARMB pin can be used as an interrupt signal to a microcontroller to
warn about error conditions that can potentially corrupt the data that is being collected so that the microcontroller
can take appropriate preventive action. The functionality of the ALARMB pin is flexible and programmable using
the MASK_ERR register. This register allows masking some of the errors in the ERROR_STATUS register so
that certain alarm events will not trigger a high to low transition on the ALARMB pin.
ERROR REGISTER AUTOMATIC CLEARING DESCRIPTION
All error bits in the registers 0x18 through 0x1E are latched in a high state when an error occurs and will only
return to zero after being read. The error bits will remember an error until the user reads the error. The sign bits
in the CH1ERR, CH2ERR and CHR3ERR registers are latched on low to high transition of the DIF_HIGH
transitions in the corresponding registers. In this way, when the differential signal goes out-of-range, the sign of
the signal can also be detected when the alarm register is read. Upon read, the error bits will be cleared. If the
error condition has disappeared before the error is read, the error bits will remain low after being read. For all
error registers, except ERROR_STATUS, the error bits will return to their high state within a few internal clock
cycles if the error condition is still present after a register read. The bits in the ERROR_STATUS register only
respond to new errors. If an error persists after the ERROR_STATUS register is read, the error condition will not
be reflected in the error status register and the ALARMB pin will not pulse low again.
ALARM PROPAGATION
Figure 31 shows how the alarms propagate through the digital circuitry inside the ADS1293. The errors
propagate from left to right. Synchronization errors are not filtered because they are generated synchronously
inside the digital circuitry, and if they occur, they are latched in the ERROR_SYNC register. Lead-off detect
errors are filtered by a counter programmed in the 4 LSBs of the ALARM_FILTER register and are latched in the
ERROR_LOD register. The instrumentation amplifier out-of-range, sigma-delta over range, right leg drive
amplifier out-of-range, common-mode amplifier out-of-range and low battery signals are also filtered by a counter
programmed in the MSBs of the ALARM_FILTER register. The out-of-range signals for the 3 channels are
latched in the ERROR_RANGE1, ERROR_RANGE2 and ERROR_RANGE3 registers. The first 6 registers on
the right hand side of the circuit latch errors until the error is being read. After being read, the error bit will be
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reset, but it will return to a logic 1 if the internal alarm condition persists. After being filtered the alarms are all
routed to a digital logic block that detects whether a new alarm has occurred. If this happens, the appropriate bit
in the ERROR_STATUS register will be set and the ALARMB pin will be pulled down. The bits in the
ERROR_STATUS register will be reset and the ALARMB pin will released when the ERROR_STATUS register is
read.
Figure 31. Graphical Illustration of Alarm Propagation
REFERENCE VOLTAGE GENERATORS
The common-mode and right leg drive reference generates VDD/2.2 volts, which are present on the RLDREF
pin. This reference is used as an internal common-mode reference, as the reference for the analog pace
channel, and should be powered on at all times when a sigma delta modulator is running. It can be powered
down by programming bit SHDN_CMREF=1 in the REF_CN register. The RLDREF pin should have a 0.1µF
bypass capacitor to ground.
The internal reference, VREF, generates 2.4V, which are present on the CVREF pin. The CVREF pin must have a
1µF bypass capacitor to ground with low ESR and is not designed to be loaded with other circuitry. This
reference should also be powered on at all times when a sigma delta modulator is running. It can be powered
down programming bit SHDN_REF=1 in the REF_CN register. It is possible to provide the reference voltage
externally on this pin when the internal reference generator is shut down.
All three voltage generators require a somewhat larger start up time compared to the other circuit blocks inside
the ADS1293, which is why they are treated differently in the global power down or standby states, as will be
described in the next section.
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POWER MANAGEMENT
The ADS1293 has many features that allow the optimization of power consumption. The common-mode detector
and right leg drive amplifier can be configured to achieve the optimum AC performance to power consumption
ratio in a given application environment. Almost all internal circuit blocks can be powered down to reduce power
consumption. Table 13 lists the typical power consumption budget for all of the circuit blocks that can be
individually powered down.
There are two master control bits, PWR_DOWN and STANDBY, in addition to the power down control bits that
are used to power down an individual circuit block, and they are located in the CONFIG register. In the power
down mode, all circuits that can be powered down are powered down, irrespective of the state of their individual
shutdown bits. With the PWR_DOWN bit, the entire ADS1293 can be quickly placed in its minimal current
consumption state without needing to do many individual configuration register writes. The STANDBY bit
operates in a similar manner, but it does not affect the state of the three voltage generators and the crystal
oscillator inside the ADS1293, which require a somewhat longer time to start up. When placing the ADS1293 in
stand-by mode, the power consumption is somewhat higher than in the power down state but the ADS1293 can
return to operation quicker. The difference between the current consumption in power-down and in stand-by
depends on the logic state of the shutdown bits of the two reference voltage generators and the crystal oscillator,
as described in Table 13.
Table 13 specifies the current consumption of the blocks that are always ON in the first row. The second group in
the table specifies the current consumption of the two reference voltage generators and the crystal oscillator that
are OFF in power-down mode but that remain active during stand-by mode. The last group of circuit blocks in the
table specifies the current consumption of the other circuit blocks. The ADS1293 will need about 100ms to return
to operation after being powered down. The time to recover from stand-by is limited by the time latency of the
programmable logic filters in the AFE channels, as described in the Filter Settling Time section.
Table 13. Typical Current Consumption per Block
GLOBAL POWER
CONTROL
Always on
Off in power down
BLOCK NAME
CURRENT
µA
Supporting circuitry
80
Reference voltage generator
17
Right leg drive reference
9
Crystal oscillator
7
Instrumentation amplifier
Analog front end fault detect
Sigma delta modulator
Off in standby
CONDITIONS / NOTES
low power, per channel
38
high resolution, per channel
121
Per channel
2
102.4kHz, per channel
22
204.8kHz, per channel
41
Analog output channel
29
Lead-off detect
Excluding excitation currents
Wilson reference
per channel
7
low speed, cap drive 1, 6 active leads
39
high speed, cap drive 4, 6 active leads
79
low speed, cap drive 1
20
high speed, cap drive 4
60
Common-mode detector
Right leg drive amplifier
38
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APPLICATION INFORMATION
EXAMPLE APPLICATIONS
3-LEAD ECG APPLICATION
A 3-Lead ECG system can be implemented using two channels as shown in Figure 32. In this example, the right
arm (RA), left arm (LA), left leg (LL) and right leg (RL) are connected to the IN1, IN2, IN3 and IN4 pins
respectively. The ADS1293 uses the Common-Mode Detector block to measure the common-mode of the
patient’s body by averaging the voltage of input pins IN1, IN2 and IN3, and uses this signal in the right leg drive
feedback circuit (1). The output of the RLD amplifier is connected internally to the IN4 pin, which is connected to
the right leg electrode, to drive the common-mode of the patient’s body. The chip uses an external 4.096MHz
crystal oscillator connected between the XTAL1 and XTAL2 pins to create the clock sources for the device.
5V
+
InA
-
Σ∆
Modulator
Digital
Filter
SELRLD
WILSON_EN
CMDET_EN
Wilson
ref.
CM
detect
II
SDO
DIGITAL
CONTROL AND
POWER
MANAGEMENT
SDI
SCLK
CSB
RLD
Amp.
ALARMB
REF for
CM & RLD
C1
R2
R1
0.1 F
VSSIO
WCT
CMOUT
LL
XTAL2
DRDYB
+
InA
RL
RSTB
Digital
Filter
CLK
SYNCB
IN6
Σ∆
Modulator
0.1 F
I
Digital
Filter
RLDREF
IN5
+
InA
-
4.096
MHz
RLDIN
CH2
IN4
Σ∆
Modulator
RLDINV
LA
+
InA
-
RLDOUT
IN3
RA
CVREF
VSS
VDD
CH1
IN2
1 F
22 pF 3.3V
-
IN1
1 MΩ
+
0.1 F
5V
22 pF
XTAL1
VDDIO
3.3V
5V
3.3V
1 MΩ
Figure 32. 3-Lead ECG Application
Follow the next steps to program the ADS1293 in a 3-lead application with an ECG bandwidth of 175Hz and an
output data rate of 853Hz; it is assumed that the device registers contain their default power-up values.
1. Set address 0x01 = 0x11: Connects channel 1’s INP to IN2 and INN to IN1.
2. Set address 0x02 = 0x19: Connects channel 2’s INP to IN3 and INN to IN1.
3. Set address 0x0A = 0x07: Enables the common-mode detector on input pins IN1, IN2 and IN3.
4. Set address 0x0C = 0x04: Connects the output of the RLD amplifier internally to pin IN4.
5. Set address 0x12 = 0x04: Uses external crystal and feeds the output of the internal oscillator module to the
digital.
(1)
The ideal values of R1, R2 and C1 will vary per system/application; typical values for these components are: R1 = 100kΩ, R2 = 1MΩ and
C1 = 1.5nF.
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6. Set address 0x14 = 0x24: Shuts down unused channel 3’s signal path.
7. Set address 0x21 = 0x02: Configures the R2 decimation rate as 5 for all channels.
8. Set address 0x22 = 0x02: Configures the R3 decimation rate as 6 for channel 1.
9. Set address 0x23 = 0x02: Configures the R3 decimation rate as 6 for channel 2.
10. Set address 0x27 = 0x08: Configures the DRDYB source to channel 1 ECG (or fastest channel).
11. Set address 0x2F = 0x30: Enables channel 1 ECG and channel 2 ECG for loop read-back mode.
12. Set address 0x01 = 0x01: Starts data conversion.
Follow the description in the Streaming section to read the data. The ADS1293 will measure lead I and lead II.
Lead III can be calculated as follows:
•
Lead III = Lead II – Lead I
Optionally, the third channel could be used to measure Lead III.
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5-LEAD ECG APPLICATION
Figure 33 shows the ADS1293 in a 5-Lead ECG system setup. Similar to the 3-Lead application, the ADS1293
uses the Common-Mode Detector to measure the common-mode of the patient’s body by averaging the voltage
of input pins IN1, IN2 and IN3, and uses this signal in the right leg drive feedback circuit (2). The output of the
RLD amplifier is connected to the right leg electrode, which is IN4, to drive the common-mode of the patient’s
body. The Wilson Central Terminal is generated by the ADS1293 and is used as a reference to measure the
chest electrode, V1. The chip uses an external 4.096MHz crystal oscillator connected between the XTAL1 and
XTAL2 pins to create the clock sources for the device.
5V
CH1
IN2
IN3
RA
LA
CH2
IN4
IN5
V1
CH3
1 F
+
InA
-
Σ∆
Modulator
+
InA
-
Σ∆
Modulator
Digital
Filter
+
InA
-
Σ∆
Modulator
Digital
Filter
22 pF 3.3V
XTAL2
RSTB
CVREF
VSS
VDD
IN1
1 MΩ
4.096
MHz
VDDIO
22 pF
5V
0.1 F
5V
XTAL1
3.3V
0.1 F
I
Digital
Filter
CLK
DRDYB
SDO
II
V
DIGITAL
CONTROL AND
POWER
MANAGEMENT
SDI
SCLK
CSB
IN6
SELRLD
C1
R2
R1
0.1 F
VSSIO
REF for
CM & RLD
SYNCB
CM
detect
RLDREF
Wilson
ref.
RLDIN
CMDET_EN
ALARMB
RLDINV
WILSON_EN
RLDOUT
WCT
CMOUT
LL
RLD
Amp.
-
+
InA
-
+
RL
3.3V
1 MΩ
Figure 33. 5-Lead ECG Application
The following steps configure the ADS1293 for a 5-lead application with an ECG bandwidth of 175Hz and an
output data rate of 853Hz; it is assumed that the device registers contain their default power-up values.
1. Set address 0x01 = 0x11: Connects channel 1’s INP to IN2 and INN to IN1.
2. Set address 0x02 = 0x19: Connect channel 2’s INP to IN3 and INN to IN1.
3. Set address 0x03 = 0x2E: Connects channel 3’s INP to IN5 and INN to IN6.
4. Set address 0x0A = 0x07: Enables the common-mode detector on input pins IN1, IN2 and IN3.
5. Set address 0x0C = 0x04: Connects the output of the RLD amplifier internally to pin IN4.
6. Set addresses 0x0D = 0x01, 0x0E = 0x02, 0x0F = 0x03: Connects the first buffer of the Wilson reference to
the IN1 pin, the second buffer to the IN2 pin, and the third buffer to the IN3 pin.
7. Set address 0x10 = 0x01: Connects the output of the Wilson reference internally to IN6.
(2)
The ideal values of R1, R2 and C1 will vary per system/application; typical values for these components are: R1 = 100kΩ, R2 = 1MΩ and
C1 = 1.5nF.
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8. Set address 0x12 = 0x04: Uses external crystal and feeds the output of the internal oscillator module to the
digital.
9. Set address 0x21 = 0x02: Configures the R2 decimation rate as 5 for all channels.
10. Set address 0x22 = 0x02: Configures the R3 decimation rate as 6 for channel 1.
11. Set address 0x23 = 0x02: Configures the R3 decimation rate as 6 for channel 2.
12. Set address 0x24 = 0x02: Configures the R3 decimation rate as 6 for channel 3.
13. Set address 0x27 = 0x08: Configures the DRDYB source to ECG channel 1 (or fastest channel).
14. Set address 0x2F = 0x70: Enables ECG channel 1, ECG channel 2, and ECG channel 3 for loop read-back
mode.
15. Set address 0x01 = 0x01: Starts data conversion.
Follow the description in the Streaming section to read the data.
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8/12-LEAD ECG APPLICATION
Figure 34 shows the ADS1293 master/slave setup for an 8-Lead to 12-Lead ECG system. The ADS1293 uses
the Common-Mode Detector to measure the common-mode of the patient’s body by averaging the voltage of
input pins IN1, IN2 and IN3, and uses this signal in the right leg drive feedback circuit (3). The output of the RLD
amplifier is connected to the right leg electrode to drive the common-mode of the patient’s body. The Wilson
Central Terminal is generated by the ADS1293 and is used as a reference to measure the chest electrodes, V1V6; it is strongly recommended to shield the external Wilson connections, which due to the high output
impedance of the Wilson reference, is prone to pick up external interference. The master ADS1293 generates a
synchronization pulse on the SYNCB pin (configured as an output). This drives the SYNCB pins (configured as
inputs) of the two slave ADS1293. The master chip uses an external 4.096MHz crystal oscillator connected
between the XTAL1 and XTAL2 pins to create the clock sources for the device and outputs this clock on the CLK
pin.
The next steps will configure the master device; it is assumed that the device registers contain their default
power-up values.
1. Set address 0x01 = 0x11: Connects channel 1’s INP to IN2 and INN to IN1.
2. Set address 0x02 = 0x19: Connect channel 2’s INP to IN3 and INN to IN1.
3. Set address 0x0A = 0x07: Enables the common-mode detector on input pins IN1, IN2 and IN3.
4. Set address 0x0C = 0x04: Connects the output of the RLD amplifier internally to pin IN4.
5. Set addresses 0x0D = 0x01, 0x0E = 0x02, 0x0F = 0x03: Connects the first buffer of the Wilson reference to
the IN1 pin, the second buffer to the IN2 pin, and the third buffer to the IN3 pin.
6. Set address 0x12 = 0x05: Uses external crystal, feeds the output of the internal oscillator module to the
digital, and enables the CLK pin output driver
7. Set address 0x14 = 0x24: Shuts down unused channel 3’s signal path.
8. Set address 0x21 = 0x02: Configures the R2 decimation rate as 5 for all channels.
9. Set address 0x22 = 0x02: Configures the R3 decimation rate as 6 for channel 1.
10. Set address 0x23 = 0x02: Configures the R3 decimation rate as 6 for channel 2.
11. Set address 0x27 = 0x08: Configures the data-ready source to channel 1 ECG (or fastest channel).
12. Set address 0x28 = 0x08: Configures the synchronization source to channel 1 ECG (or slowest channel).
13. Set address 0x2F = 0x30: Enables ECG channel 1 and ECG channel 2 for loop read-back mode.
Next, configure the slave devices; it is assumed that the device registers contain their default power-up
values. In this example, both devices will have the same configuration; therefore, they can potentially be
configured in parallel by asserting the CSB signal of both chips.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
(3)
Set address
Set address
Set address
Set address
Set address
Set address
Set address
Set address
Set address
Set address
Set address
mode.
0x01 = 0x0C: Connects channel 1’s INP to IN1 and INN to IN4.
0x02 = 0x14: Connects channel 2’s INP to IN2 and INN to IN4.
0x03 = 0x1C: Connects channel 3’s INP to IN3 and INN to IN4.
0x12 = 0x06: Uses external clock signal on the CLK pin and feeds it to the digital.
0x21 = 0x02: Configures the R2 decimation rate as 5 for all channels.
0x22 = 0x02: Configures the R3 decimation rate as 6 for channel 1.
0x23 = 0x02: Configures the R3 decimation rate as 6 for channel 2.
0x24 = 0x02: Configures the R3 decimation rate as 6 for channel 3.
0x27 = 0x00: DRDYB pin not asserted by slave devices.
0x28 = 0x40: Disables SYNCB driver and configures pin as input.
0x2F = 0x70: Enables ECG channel 1, ECG channel 2, and ECG channel 3 for loop read-back
The ideal values of R1, R2 and C1 will vary per system/application; typical values for these components are: R1 = 100kΩ, R2 = 1MΩ and
C1 = 1.5nF.
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Finally, start the conversion. This should be written to all three chips.
25. Set address 0x00 = 0x01: Starts data conversion (repeat this step for every device).
The three devices will run synchronously using the SYNCB signal. Follow the description in the Streaming
section to read the data. The ADS1293 measures lead I, lead II and leads V1-V6. For a 12-lead application, the
remaining 4 leads can be calculated as follows:
•
•
•
•
Lead III = Lead II – Lead I
aVR = – ( I + II ) / 2
aVL = I – II / 2
aVF = II – I / 2
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5V
3.3V
XTAL2
1M
RSTB
CVREF
VSS
VDD
0.1 PF
5V
22 pF
5V
1 PF
22 pF 3.3V
4.096
MHz
XTAL1
VDDIO
www.ti.com
0.1 PF
CLK
IN1
IN2
+
CH1 InA
-
¨
Modulator
Digital
Filter
+
CH2 InA
-
¨
Modulator
Digital
Filter
I
DRDYB
V4 V5 V6
IN5
IN6
WILSON_EN
CMDET_EN
Wilson
ref.
CM
detect
WCT
RLD
Amp.
SDI
SCLK
CSB
ALARMB
3.3V
VDDIO
3.3V
1 PF
VSSIO
0.1 PF
SYNCB
R2
R1
RSTB
CVREF
VSS
0.1 PF
VDD
5V
C1
RLDINV
RLDOUT
CMOUT
LL
RLDREF
REF for
CM & RLD
RL
RLDIN
V3
IN4
DIGITAL
CONTROL AND
POWER
MANAGEMENT
-
LA
V1 V2
II
+
RA
SELRLD
SDO
IN3
1M
0.1PF
CLK
IN1
IN2
+
CH1 InA
-
¨
Modulator
Digital
Filter
+
CH2 InA
-
¨
Modulator
Digital
Filter
V1
DRDYB
SDO
IN3
IN4
IN5
+
CH3 InA
-
IN6
V2
SDI
SCLK
V3
Digital
Filter
¨
Modulator
DIGITAL
CONTROL AND
POWER
MANAGEMENT
CSB
ALARMB
IN5
IN6
SYNCB
3.3V
0.1 PF
CLK
+
CH1 InA
-
¨
Modulator
Digital
Filter
+
CH2 InA
-
¨
Modulator
Digital
Filter
V4
DRDYB
SDO
IN3
IN4
VSSIO
VDDIO
1M
IN1
IN2
RLDREF
RLDIN
RLDINV
RLDOUT
1 PF
0.1 PF
3.3V
RSTB
VSS
0.1 PF
VDD
5V
CVREF
CMOUT
WCT
+
CH3 InA
-
¨
Modulator
Digital
Filter
V5
DIGITAL
CONTROL AND
POWER
MANAGEMENT
V6
SDI
SCLK
CSB
ALARMB
SYNCB
0.1 PF
RLDREF
RLDIN
RLDINV
RLDOUT
CMOUT
WCT
VSSIO
Figure 34. 8-12-Lead ECG Application
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Simultaneous ECG and PACE data read
Each of the three digital channels of the ADS1293 provides a high-performance path for ECG monitoring and a
lower resolution path for monitoring of pace-maker signals. The digitized signals from these two paths can be
read simultaneously from the Pace and ECG Data Read Back Registers.
The ECG signal path achieves higher resolution than the PACE signal path by having one extra filtering stage
(as shown in Figure 18). Due to the difference in filtering stages of the two paths, the PACE data is available for
reading at a much higher rate than the ECG data. In this sense, the PACE channel must be selected as the
driving source of the DRDYB signal.
In the Streaming mode, the data from the DATA_LOOP register should be read after the DRDYB line is asserted;
this means that new data is available. In order to read both ECG and PACE data from the DATA_LOOP register,
the channels of interest must be enabled in the CH_CNFG register.
As an example, the 3-LEAD ECG APPLICATION can be reconfigured to perform simultaneous ECG and PACE
data reads from channel 1:
1. Set address 0x00 = 0x00: Stops data conversion (if any).
2. Set address 0x2F = 0x32: Enables channel 1 PACE, channel 1 ECG, and channel 2 ECG for loop.
read-back mode
3. Set address 0x27 = 0x01: Reconfigures the DRDYB source to channel 1 PACE .
4. Set address 0x00 = 0x01: Starts data conversion.
In this case, new PACE data from channel 1 is available on every DRDYB assertion; ECG data from channel
1 and channel 2, on the other hand, is available every six DRDYB assertions (R3_RATE_CH1 =
R3_RATE_CH2 = 6).
There are different approaches for handling simultaneous ECG and PACE data read. One approach is to
read ECG data every time that PACE data is ready, over-sampling the ECG channel. This is possible
because old conversion values are retained in the data registers until new data overwrites them.
A second approach is to also read the DATA_STATUS register. Continuing from the steps above:
5. Set address 0x00 = 0x00: Stops data conversion.
6. Set address 0x2F = 0x33: Enables data ready status, channel 1 PACE, channel 1 ECG, and channel 2.
ECG for loop read-back mode
7. Set address 0x00 = 0x01: Starts data conversion.
The DATA_STATUS register indicates the channel(s) that are updated at a given DRDYB assertion; this
information can potentially be used to discard irrelevant data.
A third and more complex approach is to continuously reprogram the CH_CNFG register based on the contents
of DATA_STATUS register. The CH_CNFG register should be reprogrammed to read PACE+ECG data only
when the DATA_STATUS register indicates ECG data is available. After reading the PACE+ECG data, the
CH_CNFG register should be reprogrammed back to reading only the DATA_STATUS register and the PACE
data. In this case, the ECG data is not oversampled and the SPI communication can be significantly reduced for
cases where a decimation rate, R3_RATE_CHx, is large. The reconfiguration of the CH_CNFG register should
be done before the next DRDYB assertion to avoid losing data.
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REGISTERS
1. If written to, RESERVED bits must be written to 0 unless otherwise indicated.
2. Read back value of RESERVED bits and registers is unspecified and should be discarded.
3. Recommended values must be programmed and forbidden values must be not be programmed where they
are indicated in order to avoid unexpected results.
4. If written to, registers indicated as Reserved must have the indicated default value as shown in the register
map. Any other value can cause unexpected results.
Register map
REGISTER NAME
DESCRIPTION
ADDRESS ACCESS DEFAULT
Operation Mode Registers
CONFIG
Main Configuration
0x00
R/W
0x02
FLEX_CH1_CN
Flex Routing Switch Control for Channel 1
0x01
R/W
0x00
FLEX_CH2_CN
Flex Routing Switch Control for Channel 2
0x02
R/W
0x00
FLEX_CH3_CN
Flex Routing Switch Control for Channel 3
0x03
R/W
0x00
FLEX_PACE_CN
Flex Routing Switch Control for Pace Channel
0x04
R/W
0x00
FLEX_VBAT_CN
Flex Routing Switch for Battery Monitoring
0x05
R/W
0x00
LOD_CN
Lead-Off Detect Control
0x06
R/W
0x08
LOD_EN
Lead-Off Detect Enable
0x07
R/W
0x00
LOD_CURRENT
Lead-Off Detect Current
0x08
R/W
0x00
LOD_AC_CN
AC Lead-Off Detect Control
0x09
R/W
0x00
0x0A
R/W
0x00
Input Channel Selection Registers
Lead-off Detect Control Registers
Common-Mode Detection and Right Leg Drive Feedback Control Registers
CMDET_EN
Common-Mode Detect Enable
CMDET_CN
Common-Mode Detect Control
0x0B
R/W
0x00
RLD_CN
Right Leg Drive Control
0x0C
R/W
0x00
WILSON_EN1
Wilson Reference Input one Selection
0x0D
R/W
0x00
WILSON_EN2
Wilson Reference Input two Selection
0x0E
R/W
0x00
WILSON_EN3
Wilson Reference Input three Selection
0x0F
R/W
0x00
WILSON_CN
Wilson Reference Control
0x10
R/W
0x00
Internal Reference Voltage Control
0x11
R/W
0x00
Clock Source and Output Clock Control
0x12
R/W
0x00
AFE_RES
Analog Front-End Frequency and Resolution
0x13
R/W
0x00
AFE_SHDN_CN
Analog Front-End Shutdown Control
0x14
R/W
0x00
AFE_FAULT_CN
Analog Front-End Fault Detection Control
0x15
R/W
0x00
RESERVED
—
0x16
R/W
0x00
AFE_PACE_CN
Analog Pace Channel Output Routing Control
0x17
R/W
0x01
ERROR_LOD
Lead-Off Detect Error Status
0x18
RO
—
ERROR_STATUS
Other Error Status
0x19
RO
—
ERROR_RANGE1
Channel 1 AFE Out-of-Range Status
0x1A
RO
—
ERROR_RANGE2
Channel 2 AFE Out-of-Range Status
0x1B
RO
—
ERROR_RANGE3
Channel 3 AFE Out-of-Range Status
0x1C
RO
—
ERROR_SYNC
Synchronization Error
0x1D
RO
—
Wilson Control Registers
Reference Registers
REF_CN
OSC Control Registers
OSC_CN
AFE Control Registers
Error Status Registers
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REGISTER NAME
DESCRIPTION
ERROR_MISC
Miscellaneous Errors
ADDRESS ACCESS DEFAULT
0x1E
RO
0x00
DIGO_STRENGTH
Digital Output Drive Strength
0x1F
R/W
0x03
R2_RATE
R2 Decimation Rate
0x21
R/W
0x08
R3_RATE_CH1
R3 Decimation Rate for Channel 1
0x22
R/W
0x80
R3_RATE_CH2
R3 Decimation Rate for Channel 2
0x23
R/W
0x80
R3_RATE_CH3
R3 Decimation Rate for Channel 3
0x24
R/W
0x80
R1_RATE
R1 Decimation Rate
0x25
R/W
0x00
DIS_EFILTER
ECG Filter Disable
0x26
R/W
0x00
DRDYB_SRC
Data Ready Pin Source
0x27
R/W
0x00
SYNCB_CN
SYNCB In/Out Pin Control
0x28
R/W
0x40
MASK_DRDYB
Optional Mask Control for DRDYB Output
0x29
R/W
0x00
MASK_ERR
Mask Error on ALARMB Pin
0x2A
R/W
0x00
Reserved
—
0x2B
—
0x00
Reserved
—
0x2C
—
0x00
Reserved
—
0x2D
—
0x09
ALARM_FILTER
Digital Filter for Analog Alarm Signals
0x2E
R/W
0x33
CH_CNFG
Configure Channel for Loop Read Back Mode
0x2F
R/W
0x00
Digital Registers
Pace and ECG Data Read Back Registers
DATA_STATUS
ECG and Pace Data Ready Status
0x30
RO
—
DATA_CH1_PACE
Channel 1 Pace Data
0x31
0x32
RO
—
DATA_CH2_PACE
Channel 2 Pace Data
0x33
0x34
RO
—
DATA_CH3_PACE
Channel 3 Pace Data
0x35
0x36
RO
—
DATA_CH1_ECG
Channel 1 ECG Data
0x37
0x38
0x39
RO
—
DATA_CH2_ECG
Channel 2 ECG Data
0x3A
0x3B
0x3C
RO
—
DATA_CH3_ECG
Channel 3 ECG Data
0x3D
0x3E
0x3F
RO
—
REVID
Revision ID
0x40
RO
0x01
DATA_LOOP
Loop Read Back Address
0x50
RO
—
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Operation Mode Registers
Table 14. CONFIG: Main Configuration
Addr
0x00
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
PWR_DOWN
BIT1
STANDBY
BIT0
START_CON
[7:3]
RESERVED
—
[2]
PWR_DOWN
Power-down mode
0: Disabled (default)
1: Circuit powered down
[1]
STANDBY
Stand-by mode
0: Disabled
1: Most circuits powered down (default)
[0]
START_CON
Start conversion
0: Disabled (default)
1: Conversion active
Note: Programming START_CON = 1 locks write access to registers 0x11, 0x12, 0x13 and 0x21–0x29.
Input Channel Selection Registers
Table 15. FLEX_CH1_CN: Flex Routing Switch Control for Channel 1
Addr
0x01
BIT7
BIT6
TST1
BIT5
BIT4
POS1
BIT3
BIT2
[7:6]
TST1
Test signal selector
00: Test signal disconnected and CH1 inputs determined by POS1 and NEG1 (default)
01: Connect channel one to positive test signal
10: Connect channel one to negative test signal
11: Connect channel one to zero test signal
[5:3]
POS1
Positive terminal of channel 1
000: Positive terminal is disconnected (default)
001: Positive terminal connected to input IN1
010: Positive terminal connected to input IN2
011: Positive terminal connected to input IN3
100: Positive terminal connected to input IN4
101: Positive terminal connected to input IN5
110: Positive terminal connected to input IN6
[2:0]
NEG1
Negative terminal of channel 1
000: Negative terminal is disconnected (default)
001: Negative terminal connected to input IN1
010: Negative terminal connected to input IN2
011: Negative terminal connected to input IN3
100: Negative terminal connected to input IN4
101: Negative terminal connected to input IN5
110: Negative terminal connected to input IN6
BIT1
NEG1
BIT0
49
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Table 16. FLEX_CH2_CN: Flex Routing Switch Control for Channel 2
Addr
0x02
BIT7
BIT6
BIT5
TST2
BIT4
POS2
BIT3
BIT2
[7:6]
TST2
Test signal selector
00: Test signal disconnected and CH2 inputs determined by POS2 and NEG2 (default)
01: Connect channel two to positive test signal
10: Connect channel two to negative test signal
11: Connect channel two to zero test signal
[5:3]
POS2
Positive terminal of channel 2
000: Positive terminal is disconnected (default)
001: Positive terminal connected to input IN1
010: Positive terminal connected to input IN2
011: Positive terminal connected to input IN3
100: Positive terminal connected to input IN4
101: Positive terminal connected to input IN5
110: Positive terminal connected to input IN6
[2:0]
NEG2
Negative terminal of channel 2
000: Negative terminal is disconnected (default)
001: Negative terminal connected to input IN1
010: Negative terminal connected to input IN2
011: Negative terminal connected to input IN3
100: Negative terminal connected to input IN4
101: Negative terminal connected to input IN5
110: Negative terminal connected to input IN6
BIT1
NEG2
BIT0
Table 17. FLEX_CH3_CN: Flex Routing Switch Control for Channel 3
Addr
0x03
BIT7
BIT6
TST3
BIT5
BIT4
POS3
BIT3
BIT2
[7:6]
TST3
Test signal selector
00: Test signal disconnected and CH3 inputs determined by POS3 and NEG3 (default)
01: Connect channel three to positive test signal
10: Connect channel three to negative test signal
11: Connect channel three to zero test signal
[5:3]
POS3
Positive terminal of channel 3
000: Positive terminal is disconnected (default)
001: Positive terminal connected to input IN1
010: Positive terminal connected to input IN2
011: Positive terminal connected to input IN3
100: Positive terminal connected to input IN4
101: Positive terminal connected to input IN5
110: Positive terminal connected to input IN6
[2:0]
NEG3
Negative terminal of channel 3
000: Negative terminal is disconnected (default)
001: Negative terminal connected to input IN1
010: Negative terminal connected to input IN2
011: Negative terminal connected to input IN3
100: Negative terminal connected to input IN4
101: Negative terminal connected to input IN5
110: Negative terminal connected to input IN6
50
BIT1
NEG3
BIT0
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Table 18. FLEX_PACE_CN: Flex Routing Switch Control for Pace Channel
Addr
0x04
BIT7
BIT6
BIT5
TST4
BIT4
POS4
BIT3
BIT2
[7:6]
TST4
Test signal selector
00: Test signal disconnected and PACE inputs determined by POS4 and NEG4 (default)
01: Connect pace channel to positive test signal
10: Connect pace channel to negative test signal
11: Connect pace channel to zero test signal
[5:3]
POS4
Positive terminal of pace channel
000: Positive terminal is disconnected (default)
001: Positive terminal connected to input IN1
010: Positive terminal connected to input IN2
011: Positive terminal connected to input IN3
100: Positive terminal connected to input IN4
101: Positive terminal connected to input IN5
110: Positive terminal connected to input IN6
[2:0]
NEG4
Negative terminal of pace channel
000: Negative terminal is disconnected (default)
001: Negative terminal connected to input IN1
010: Negative terminal connected to input IN2
011: Negative terminal connected to input IN3
100: Negative terminal connected to input IN4
101: Negative terminal connected to input IN5
110: Negative terminal connected to input IN6
BIT1
NEG4
BIT0
Table 19. FLEX_VBAT_CN: Flex Routing Switch for Battery Monitoring
Addr
0x05
[7:3]
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
VBAT_
MONI_CH3
RESERVED
—
[2]
VBAT_MONI_CH3
Battery monitor configuration for channel 3
0: Battery voltage monitor disabled (default)
1: Battery voltage monitor enabled and overrides FLEX_CH3_CN register
[1]
VBAT_MONI_CH2
Battery monitor configuration for channel 2
0: Battery voltage monitor disabled (default)
1: Battery voltage monitor enabled and overrides FLEX_CH2_CN register
[0]
VBAT_MONI_CH1
BIT1
VBAT_
MONI_CH2
BIT0
VBAT_
MONI_CH1
Battery monitor configuration for channel 1
0: Battery voltage monitor disabled (default)
1: Battery voltage monitor enabled and overrides FLEX_CH1_CN register
Note: The INA of the corresponding monitoring channel must be shut down in 0x14.
51
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Lead-Off Detect Control Registers
Table 20. LOD_CN: Lead-Off Detect Control
Addr
0x06
BIT7
BIT6
BIT5
BIT4
ACAD_LOD
BIT3
SHDN_LOD
BIT2
SELAC_LOD
[7:5]
RESERVED
—
[4]
ACAD_LOD
AC analog/digital lead-off mode select
0: Digital AC lead-off detect (default)
1: Analog AC lead-off detect
[3]
SHDN_LOD
Shut down lead-off detection
0: Lead-off detection circuitry is active
1: Lead-off detection circuitry is shut down (default)
[2]
SELAC_LOD
Lead-off detect operation mode
0: DC lead-off mode (default)
1: AC lead-off mode
[1:0]
ACLVL_LOD
Programmable comparator trigger level for AC lead-off detection
00: Level 1 (default)
01: Level 2
10: Level 3
11: Level 4
52
BIT1
BIT0
ACLVL_LOD
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Table 21. LOD_EN: Lead-Off Detect Enable
Addr
0x07
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
EN_LOD
[7:6]
RESERVED
—
[5]
EN_LOD_6
DC or Analog AC Lead-off-Detection:
These bits enable the lead-off-detection for input IN6.
0: Lead-off detection disabled (default)
1: Lead-off detection enabled
Digital AC Lead-off-Detection:
These bits configure the phase of the current injected into channel CH3.
0: In-phase (default)
1: Anti-phase
[4]
EN_LOD_5
DC or Analog AC Lead-off-Detection:
These bits enable the lead-off-detection for input IN5.
0: Lead-off detection disabled (default)
1: Lead-off detection enabled
Digital AC Lead-off-Detection:
These bits configure the phase of the current injected into channel CH2.
0: In-phase (default)
1: Anti-phase
[3]
EN_LOD_4
DC or Analog AC Lead-off-Detection:
These bits enable the lead-off-detection for input IN4.
0: Lead-off detection disabled (default)
1: Lead-off detection enabled
Digital AC Lead-off-Detection:
These bits configure the phase of the current injected into channel CH1.
0: In-phase (default)
1: Anti-phase
[2]
EN_LOD_3
DC or Analog AC Lead-off-Detection:
These bits enable the lead-off-detection for input IN3.
0: Lead-off detection disabled (default)
1: Lead-off detection enabled
Digital AC Lead-off-Detection:
These bits enable the lead-off-detection for channel CH3.
0: Lead-off detection disabled (default)
1: Lead-off detection enabled
[1]
EN_LOD_2
DC or Analog AC Lead-off-Detection:
These bits enable the lead-off-detection for input IN2.
0: Lead-off detection disabled (default)
1: Lead-off detection enable
Digital AC Lead-off-Detection:
These bits enable the lead-off-detection for channel CH2.
0: Lead-off detection disabled (default)
1: Lead-off detection enabled
[0]
EN_LOD_1
DC or Analog AC Lead-off-Detection:
These bits enable the lead-off-detection for input IN1.
0: Lead-off detection disabled (default)
1: Lead-off detection enable
Digital AC Lead-off-Detection:
These bits enable the lead-off-detection for channel CH1.
0: Lead-off detection disabled (default)
1: Lead-off detection enabled
53
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Table 22. LOD_CURRENT: Lead-Off Detect Current
Addr
0x08
[7:0]
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BIT1
BIT0
CUR_LOD
CUR_LOD
Lead-off detect current select
The lead-off detect current is programmable in a range of 2.04μA with steps of 8nA.
00000000: 0.000 μA (default)
00000001: 0.008 μA
..
..
11111110: 2.032 μA
11111111: 2.040 μA
Table 23. LOD_AC_CN: AC Lead-Off Detect Control
Addr
0x09
[7]
[6:0]
BIT7
ACDIV_
FACTOR
BIT6
BIT5
BIT4
BIT3
ACDIV_LOD
BIT2
ACDIV_FACTOR
AC lead off test frequency division factor
0: Clock divider factor K = 1 (default)
1: Clock divider factor K = 16
ACDIV_LOD
Clock divider ratiio for AC lead off
There are 7 bits available to program the clock divider that generates the AC lead off test frequency.
Common-Mode Detection and Right Leg Drive Common-Mode Feedback Control Registers
Table 24. CMDET_EN: Common-Mode Detect Enable
Addr
0x0A
BIT7
BIT6
BIT5
CMDET_
EN_IN6
BIT4
CMDET_
EN_IN5
BIT3
CMDET_
EN_IN4
BIT2
CMDET_
EN_IN3
BIT1
CMDET_
EN_IN2
BIT0
CMDET_
EN_IN1
[7:6]
RESERVED
—
[5:0]
CMDET_EN_INx
Common-mode detect input enable
There is one bit available per input pin, where the MSB corresponds to input pin IN6 and the LSB
corresponds to input pin IN1.
0: Disable (default)
1: Enable the corresponding pin's voltage to contribute to the average voltage of the common-mode
detect block.
Table 25. CMDET_CN: Common-Mode Detect Control
Addr
0x0B
BIT7
BIT6
BIT5
BIT4
[7:6]
RESERVED
—
[2]
CMDET_BW
Common-mode detect bandwidth mode
0: Low bandwidth mode (default)
1: High bandwidth mode
[1:0]
BIT3
BIT2
CMDET_BW
BIT1
BIT0
CMDET_CAPDRIVE
CMDET_CAPDRIVE Common-mode detect capacitive load drive capability
00: Low cap-drive mode (default)
01: Medium low cap-drive mode
10: Medium high cap-drive mode
11: High cap-drive mode
54
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Table 26. RLD_CN: Right Leg Drive Control
Addr
0x0C
BIT7
BIT6
RLD_BW
BIT5
BIT4
RLD_CAPDRIVE
BIT3
SHDN_RLD
[7]
RESERVED
—
[6]
RLD_BW
Right leg drive bandwidth mode
0: Low bandwidth mode (default)
1: High bandwidth mode
RLD_CAPDRIVE
Right leg drive capacitive load drive capability
00: Low cap-drive mode (default)
01: Medium low cap-drive mode
10: Medium high cap-drive mode
11: High cap-drive mode
SHDN_RLD
Shut down right leg drive amplifier
0: RLD amplifier powered up (default)
1: RLD amplifier powered down
SELRLD
Right leg drive multiplexer
000: Right leg drive output disconnected (default)
001: Right leg drive output connected to IN1
010: Right leg drive output connected to IN2
011: Right leg drive output connected to IN3
100: Right leg drive output connected to IN4
101: Right leg drive output connected to IN5
110: Right leg drive output connected to IN6
[5:4]
[3]
[2:0]
BIT2
BIT1
SELRLD
BIT0
BIT1
SELWILSON1
BIT0
Wilson Control Registers
Table 27. WILSON_EN1: Wilson Reference Input one Selection
Addr
0x0D
[7]
[2:0]
BIT7
BIT6
BIT5
BIT4
BIT3
RESERVED
—
SELWILSON1
Wilson reference routing for the first buffer amplifier
000: No connection to the first buffer amplifier (default)
001: First buffer amplifier connected to input IN1
010: First buffer amplifier connected to input IN2
011: First buffer amplifier connected to input IN3
100: First buffer amplifier connected to input IN4
101: First buffer amplifier connected to input IN5
110: First buffer amplifier connected to input IN6
BIT2
Table 28. WILSON_EN2: Wilson Reference Input two Selection
Addr
0x0E
BIT7
BIT6
BIT5
BIT4
BIT3
[7:3]
RESERVED
—
[2:0]
SELWILSON2
Wilson reference routing for the second buffer amplifier
000: No connection to the second buffer amplifier (default)
001: Second buffer amplifier connected to input IN1
010: Second buffer amplifier connected to input IN2
011: Second buffer amplifier connected to input IN3
100: Second buffer amplifier connected to input IN4
101: Second buffer amplifier connected to input IN5
110: Second buffer amplifier connected to input IN6
BIT2
BIT1
SELWILSON2
BIT0
55
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Table 29. WILSON_EN3: Wilson Reference Input three Selection
Addr
0x0F
BIT7
BIT6
BIT5
BIT4
BIT3
[7:3]
RESERVED
—
[2:0]
SELWILSON3
Wilson reference routing for the third buffer amplifier
000: No connection to the third buffer amplifier (default)
001: Third buffer amplifier connected to input IN1
010: Third buffer amplifier connected to input IN2
011: Third buffer amplifier connected to input IN3
100: Third buffer amplifier connected to input IN4
101: Third buffer amplifier connected to input IN5
110: Third buffer amplifier connected to input IN6
BIT2
BIT1
SELWILSON3
BIT0
BIT1
GOLDINT
BIT0
WILSONINT
Table 30. WILSON_CN: Wilson Reference Control
Addr
0x10
[7:2]
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
RESERVED
—
[1]
GOLDINT
Goldberger reference routing
0: Goldberger reference disabled (default)
1: Goldberger reference outputs internally connected to IN4, IN5 and IN6
Note: GOLDINT bit can not be 1 when WILSONINT is 1.
[0]
WILSONINT
Wilson reference routing
0: Wilson reference output internally disconnected from IN6 (default)
1: Wilson reference output internally connected to IN6
Note: WILSONINT bit can not be 1 when GOLDINT is 1.
Reference Registers
Table 31. REF_CN: Internal Reference Voltage Control
Addr
0x11
[7:2]
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
SHDN_ CMREF
BIT0
SHDN_REF
RESERVED
—
[1]
SHDN_CMREF
Shut down the common-mode and right leg drive reference voltage circuitry
0: CM and RLD reference voltage is on (default)
1: Shut down CM and RLD reference voltage
Note: Enable this bit to save power when the analog block is shut down (SHDN_REF = 1).
Power-down mode automatically shuts down the common-mode and right leg drive reference.
[0]
SHDN_REF
Shut down internal 2.4V reference voltage
0: Internal reference voltage is on (default)
1: Shut down internal reference voltage
Note: Enabling this bit allows driving the IC with an external reference voltage on the CVREF pin. Powerdown mode automatically shuts down the internal 2.4V reference.
56
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OSC Control Registers
Table 32. OSC_CN: Clock Source and Output Clock Control
Addr
0x12
[7:3]
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
STRTCLK
BIT1
SHDN_OSC
BIT0
EN_CLKOUT
RESERVED
—
[2]
STRTCLK
Start the clock
0: Clock to digital disabled (default)
1: Enable clock to digital
Note: Set this bit high only after the oscillator has started up or after the oscillator has shut down and the
external clock has started up.
[1]
SHDN_OSC
Select clock source
0: Use internal clock with external crystal on XTAL1 and XTAL2 pins (default)
1: Shut down internal oscillator and use external clock from CLK pin
Note: STRTCLK bit should be low at the time this bit is reconfigured.
[0]
EN_CLKOUT
Enable CLK pin output driver
0: Clock output driver disabled (default)
1: Clock output driver enabled
AFE Control Registers
Table 33. AFE_RES: Analog Front-End Frequency and Resolution
Addr
0x13
[7:6]
BIT7
BIT6
BIT5
FS_HIGH_
CH3
BIT4
FS_HIGH_
CH2
BIT3
FS_HIGH_
CH1
BIT2
EN_HIRES_
CH3
RESERVED
—
[5]
FS_HIGH_CH3
Clock frequency for channel 3
0: 102400Hz (default)
1: 204800Hz
[4 ]
FS_HIGH_CH2
Clock frequency for channel 2
0: 102400Hz (default)
1: 204800Hz
[3]
FS_HIGH_CH1
Clock frequency for channel 1
0: 102400Hz (default)
1: 204800Hz
[2]
EN_HIRES_CH3
High resolution mode for channel 3 instrumentation amplifier
0: Disabled (default)
1: Enabled
[1]
EN_HIRES_CH2
High resolution mode for channel 2 instrumentation amplifier
0: Disabled (default)
1: Enabled
[0]
EN_HIRES_CH1
High resolution mode for channel 1 instrumentation amplifier
0: Disabled (default)
1: Enabled
BIT1
EN_HIRES_
CH2
BIT0
EN_HIRES_
CH1
57
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Table 34. AFE_SHDN_CN: Analog Front-End Shutdown Control
Addr
0x14
[7:6]
BIT7
BIT6
BIT5
SHDN_
SDM_CH3
BIT4
SHDN_
SDM_CH2
BIT3
SHDN_
SDM_CH1
BIT2
SHDN_
INA_CH3
RESERVED
—
[5]
SHDN_SDM_CH3
Shut down the sigma-delta modulator for channel 3
0: Active (default)
1: Shut down
[4 ]
SHDN_SDM_CH2
Shut down the sigma-delta modulator for channel 2
0: Active (default)
1: Shut down
[3]
SHDN_SDM_CH1
Shut down the sigma-delta modulator for channel 1
0: Active (default)
1: Shut down
[2]
SHDN_INA_CH3
Shut down the instrumentation amplifier for channel 3
0: Active (default)
1: Shut down
[1]
SHDN_INA_CH2
Shut down the instrumentation amplifier for channel 2
0: Active (default)
1: Shut down
[0]
SHDN_INA_CH1
Shut down the instrumentation amplifier for channel 1
0: Active (default)
1: Shut down
BIT1
SHDN_
INA_CH2
BIT0
SHDN_
INA_CH1
Table 35. AFE_FAULT_CN: Analog Front-End Fault Detection Control
Addr
0x15
[7:3]
[2]
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
SHDN_
FAULTDET_
CH3
RESERVED
—
SHDN_
FAULTDET_CH3
Disable the instrumentation amplifier fault detection for channel 3
BIT1
SHDN_
FAULTDET_
CH2
BIT0
SHDN_
FAULTDET_
CH1
0: Fault detection active (default)
1: Disable the fault detection
[1 ]
SHDN_
FAULTDET_CH2
Disable the instrumentation amplifier fault detection for channel 2
0: Active (default)
1: Disable the fault detection
[0]
SHDN_
FAULTDET_CH1
Disable the instrumentation amplifier fault detection for channel 1
0: Active (default)
1: Disable the fault detection
58
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Table 36. AFE_PACE_CN: Analog Pace Channel Output Routing Control
Addr
0x17
[7:3]
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
PACE2RLDI
N
BIT1
PACE2WCT
BIT0
SHDN_PACE
RESERVED
—
[2]
PACE2RLDIN
Connect the analog pace channel output to RLDIN pin
0: Analog pace channel output is disconnected from the RLDIN pin (default)
1: Connect the analog pace channel output to the RLDIN pin.
Note: The right leg drive amplifier is disconnected from the RLDIN pin and connected internally to the
RLDREF pin when this bit is 1.
[1 ]
PACE2WCT
Connect the analog pace channel output to WCT pin
0: Analog pace channel output is disconnected from the WCT pin (default)
1: Connect the analog pace channel output to the WCT pin.
Note: The Wilson reference output is disconnected from the WCT pin when this bit is 1. The Wilson
output can be connected internally to IN6 pin with the WILSON_CN register.
[0]
SHDN_PACE
Shut down analog pace channel
0: Analog pace channel is powered up
1: Analog pace channel is shut down (default)
Error Status Registers
Table 37. ERROR_LOD: Lead Off Detect Error Status
Addr
0x18
BIT7
[7:6]
RESERVED
[5:0]
OUT_LOD
BIT6
BIT5
BIT4
BIT3
BIT2
OUT_LOD
BIT1
BIT0
—
Lead Off Detect Status
There is one bit available per input pin, where the MSB corresponds to input pin IN6 and the LSB corresponds
to input pin IN1.
1: Indicates a lead off error detected on the corresponding input pin.
Note: The clock to digital (internal or external) must be enabled in 0x12[2] for this error register to update.
59
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Table 38. ERROR_STATUS: Other Error Status
Addr
0x19
BIT7
SYNC EDGEERR
BIT6
CH3ERR
BIT5
CH2ERR
BIT4
CH1ERR
BIT3
LEADOFF
BIT2
BATLOW
BIT1
RLDRAIL
BIT0
CMOR
[7]
SYNCEDGEERR
Digital synchronization error
1: Indicates a digital synchronization error occurred
[6]
CH3ERR
Channel 3 out-of-range error
1: Indicates an out-of-range error detected on channel 3
[5]
CH2ERR
Channel 2 out-of-range error
1: Indicates an out-of-range error detected on channel 2
[4 ]
CH1ERR
Channel 1 out-of-range error
1: Indicates an out-of-range error detected on channel 1
[3]
LEADOFF
Lead off detected
1: Indicates a lead off was detected on at least one input pin
[2]
BATLOW
Low battery
1: Indicates the battery voltage has dropped below 2.7 V
[1]
RLDRAIL
Right leg drive near rail
1: Indicates the right leg drive amplifier output is approaching the supply rails
[0]
CMOR
Common-mode level out-of-range
1: Indicates the level detected by the common-mode detect block is outside of the input common-mode
range of the amplifiers in the analog front-end
Note: The clock to digital (internal or external) must be enabled in 0x12[2] for this error register to update.
Table 39. ERROR_RANGE1: Channel 1 AFE Out-of-Range Status
Addr
0x1A
BIT7
BIT6
SDM_ OR_CH1
BIT5
SIGN_CH1
BIT4
OUTN_
LOW_CH1
BIT3
OUTN_
HIGH_CH1
BIT2
OUTP_
LOW_CH1
BIT1
OUTP_
HIGH_CH1
BIT0
DIF_HIGH_
CH1
[7]
RESERVED
—
[6]
SDM_OR_CH1
Channel 1 sigma-delta modulator over range
1: Indicates an over range detected for channel 1 SDM
[5]
SIGN_CH1
Channel 1 instrumentation amplifier output sign
This bit specifies the sign of the output signal of the instrumentation amplifier for channel 1.
0: Positive output of INA larger than negative output
1: Positive output of INA smaller than negative output
[4 ]
OUTN_LOW_CH1
Channel 1 instrumentation amplifier negative output near negative rail
1: Indicates the negative output of the INA is close to the negative rail for channel 1
[3]
OUTN_HIGH_CH1
Channel 1 instrumentation amplifier negative output near positive rail
1: Indicates the negative output of the INA is close to the positive rail for channel 1
[2]
OUTP_LOW_CH1
Channel 1 instrumentation amplifier positive output near negative rail
1: Indicates the positive output of the INA is close to the negative rail for channel 1
[1]
OUTP_HIGH_CH1
Channel 1 instrumentation amplifier positive output near positive rail
1: Indicates the positive output of the INA is close to the positive rail for channel 1
[0]
DIF_HIGH_CH1
Channel 1 instrumentation amplifier output out-of-range
1: Indicates the differential output voltage of the INA is out-of-range for channel 1
Note: The clock to digital (internal or external) must be enabled in 0x12[2] for this error register to update.
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Table 40. ERROR_RANGE2: Channel 2 AFE Out-of-Range Status
Addr
0x1B
BIT7
BIT6
SDM_ OR_CH2
BIT5
SIGN_CH2
BIT4
OUTN_
LOW_CH2
BIT3
OUTN_
HIGH_CH2
BIT2
OUTP_
LOW_CH2
BIT1
OUTP_
HIGH_CH2
BIT0
DIF_HIGH_
CH2
[7]
RESERVED
—
[6]
SDM_OR_CH2
Channel 2 sigma-delta modulator over range
1: Indicates an over range detected for channel 2 SDM
[5]
SIGN_CH2
Channel 2 instrumentation amplifier output sign
This bit specifies the sign of the output signal of the instrumentation amplifier for channel 2.
0: Positive output of INA larger than negative output
1: Positive output of INA smaller than negative output
[4 ]
OUTN_LOW_CH2
Channel 2 instrumentation amplifier negative output near negative rail
1: Indicates the negative output of the INA is close to the negative rail for channel 2
[3]
OUTN_HIGH_CH2
Channel 2 instrumentation amplifier negative output near positive rail
1: Indicates the negative output of the INA is close to the positive rail for channel 2
[2]
OUTP_LOW_CH2
Channel 2 instrumentation amplifier positive output near negative rail
1: Indicates the positive output of the INA is close to the negative rail for channel 2
[1]
OUTP_HIGH_CH2
Channel 2 instrumentation amplifier positive output near positive rail
1: Indicates the positive output of the INA is close to the positive rail for channel 2
[0]
DIF_HIGH_CH2
Channel 2 instrumentation amplifier output out-of-range
1: Indicates the differential output voltage of the INA is out-of-range for channel 2
Note: The clock to digital (internal or external) must be enabled in 0x12[2] for this error register to update.
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Table 41. ERROR_RANGE3: Channel 3 AFE Out-of-Range Status
Addr
0x1C
BIT7
BIT6
SDM_ OR_CH3
BIT5
SIGN_CH3
BIT4
OUTN_
LOW_CH3
BIT3
OUTN_
HIGH_CH3
BIT2
OUTP_
LOW_CH3
BIT1
OUTP_
HIGH_CH3
BIT0
DIF_HIGH_
CH3
[7]
RESERVED
—
[6]
SDM_OR_CH3
Channel 3 sigma-delta modulator over range
1: Indicates an over range detected for channel 3 SDM
[5]
SIGN_CH3
Channel 3 instrumentation amplifier output sign
This bit specifies the sign of the output signal of the instrumentation amplifier for channel 3.
0: Positive output of INA larger than negative output
1: Positive output of INA smaller than negative output
[4 ]
OUTN_LOW_CH3
Channel 3 instrumentation amplifier negative output near negative rail
1: Indicates the negative output of the INA is close to the negative rail for channel 3
[3]
OUTN_HIGH_CH3
Channel 3 instrumentation amplifier negative output near positive rail
1: Indicates the negative output of the INA is close to the positive rail for channel 3
[2]
OUTP_LOW_CH3
Channel 3 instrumentation amplifier positive output near negative rail
1: Indicates the positive output of the INA is close to the negative rail for channel 3
[1]
OUTP_HIGH_CH3
Channel 3 instrumentation amplifier positive output near positive rail
1: Indicates the positive output of the INA is close to the positive rail for channel 3
[0]
DIF_HIGH_CH3
Channel 3 instrumentation amplifier output out-of-range
1: Indicates the differential output voltage of the INA is out-of-range for channel 3
Note: The clock to digital (internal or external) must be enabled in 0x12[2] for this error register to update.
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Table 42. ERROR_SYNC: Synchronization Error
Addr
0x1D
[7:4]
BIT7
BIT6
BIT5
BIT4
BIT3
SYNC_PHASEE
RR
BIT2
SYNC_
CH3ERR
RESERVED
—
[3]
SYNC_PHASEERR
Clock timing generator phase error
1: Timing generator phase adjusted to comply with SYNCB signal
[2]
SYNC_CH3ERR
Channel 3 synchronization error
1: Channel's filter timing updated to comply with synchronization source
[1]
SYNC_CH2ERR
Channel 2 synchronization error
1: Channel's filter timing updated to comply with synchronization source
[0]
SYNC_CH1ERR
Channel 1 synchronization error
1: Channel's filter timing updated to comply with synchronization source
BIT1
SYNC_
CH2ERR
BIT0
SYNC_
CH1ERR
BIT1
RLDRAIL_
STATUS
BIT0
CMOR_
STATUS
Table 43. ERROR_MISC: Miscellaneous Error
Addr
0x1E
[7:3]
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BATLOW_
STATUS
RESERVED
—
[2]
BATLOW_STATUS
Low battery error status
1: Indicates the battery voltage has dropped below 2.7 V
[1]
RLDRAIL_STATUS
Right leg drive near rail error status
1: Indicates the right leg drive amplifier output is approaching the supply rails
[0]
CMOR_STATUS
Common-mode level out-of-range error status
1: Indicates the level detected by the common-mode detect block is outside of the input common-mode
range of the amplifiers in the analog front-end
Note: The clock to digital (internal or external) must be enabled in 0x12[2] for this error register to update.
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Digital Registers
Table 44. DIGO_STRENGTH: Digital Output Drive Strength
Addr
0x1F
BIT7
BIT6
BIT5
[7:2]
RESERVED
—
[1:0]
DIGO_STRENGTH
Digital Output Drive Strength
00: Low drive mode
01: Mid-low drive mode
10: Mid-high drive mode
11: High drive mode (Default)
BIT4
BIT3
BIT2
BIT1
BIT0
DIGO_STRENGTH
Table 45. R2_RATE: R2 Decimation Rate
Addr
0x21
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BIT1
BIT0
BIT1
BIT0
R2_RATE
[7:2]
RESERVED
—
[1:0]
R2_RATE
R2 decimation rate
0001: 4
0010: 5
0100: 6
1000: 8 (default)
Note: The register sets to its default value if none or more than one bit are enabled.
Table 46. R3_RATE_CH1: R3 Decimation Rate for Channel 1
Addr
0x22
[7:0]
BIT7
R3_RATE_CH1
BIT6
BIT5
BIT4
BIT3
R3_RATE_CH1
BIT2
R3 decimation rate for channel 1
00000001: 4
00000010: 6
00000100: 8
00001000: 12
00010000: 16
00100000: 32
01000000: 64
10000000: 128 (default)
Note: The register sets to its default value if none or more than one bit are enabled.
Table 47. R3_RATE_CH2: R3 Decimation Rate for Channel 2
Addr
0x23
[7:0]
BIT7
R3_RATE_CH2
BIT6
BIT5
BIT4
BIT3
R3_RATE_CH2
BIT2
R3 decimation rate for channel 2
00000001: 4
00000010: 6
00000100: 8
00001000: 12
00010000: 16
00100000: 32
01000000: 64
10000000: 128 (default)
Note: The register sets to its default value if none or more than one bit are enabled.
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Table 48. R3_RATE_CH3: R3 Decimation Rate for Channel 3
Addr
0x24
[7:0]
BIT7
R3_RATE_CH3
BIT6
BIT5
BIT4
BIT3
R3_RATE_CH3
BIT2
BIT1
BIT0
R3 decimation rate for channel 3
00000001: 4
00000010: 6
00000100: 8
00001000: 12
00010000: 16
00100000: 32
01000000: 64
10000000: 128 (default)
Note: The register sets to its default value if none or more than one bit are enabled.
Table 49. R1_RATE: R1 Decimation Rate
Addr
BIT7
BIT6
BIT5
BIT4
BIT3
0x25
[7:3]
RESERVED
—
[2]
R1_RATE_CH3
Pace data rate for channel 3
0: R1 = 4: Standard PACE Data Rate (default)
1: R1 = 2: Double PACE Data Rate
[1]
R1_RATE_CH2
Pace data rate for channel 2
0: R1 = 4: Standard PACE Data Rate (default)
1: R1 = 2: Double PACE Data Rate
[0]
R1_RATE_CH1
Pace data rate for channel 1
0: R1 = 4: Standard PACE Data Rate (default)
1: R1 = 2: Double PACE Data Rate
Addr
0x26
BIT7
BIT2
BIT1
BIT0
R1_RATE_
CH3
R1_RATE_
CH2
R1_RATE_
CH1
BIT1
DIS_E2
BIT0
DIS_E1
Table 50. DIS_EFILTER: ECG Filter Disable
[7:3]
BIT6
BIT5
BIT4
RESERVED
—
[2]
DIS_E3
Disable the ECG filter for channel 3
0: ECG filter enabled (default)
1: ECG filter disabled
[1]
DIS_E2
Disable the ECG filter for channel 2
0: ECG filter enabled (default)
1: ECG filter disabled
[0]
DIS_E1
Disable the ECG filter for channel 1
0: ECG filter enabled (default)
1: ECG filter disabled
BIT3
BIT2
DIS_E3
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Table 51. DRDYB_SRC: Data Ready Pin Source
Addr
0x27
BIT7
BIT6
BIT5
BIT4
BIT3
[7:6]
RESERVED
—
[6:0]
DRDYB_SRC
Select channel to drive the DRDYB pin
000000: DRDYB pin not asserted (default)
000001: Driven by channel 1 pace
000010: Driven by channel 2 pace
000100: Driven by channel 3 pace
001000: Driven by channel 1 ECG
010000: Driven by channel 2 ECG
100000: Driven by channel 3 ECG
Addr
0x28
BIT7
BIT2
DRDYB_SRC
BIT1
BIT0
BIT1
BIT0
Table 52. SYNCB_CN: SYNCB In/Out Pin Control
BIT6
DIS_SYNCB
OUT
BIT5
BIT4
BIT3
BIT2
SYNCB_SRC
[7]
RESERVED
—
[6]
DIS_SYNCBOUT
Disable the SYNCB pin output driver
0: Driver enabled and pin configured as output
1: Driver disabled and pin configured as input (default)
Note: Bit should be set to 1 for slave devices.
[5:0]
SYNCB_SRC
Select channel to drive the SYNCB pin
000000: No source selected (default)
000001: Driven by channel 1 pace
000010: Driven by channel 2 pace
000100: Driven by channel 3 pace
001000: Driven by channel 1 ECG
010000: Driven by channel 2 ECG
100000: Driven by channel 3 ECG
Note: Choose the slowest pace or ECG channel as source. Bits[5:0] must be cleared to 0 for slave
devices.
Addr
0x29
BIT7
Table 53. MASK_DRDYB: Optional Mask Control for DRDYB Output
[7:2]
BIT6
BIT5
BIT4
BIT3
BIT2
RESERVED
—
[1]
DRDYBMASK_CTL1
START_CON mask control for DRDYB output
0: DRDYB signal is masked when START_CON is set (default)
1: Disable initial DRDYB masking when START_CON is set
[0]
DRDYBMASK_CTL0
Optional mask control for DRDYB output
0: DRDYB signal is masked after out of sync is detected (default)
1: Disable DRDYB masking after out of sync is detected
BIT1
DRDYB
MASK_CTL1
BIT0
DRDYB
MASK_CTL0
Note: If an ECG channel is enabled, DRDYB is masked during 6 ECG output data periods.
If all ECG channels are disabled, DRDYB is masked during 6 or 11 pace output data periods, for 1x pace or 2x pace mode respectively.
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Table 54. MASK_ERR: Mask Error on ALARMB Pin
Addr
0x2A
BIT7
MASK_SYNC
EDGEERR
BIT6
MASK_
CH3ERR
BIT5
MASK_
CH2ERR
BIT4
MASK_
CH1ERR
BIT3
MASK_
OUTLOD
[7]
MASK_SYNCEDGEERR
Mask alarm condition when SYNCEDGEERR=1
0: Alarm condition is active (default)
1: Alarm condition is masked
[6]
MASK_CH3ERR
Mask alarm condition for CH3ERR=1
0: Alarm condition active (default)
1: Alarm condition is masked
[5]
MASK_CH2ERR
Mask alarm condition for CH2ERR=1
0: Alarm condition active (default)
1: Alarm condition is masked
[4 ]
MASK_CH1ERR
Mask alarm condition for CH1ERR=1
0: Alarm condition active (default)
1: Alarm condition is masked
[3]
MASK_LEADOFF
Mask alarm condition for LEADOFF=1
0: Alarm condition active (default)
1: Alarm condition is masked
[2]
MASK_BATLOW
Mask alarm condition for BATLOW=1
0: Alarm condition active (default)
1: Alarm condition is masked
[1]
MASK_RLDRAIL
Mask alarm condition for RLDRAIL=1
0: Alarm condition active (default)
1: Alarm condition is masked
[0]
MASK_CMOR
Mask alarm condition for CMOR=1
0: Alarm condition active (default)
1: Alarm condition is masked
Addr
0x2E
BIT7
BIT2
MASK_
BATLOW
BIT1
MASK_
RLDRAIL
BIT0
MASK_
CMOR
Table 55. ALARM_FILTER: Digital Filter for Analog Alarm Signals
BIT6
BIT5
AFILTER_OTHER
BIT4
BIT3
BIT2
BIT1
AFILTER_LOD
[7:4]
AFILTER_OTHER
Filter for all other alarms count
Number of consecutive analog alarm signal counts+1 before ALARMB is asserted.
0011: (default)
[3:0]
AFILTER_LOD
Filter for OUT_LOD[5:0] alarm count
Number of consecutive lead off alarm signal counts+1 before ALARMB is asserted.
0011: (default)
BIT0
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Table 56. CH_CNFG: Configure Channel for Loop Read Back Mode
Addr
0x2F
BIT7
BIT6
E3_EN
BIT5
E2_EN
BIT4
E1_EN
BIT3
P3_EN
[7]
RESERVED
—
[6]
E3_EN
Enable DATA_CH3_ECG read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[5]
E2_EN
Enable DATA_CH2_ECG read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[4 ]
E1_EN
Enable DATA_CH1_ECG read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[3]
P3_EN
Enable DATA_CH3_PACE read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[2]
P2_EN
Enable DATA_CH2_PACE read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[1]
P1_EN
Enable DATA_CH1_PACE read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[0]
STS_EN
Enable DATA_STATUS read back
0: Disable data status read back (default)
1: Enable data status read back
BIT2
P2_EN
BIT1
P1_EN
BIT0
STS_EN
BIT1
ALARMB
BIT0
0
Pace and ECG Data Read Back Registers
Table 57. DATA_STATUS: ECG and Pace Data Ready Status
Addr
0x30
BIT7
E3_DRDY
BIT6
E2_DRDY
BIT5
E1_DRDY
BIT4
P3_DRDY
BIT3
P2_DRDY
[7]
E3_DRDY
Channel 3 ECG data ready
1: Channel 3 ECG data ready
[6]
E2_DRDY
Channel 2 ECG data ready
1: Channel 2 ECG data ready
[5]
E1_DRDY
Channel 1 ECG data ready
1: Channel 1 ECG data ready
[4 ]
P3_DRDY
Channel 3 pace data ready
1: Channel 3 pace data ready
[3]
P2_DRDY
Channel 2 pace data ready
1: Channel 2 pace data ready
[2]
P1_DRDY
Channel 1 pace data ready
1: Channel 1 pace data ready
[1]
ALARMB
ALARMB status
1: Alarm active (ALARMB output pin driven low)
[0]
Reserved
—
0
68
BIT2
P1_DRDY
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Table 58. DATA_CH1_PACE: Channel 1 Pace Data
Addr
0x31
BIT15
BIT14
BIT13
BIT7
BIT6
BIT5
0x32
BIT12
BIT11
DATA_CH1_PACE
BIT4
BIT3
DATA_CH1_PACE
[15:8]
DATA_CH1_PACE
Channel 1 pace data
Address 0x31 contains the upper byte
[7:0]
DATA_CH1_PACE
Channel 1 pace data
Address 0x32 contains the lower byte
BIT10
BIT9
BIT8
BIT2
BIT1
BIT0
BIT10
BIT9
BIT8
BIT2
BIT1
BIT0
BIT10
BIT9
BIT8
BIT2
BIT1
BIT0
BIT18
BIT7
BIT6
BIT10
BIT9
BIT8
BIT2
BIT1
BIT0
Table 59. DATA_CH2_PACE: Channel 2 Pace Data
Addr
0x33
BIT15
BIT14
BIT13
BIT7
BIT6
BIT5
0x34
[15:8]
BIT12
BIT11
DATA_CH2_PACE
BIT4
BIT3
DATA_CH2_PACE
DATA_CH2_PACE
Channel 2 pace data
Address 0x33 contains the upper byte
DATA_CH2_PACE
Channel 2 pace data
Address 0x34 contains the lower byte
[7:0]
Table 60. DATA_CH3_PACE: Channel 3 Pace Data
Addr
0x35
BIT15
BIT14
BIT13
BIT7
BIT6
BIT5
0x36
BIT12
BIT11
DATA_CH3_PACE
BIT4
BIT3
DATA_CH3_PACE
[15:8]
DATA_CH3_PACE
Channel 3 pace data
Address 0x35 contains the upper byte
[7:0]
DATA_CH3_PACE
Channel 3 pace data
Address 0x36 contains the lower byte
Table 61. DATA_CH1_ECG: Channel 1 ECG Data
Addr
0x37
BIT23
BIT22
BIT21
BIT15
BIT14
BIT13
BIT7
BIT6
BIT5
0x38
0x39
BIT20
BIT19
DATA_CH1_ECG
BIT12
BIT11
DATA_CH1_ECG
BIT4
BIT3
DATA_CH1_ECG
[23:16]
DATA_CH1_ECG
Channel 1 ECG data
Address 0x37 contains the upper byte
[15:8]
DATA_CH1_ECG
Channel 1 ECG data
Address 0x38 contains the middle byte
[7:0]
DATA_CH1_ECG
Channel 1 ECG data
Address 0x39 contains the lower byte
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Table 62. DATA_CH2_ECG: Channel 2 ECG Data
Addr
0x3A
BIT23
BIT22
BIT21
BIT15
BIT14
BIT13
BIT7
BIT6
BIT5
BIT20
BIT19
DATA_CH2_ECG
BIT12
BIT11
DATA_CH2_ECG
BIT4
BIT3
DATA_CH2_ECG
0x3B
0x3C
[23:16]
DATA_CH2_ECG
Channel 2 ECG data
Address 0x3A contains the upper byte
[15:8]
DATA_CH2_ECG
Channel 2 ECG data
Address 0x3B contains the middle byte
[7:0]
DATA_CH2_ECG
Channel 2 ECG data
Address 0x3C contains the lower byte
BIT18
BIT7
BIT6
BIT10
BIT9
BIT8
BIT2
BIT1
BIT0
BIT18
BIT7
BIT6
BIT10
BIT9
BIT8
BIT2
BIT1
BIT0
BIT2
BIT1
BIT0
BIT1
BIT0
Table 63. DATA_CH3_ECG: Channel 3 ECG Data
Addr
0x3D
BIT23
BIT22
BIT21
BIT15
BIT14
BIT13
BIT7
BIT6
BIT5
BIT20
BIT19
DATA_CH3_ECG
BIT12
BIT11
DATA_CH3_ECG
BIT4
BIT3
DATA_CH3_ECG
0x3E
0x3F
[23:16]
DATA_CH3_ECG
Channel 3 ECG data
Address 0x3D contains the upper byte
[15:8]
DATA_CH3_ECG
Channel 3 ECG data
Address 0x3E contains the middle byte
[7:0]
DATA_CH3_ECG
Channel 3 ECG data
Address 0x3F contains the lower byte
Table 64. REVID: Revision ID
Addr
0x40
[7:0]
BIT7
REVID
BIT6
BIT5
BIT4
BIT3
REVID
Revision ID
00000001 (Default)
Table 65. DATA_LOOP: Loop Read Back Address
Addr
0x50
BIT7
[7:0]
PE_LPRD
BIT6
BIT5
BIT4
BIT3
PE_LPRD
BIT2
Loop read back address
Special address to read back the contents of registers 0x30 - 0x3F if they are enabled in CH_CNFG.
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PACKAGE OPTION ADDENDUM
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24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS1293CISQ/NOPB
ACTIVE
WQFN
RSG
28
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-20 to 85
ADS1293
ADS1293CISQE/NOPB
ACTIVE
WQFN
RSG
28
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-20 to 85
ADS1293
ADS1293CISQX/NOPB
ACTIVE
WQFN
RSG
28
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-20 to 85
ADS1293
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS1293CISQ/NOPB
WQFN
RSG
28
ADS1293CISQE/NOPB
WQFN
RSG
ADS1293CISQX/NOPB
WQFN
RSG
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
28
250
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
28
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1293CISQ/NOPB
WQFN
RSG
28
1000
203.0
190.0
41.0
ADS1293CISQE/NOPB
WQFN
RSG
28
250
203.0
190.0
41.0
ADS1293CISQX/NOPB
WQFN
RSG
28
4500
358.0
343.0
63.0
Pack Materials-Page 2
MECHANICAL DATA
RSG0028A
SQA28A (Rev B)
www.ti.com
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