LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 LDC1000 Inductance to Digital Converter Check for Samples: LDC1000 FEATURES DESCRIPTION • • • • • Inductive Sensing is a contact-less, short-range sensing technology that enables low-cost, highresolution sensing of conductive targets in the presence of dust, dirt, oil, and moisture, making it extremely reliable in hostile environments. Using a coil which can be created on a PCB as a sensing element, the LDC1000 enables ultra-low cost system solutions. 1 • • • • • • • • Magnet-Free Operation Sub-Micron Precision Adjustable Sensing Range (via Coil Design) Lower System Cost Remote Sensor Placement (Decoupling the LDC from Harsh Environments) High Durability (by Virtue of Contact-Less Operation) Insensitivity to Environmental Interference (such as Dirt, Dust, Water, Oil) Supply Voltage, Analog: 4.75V to 5.25V Supply Voltage, IO: 1.8V to 5.25V Supply Current (w/o LC Tank): 1.7mA Rp Resolution: 16-bit L Resolution: 24-bit LC Frequency Range: 5kHz to 5MHz APPLICATIONS • • • • • • • • • Drive-by-Wire Systems Gear-Tooth Counting Flow Meters Push-Button Switches Notebook Computers Game Controllers Multi-Function Printers Digital Cameras Medical Devices Inductive sensing technology enables precise measurement of linear/angular position, displacement, motion, compression, vibration, metal composition, and many other applications in markets including automotive, consumer, computer, industrial, medical, and communications. Inductive sensing offers better performance and reliability at lower cost than other, competitive solutions. The LDC1000 is the world’s first inductance-to-digital converter, offering the benefits of inductive sensing in a low-power, small-footprint solution. The product is available in a SON-16 package and offers several modes of operation. An SPI interface simplifies connection to an MCU. TYPICAL APPLICATION Figure 1. Axial Distance Sensing 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. BLOCK DIAGRAM CFA CFB Threshold Detector L SCLK INA INB C SDI 4-Wire Serial Interface Proximity Data Register LDC SDO CS Frequency Counter Data Register INTB Rs Power GND VDD VIO Frequency Counter DGND CLDO TBCLK/XIN XOUT Figure 2. LDC1000 Block Diagram TYPICAL APPLICATION SCHEMATIC 5V VIO 5V LDO VIO VDD MOSI SDI INA MISO SDO SCLK SCLK GPIO CSB INT/GPIO INTB CFA TBCLK CFB VIO MCU Timer/Aux CLK INB LDC1000 DGND Sensor GND DGND CLDO DGND DAP AGND DGND Figure 3. Typical Application Schematic 2 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 CONNECTION DIAGRAM SCLK 1 16 INTB CSB 2 15 XOUT SDI 3 14 TBCLK/XIN VIO 4 13 CLDO SDO 5 12 VDD DGND 6 11 GND CFB 7 10 INB CFA 8 9 INA DAP (GND) Figure 4. LDC1000 Pin Diagram SON-16 Table 1. Pin Description (1) PIN NAME PIN NO. PIN TYPE FUNCTION SCLK 1 DO SPI clock input. SCLK is used to clock-out/clock-in the data from/into the chip CSB 2 DI SPI CSB. Multiple devices can be connected on the same SPI bus and CSB can be used to select the device to be communicated with SDI 3 DI SPI Slave Data In (Master Out Slave In). This should be connected to the Master Out Slave In of the master VIO 4 P Digital IO Supply SDO 5 DO SPI Slave Data Out (Master In Slave Out).It is high-z when CSB is high DGND 6 P Digital ground CFB 7 A LDC filter capacitor CFA 8 A LDC filter capacitor INA 9 A External LC Tank. Connected to external LC tank INB 10 A External LC Tank. Connected to external LC tank GND 11 P Analog ground VDD 12 P Analog supply CLDO 13 A LDO bypass capacitor. A 56nF capacitor should be connected from this pin to GND TBCLK/XIN 14 DI/A External time-base clock/XTAL. Either an external clock or crystal can be connected XOUT 15 A XTAL. Crystal out. Recommended to connect 8Mhz crystal between XIN and XOUT with 20pF cap from each pin to ground. Should be floating when external clock is used INTB 16 DO Configurable interrupt. This pin can be configured to behave in 3 different ways by programing the INT pin mode register. Either threshold detect, wakeup, or DRDYB DAP 17 P Connect to GND (1) DO: Digital Output, DI: Digital Input, P: Power, A: Analog 3 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) Human Body Model ESD Tolerance (2) 1kV Charge Device Model 250V Analog Supply Voltage (VDD – GND) 6V IO Supply Voltage (VIO – GND) 6V Voltage on any Analog Pin -0.3V to VDD + 0.3V Voltage on any Digital Pin -0.3V to VIO + 0.3V Input Current on INA and INB Junction Temperature, TJ 8mA (3) +150°C Storage Temperature Range , Tstg (1) (2) (3) -65°C to +150°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) MIN MAX UNIT Analog Supply Voltage (VDD – GND) 4.75 5.25 V IO Supply Voltage (VIO – GND) 1.8 5.25 V VDD-VIO >=0 Operating Temperature, TA -40 125 °C 28 °C/W Package Thermal Resistance (2) (1) (2) SON (θJA) V Absolute Maximum Ratings are limits beyond which damage to the device may occur. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. The package thermal impedance is calculated in accordance with JESD 51-7. 4 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (1) Unless otherwise specified, all limits ensured for TA = TJ = 25°C, VDD = 5.0V, VIO = 3.3V (2) SYMBOL PARAMETER CONDITIONS/ COMMENTS MIN (3) TYP (4) MAX (3) UNITS 4.75 5 5.25 V 1.8 3.3 5.25 V 1.7 2.3 mA 14 uA POWER VDD Analog Supply Voltage VIO IO Supply Voltage VIO≤VDD IDD Supply Current, VDD Does not include LC tank current IVIO IO Supply Current Static current IDD_LP Low-Power Mode Supply Current With out LC Tank 250 uA Start-Up Time From POR to ready-toconvert. Crystal not used for frequency counter 2 ms tSTART LDC fsensor_MIN Minimum sensor frequency 5 kHz fsensor_MAX Maximum sensor frequency 5 MHz Asensor_MIN Minimum sensor amplitude 1 VPP Asensor_MAX Maximum sensor amplitude 4 VPP 10 1/fsensor tREC Recovery time Oscillation start-up time after RP under-range condition Rp_MIN Minimum Sensor Rp Range 798 Ω Rp_MAX Maximum Sensor Rp Range 3.93M Ω Rp_RES Rp Measurement Resolution 16 Bits tS_MIN tS_MAX Minimum Response Time Minimum programmable settling time of digital filter 192×1/fsensor s Maximum Response Time Maximum programmable settling time of digital filter 6144×1/fsensor s Frequency 8 MHz Startup time 30 ms EXTERNAL CLOCK/CRYSTAL FOR FREQUENCY COUNTER Crystal External Clock (1) (2) (3) (4) Frequency 8 MHz Clock Input High Voltage VIO V Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. The package thermal impedance is calculated in accordance with JESD 51-7. Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. 5 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) Unless otherwise specified, all limits ensured for TA = TJ = 25°C, VDD = 5.0V, VIO = 3.3V(2) SYMBOL PARAMETER CONDITIONS/ COMMENTS MIN (3) TYP (4) MAX (3) UNITS DIGITAL I/O CHARACTERISTICS VIH Logic "1" Input Voltage VIL Logic "0" Input Voltage 0.8×VIO VOH Logic "1" Output Voltage ISOURCE=400uA VOL Logic "0" Output Voltage ISINK=400uA IIOHL Digital IO Leakage Current V 0.2×VIO VIO-0.3 -500 6 V V 0.3 V 500 nA Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 TIMING DIAGRAMS Unless otherwise noted, all limits specified at TA = 25°C, VDD=5.0, VIO=3.3, 10pF capacitive load in parallel with a 10kΩ load on SDO. Specified by design; not production tested. ttPLt ttPHt 16th Clock SCLK ttSUt ttHt Valid Data SDI Valid Data Figure 5. Write Timing Diagram Table 2. PARAMETER CONDITIONS MIN TYP MAX UNIT 4 MHz FSCLK Serial Clock Frequency tPH SCLK Pulse Width High FSCLK=4Mhz 0.4/Fsclk tPL SCLK Pulse Width Low FSCLK=4Mhz 0.4/Fsclk s tSU SDI Setup Time 10 ns tH SDI Hold Time 10 ns 1st Clock 8th Clock s 16th Clock xx xx SCLK t t t CSHt SCLK t CSSt t x tOZD tOD D7 t t CSSt ttHt x SDI tCSHt D1 D0 Figure 6. Read Timing Diagram PARAMETER CONDITIONS MIN TYP MAX UNIT tODZ SDO Driven-to-Tristate Time Measured at 10% / 90% point 20 ns tOZD SDO Tristate-to-Driven Time Measured at 10% / 90% point 20 ns 20 ns tOD SDO Output Delay Time tCSS CSB Setup Time 20 ns tCSH CSB Hold Time 20 ns tIAG Inter-Access Gap tDRDYB Data ready pulse width 100 Data ready pulse at every 1/ODR if no data is read ns 1/fsensor s 7 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com THEORY OF OPERATION Inductive Sensing An AC current flowing through a coil will generate an AC magnetic field. If a conductive material, such as a metal target, is brought into the vicinity of the coil, this magnetic field will induce circulating currents (eddy currents) on the surface of the target. These eddy currents are a function of the distance, size, and composition of the target. These eddy currents then generate their own magnetic field, which opposes the original field generated by the coil. This mechanism is best compared to a transformer, where the coil is the primary core and the eddy current is the secondary core. The inductive coupling between both cores depends on distance and shape. Hence the resistance and inductance of the secondary core (Eddy current), shows up as a distant dependent resistive and inductive component on the primary side (coil). The figures below show a simplified circuit model. d Metal Target Figure 7. Inductor with a Metal Target Eddy currents generated on the surface of the target can be modeled as a transformer as shown in Figure 8. The coupling between the primary and secondary coils is a function of the distance and conductor’s characteristics. In Figure 8, the inductance Ls is the coil’s inductance, and Rs is the coil’s parasitic series resistance. The inductance L(d), which is a function of distance d, is the coupled inductance of the metal target. Likewise, R(d) is the parasitic resistance of the eddy currents. Eddy Currents Ls + L(d) Conductance of Metal Target Metal Surface Distance d Rs + R(d) Figure 8. Metal Target Modeled as L and R with Circulating Eddy Currents 8 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 Generating an alternating magnetic field with just an inductor will consume a large amount of power. This power consumption can be reduced by adding a parallel capacitor, turning it into a resonator as shown in Figure 9 . In this manner the power consumption is reduced to the eddy and inductor losses Rs+R(d) only. L(d) C Oscillator Rs(d) Figure 9. LC Tank Connected to Oscillator The LDC1000 doesn’t measure the series resistance directly; instead it measures the equivalent parallel resonance impedance Rp (see Figure 10). This representation is equivalent to the one shown in Figure 10 , where the parallel resonance impedance Rp(d) is given by: Rp(d)=(1⁄([Rs+R(d)])*([Ls+L(d)])⁄C. L(d) C Rp(d) Oscillator Figure 10. Equivalent Resistance of Rs in Parallel with LC Tank Rp = (1/Rs)*(L/C). 9 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com Figure 11 below shows the variation in Rp as a function of distance for a 14mm diameter PCB coil(23 turns,4 mil trace width, 4mil spacing between trace,1oz Cu thickness,FR4). Target used is a Stainless steel 2mm thick. 20 18 16 Rp (K) 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 Distance (mm) C001 Figure 11. Typical Rp Vs Distance with 14mm PCB Coil Measuring Parallel Resonance Impedance and Inductance with LDC1000 The LDC1000 is an Inductance-to-Digital Converter that simultaneously measures the impedance and resonant frequency of an LC resonator. It accomplishes this task by regulating the oscillation amplitude in a closed loop configuration to a constant level, while monitoring the energy dissipated by the resonator. By monitoring the amount of power injected into the resonator, the LDC1000 can determine the value of Rp; it returns this as a digital value which is inversely proportional to Rp. In addition, the LDC1000 can also measure the oscillation frequency of the LC circuit; this frequency is used to determine the inductance of the LC circuit. The oscillation frequency is returned as a digital value. The LDC1000 supports a wide range of LC combinations, with oscillation frequencies ranging from 5kHz to 5MHz and Rp ranging from 798Ω to 3.93MΩ. This range of Rp can be viewed as the maximum input range of an ADC. As illustrated in Figure 11, the range of Rp is typically a much smaller than maximum input range supported by the LDC1000. To get better resolution in the desired sensing range, the LDC1000 offers programmable input range through the Rp_MIN and Rp_MAX registers. Refer to Calculation of Rp Min and Rp Max below for how to set these registers. When the sensor’s resonance impedance Rp drops below the programed Rp_MIN, the LDC’s Rp output will clip at its full scale output. This situation could for example happen when a target comes too close to the coil. 30000 Code (decimal) 25000 20000 15000 10000 5000 0 12 17 22 27 32 Rp (K) 37 42 47 C001 Figure 12. Transfer Characteristics of LDC1000 with Rp_MIN= 16.160 kΩ and Rp_MAX= 48.481 kΩ 10 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 The resonance impedance can be calculated from the digital output code as follows: RP = (RPMAX × RPMIN ) / ( RPMIN×(1-Y) + RPMAX × Y ) , in Ω. Where: • • Y=Proximity Data/215 Proximity data is the LDC output, register address 0x21 and 0x22. (1) Example: If Proximity data (address 0x22:0x21) is 5000, Rp_MIN is 2.394 kΩ, and Rp_MAX is 38.785 kΩ ,the resonance impedance is given by: Y=5000/215 = 0.1526 RP=(38785*2394)/(2394×(1-0.1526) + 38785×0.1526) =(92851290)/(2028.675 + 5918.591) RP =11.683 kΩ Figure 13 and Figure 14below show the change in RMS noise versus distance and a histogram of noise, with the target at 0.8mm distance from the sensor coil. Data was collected with a 14mm PCB coil(23 turns,4 mil trace width, 4mil spacing between trace,1oz Cu thickness,FR4) with a sensing range of 0.125mm to 1.125mm. At a distance of 0.8mm, the RMS noise is approximately 250nm. 140 0.6 120 100 0.4 Count 0.3 0.2 80 60 40 0.1 Distance (mm) 1.2 C001 Figure 13. Typical RMS Noise Vs. Distance with PCB Coil Deviation (µm) 1.00 1.0 0.75 0.8 0.50 0.6 0.25 0.4 0.00 0.2 ±0.25 0.0 ±0.50 0 0.0 ±0.75 20 ±1.00 RMS Noise (µm) 0.5 C001 Figure 14. Histogram of Output Codes at 0.8mm Distance Note that while the LDC1000 has high resolution, its absolute accuracy depends on offset and gain correction which can be achieved by two-point calibration. Calculation of Rp Min and Rp Max Different sensing applications may have a different ranges of the resonance impedance Rp to measure. The LDC1000 measurement range of Rp is controlled by setting 2 registers – Rp_MIN and Rp_MAX. For a given application, Rp must never be outside the range set by these register values, otherwise the measured value will be clipped. For optimal sensor resolution, the range of Rp_MIN to Rp_MAX should not be unnecessarily large. The following procedure is recommended to determine the Rp_MIN and Rp_MAX register values. Rp_MAX Rp_MAX sets the upper limit of the LDC1000 resonant impedance input range. • • • Configure the sensor such that the eddy current losses are minimized. As an example, for a proximity sensing application, set the distance between the sensor and the target to the maximum sensing distance. Measure the resonant impedance Rp using an impedance analyzer. Multiply Rp by 2 and use the next higher value from Table 6. 11 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com For example, if Rp at 8mm is measured to be 18kΩ, 18000×2 = 36000. In Table 6, then 38.785kΩ is the smallest value larger than 36kΩ; this corresponds to Rp_MAX value of 0x11. Note that setting Rp_MAX to a value not listed in Table 6 can result in indeterminate behavior. Rp_MIN Rp_MIN sets the lower limit of the LDC1000 resonant impedance input range. • • • Configure the sensor such that the eddy current losses are maximized. As an example, for a proximity sensing application, set the distance between the sensor and the metal target to the minimum sensing distance. Measure the resonant impedance Rp using an impedance analyzer. Divide the Rp value by 2 and then select the next lower Rp value from Table 8. For example, if Rp at 1mm is measured to be 5kΩ, 5000/2 = 2500. In Table 8 , 2.394kΩ is the smallest value lower than 2.5kΩ; this corresponds to Rp_MIN value of 0x3B. Note that setting Rp_MIN to a value not listed on Table 8 can result in indeterminate behavior. In addition, Rp_MIN powers on with a default value of 0x14 which must be set to a value from Table 8 prior to powering on the LDC. Measuring Inductance LDC1000 measures the sensor’s frequency of oscillation by a frequency counter. The frequency counter timing is set by an external clock or crystal. Either the external clock(8MHz typical) from microcontroller can be provided on the TBCLK pin or a crystal can be connected on the XTALIN and XTALOUT pins. The clock mode is controlled through Clock Configuration register (address 0x05). The sensor resonance frequency is derived from the frequency counter registers value (see registers 0x23 through 0x25) as follows: Sensor frequency, fsensor = (1/3)*(Fext/Fcount)*(Response Time) where Fext is the frequency of the external clock or crystal, Fcount is the value obtained from the Frequency Counter Data register(address 0x23,0x24,0x25), and Response Time is the programmed response time (see LDC configuration register, address 0x04). The Inductance can be calculated as follows: L=1/[C*(2*π*fsensor)2], (2) where C is the parallel capacitance of the resonator. Example: If Fext=6Mhz, Response time=6144, C=100pF and measured Fcount= 3000 (dec) (address 0x23 through 0x25) fsensor=(1/3)*(6000000/3000)*(6144)= 4.096Mhz Now using, L=1/[C*(2*π*fsensor)2] Inductance, L = 15.098uH The accuracy of measurement largely depends upon the choice of the external time-base clock (TBCLK) or the crystal oscillator (XIN/XOUT). Output Data Rate Output data rate of LDC1000 depends on the sensor frequency, fsensor and 'Response Time' field in LDC Configuration register(Address:0x04). Output data rate=( fsensor)/(Response Time/3), Sample per second(SPS) Example: If fsensor=5Mhz and Response Time=192 Output data rate= (5M)/(192/3)= 78.125 KSPS 12 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 Choosing Filter Capacitor (CFA and CFB Pins) The Filter capacitor is critical to the operation of the LDC1000. The capacitor should be low leakage, temperature stable, and it must not generate any piezoelectric noise (the dielectrics of many capacitors exhibit piezoelectric characteristics and any such noise is coupled directly through Rp into the converter). The optimal capacitance values range from 20pF to 100nF. The value of the capacitor is based on the time constant and resonating frequency of the LC tank. If a ceramic capacitor is used, then a C0G (or NP0) grade dielectric is recommended; the voltage rating should be ≥10V. The traces connecting CFA and CFB to the capacitor should be as short as possible to minimize any parasitics. For optimal performance, the chosen filter capacitor, connected between pins CFA and CFB, needs to be as small as possible, but large enough such that the active filter does not saturate. The size of this capacitor depends on the time constant of the sense coil, which is given by L/Rs, (L=inductance, Rs=series resistance of the inductor at oscillation frequency). The larger this time constant, the larger filter capacitor is required. Hence, this time constant reaches its maximum when there is no target present in front of the sensing coil. The following procedure can be used to find the optimal filter capacitance: 1. Start with a large filter capacitor. For a ferrite core coil, 10nF is usually large enough. For an air coil or PCB coil, 100pF is usually large enough. 2. Power on the LDC and set the desired register values. Minimize the eddy currents losses by ensuring there is maximum clearance between the target and the sensing coil. 3. Observe the signal on the CFB pin using a scope. Since this node is very sensitive to capacitive loading, it is recommended to use an active probe. As an alternative, a passive probe with a 1kΩ series resistance between the tip and the CFB pin can be used. 4. Vary the values of the filter capacitor until that the signal observed on the CFB pin has an amplitude of approximate 1V peak-to-peak. This signal scales linearly with the reciprocal of the filter capacitance. For example, if a 100pF filter capacitor is applied and the signal observed on the CFB pin has a peak-to-peak value of 200mV, the desired 1V peak-to-peak value is obtained using a 200mV / 1V * 100pF = 20pF filter capacitor. The waveforms below were taken on the CFB pin with a 14mm, 2 layer PCB coil(23 turns,4 mil trace width, 4mil spacing between trace,1oz Cu thickness,FR4): Figure 15. Waveform on CFB with 100pF Figure 16. Waveform on CFB with 20pF 13 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com PROGRAMMABLE REGISTERS Table 3. Register Map (1) (2) (3) Register Name Address Direction Default Device ID 0x00 RO 0x80 Device ID Rp_MAX 0x01 R/W 0x0E Rp Maximum Rp_MIN 0x02 R/W 0x14 Rp Minimum Sensor Frequency 0x03 R/W 0x45 Min Resonating Frequency LDC Configuration 0x04 R/W 0x1B Clock Configuration 0x05 R/W 0x01 Comparator Threshold High LSB 0x06 R/W 0xFF Threshold High LSB Comparator Threshold High MSB 0x07 R/W 0xFF Threshold High MSB Comparator Threshold Low LSB 0x08 R/W 0x00 Threshold Low LSB Comparator Threshold Low MSB 0x09 R/W 0x00 Threshold Low MSB INTB Pin Configuration 0x0A R/W 0x00 Power Configuration 0x0B R/W 0x00 Status 0x20 RO Proximity Data LSB 0x21 RO Proximity Data[7:0] Proximity Data MSB 0x22 RO Proximity Data[15:8] Frequency Counter Data LSB 0x23 RO ODR LSB Frequency Counter Data Mid-Byte 0x24 RO ODR Mid Byte Frequency Counter Data MSB 0x25 RO ODR MSB (1) (2) (3) Bit 7 Bit 6 Bit 5 Bit 4 Reserved(000) Bit 3 Amplitude Reserved(000000) Bit 2 Bit 1 Response Time CLK_SE L Reserved(00000) DRDYB Wake-up CLK_PD INTB_MODE Reserved(0000000) OSC Dead Bit 0 Compara tor PWR_M ODE Do not Care Values of Bits which are unused should be set to default values only. Registers 0x01 through 0x05 are Read Only when the part is awake (DIS_STBY bit is SET) R/W: Read/Write. RO: Read Only. WO: Write Only. Register Description Table 4. Revision ID Address = 0x00, Default=0x80, Direction=RO Bit Field Field Name Description 7:0 Revision ID Revision ID of Silicon. 14 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 Table 5. Rp_MAX Address = 0x01, Default=0x0E, Direction=R/W Bit Field Field Name Description 7:0 Rp Maximum Maximum Rp that LDC1000 needs to measure. Configures the input dynamic range of LDC1000. See Table 6 for register settings. Table 6. Register settings for Rp_MAX Register setting Rp (kΩ) 0x00 3926.991 0x01 3141.593 0x02 2243.995 0x03 1745.329 0x04 1308.997 0x05 981.748 0x06 747.998 0x07 581.776 0x08 436.332 0x09 349.066 0x0A 249.333 0x0B 193.926 0x0C 145.444 0x0D 109.083 0x0E 83.111 0x0F 64.642 0x10 48.481 0x11 38.785 0x12 27.704 0x13 21.547 0x14 16.160 0x15 12.120 0x16 9.235 0x17 7.182 0x18 5.387 0x19 4.309 0x1A 3.078 0x1B 2.394 0x1C 1.796 0x1D 1.347 0x1E 1.026 0x1F 0.798 Table 7. Rp_MIN Address = 0x02, Default=0x14, Direction=R/W (1) Bit Field Field Name Description 7:0 Rp Minimum Minimum Rp that LDC1000 needs to measure. Configures the input dynamic range of LDC1000. See Table 8 for register settings. (1) This Register needs a mandatory write as it defaults to 0x14. 15 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com Table 8. Register Settings for Rp_MIN Register setting Rp (kΩ) 0x20 3926.991 0x21 3141.593 0x22 2243.995 0x23 1745.329 0x24 1308.997 0x25 981.748 0x26 747.998 0x27 581.776 0x28 436.332 0x29 349.066 0x2A 249.333 0x2B 193.926 0x2C 145.444 0x2D 109.083 0x2E 83.111 0x2F 64.642 0x30 48.481 0x31 38.785 0x32 27.704 0x33 21.547 0x34 16.160 0x35 12.120 0x36 9.235 0x37 7.182 0x38 5.387 0x39 4.309 0x3A 3.078 0x3B 2.394 0x3C 1.796 0x3D 1.347 0x3E 1.026 0x3F 0.798 Table 9. Sensor Frequency (1) (2) Address = 0x03, Default=0x45, Direction=R/W (1) (2) Bit Field Field Name Description 7:0 Min Resonating Frequency Sets the minimum resonating frequency to approximately 20% below the lowest resonating frequency of the sensor with no target in front. Use the formula below to determine the value of register. N = 68.94 * log10(F/2000) F = 20% below resonating frequency, Hz N = Register Value. Round to nearest value. Example: Sensor Frequency: 1MHz F = 0.8*1Mhz=800Khz N = 68.94 * log10(800KHz/2000)= Round to nearest(179.38)=179 (Value to be programmed in Sensor Frequency register) 16 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 Table 10. LDC Configuration Address = 0x04, Default=0x1B, Direction=R/W Bit Field Field Name Description 7:5 Reserved Reserved to 0 4:3 Amplitude Sets the oscillation amplitude 00:1V 01:2V 10:4V 11:Reserved 2:0 Response Time 000: Reserved 001: Reserved 010: 192 011: 384 100: 768 101: 1536 110: 3072 111: 6144 Table 11. Clock Configuration Address = 0x05, Default=0x01, Direction=R/W Bit Field Field Name 7:2 Reserved Reserved to 0 Description 1 CLK_SEL 1:External Crystal used for Frequency Counter (XIN/XOUT). 0:External Time-Base Clock used for Frequency Counter (TBCLK). 0 CLK_PD 1:Disable External time base clock. Crystal Oscillator Power Down. 0:Enable External time base clock. Table 12. Comparator Threshold High LSB Address = 0x06, Default=0xFF, Direction=R/W Bit Field Field Name Description 7:0 Threshold High LSB Threshold High[7:0] Least Significant byte of Threshold High Register. This register is a buffer. Read will reflect the current value of Threshold High [7:0] .See register 0x07 for details on Updating the Threshold High register. Table 13. Comparator Threshold High MSB Address = 0x07, Default=0xFF, Direction=R/W Bit Field Field Name Description 7:0 Threshold High MSB Threshold High[15:8] Most Significant byte of Threshold High Register. Write to this register copies the contents of 0x06 register and Writes to Threshold High register[15:0]. Read will return Threshold high [15:8]. To Update Threshold high register write register 0x06 first and then 0x07. Table 14. Comparator Threshold Low LSB Address = 0x08, Default=0x00, Direction=R/W Bit Field Field Name Description 7:0 Threshold Low LSB Threshold Low[7:0] Least Significant byte of Threshold Low Value. This register is a buffer. Read will reflect the current value of Threshold Low [7:0]. See register 0x09 for details on Updating the Threshold Low register. 17 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com Table 15. Comparator Threshold Low MSB Address = 0x09, Default=0x00, Direction=R/W Bit Field Field Name Description 7:0 Threshold Low MSB Threshold Low[15:8] Most Significant byte of Threshold Low Register. Write to this register copies the contents of 0x08 register and Writes to Threshold Low register[15:0]. Read will return Threshold Low [15:8]. To Update Threshold low register write register addr 0x08 first and then 0x09. Table 16. INTB Pin Configuration Address = 0x0A, Default=0x00, Direction=R/W Bit Field Field Name Description 7:3 Reserved Reserved to 0 2:0 Mode 100: DRDYB Enabled on INTB pin 010: INTB pin indicates the status of Comparator output 001: Wake-up Enabled on INTB pin 000: All modes disabled All other combinations are Reserved Table 17. Power Configuration Address = 0x0B, Default=0x00, Direction=R/W Bit Field Field Name Description 7:1 Reserved Reserved to 0 0 PWR_MODE 0:Stand-By mode 1:Active Mode. Conversion is Enabled Table 18. Status Address = 0x20, Default=NA, Direction=RO Bit Field Field Name Description 7 OSC status 1:Indicates oscillator overloaded and stopped 0:Oscillator working 6 Data Ready 0:Data is ready to be read 5 Wake-up 0:Wake-up triggered. Proximity data is more than Threshold High value. 4 Comparator 0:Proximity data is more than Threshold High value 3:0 Do not Care 1:No new data available 1:Wake-up disabled 1:Proximity data is less than Threshold Low value Table 19. Proximity Data LSB Address = 0x21, Default=NA, Direction=RO Bit Field Field Name Description 7:0 Proximity Data[7:0] Least Significant Byte of Proximity Data Table 20. Proximity Data MSB Address = 0x22, Default=NA, Direction=RO Bit Field Field Name Description 7:0 Proximity data [15:8] Most Significant Byte of Proximity data 18 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 Table 21. Frequency Counter LSB Address = 0x23, Default=NA, Direction=RO Bit Field Field Name Description 7:0 ODR LSB (ODR[7:0]) LSB of Output data rate. Sensor frequency can be calculated using the output data rate. Please refer to the Measuring Inductance. Table 22. Frequency Counter Mid-Byte Address = 0x24, Default=NA, Direction=RO Bit Field Field Name Description 7:0 ODR Mid byte (ODR[15:8]) Middle Byte of Output data rate Table 23. Frequency Counter MSB Address = 0x25, Default=NA, Direction=RO Bit Field Field Name Description 7:0 ODR MSB (ODR[23:16]) MSB of Output data rate Care must be taken to ensure that Proximity Data[15:0] and Frequency Counter[23:0] are all from same conversion. Conversion data is updated to these registers only when a read is initiated on 0x21 register. If the read is delayed between subsequent conversions, these registers are not updated until another read is initiated on 0x21. DIGITAL INTERFACE The LDC1000 utilizes a 4-wire SPI interface to access control and data registers. The LDC1000 is an SPI slave device and does not initiate any transactions. SPI Description A typical serial interface transaction begins with an 8-bit instruction, which is comprised of a read/write bit (MSB, R=1) and a 7 bit address of the register, followed by a Data field which is typically 8 bits. However, the data field can be extended to a multiple of 8 bits by providing sufficient SPI clocks. Refer to the Extended SPI Transactions section below. 1 2 3 4 5 C7 C6 C5 C4 C3 R/Wb A6 A5 A4 A3 6 7 8 C2 C1 C0 A2 A1 A0 9 10 11 D7 D6 (MSB) D5 12 13 14 15 16 D2 D1 D0 (LSB) D2 D1 D0 (LSB) 17 SCLK CSB tCOMMAND FIELDt SDI R/Wb = Read/Write 0: Write Data 1: Read Data SDO Address (7-bits) tDATA FIELDt D4 D3 Write DATA D7 D6 (MSB) D5 High-Z D4 D3 Read DATA Data (8-bits) tSingle Access Cyclet Figure 17. Serial Interface Protocol 19 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com Each assertion of chip select bar (CSB) starts a new register access. The R/Wb bit in the command field configures the direction of the access; a value of 0 indicates a write operation and a value of 1 indicates a read operation. All output data is driven on the falling edge of the serial clock (SCLK), and all input data is sampled on the rising edge of the serial clock (SCLK). Data is written into the register on the rising edge of the 16th clock. It is required to deassert CSB after the 16th clock; if CSB is deasserted before the 16th clock, no data write will occur. Extended SPI Transactions A transaction may be extended to multiple registers by keeping the CSB asserted beyond the stated 16 clocks. In this mode, the register addresses increment automatically. CSB must be asserted during 8*(1+N) clock cycles of SCLK, where N is the amount of bytes to write or read during the transaction. During an extended read access, SDO outputs the register contents every 8 clock cycles after the initial 8 clocks of the command field. During an extended write access, the data is written to the registers every 8 clock cycles after the initial 8 clocks of the command field. Extended transactions can be used to read 16-bits of Proximity data and 24-bits of frequency data all in one SPI transaction by initiating a read from register 0x21. INTB Pin Modes The INTB pin is a configurable output pin which can be used to drive an interrupt on an MCU. The LDC1000 provides three different modes on INTB Pin: 1. Comparator Mode 2. Wake-Up Mode 3. DRDY Mode LDC1000 has a build-in High and Low trigger threshold registers which can be as a comparator with programmable hysteresis or a special mode which can be used to wake-up an MCU. These modes are explained in detail below. Comparator Mode In the Comparator mode, the INTB pin is asserted or de-asserted when the proximity register value increases above Threshold High or decreases below Threshold Low registers respectively. In this mode, the LDC1000 essentially behaves as a proximity switch with programmable hysteresis. Threshold High Rp Data Threshold Low INTB t Figure 18. Behavior of INTB Pin in Comparator Mode 20 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 www.ti.com SNOSCX2 – SEPTEMBER 2013 Wake-Up Mode In Wake-Up mode, the INTB pin is asserted when proximity register value increases above Threshold High and de-asserted when wake-up mode is disabled in INTB pin mode register. This Mode can be used to wake-up an MCU which is asleep, to conserve power. Threshold High Rp Data Threshold Low INTB CSB SPI SPI: INTB Pin Mode Changed to DRDYB t Figure 19. Behavior of INTB Pin in Wake-Up Mode DRDYB Mode In DRDY mode (default), the INTB pin is asserted every time the conversion data is available and de-asserted once the read command on register 0x21 is registered internally; if the read is in progress, the pin is pulsed instead. ODRt t INTB CSB CMD: Read 0x21 SPI Data Read t Figure 20. Behavior of INTB Pin in DRDYB Mode 21 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 LDC1000 SNOSCX2 – SEPTEMBER 2013 www.ti.com TYPICAL APPLICATIONS Figure 21. Axial Distance Measurement Figure 22. Linear Position Sensing Figure 23. Angular Position Sensing 22 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LDC1000 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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