CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Features Functional Description ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ■ Data transfers on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte Write capability ■ 2.5 V IO supply (VDDQ) ■ Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device) ■ Clock Enable (CEN) pin to enable clock and suspend operation ■ Synchronous self timed writes ■ Asynchronous Output Enable (OE) ■ CY7C1471BV25, CY7C1473BV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1475BV25 available in Pb-free and non-Pb-free 209-ball FBGA package. ■ Three Chip Enables (CE1, CE2, CE3) for simple depth expansion. ■ Automatic power down feature available using ZZ mode or CE deselect. ■ IEEE 1149.1 JTAG Boundary Scan compatible ■ Burst Capability - linear or interleaved burst order ■ Low standby power The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are 2.5 V, 2 M × 36/4 M × 18/1 M × 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Selection Guide Description 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.5 ns Maximum Operating Current 305 275 mA Maximum CMOS Standby Current 120 120 mA Cypress Semiconductor Corporation Document Number: 001-15013 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 13, 2011 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Logic Block Diagram – CY7C1471BV25 (2 M × 36) ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN CE C ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BW A WRITE DRIVERS WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BW B BW C MEMORY ARRAY S E N S E A M P S BW D WE INPUT REGISTER OE CE1 CE2 CE3 D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQP A DQP B DQP C DQP D E E READ LOGIC SLEEP CONTROL ZZ Logic Block Diagram – CY7C1473BV25 (4 M × 18) ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN CE C ADV/LD C BURST LOGIC A1' Q1 A0' Q0 WRITE ADDRESS REGISTER ADV/LD BW A BW B WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S WE OE CE1 CE2 CE3 ZZ Document Number: 001-15013 Rev. *H D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQP A DQP B E INPUT E REGISTER READ LOGIC SLEEP CONTROL Page 2 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Logic Block Diagram – CY7C1475BV25 (1 M × 72) A0, A1, A ADDRESS REGISTER 0 MODE CLK ADV/LD C C CEN A1 A1' D1 Q1 A0 A0' D0 BURST Q0 LOGIC WRITE ADDRESS REGISTER 2 WRITE ADDRESS REGISTER 1 ADV/LD BW a BW b BW c BW d BW e BW f BW g BW h WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G E O U T P U T B U F F E R S E DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg DQ Ph WE INPUT E REGISTER 1 OE CE1 CE2 CE3 ZZ INPUT E REGISTER 0 READ LOGIC Sleep Control Document Number: 001-15013 Rev. *H Page 3 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Contents Pin Configurations ........................................................... 5 Pin Definitions .................................................................. 9 Functional Overview ...................................................... 10 Single Read Accesses .............................................. 10 Burst Read Accesses ................................................ 10 Single Write Accesses ............................................... 10 Burst Write Accesses ................................................ 11 Sleep Mode ............................................................... 11 Interleaved Burst Address Table (MODE = Floating or VDD) ............................................. 11 Linear Burst Address Table (MODE = GND) ................................................................ 11 ZZ Mode Electrical Characteristics ............................... 11 Truth Table ...................................................................... 12 Truth Table for Read/Write ............................................ 13 Truth Table for Read/Write ............................................ 13 Truth Table for Read/Write ............................................ 13 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14 Disabling the JTAG Feature ...................................... 14 TAP Controller State Diagram ....................................... 14 Test Access Port (TAP) ............................................. 14 TAP Controller Block Diagram ...................................... 14 PERFORMING A TAP RESET .................................. 14 TAP REGISTERS ...................................................... 15 TAP Instruction Set ................................................... 15 TAP AC Switching Characteristics ............................... 17 2.5 V TAP AC Test Conditions ....................................... 17 2.5 V TAP AC Output Load Equivalent ......................... 17 Document Number: 001-15013 Rev. *H TAP DC Electrical Characteristics and Operating Conditions ..................................................... 17 Identification Register Definitions ................................ 18 Scan Register Sizes ....................................................... 18 Identification Codes ....................................................... 18 Boundary Scan Exit Order (2 M × 36) ........................... 19 Boundary Scan Exit Order (4 M × 18) ........................... 19 Boundary Scan Exit Order (1 M × 72) ........................... 20 Maximum Ratings ........................................................... 21 Operating Range ............................................................. 21 Electrical Characteristics ............................................... 21 Capacitance .................................................................... 22 Thermal Resistance ........................................................ 22 Switching Characteristics .............................................. 23 Switching Waveforms .................................................... 24 Ordering Information ...................................................... 27 Ordering Code Definitions ......................................... 27 Package Diagrams .......................................................... 28 Acronyms ........................................................................ 31 Document Conventions ................................................. 31 Units of Measure ....................................................... 31 Document History Page ................................................. 32 Sales, Solutions, and Legal Information ...................... 33 Worldwide Sales and Design Support ....................... 33 Products .................................................................... 33 PSoC Solutions ......................................................... 33 Page 4 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Configurations A 40 41 42 43 44 45 46 47 48 49 50 VDD A A A A A A A A A 37 A0 VSS 36 A1 39 35 A NC/144M 34 A 38 33 A NC/288M 32 A Document Number: 001-15013 Rev. *H 81 A 82 83 A A 84 ADV/LD VSS 90 85 VDD 91 OE CE3 92 86 BWA 93 CEN BWB 94 WE BWC 95 88 BWD 96 CLK CE2 97 89 CE1 A 98 87 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1471BV25 31 BYTE D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE BYTE C DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 99 100 A Figure 1. 100-pin TQFP Pinout DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA BYTE B BYTE A Page 5 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Configurations (continued) A 40 41 42 43 44 45 46 47 48 49 50 VDD A A A A A A A A A 37 A0 VSS 36 A1 39 35 A NC/144M 34 A 38 33 A NC/288M 32 A Document Number: 001-15013 Rev. *H 81 A 82 A 83 A 84 ADV/LD 85 OE 86 VSS 90 CEN VDD 91 WE CE3 92 88 BWA 93 CLK BWB 94 89 NC 95 NC CE2 97 96 CE1 A 98 87 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1473BV25 31 BYTE B VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE NC NC NC 99 100 A Figure 2. 100-pin TQFP Pinout A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ BYTE A DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Page 6 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Configurations (continued) 165-ball FBGA (15 × 17 × 1.4 mm) Pinout CY7C1471BV25 (2 M × 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/576M A CE1 BWC BWB CE3 CEN ADV/LD A A NC NC/1G A CE2 A A VDDQ VSS VSS VSS VDD VDDQ VDDQ VSS VSS WE VSS OE NC DQC BWA VSS CLK DQPC DQC BWD VSS VDD VDDQ NC DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC NC DQD DQC NC DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC/144M A A A TDI NC A1 VSS NC TDO A A A NC/288M R MODE A A A TMS A0 TCK A A A A 8 9 10 11 ADV/LD A A A A A NC NC CY7C1473BV25 (4 M × 18) 1 A B C D E F G H J K L M N P R 2 3 4 5 6 NC/576M A CE1 BWB NC CE3 NC/1G A CE2 NC NC NC NC DQB VDDQ VDDQ VSS VDD BWA VSS CLK NC DQB VDDQ NC NC NC DQB DQB DQB NC NC DQB 7 CEN WE VSS VSS OE VSS VDD VDDQ VSS VSS VSS VDDQ NC NC DQPA DQA VDD VSS VSS VSS VDD VDDQ NC DQA VDDQ VDDQ NC VDDQ VDD VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ NC VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD NC NC DQA DQA DQA ZZ NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC/144M A A A MODE A A A Document Number: 001-15013 Rev. *H VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC TDI NC A1 TDO A A A NC/288M TMS A0 TCK A A A A Page 7 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Configurations (continued) 209-ball FBGA (14 × 22 × 1.76 mm) Pinout CY7C1475BV25 (1 M × 72) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CE2 A ADV/LD A CE3 A DQb DQb B DQg DQg BWSc BWSg NC WE A BWSb BWSf DQb DQb C DQg DQg BWSh BWSd NC/576M CE1 NC BWSe BWSa DQb DQb D DQg DQg VSS NC NC/1G OE NC NC VSS DQb DQb E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS CEN VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe T DQd DQd VSS NC NC MODE NC NC VSS DQe DQe U DQd DQd NC/144M A A A A A NC/288M DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe Document Number: 001-15013 Rev. *H Page 8 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Definitions Name IO Description A0, A1, A InputSynchronous Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH InputSynchronous Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. WE InputSynchronous Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a new address. CLK InputClock Clock Input. Captures all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. CE2 InputSynchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE3 InputSynchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. OE InputAsynchronous Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN InputSynchronous Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ InputAsynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. DQs IOSynchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX IOSynchronous Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write sequences, DQPX is controlled by BWX correspondingly. MODE Input Strap Pin Mode Input. Selects the Burst Order of the Device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. VDD Power Supply Power Supply Inputs to the Core of the Device. VDDQ VSS TDO IO Power Supply Ground Power Supply for the IO Circuitry. Ground for the Device. JTAG serial output Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG Synchronous feature is not used, this pin must be left unconnected. This pin is not available on TQFP packages. Document Number: 001-15013 Rev. *H Page 9 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Definitions (continued) Name IO Description TDI JTAG serial input Synchronous Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, leave this pin floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. TMS JTAG serial input Synchronous Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG-Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not used, connect this pin to VSS. This pin is not available on TQFP packages. NC - No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Functional Overview The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are synchronous flow through burst SRAMs designed specifically to eliminate wait states during write read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses are initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If CEN is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access is either a read or write operation, depending on the status of the Write Enable (WE). Use Byte Write Select (BWX) to conduct Byte Write operations. Write operations are qualified by the WE. All writes are simplified with on-chip synchronous self- timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD must be driven LOW after the device is deselected to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: ■ CEN is asserted LOW ■ CE1, CE2, and CE3 are ALL asserted active ■ WE is deasserted HIGH ■ ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW to drive out the requested data. On the subsequent clock, another operation Document Number: 001-15013 Rev. *H (read/write/deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, the output is tri-stated immediately. Burst Read Accesses The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 has an on-chip burst counter that enables the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Accesses section. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when these conditions are satisfied at clock rise: ■ CEN is asserted LOW ■ CE1, CE2, and CE3 are ALL asserted active ■ WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise the data presented to DQs and DQPX (or a subset for Byte Write operations, see Truth Table for Read/Write on page 13 for details) inputs is latched into the device and the write is complete. Additional accesses (read/write/deselect) can be initiated on this cycle. The data written during the write operation is controlled by BWX signals. The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 provide Byte Write capability that is described in the Truth Table for Read/Write on page 13. The input WE with the selected BWx input selectively writes to only the desired bytes. Bytes not selected during a Byte Write operation remain unaltered. A synchronous self timed write mechanism is Page 10 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 provided to simplify the write operations. Byte Write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. Because the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are common IO devices, data must not be driven into the device while the outputs are active. The OE can be deasserted HIGH before presenting data to the DQs and DQPX inputs. This tri-states the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 have an on-chip burst counter that makes it possible to supply a single address and conduct up to four Write operations without reasserting the address inputs. Drive ADV/LD LOW to load the initial address, as described in the Single Write Accesses section. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. You must drive the correct BWX inputs in each cycle of the Burst Write to write the correct data bytes. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 10 11 00 Sleep Mode 10 11 00 01 The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. You must select the device before entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 120 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 001-15013 Rev. *H Page 11 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Truth Table The truth table for CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 follows.[1, 2, 3, 4, 5, 6, 7] Operation Address CE CE 1 2 CE3 Used ZZ ADV/LD WE BWX OE CEN CLK DQ Deselect Cycle None H X X L L X X X L L->H Tri-State Deselect Cycle None X X H L L X X X L L->H Tri-State Deselect Cycle None X L X L L X X X L L->H Tri-State Continue Deselect Cycle None X X X L H X X X L L->H Tri-State Read Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q) Read Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q) External L H L L L H X H L L->H Tri-State Next X X X L H X X H L L->H Tri-State External L H L L L L L X L L->H Data In (D) Write Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D) NOP/Write Abort (Begin Burst) None L H L L L L H X L L->H Tri-State Write Abort (Continue Burst) Next X X X L H X H X L L->H Tri-State NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Ignore Clock Edge (Stall) Sleep Mode Current X X X L X X X X H L->H - None X X X H X X X X X X Tri-State Notes 1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects are asserted, see Truth Table for Read/Write on page 13 for details. 2. Write is defined by BWX, and WE. See Truth Table for Read/Write on page 13. 3. When a write cycle is detected, all IOs are tri-stated, even during byte writes. 4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CEN = H, inserts wait states. 6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active. Document Number: 001-15013 Rev. *H Page 12 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Truth Table for Read/Write The read-write truth table for CY7C1471BV25 follows.[8, 9, 10] Function WE BWA BWB BWC BWD Read H X X X X Write No bytes written L H H H H Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) L L H H H L H L H H Write Byte C – (DQC and DQPC) L H H L H Write Byte D – (DQD and DQPD) L H H H L Write All Bytes L L L L L Truth Table for Read/Write The read-write truth table for CY7C1473BV25 follows.[8, 9, 10] Function WE BWb BWa Read H X X Write – No Bytes Written L H H Write Byte a – (DQa and DQPa) L H L Write Byte b – (DQb and DQPb) L L H Write Both Bytes L L L Truth Table for Read/Write The read-write truth table for CY7C1475BV25 follows.[8, 9, 10] Function WE BWx Read H X Write – No Bytes Written L H Write Byte X(DQx and DQPx) L L Write All Bytes L All BW = L Notes 8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects are asserted, see Truth Table for Read/Write on page 13 for details. 9. Write is defined by BWX, and WE. See Truth Table for Read/Write on page 13. 10. This table is only a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active. Document Number: 001-15013 Rev. *H Page 13 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port (TAP) The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 incorporate a serial boundary scan Test Access Port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5 V IO logic levels. Test Clock (TCK) The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 contain a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. During power up, the device comes up in a reset state, which does not interfere with the operation of the device. TEST-LOGIC RESET 0 RUN-TEST/ IDLE 0 1 SELECT DR-SCA N 1 SELECT IR-SCAN 0 1 The TMS input gives commands to the TAP controller and is sampled on the rising edge of TCK. You can leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data In (TDI) The TDI ball serially inputs information into the registers and is connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data Out (TDO) 1 TAP Controller Block Diagram 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 Bypass Register SHIFT-IR 1 0 2 1 0 1 EXIT1-DR 1 EXIT1-IR 0 1 TDI 0 0 0 TDO Boundary Scan Register EXIT2-IR 1 1 UPDATE-DR UPDATE-IR TCK 1 Selection Circuitry x . . . . . 2 1 0 1 EXIT2-DR Instruction Register Identification Register PAUSE-IR 1 Selection Circuitry 31 30 29 . . . 2 1 0 0 PAUSE-DR 0 Test Mode Select (TMS) The TDO output ball serially clocks data out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.) TAP Controller State Diagram 1 The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. 0 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. TM S TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. During power up, the TAP is reset internally to ensure that TDO comes up in a High Z state. Document Number: 001-15013 Rev. *H Page 14 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 TAP Registers Registers are connected between the TDI and TDO balls and enable the scanning of data into and out of the SRAM test circuitry. Only one register is selectable at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 14. During power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path. Bypass Register The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. You cannot use the TAP controller to load address data or control signals into the SRAM and you cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller making this device not compliant with 1149.1. The TAP controller does recognize an all-0 instruction. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This shifts the data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction is loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High Z state. Boundary Scan Register IDCODE The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The IDCODE instruction causes a vendor specific, 32-bit code to load into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE for shifting out of the device when the TAP controller enters the Shift-DR state. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor specific, 32-bit code during the Capture DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 18. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Identification Codes on page 18. Three of these instructions are listed as RESERVED and are not for use. The other five instructions are described in this section in detail. Document Number: 001-15013 Rev. *H The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. Be aware that the TAP controller clock only operates at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that, during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is Page 15 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct signal value, make certain that the SRAM signal is stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Reserved After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. These instructions are not implemented but are reserved for future use. Do not use these instructions. Figure 3. TAP Timing 1 2 Test Clock (TCK ) 3 t TH t TM SS t TM SH t TDIS t TDIH t TL 4 5 6 t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE Document Number: 001-15013 Rev. *H UNDEFINED Page 16 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 TAP AC Switching Characteristics Over the Operating Range[11, 12] Parameter Description Min Max Unit Clock tTCYC TCK Clock Cycle Time 50 – ns tTF TCK Clock Frequency – 20 MHz tTH TCK Clock HIGH Time 20 – ns tTL TCK Clock LOW Time 20 – ns Output Times tTDOV TCK Clock LOW to TDO Valid – 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 – ns tTMSS TMS Setup to TCK Clock Rise 5 – ns tTDIS TDI Setup to TCK Clock Rise 5 – ns tCS Capture Setup to TCK Rise 5 – ns Setup Times Hold Times tTMSH TMS Hold after TCK Clock Rise 5 – ns tTDIH TDI Hold after Clock Rise 5 – ns tCH Capture Hold after Clock Rise 5 – ns 2.5 V TAP AC Test Conditions 2.5 V TAP AC Output Load Equivalent Input pulse levels................................................VSS to 2.5 V 1.25V Input rise and fall time .....................................................1 ns Input timing reference levels........................................ 1.25 V 50Ω Output reference levels ............................................... 1.25 V Test load termination supply voltage ........................... 1.25 V TDO Z O= 50Ω 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 2.375 to 2.625 unless otherwise noted) [13] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5 V 2.0 – V VOH2 Output HIGH Voltage IOH = –100 µA, VDDQ = 2.5 V 2.1 – V VOL1 Output LOW Voltage IOL = 1.0 mA, VDDQ = 2.5 V – 0.4 V VOL2 Output LOW Voltage IOL = 100 µA, VDDQ = 2.5 V – 0.2 V VIH Input HIGH Voltage VDDQ = 2.5 V 1.7 VDD + 0.3 V VIL Input LOW Voltage VDDQ = 2.5 V –0.3 0.7 V IX Input Load Current GND < VIN < VDDQ –5 5 µA Notes 11. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 12. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. 13. All voltages refer to VSS (GND). Document Number: 001-15013 Rev. *H Page 17 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Identification Register Definitions Instruction Field CY7C1471BV25 CY7C1473BV25 CY7C1475BV25 (2 M × 36) (4 M × 18) (1 M × 72) Revision Number (31:29) Description 000 000 000 01011 01011 01011 Architecture/Memory Type (23:18) 001001 001001 001001 Defines memory type and architecture Bus Width/Density (17:12) 100100 010100 110100 Defines width and density 00000110100 00000110100 00000110100 1 1 1 Device Depth (28:24) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) Describes the version number Reserved for internal use Allows unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size (× 36) Bit Size (× 18) Bit Size (× 72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order – 165-ball FBGA 71 52 – Boundary Scan Order – 209-ball BGA – – 110 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High Z state. This instruction is not 1149.1 compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-15013 Rev. *H Page 18 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Boundary Scan Exit Order (2 M × 36) Bit # 165-ball ID Bit # 165-ball ID Bit # 165-ball ID Bit # 165-ball ID 1 C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4 D2 24 P6 44 H11 64 B5 5 E2 25 R6 45 G11 65 A5 6 F1 26 R8 46 F11 66 A4 7 G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9 G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 165-ball ID Bit # 165-ball ID Boundary Scan Exit Order (4 M × 18) Bit # 165-ball ID Bit # 165-ball ID Bit # 1 D2 14 R4 27 L10 40 B10 2 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 A7 5 J1 18 P3 31 G11 44 B7 6 K1 19 P4 32 F11 45 B6 7 L1 20 P8 33 E11 46 A6 8 M1 21 P9 34 D11 47 B5 9 N1 22 P10 35 C11 48 A4 10 R1 23 R9 36 A11 49 B3 11 R2 24 R10 37 A9 50 A3 12 R3 25 R11 38 B9 51 A2 13 P2 26 M10 39 A10 52 B2 Document Number: 001-15013 Rev. *H Page 19 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Boundary Scan Exit Order (1 M × 72) Bit # 209-ball ID Bit # 209-ball ID Bit # 209-ball ID 1 A1 29 2 A2 30 3 B1 4 B2 5 6 7 8 Bit # 209-ball ID T1 57 U10 85 B11 T2 58 T11 86 B10 31 U1 59 T10 87 A11 32 U2 60 R11 88 A10 C1 33 V1 61 R10 89 A7 C2 34 V2 62 P11 90 A5 D1 35 W1 63 P10 91 A9 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73 H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E10 107 A4 24 N2 52 W11 80 E11 108 C6 25 P1 53 W10 81 D11 109 B7 26 P2 54 V11 82 D10 110 A3 27 R2 55 V10 83 C11 28 R1 56 U11 84 C10 Document Number: 001-15013 Rev. *H Page 20 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Maximum Ratings DC Input Voltage ................................. –0.5 V to VDD + 0.5 V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage......................................... > 2001 V (MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA Ambient Temperature with Power Applied .......................................... –55C to +125 C Operating Range Supply Voltage on VDD Relative to GND ......–0.5 V to +3.6 V Ambient VDD VDDQ Temperature Commercial 0 °C to +70 °C 2.5 V – 5% / + 5% 2.5 V – 5% to VDD Industrial –40 °C to +85 °C Range Supply Voltage on VDDQ Relative to GND ..... –0.5 V to +VDD DC Voltage Applied to Outputs in Tri-State .........................................–0.5 V to VDDQ + 0.5 V Electrical Characteristics Over the Operating Range [14, 15] Parameter Description Test Conditions VDD Power Supply Voltage VDDQ IO Supply Voltage VOH Output HIGH Voltage For 2.5 V IO, IOH =–1.0 mA VOL Output LOW Voltage For 2.5 V IO, IOL=1.0 mA For 2.5 V IO Min Max Unit 2.375 2.625 V 2.375 VDD V 2.0 – V – 0.4 V V Input HIGH Voltage[14] For 2.5 V IO 1.7 VDD + 0.3 V VIL Input LOW Voltage[14] For 2.5 V IO –0.3 0.7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ –5 5 A Input Current of MODE Input = VSS –30 – A Input = VDD – 5 A Input = VSS –5 – A Input = VDD – 30 A –5 5 A VIH Input Current of ZZ Output Leakage Current GND VI VDDQ, Output Disabled IOZ [16] VDD Operating Supply Current VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC Automatic CE Power Down Current—TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = fMAX, inputs switching ISB2 Automatic CE Power Down Current—CMOS Inputs VDD = Max, Device Deselected, VIN 0.3 V or VIN > VDD – 0.3 V, f = 0, inputs static ISB3 Automatic CE Power Down Current—CMOS Inputs VDD = Max, Device Deselected, or 6.5 ns cycle, 133 MHz VIN 0.3 V or VIN > VDDQ – 0.3 V 8.5 ns cycle, 100 MHz f = fMAX, inputs switching Automatic CE Power Down Current—TTL Inputs VDD = Max, Device Deselected, VIN VDD – 0.3 V or VIN 0.3 V, f = 0, inputs static IDD ISB1 ISB4 6.5 ns cycle, 133 MHz – 305 mA 8.5 ns cycle, 100 MHz – 275 mA 6.5 ns cycle, 133 MHz – 170 mA 8.5 ns cycle, 100 MHz – 170 mA All speeds – 120 mA – 170 mA – 170 mA – 135 mA All Speeds Notes 14. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 15. TPower-up: assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-15013 Rev. *H Page 21 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description CADDRESS Address Input Capacitance CDATA Data Input Capacitance CCTRL 100-pin TQFP 165-ball FBGA 209-ball FBGA Max Max Max Test Conditions TA = 25°C, f = 1 MHz, VDD = 2.5 V, VDDQ = 2.5 V Unit 6 6 6 pF 5 5 5 pF Control Input Capacitance 8 8 8 pF CCLK Clock Input Capacitance 6 6 6 pF CIO Input-Output Capacitance 5 5 5 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) 100-pin TQFP 165-ball FBGA 209-ball FBGA Package Package Package Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51. Unit 24.63 16.3 15.2 C/W 2.28 2.1 1.7 C/W Figure 4. AC Test Loads and Waveforms 2.5 V IO Test Load R = 1667 2.5 V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 1538 VL = 1.25 V (a) Document Number: 001-15013 Rev. *H ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% 1 ns 1 ns (c) Page 22 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Switching Characteristics Over the Operating Range[17, 18] Parameter Description tPOWER[19] 133 MHz 100 MHz Unit Min Max Min Max 1 – 1 – ms 7.5 – 10 – ns Clock tCYC Clock Cycle Time tCH Clock HIGH 2.5 – 3.0 – ns tC]L Clock LOW 2.5 – 3.0 – ns Output Times tCDV Data Output Valid After CLK Rise – 6.5 – 8.5 ns tDOH Data Output Hold After CLK Rise 2.5 – 2.5 – ns tCLZ Clock to Low Z [20, 21, 22] 3.0 – 3.0 – ns tCHZ Clock to High Z [20, 21, 22] – 3.8 – 4.5 ns tOEV OE LOW to Output Valid – 3.0 – 3.8 ns 0 – 0 – ns – 3.0 – 4.0 ns [20, 21, 22] tOELZ OE LOW to Output Low Z tOEHZ OE HIGH to Output High Z [20, 21, 22] Setup Times tAS Address Setup Before CLK Rise 1.5 – 1.5 – ns tALS ADV/LD Setup Before CLK Rise 1.5 – 1.5 – ns tWES WE, BWX Setup Before CLK Rise 1.5 – 1.5 – ns tCENS CEN Setup Before CLK Rise 1.5 – 1.5 – ns tDS Data Input Setup Before CLK Rise 1.5 – 1.5 – ns tCES Chip Enable Setup Before CLK Rise 1.5 – 1.5 – ns tAH Address Hold After CLK Rise 0.5 – 0.5 – ns tALH ADV/LD Hold After CLK Rise 0.5 – 0.5 – ns Hold Times tWEH WE, BWX Hold After CLK Rise 0.5 – 0.5 – ns tCENH CEN Hold After CLK Rise 0.5 – 0.5 – ns tDH Data Input Hold After CLK Rise 0.5 – 0.5 – ns tCEH Chip Enable Hold After CLK Rise 0.5 – 0.5 – ns Notes 17. Timing reference level is 1.25 V when VDDQ = 2.5 V. 18. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted. 19. This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD(minimum) initially, before a read or write operation can be initiated. 20. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 22. Transition is measured ±200 mV from steady-state voltage. 21. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z before Low Z under the same system conditions. 22. This parameter is sampled and not 100% tested. Document Number: 001-15013 Rev. *H Page 23 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Switching Waveforms Figure 5 shows read-write timing waveform.[23, 24, 25] Figure 5. Read/Write Timing 1 2 3 t CYC 4 5 A3 A4 6 7 8 9 A5 A6 A7 10 CLK t CENS t CENH t CES t CEH t CH t CL CEN CE ADV/LD WE BW X A1 ADDRESS t AS A2 t CDV t AH t DOH t CLZ DQ D(A1) t DS D(A2) Q(A3) D(A2+1) t OEV Q(A4+1) Q(A4) t OELZ W RITE D(A1) W RITE D(A2) D(A5) Q(A6) D(A7) W RITE D(A7) DESELECT t OEHZ t DH OE COM M AND t CHZ BURST W RITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) t DOH W RITE D(A5) READ Q(A6) UNDEFINED Notes 23. For this waveform ZZ is tied LOW. 24. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH. 25. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document Number: 001-15013 Rev. *H Page 24 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Switching Waveforms (continued) [26, 27, 28] Figure 6 shows NOP, STALL and DESELECT Cycles waveform. Figure 6. NOP, STALL and DESELECT Cycles 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW [A:D] ADDRESS A5 t CHZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) t DOH COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) DON’T CARE STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Notes 26. For this waveform ZZ is tied LOW. 27. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH. 28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document Number: 001-15013 Rev. *H Page 25 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Switching Waveforms (continued) Figure 7 shows ZZ Mode timing waveform. [29, 30] Figure 7. ZZ Mode Timing CLK t ZZ I t ZZREC ZZ t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 29. Device must be deselected when entering ZZ mode. See Truth Table on page 12 for all possible signal conditions to deselect the device. 30. DQs are in high Z when exiting ZZ sleep mode. Document Number: 001-15013 Rev. *H Page 26 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Ordering Information Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products, or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 133 Package Diagram Ordering Code CY7C1471BV25-133AXI Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Operating Range lndustrial Ordering Code Definitions CY 7C 1471 B V25 - 133 AX I Temperature Range: I = Industrial Package Type: AX = 100-pin TQFP (Pb-free) Frequency Range: 133 MHz V25 = 2.5 V Die Revision 1471 = FT, 2 Mb × 36 (72 Mb) Marketing Code: 7C = SRAM Company ID: CY = Cypress Document Number: 001-15013 Rev. *H Page 27 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Package Diagrams Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050 51-85050 *D Document Number: 001-15013 Rev. *H Page 28 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Package Diagrams (continued) Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 51-85165 *B Document Number: 001-15013 Rev. *H Page 29 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Package Diagrams (continued) Figure 10. 209-ball FBGA (14 × 22 × 1.76 mm), 51-85167 51-85167 *A Document Number: 001-15013 Rev. *H Page 30 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Acronyms Document Conventions Acronym Description Units of Measure BWS byte write select BGA ball grid array °C degree Celcius CMOS complementary metal oxide semiconductor µA micro Amperes FBGA fine-pitch ball grid array mA milli Amperes I/O input/output mm milli meter JTAG Joint Test Action Group ms milli seconds LSB least significant bit MHz Mega Hertz MSB most significant bit ns nano seconds OE output enable Ohms SRAM static random access memory % percent TAP test access port pF pico Farad TCK test clock V Volts TDI test data-in W Watts TDO test data-out TMS test mode select TQFP thin quad flat pack TTL transistor transistor logic WE write enable Document Number: 001-15013 Rev. *H Symbol Unit of Measure Page 31 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document History Page Document Title: CY7C1471BV25/CY7C1473BV25/CY7C1475BV25, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 001-15013 REV. ECN NO. Issue Date ** 1024500 See ECN Orig. of Change Description of Change VKN/KKVTMP New Data Sheet *A 1274731 See ECN VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform *B 1562503 See ECN VKN/AESA Removed 1.8V IO offering from the data sheet *C 1897447 See ECN VKN/AESA *D 2082487 See ECN VKN *E 2159486 See ECN VKN/PYRS *F 2898501 03/24/2010 NJY Removed inactive part numbers from Ordering Information table; Updated package diagrams. *G 3207526 03/28/2011 NJY Updated Ordering Information and added Ordering Code Definitions. Updated Package Diagrams. Updated in new template. *H 3256583 05/13/2011 NJY Added Acronyms and Units of Measure. Document Number: 001-15013 Rev. *H Added footnote 14 related to IDD Converted from preliminary to final Minor Change-Moved to the external web Page 32 of 33 [+] Feedback CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2007-2011. 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Document Number: 001-15013 Rev. *H Revised May 13, 2011 Page 33 of 33 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback