CY7C1354D 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description ■ Pin-compatible and functionally equivalent to ZBT ■ Supports 200 MHz bus operations with zero wait states ❐ Available speed grade is 200 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte write capability ■ Single 3.3 V power supply (VDD) ■ 3.3 V or 2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.2 ns (for 200 MHz device) ■ Clock enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ Available in non Pb-free 165-ball FBGA package ■ IEEE 1149.1 JTAG-compatible boundary scan ■ Burst capability – linear or interleaved burst order ■ “ZZ” sleep mode option and stop clock option The CY7C1354D are 3.3 V, 256 K × 36 synchronous pipelined burst SRAM with No Bus Latency™ (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354D are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature greatly improves the throughput of data in systems that require frequent write/read transitions. The CY7C1354D are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the byte write selects (BWa–BWd for CY7C1354D) and a write enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. For a complete list of related documentation, click here. Logic Block Diagram – CY7C1354D A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 S E N S E ADV/LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BW a BW b BW c BW d MEMORY ARRAY WRITE DRIVERS A M P S WE O U T P U T R E G I S T E R S E INPUT REGISTER 1 OE CE1 CE2 CE3 S T E E R I N G INPUT REGISTER 0 B U F F E R S DQ s DQ Pa DQ Pb DQ Pc DQ Pd E E READ LOGIC SLEEP CONTROL ZZ Cypress Semiconductor Corporation Document Number: 001-88918 Rev. *A E O U T P U T D A T A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 18, 2014 CY7C1354D Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Pin Definitions .................................................................. 4 Functional Overview ........................................................ 5 Single Read Accesses ................................................ 5 Burst Read Accesses .................................................. 5 Single Write Accesses ................................................. 5 Burst Write Accesses .................................................. 6 Sleep Mode ................................................................. 6 Interleaved Burst Address Table ................................. 6 Linear Burst Address Table ......................................... 6 ZZ Mode Electrical Characteristics .............................. 6 Truth Table ........................................................................ 7 Partial Truth Table for Read/Write .................................. 8 IEEE 1149.1 Serial Boundary Scan (JTAG) .................... 9 Disabling the JTAG Feature ........................................ 9 Test Access Port (TAP) ............................................... 9 PERFORMING A TAP RESET .................................... 9 TAP REGISTERS ........................................................ 9 TAP Instruction Set ..................................................... 9 TAP Controller State Diagram ....................................... 11 TAP Controller Block Diagram ...................................... 12 TAP Timing ...................................................................... 12 TAP AC Switching Characteristics ............................... 13 3.3 V TAP AC Test Conditions ....................................... 13 3.3 V TAP AC Output Load Equivalent ......................... 13 2.5 V TAP AC Test Conditions ....................................... 13 2.5 V TAP AC Output Load Equivalent ......................... 13 Document Number: 001-88918 Rev. *A TAP DC Electrical Characteristics and Operating Conditions ..................................................... 14 Identification Register Definitions ................................ 14 Scan Register Sizes ....................................................... 14 Instruction Codes ........................................................... 15 Boundary Scan Exit Order ............................................. 16 Maximum Ratings ........................................................... 17 Operating Range ............................................................. 17 Neutron Soft Error Immunity ......................................... 17 Electrical Characteristics ............................................... 17 Capacitance .................................................................... 18 Thermal Resistance ........................................................ 18 AC Test Loads and Waveforms ..................................... 19 Switching Characteristics .............................................. 20 Switching Waveforms .................................................... 21 Ordering Information ...................................................... 24 Ordering Code Definitions ......................................... 24 Package Diagrams .......................................................... 25 Acronyms ........................................................................ 26 Document Conventions ................................................. 26 Units of Measure ....................................................... 26 Document History Page ................................................. 27 Sales, Solutions, and Legal Information ...................... 28 Worldwide Sales and Design Support ....................... 28 Products .................................................................... 28 PSoC® Solutions ...................................................... 28 Cypress Developer Community ................................. 28 Technical Support ..................................................... 28 Page 2 of 28 CY7C1354D Selection Guide Description 200 MHz Unit Maximum access time 3.2 ns Maximum operating current 220 mA Maximum CMOS standby current 40 mA Pin Configurations Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout 3 CY7C1354D (256 K × 36) 4 5 6 7 1 2 8 A B C D E F G H J K L M N P NC/576M A CE1 BWc BWb CE3 CE2 VDDQ BWa VSS VSS OE VDDQ BWd VSS VDD CLK DQPc DQc A NC DQc CEN WE ADV/LD NC/1G VSS VSS VSS VSS VSS VDD DQc DQc VDDQ VDD VSS VSS VSS VDD R MODE 9 10 11 A A NC NC/18M A NC VDDQ VDDQ NC DQb DQPb DQb VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc NC DQd DQc NC DQd VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ DQb NC DQa DQb ZZ DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQPd DQd NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC DQa DQPa A A TDI A1 TDO A A A NC/288M A A TMS A0 TCK A A A A NC/144M NC/72M NC/36M Document Number: 001-88918 Rev. *A NC Page 3 of 28 CY7C1354D Pin Definitions Pin Name A0, A1, A I/O Type Pin Description InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK. synchronous BWa, BWb, InputByte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on BWc, BWd synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd. WE InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal synchronous must be asserted LOW to initiate a write sequence. ADV/LD InputAdvance/load input used to advance the on-chip address counter or load a new address. When synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW to load a new address. CLK Inputclock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 synchronous and CE3 to select/deselect the device. CE2 InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE3 to select/deselect the device. CE3 InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE2 to select/deselect the device. OE InputOutput enable, active LOW. Combined with the synchronous logic block inside the device to control asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a Write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQS I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by addresses during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tristate condition. The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQ[a:d]. During write synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd. MODE Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. TDO JTAG serial Serial data out to the JTAG circuit. Delivers data on the negative edge of TCK. output synchronous TDI JTAG serial Serial data in to the JTAG circuit. Sampled on the rising edge of TCK. input synchronous TMS Test mode This pin controls the test access port state machine. Sampled on the rising edge of TCK. select synchronous Document Number: 001-88918 Rev. *A Page 4 of 28 CY7C1354D Pin Definitions (continued) Pin Name TCK VDD VDDQ I/O Type JTAG-clock Pin Description Clock input to the JTAG circuitry. Power supply Power supply inputs to the core of the device. I/O power supply Power supply for the I/O circuitry. VSS Ground NC – No connects. This pin is not connected to the die. NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M, NC/1G – These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M, 288M, 576M, and 1G densities. ZZ Ground for the device. Should be connected to ground of the system. InputZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Functional Overview The CY7C1354D are synchronous-pipelined burst NoBL SRAMs designed specifically to eliminate wait states during write/read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.2 ns (200 MHz device). Accesses can be initiated by asserting all three chip enables (CE1, CE2, CE3) active at the rising edge of the clock. If clock enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the write enable (WE). BW[d:a] can be used to conduct byte write operations. Write operations are qualified by the write enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, (3) the write enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and enables the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output Document Number: 001-88918 Rev. *A register and to the data bus within 3.2 ns (200 MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW for the device to drive out the requested data. During the second clock, a subsequent operation (read/write/deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output tristates following the next clock rise. Burst Read Accesses The CY7C1354D has an on-chip burst counter that enables the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in Single Read Accesses. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wrap around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, and (3) the write signal WE is asserted LOW. The address presented to A0–A16 is loaded into the address register. The write signals are latched into the control logic block. On the subsequent clock rise the data lines are automatically tristated regardless of the state of the OE input signal. This enables the external logic to present the data on DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1354D). In addition, the address for the subsequent access (read/write/deselect) is latched into Page 5 of 28 CY7C1354D the address register if the appropriate control signals are asserted. be driven in each cycle of the burst write to write the correct bytes of data. On the next clock rise the data presented to DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1354D or a subset for byte write operations, see the table Partial Truth Table for Read/Write on page 8 for details) inputs is latched into the device and the write is complete. The data written during the write operation is controlled by BW (BWa,b,c,d for CY7C1354D) signals. The CY7C1354D provides byte write capability that is described in the Write Cycle Description table. Asserting the write enable input (WE) with the selected byte write select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism is provided to simplify the write operations. Byte write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. Sleep Mode Because the CY7C1354D is common I/O devices, data should not be driven into the device while the outputs are active. The output enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1354D ) inputs. Doing so will tristate the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1354D ) are automatically tristated during the data portion of a write cycle, regardless of the state of OE. The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation ‘sleep’ mode. Two clock cycles are required to enter into or exit from this ‘sleep’ mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Burst Write Accesses Linear Burst Address Table The CY7C1354D has an on-chip burst counter that enables the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in Single Write Accesses on page 5. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1354D) inputs must (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Document Number: 001-88918 Rev. *A Test Conditions ZZ VDD 0.2 V ZZ VDD 0.2 V ZZ 0.2 V This parameter is sampled This parameter is sampled Min – – 2tCYC – 0 Max 50 2tCYC – 2tCYC – Unit mA ns ns ns ns Page 6 of 28 CY7C1354D Truth Table The Truth Table for CY7C1354D follows. [1, 2, 3, 4, 5, 6, 7] Operation Address Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ Deselect cycle None H L L X X X L L–H Tri-state Continue deselect cycle None X L H X X X L L–H Tri-state Read cycle (begin burst) External L L L H X L L L–H Data out (Q) Next X L H X X L L L–H Data out (Q) Read cycle (continue burst) NOP/dummy read (begin burst) Dummy read (continue burst) Write cycle (begin burst) External L L L H X H L L–H Tri-state Next X L H X X H L L–H Tri-state External L L L L L X L L–H Data in (D) Write cycle (continue burst) Next X L H X L X L L–H Data in (D) NOP/WRITE ABORT (begin burst) None L L L L H X L L–H Tri-state WRITE ABORT (continue burst) Next X L H X H X L L–H Tri-state IGNORE CLOCK EDGE (stall) SLEEP MODE Current X L X X X X H L–H – None X H X X X X X X Tri-state Notes 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWX = L signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWX. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power up deselected and the I/Os in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is inactive or when the device is deselected, and DQs = data when OE is active. Document Number: 001-88918 Rev. *A Page 7 of 28 CY7C1354D Partial Truth Table for Read/Write The Partial Truth Table for Read/Write for CY7C1354D follows. [8, 9, 10, 11] Function (CY7C1354D) Read WE H BWd X BWc X BWb X BWa X Write– no bytes written L H H H H Write byte a –(DQa and DQPa) L H H H L Write byte b – (DQb and DQPb) L H H L H Write bytes b, a L H H L L Write byte c –(DQc and DQPc) L H L H H Write bytes c, a L H L H L Write bytes c, b L H L L H Write bytes c, b, a L H L L L Write byte d –(DQd and DQPd) L L H H H Write bytes d, a L L H H L Write bytes d, b L L H L H Write bytes d, b, a L L H L L Write bytes d, c L L L H H Write bytes d, c, a L L L H L Write bytes d, c, b L L L L H Write all bytes L L L L L Notes 8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 9. Write is defined by WE and BWX. See Write Cycle Description table for details. 10. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 11. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document Number: 001-88918 Rev. *A Page 8 of 28 CY7C1354D IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1354D incorporates a serial boundary scan test access port (TAP) in the BGA package. This part operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels. The CY7C1354D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO should be left unconnected. Upon power-up, the device comes up in a reset state which does not interfere with the operation of the device. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram on page 11. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction Codes on page 15). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. Document Number: 001-88918 Rev. *A At power-up, the TAP is reset internally to ensure that TDO comes up in a high Z state. TAP Registers Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 12. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This enables data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Exit Order on page 16 and Boundary Scan Exit Order on page 20 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 14. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Page 9 of 28 CY7C1354D Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail in this section. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a high Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP Document Number: 001-88918 Rev. *A controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 10 of 28 CY7C1354D TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 0 1 EXIT1-DR 0 1 0 UPDATE-IR 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 001-88918 Rev. *A Page 11 of 28 CY7C1354D TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Circuitry TDI Selection Circuitry Instruction Register TDO 31 30 29 . . . 2 1 0 Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TAP CONTROLLER TM S TAP Timing 1 2 Test Clock (TCK ) 3 t TH t TM SS t TM SH t TDIS t TDIH t TL 4 5 6 t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE Document Number: 001-88918 Rev. *A UNDEFINED Page 12 of 28 CY7C1354D TAP AC Switching Characteristics Over the Operating Range Parameter [12, 13] Description Min Max Unit Clock tTCYC TCK clock cycle time 50 – ns tTF TCK clock frequency – 20 MHz tTH TCK clock HIGH time 20 – ns tTL TCK clock LOW time 20 – ns tTDOV TCK clock LOW to TDO valid – 10 ns tTDOX TCK clock LOW to TDO invalid 0 – ns tTMSS TMS setup to TCK clock rise 5 – ns tTDIS TDI setup to TCK clock rise 5 – ns tCS Capture setup to TCK rise 5 – ns tTMSH TMS hold after TCK clock rise 5 – ns tTDIH TDI hold after clock rise 5 – ns tCH Capture hold after clock rise 5 – ns Output Times Setup Times Hold Times 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input rise and fall times ...................................................1 ns Input pulse levels ............................................... VSS to 2.5 V Input rise and fall time ....................................................1 ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ....................................... 1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω TDO 50Ω TDO Z O= 50Ω 20pF Z O= 50Ω 20pF Notes 12. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 13. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document Number: 001-88918 Rev. *A Page 13 of 28 CY7C1354D TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted) Parameter [14] Description Test Conditions Output HIGH voltage VOH1 Min Max Unit IOH = –4.0 mA, VDDQ = 3.3 V 2.4 – V IOH = –1.0 mA, VDDQ = 2.5 V 2.0 – V VDDQ = 3.3 V 2.9 – V VDDQ = 2.5 V 2.1 – V VDDQ = 3.3 V – 0.4 V VDDQ = 2.5 V – 0.4 V VDDQ = 3.3 V – 0.2 V VOH2 Output HIGH voltage IOH = –100 µA VOL1 Output LOW voltage IOL = 8.0 mA VOL2 Output LOW voltage VIH Input HIGH voltage VIL Input LOW voltage IX Input load current IOL = 100 µA VDDQ = 2.5 V – 0.2 V VDDQ = 3.3 V 2.0 VDD + 0.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VDDQ = 3.3 V –0.3 0.8 V VDDQ = 2.5 V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Identification Register Definitions Instruction Field CY7C1354D Revision number (31:29) 000 Cypress device ID (28:12) [15] 01011001000100110 Cypress JEDEC ID (11:1) 00000110100 ID register presence (0) 1 Description Reserved for version number. Reserved for future use. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size (× 36) Instruction 3 Bypass 1 ID 32 Boundary scan order (165-ball FBGA package) 61 Notes 14. All voltages referenced to VSS (GND). 15. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 001-88918 Rev. *A Page 14 of 28 CY7C1354D Instruction Codes Code Description EXTEST Instruction 000 Captures the input/output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to high Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the input/output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input/output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-88918 Rev. *A Page 15 of 28 CY7C1354D Boundary Scan Exit Order (256 K × 36) Bit # 165-ball ID Bit # 165-ball ID 1 B6 31 R9 2 B7 32 P9 3 A7 33 R8 4 B8 34 P8 5 A8 35 R6 6 A9 36 P6 7 B10 37 R4 8 A10 38 P4 9 C11 39 R3 10 E10 40 P3 11 F10 41 R1 12 G10 42 N1 13 D10 43 L2 14 D11 44 K2 15 E11 45 J2 16 F11 46 M2 17 G11 47 M1 18 H11 48 L1 19 J10 49 K1 20 K10 50 J1 21 L10 51 Not Bonded (Preset to 1) 22 M10 52 G2 23 J11 53 F2 24 K11 54 E2 25 L11 55 D2 26 M11 56 G1 27 N11 57 F1 28 R11 58 E1 29 R10 59 D1 30 P10 60 C1 61 B2 Document Number: 001-88918 Rev. *A Page 16 of 28 CY7C1354D Maximum Ratings Operating Range Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Range Ambient Temperature Commercial 0 °C to +70 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V DC input voltage ................................. –0.5 V to VDD + 0.5 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, method 3015) .......................... > 2001 V Latch-up current .................................................... > 200 mA VDD VDDQ 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Neutron Soft Error Immunity Parameter Description Test Conditions Typ Max* Unit 368 FIT/M b LSBU Logical single-bit upsets 25 °C 320 LMBU Logical multi-bit upsets 25 °C 0 0.01 FIT/M b Single event latch-up 85 °C 0 0.1 SEL FIT/D ev * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”. Electrical Characteristics Over the Operating Range Parameter [16, 17] Description VDD Power supply voltage VDDQ I/O supply voltage VOH VOL VIH VIL IX Output HIGH voltage Output LOW voltage Input HIGH voltage Min Max Unit 3.135 3.6 V for 3.3 V I/O 3.135 VDD V for 2.5 V I/O 2.375 2.625 V for 3.3 V I/O, IOH =4.0 mA 2.4 – V for 2.5 V I/O, IOH =1.0 mA 2.0 – V for 3.3 V I/O, IOL=8.0 mA – 0.4 V for 2.5 V I/O, IOL=1.0 mA – 0.4 V for 3.3 V I/O 2.0 VDD + 0.3 V V for 2.5 V I/O 1.7 VDD + 0.3 V V for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O –0.3 0.7 V Input leakage current except ZZ GND VI VDDQ and MODE –5 5 A Input current of MODE Input = VSS –30 – A Input = VDD – 5 A Input = VSS –5 – A Input = VDD – 30 A GND VI VDDQ, output disabled –5 5 A Input LOW voltage [18] Input current of ZZ IOZ Test Conditions Output leakage current Notes 16. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 17. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ <VDD. 18. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-88918 Rev. *A Page 17 of 28 CY7C1354D Electrical Characteristics (continued) Over the Operating Range Parameter [16, 17] Description Test Conditions Min Max Unit IDD VDD operating supply VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 5 ns cycle, 200 MHz – 220 mA ISB1 Automatic CE power-down current — TTL inputs Max VDD, device deselected, VIN VIH or VIN VIL, f = fMAX = 1/tCYC 5 ns cycle, 200 MHz – 120 mA ISB2 Automatic CE power-down current — CMOS inputs Max VDD, device deselected, 5 ns cycle, VIN 0.3 V or VIN > VDDQ 0.3 V, 200 MHz f=0 – 40 mA ISB3 Automatic CE power-down current — CMOS inputs Max VDD, device deselected, VIN 0.3 V or VIN > VDDQ 0.3 V, f = fMAX = 1/tCYC 5 ns cycle, 200 MHz – 110 mA ISB4 Automatic CE power-down current — TTL inputs Max VDD, device deselected, VIN VIH or VIN VIL, f = 0 5 ns cycle, 200 MHz – 40 mA Capacitance Parameter [19] Description CIN Input capacitance CCLK Clock input capacitance CI/O Input/output capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 165-ball FBGA Unit Max 5 pF 5 pF 7 pF Thermal Resistance Parameter [19] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 165-ball FBGA Unit Max 16.8 °C/W 3.0 °C/W Note 19. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-88918 Rev. *A Page 18 of 28 CY7C1354D AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 VT = 1.5 V (a) INCLUDING JIG AND SCOPE OUTPUT RL = 50 VT = 1.25 V (a) Document Number: 001-88918 Rev. *A R = 351 10% (c) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE 1 ns (b) GND 5 pF R = 1538 (b) 90% 10% 90% 1 ns R = 1667 2.5 V Z0 = 50 GND 5 pF 2.5 V I/O Test Load OUTPUT ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1 ns 1 ns (c) Page 19 of 28 CY7C1354D Switching Characteristics Over the Operating Range Parameter [20, 21] Description -200 Unit Min Max VCC(typical) to the first access read or write 1 – ms tCYC Clock cycle time 5 – ns FMAX Maximum operating frequency – 200 MHz tCH Clock HIGH 2.0 – ns tCL Clock LOW 2.0 – ns tEOV OE LOW to output valid – 3.2 ns tCLZ [23, 24, 25] 1.5 – ns tPower[22] Clock Clock to low Z Output Times tCO Data output valid after CLK rise – 3.2 ns tEOV OE LOW to output valid – 3.2 ns tDOH Data output hold after CLK rise 1.5 – ns 1.5 3.2 ns 1.5 – ns – 3.2 ns 0 – ns [23, 24, 25] tCHZ Clock to high Z tCLZ Clock to low Z [23, 24, 25] tEOHZ tEOLZ OE HIGH to output high Z OE LOW to output low Z [23, 24, 25] [23, 24, 25] Setup Times tAS Address setup before CLK rise 1.5 – ns tDS Data input setup before CLK rise 1.5 – ns tCENS CEN setup before CLK rise 1.5 – ns tWES WE, BWx setup before CLK rise 1.5 – ns tALS ADV/LD setup before CLK rise 1.5 – ns tCES Chip select setup 1.5 – ns tAH Address hold after CLK rise 0.5 – ns tDH Data input hold after CLK rise 0.5 – ns tCENH CEN hold after CLK rise 0.5 – ns tWEH WE, BWx hold after CLK rise 0.5 – ns tALH ADV/LD hold after CLK rise 0.5 – ns tCEH Chip select hold after CLK rise 0.5 – ns Hold Times Notes 20. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 21. Test conditions shown in (a) of Figure 2 on page 19 unless otherwise noted. 22. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated. 23. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 24. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 25. This parameter is sampled and not 100% tested. Document Number: 001-88918 Rev. *A Page 20 of 28 CY7C1354D Switching Waveforms Figure 3. Read/Write Timing [26, 27, 28] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 10 CLK t CENS t CENH t CES t CEH t CH t CL CEN CE ADV/LD WE BW x A1 ADDRESS A2 A7 t CO t AS t DS t AH Data In-Out (DQ) t DH D(A1) t CLZ D(A2) D(A2+1) t DOH Q(A3) t OEV Q(A4) t CHZ Q(A4+1) D(A5) Q(A6) t OEHZ t DOH t OELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) DON’T CARE READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINED Notes 26. For this waveform ZZ is tied low. 27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document Number: 001-88918 Rev. *A Page 21 of 28 CY7C1354D Switching Waveforms (continued) Figure 4. NOP, STALL, and DESELECT Cycles [29, 30, 31] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BWx ADDRESS A5 t CHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) DON’T CARE STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Notes 29. For this waveform ZZ is tied low. 30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 31. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. Document Number: 001-88918 Rev. *A Page 22 of 28 CY7C1354D Switching Waveforms (continued) Figure 5. ZZ Mode Timing [32, 33] CLK t ZZ ZZ I t t ZZREC ZZI SUPPLY I DDZZ t RZZI A LL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 32. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 33. I/Os are in high Z when exiting ZZ sleep mode. Document Number: 001-88918 Rev. *A Page 23 of 28 CY7C1354D Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices Speed (MHz) 200 Package Diagram Ordering Code CY7C1354D-200BZC Part and Package Type 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Operating Range Commercial Ordering Code Definitions CY 7 C 1354 D - 200 BZ C Temperature Range: C = Commercial; Package Type: BZ = 165-ball FBGA Speed Grade: 200 MHz Process Technology 90 nm Part Identifier: 1354 = PL, 256 Kb × 36 (9 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-88918 Rev. *A Page 24 of 28 CY7C1354D Package Diagrams Figure 6. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *F Document Number: 001-88918 Rev. *A Page 25 of 28 CY7C1354D Acronyms Acronym Document Conventions Description Units of Measure BGA Ball Grid Array CMOS Complementary Metal Oxide Semiconductor °C degree Celsius Symbol Unit of Measure CE Chip Enable MHz megahertz CEN Clock Enable µA microampere EIA Electronic Industries Alliance mA milliampere FBGA Fine-Pitch Ball Grid Array mm millimeter I/O Input/Output ms millisecond JEDEC Joint Electron Devices Engineering Council mV millivolt JTAG Joint Test Action Group ns nanosecond LMBU Logical Multi-Bit Upsets ohm LSB Least Significant Bit % percent LSBU Logical Single-Bit Upsets pF picofarad MSB Most Significant Bit V volt NoBL No Bus Latency W watt OE Output Enable SEL Single Event Latch-up SRAM Static Random Access Memory TAP Test Access Port TCK Test Clock TDI Test Data-In TDO Test Data-Out TMS Test Mode Select TTL Transistor-Transistor Logic WE Write Enable Document Number: 001-88918 Rev. *A Page 26 of 28 CY7C1354D Document History Page Document Title: CY7C1354D, 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture Document Number: 001-88918 Revision ECN Submission Date Orig. of Change ** 4103005 08/23/2013 PRIT New data sheet. *A 4571750 11/18/2014 PRIT Added documentation related hyperlink in page 1 Document Number: 001-88918 Rev. *A Description of Change Page 27 of 28 CY7C1354D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory PSoC Touch Sensing cypress.com/go/memory cypress.com/go/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2013-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-88918 Rev. *A Revised November 18, 2014 Page 28 of 28 No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.