CY7C1012AV25 PRELIMINARY 512K x 24 Static RAM Features Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input/output (I/O) pins is then written into the location specified on the address pins (A0–A16). Asserting all of the chip selects LOW and write enable LOW will write all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. • High speed — tAA = 8, 10, 12 ns • Low active power — 1080 mW (max.) • Operating voltages of 2.5 ± 0.2V • 1.5V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE0, CE1 and CE2 features Data bytes can also be individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins will appear on the specified data input/output (I/O) pins. Asserting all the chip selects LOW will read all 24 bits of data from the SRAM. Functional Description The CY7C1012AV25 is a high-performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE0, CE1, CE2). CE0 controls the data on the I/O0–I/O7, while CE1 controls the data on I/O8–I/O15, and CE2 controls the data on the data pins I/O16–I/O23. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For further details, refer to the truth table of this data sheet. The CY7C1012AV25 is available in a standard 119-ball BGA. Functional Block Diagram I/O0–I/O7 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER 512K x 24 ARRAY 4096 x 4096 COLUMN DECODER I/O8–I/O15 I/O16–I/O23 CE0, CE1, CE2 WE OE A10 A11 A 12 A 13 A 14 A 15 A 16 A 17 A18 CONTROL LOGIC Selection Guide Maximum Access Time Maximum Operating Current Commercial Industrial Commercial/Industrial Maximum CMOS Standby Current Cypress Semiconductor Corporation Document #: 38-05337 Rev. ** • 3901 North First Street • -8 8 300 300 50 -10 10 275 275 50 -12 12 260 260 50 Unit ns mA mA San Jose, CA 95134 • 408-943-2600 Revised January 27, 2003 CY7C1012AV25 PRELIMINARY Pin Configurations 119 BGA Top View 1 2 3 4 5 6 7 A NC A A A A A NC B NC A A CE0 A A NC C I/O12 NC CE1 NC CE2 NC I/O0 D I/O13 VDD VSS VSS VSS VDD I/O1 E I/O14 VSS VDD VSS VDD VSS I/O2 F I/O15 VDD VSS VSS VSS VDD I/O3 G I/O16 VSS VDD VSS VDD VSS I/O4 H I/O17 VDD VSS VSS VSS VDD I/O5 J NC VSS VDD VSS VDD VSS DNU K I/O18 VDD VSS VSS VSS VDD I/O6 L I/O19 VSS VDD VSS VDD VSS I/O7 M I/O20 VDD VSS VSS VSS VDD I/O8 N I/O21 VSS VDD VSS VDD VSS I/O9 P I/O22 VDD VSS VSS VSS VDD I/O10 R I/O23 A NC NC NC A I/O11 T NC A A WE A A NC U NC A A OE A A NC Document #: 38-05337 Rev. ** Page 2 of 9 CY7C1012AV25 PRELIMINARY Maximum Ratings DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Current into Outputs (LOW)......................................... 20 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Range Supply Voltage on VCC to Relative GND[1] .... –0.5V to +3.6V Commercial DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V Industrial Ambient Temperature VCC 0°C to +70°C 2.5V ± 0.2V –40°C to +85°C DC Electrical Characteristics Over the Operating Range -8 Parameter Test Conditions[2] Description VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA VOL Output LOW Voltage VCC = Min., IOL = 1.0 mA VIH Input HIGH Voltage Min. -10 Max. 2.0 Min. 2.0 0.4 VIL[1] Input LOW Voltage IIX Input Load Current IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC ISB1 Automatic CE Power-down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-down Current —CMOS Inputs Max. VCC, Commercial CE > VCC – 0.2V, /Industrial VIN > VCC – 0.2V, or VIN < 0.2V, f = 0 GND < VI < VCC -12 Max. Min. Max. 2.0 0.4 Unit V 0.4 V V 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 –0.3 0.8 –0.3 0.8 –0.3 0.8 V –1 +1 –1 +1 –1 +1 µA +1 –1 +1 –1 +1 µA Commercial 300 275 260 mA Industrial 300 275 260 mA 100 100 100 mA 50 50 50 mA –1 Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = 2.5V 8 pF 10 pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05337 Rev. ** Page 3 of 9 CY7C1012AV25 PRELIMINARY AC Test Loads and Waveforms[4] 50Ω Z0 = 50Ω (a) R1 317 Ω 2.5V VTH = VDD/2 OUTPUT OUTPUT 30 pF* * Capacitive Load consists of all components of the test environment. R2 351Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES (b) 2.5V 90% 90% 10% GND 10% Fall time: > 1 V/ns Rise time > 1 V/ns (c) AC Switching Characteristics Over the Operating Range [5] -8 Parameter Description Min. -10 Max. Min. -12 Max. Min. Max. Unit Read Cycle tpower[6] VCC(typical) to the first access 1 1 1 ms tRC Read Cycle Time 8 10 12 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1, CE2, and CE3 LOW to Data Valid 8 10 12 ns tDOE OE LOW to Data Valid 5 5 6 ns tLZOE OE LOW to Low 8 Z[7] OE HIGH to High tLZCE CE1, CE2, and CE3 LOW to Low Z[7] CE1, CE2, and CE3 LOW to tPD CE1, CE2, or CE3 HIGH to tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low tHZBE Write Z[7] Power-up[8] 5 0 0 6 ns ns 6 ns ns 0 8 10 12 ns 5 5 6 ns 1 Z[7] ns 3 5 ns ns 1 3 5 Power-down[8] Z[7] Byte Disable to High 3 12 3 1 5 CE1, CE2, or CE3 HIGH to High tPU 3 1 Z[7] tHZOE tHZCE 3 10 1 5 1 5 ns 6 ns Cycle[9, 10] tWC Write Cycle Time 8 10 12 ns tSCE CE1, CE2, and CE3 LOW to Write End 6 7 8 ns Notes: 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (2.3V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5V) voltage. 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise. 6. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation is started. 7. tHZOE, tHZCE , tHZWE, tHZBE, and t LZOE, t LZCE , tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal write time of the memory is defined by the overlap of CE1, CE2, and CE3 LOW and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05337 Rev. ** Page 4 of 9 CY7C1012AV25 PRELIMINARY AC Switching Characteristics Over the Operating Range (continued)[5] -8 Parameter Description Min. -10 Max. Min. -12 Max. Min. Max. Unit tAW Address Set-Up to Write End 6 7 8 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 6 7 8 ns tSD Data Set-Up to Write End 5 5.5 6 ns tHD Data Hold from Write End 0 0 0 ns 3 3 3 ns [7] tLZWE WE HIGH to Low Z [7] tHZWE WE LOW to High Z 5 tBW Byte Enable to End of Write 6 5 6 7 8 ns ns Data Retention Waveform DATA RETENTION MODE 2.3V VCC 2.3V VDR > 1.5V tCDR tR CE Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[2, 12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05337 Rev. ** Page 5 of 9 CY7C1012AV25 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[2, 14, 15] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 16 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[2, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 16 tHD DATA VALID tHZWE tLZWE Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05337 Rev. ** Page 6 of 9 CY7C1012AV25 PRELIMINARY Truth Table CE0 CE1 CE2 OE WE I/O0–I/O23 Mode Power H H H X X High-Z Power-down Standby (ISB) L H H L H I/O0–I/O7 Data Out Read Active (ICC) H L H L H I/O8–I/O15 Data Out Read Active (ICC) H H L L H I/O16–I/O23 Data Out Read Active (ICC) L L L L H Full Data Out Read Active (ICC) L H H X L I/O0–I/O7 Data In Write Active (ICC) H L H X L I/O8–I/O15 Data In Write Active (ICC) H H L X L I/O16–I/O23 Data In Write Active (ICC) L L L X L Full Data In Write Active (ICC) L L L H H High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 8 Ordering Code CY7C1012AV25-8BGC CY7C1012AV25-8BGI 10 12 Package Name BG119 Package Type 14 × 22 mm 119-ball BGA Operating Range Commercial Industrial CY7C1012AV25-10BGC Commercial CY7C1012AV25-10BGI Industrial CY7C1012AV25-12BGC Commercial CY7C1012AV25-12BGI Industrial Document #: 38-05337 Rev. ** Page 7 of 9 PRELIMINARY CY7C1012AV25 Package Diagram 119-lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05337 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1012AV25 Document History Page Document Title: CY7C1012AV25 512K x 24 Static RAM Document Number: 38-05337 REV. ECN NO. Issue Date Orig. of Change ** 119630 01/29/03 DFP Document #: 38-05337 Rev. ** Description of Change New Data Sheet Page 9 of 9