CY7C1012DV33 PRELIMINARY 12-Mbit (512K X 24) Static RAM Features power-down feature that significantly consumption when deselected. • High speed reduces power Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input/output (I/O) pins is then written into the location specified on the address pins (A0–A18). Asserting all of the chip selects LOW and write enable LOW will write all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. — tAA = 8 ns • Low active power — ICC = 185 mA @ 8 ns • Low CMOS standby power — ISB2 = 25 mA • Operating voltages of 3.3 ± 0.3V Data bytes can also be individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins will appear on the specified data input/output (I/O) pins. Asserting all the chip selects LOW will read all 24 bits of data from the SRAM. • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Available in Lead Pb-Free Standard 119-ball PBGA Functional Description The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For further details, refer to the truth table of this data sheet. The CY7C1012DV33 is a high-performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE1, CE2, CE3). CE1 controls the data on the I/O0–I/O7, while CE2 controls the data on I/O8–I/O15, and CE3 controls the data on the data pins I/O16–I/O23. This device has an automatic Functional Block Diagram 512K x 24 ARRAY I/O8–I/O15 I/O16–I/O23 CE1, CE2, CE3 WE OE CONTROL LOGIC A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 COLUMN DECODER I/O0–I/O7 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER Selection Guide Maximum Access Time –8 Unit 8 ns Maximum Operating Current 185 mA Maximum CMOS Standby Current 25 mA Cypress Semiconductor Corporation Document #: 38-05610 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 4, 2006 [+] Feedback CY7C1012DV33 PRELIMINARY Pin Configurations[1] 119 PBGA Top View 1 2 3 4 5 6 7 A NC A A A A A NC B NC A A CE1 A A NC C I/O12 NC CE2 NC CE3 NC I/O0 D I/O13 VDD VSS VSS VSS VDD I/O1 E I/O14 VSS VDD VSS VDD VSS I/O2 F I/O15 VDD VSS VSS VSS VDD I/O3 G I/O16 VSS VDD VSS VDD VSS I/O4 H I/O17 VDD VSS VSS VSS VDD I/O5 J NC VSS VDD VSS VDD VSS NC K I/O18 VDD VSS VSS VSS VDD I/O6 L I/O19 VSS VDD VSS VDD VSS I/O7 M I/O20 VDD VSS VSS VSS VDD I/O8 N I/O21 VSS VDD VSS VDD VSS I/O9 P I/O22 VDD VSS VSS VSS VDD I/O10 R I/O23 A NC NC NC A I/O11 T NC A A WE A A NC U NC A A OE A A NC Note: 1. NC pins are not connected on the die Document #: 38-05610 Rev. *B Page 2 of 9 [+] Feedback CY7C1012DV33 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current...................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC Relative to GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................–0.5V to VCC + 0.5V DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Range Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range –8 Parameter [7] Description Test Conditions Min. 2.4 Max. Unit 0.4 V 2.0 VCC + 0.3 V VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA V VIH Input HIGH Voltage VIL[2] Input LOW Voltage –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC IOUT = 0 mA CMOS levels 185 mA ISB1 Automatic CE Power-down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 30 mA ISB2 Automatic CE Power-down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 25 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF 10 pF Thermal Resistance[3] Parameter ΘJA ΘJC Description Test Conditions All - Packages Unit TBD °C/W TBD °C/W Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board Thermal Resistance (Junction to Case) AC Test Loads and Waveforms[4] 50Ω 3.3V R1 317Ω VTH = 1.5V OUTPUT Z0 = 50Ω OUTPUT 30 pF* * Capacitive Load consists of all components of the test environment. (a) ALL INPUT PULSES 3.0V 90% GND 90% 10% R2 351Ω 5 pF INCLUDING JIG AND SCOPE (b) 10% Rise time > 1 V/ns (c) Fall time: > 1 V/ns Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 µs (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document #: 38-05610 Rev. *B Page 3 of 9 [+] Feedback CY7C1012DV33 PRELIMINARY AC Switching Characteristics Over the Operating Range [5] –8 Parameter Description Min. Max. Unit Read Cycle tpower[6] VCC(typical) to the first access tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE tDOE ns CE active LOW to Data Valid[7] 8 ns OE LOW to Data Valid 5 ns [8] 3 OE HIGH to High-Z CE active LOW to Low-Z[7, 8] CE deselect HIGH to tHZCE CE active LOW to tPU 3 High-Z[7, 8] Power-up[7, 9] CE deselect HIGH to Byte Enable to Data Valid tLZBE Byte Enable to Low-Z[8] 0 ns ns 8 ns 5 ns 1 High-Z[8] ns ns 5 Power-down[7, 9] tDBE Byte Disable to ns 5 tPD tHZBE ns 1 [8] tLZCE Write Cycle 8 ns tHZOE tWC µs 8 OE LOW to Low-Z tLZOE 100 ns 5 ns [10, 11] Write Cycle Time End[7] 8 ns 6 ns 6 ns tSCE CE active LOW to Write tAW Address Set-up to Write End tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 6 ns tSD Data Set-up to Write End 5 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low-Z[8] 3 ns tHZWE WE LOW to High-Z[8] tBW Byte Enable to End of Write 5 6 ns ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed. 7. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 or CE2 or CE3 LOW. When deselect HIGH, CE indicates the CE1 and CE2 and CE3 HIGH 8. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal write time of the memory is defined by the overlap of CE1 or CE2 or CE3 LOW and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05610 Rev. *B Page 4 of 9 [+] Feedback CY7C1012DV33 PRELIMINARY Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[12] Operation Recovery Time Min. Typ. Max. 2 Unit V 25 VCC = 2V , CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3V VCC VDR > 2V 3V tR tCDR CE Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[7, 14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05610 Rev. *B Page 5 of 9 [+] Feedback CY7C1012DV33 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[7, 16, 17] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[7, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATA VALID tHZWE tLZWE Notes: 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05610 Rev. *B Page 6 of 9 [+] Feedback CY7C1012DV33 PRELIMINARY Truth Table CE1 CE2 CE3 OE WE H H H X X High-Z I/O0–I/O7 High-Z I/O8–I/O15 High-Z I/O16–I/O23 Power-down Mode Standby (ISB) Power L H H L H Data Out High-Z High-Z Read Active (ICC) H L H L H High-Z Data Out High-Z Read Active (ICC) H H L L H High-Z High-Z Data Out Read Active (ICC) L L L L H Full Data Out Full Data Out Full Data Out Read Active (ICC) L H H X L Data In High-Z High-Z Write Active (ICC) H L H X L High-Z Data In High-Z Write Active (ICC) H H L X L High-Z High-Z Data In Write Active (ICC) L L L X L Full Data In Full Data In Full Data In Write Active (ICC) L L L H H High-Z High-Z High-Z Selected, Active (ICC) Outputs Disabled Ordering Information Speed (ns) Ordering Code Package Name 8 CY7C1012DV33-8BGXC 51-85115 Document #: 38-05610 Rev. *B Package Type Operating Range 119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free) Commercial Page 7 of 9 [+] Feedback PRELIMINARY CY7C1012DV33 Package Diagram 119-ball PBGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05610 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback PRELIMINARY CY7C1012DV33 Document History Page Document Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM Document Number: 38-05610 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 250650 See ECN SYT New Data Sheet *A 469517 See ECN NXR Converted from Advance Information to Preliminary Corrected typo in the Document Title Removed –10 and –12 speed bins from product offering Changed J7 ball of BGA from DNU to NC Removed Industrial Operating range from product offering Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page #3 Changed ICC(Max) from 220 mA to 150 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot spec in footnote # 1 Updated the Truth Table Updated the ordering Information table *B 499604 See ECN NXR Added note# 1 for NC pins Changed ICC spec from 150 mA to 185 mA Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics Table on page# 4 Document #: 38-05610 Rev. *B Page 9 of 9 [+] Feedback