DS80EP100 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables General Description Features National’s Power-saver equalizer compensates for transmission medium losses and minimizes medium-induced deterministic jitter. Performance is guaranteed over the full range of 5 to 12.5 Gbps. The DS80EP100 requires no power to operate. The equalizer operates anywhere in the data path to minimize media-induced deterministic jitter in both FR4 traces and cable applications. Symmetric I/O structures support full duplex or half duplex applications. Linear compensation is provided independent of line coding or protocol. The device is ideal for both bi-level and multi-level signaling. The equalizer is available in a 6 pin leadless LLP package with a space saving 2.2 mm X 2.5 mm footprint. This tiny package provides maximum flexibility in placement and routing of the Power-saver equalizer. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5 to 12.5 Gbps Operation No Power or Ground Required Equalization effective anywhere in data path Equalizes CML, LV-PECL, LVDS signals Symmetric I/O structures provide equal boost for bidirectional operation 7 dB Maximum Boost Code independent, 8b/10b or Scrambled Supports both bi-level and multi-level signaling Extends reach over backplanes and cables Compatible with PCI-Express Gen1 and Gen2 Compatible with XAUI Will operate in series with existing active Equalizer Easy to handle 6 pin LLP Simplified Application Diagram 30029401 Note: The DS80EP100 provides the flexibility of passing the data from either side of the device. It can be placed anywhere in the data path. © 2007 National Semiconductor Corporation 300294 www.national.com DS80EP100 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables July 2007 DS80EP100 Pin Descriptions Pin Name Pin Number I/O Type Description IOAIOA+ 3 1 I/O Symmetric differential I/O IOBIOB+ 4 6 I/O Symmetric differential I/O NC Exposed Pad 2, 5 DAP N/A Reserved. Do not connect. High speed differential I/O Note: I = Input / O = Output Connection Diagram 30029405 Bottom View Shown 2.2mm x 2.5mm 6-Pin LLP Package Order Number DS80EP100 See NS Package Number SDA14A www.national.com 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. INPUT/OUTPUT (IOA+ and IOB+) or (IOA- and IOB-) (IOA+ and IOA-) or (IOB+ and IOB-) (IOA+ and IOB-) or (IOA- and IOB+) Junction Temperature Storage Temperature +260°C HBM, 1.5 kΩ, 100 pF 1.3kV Recommended Operating Conditions +2V +4V +4V +150°C −65°C to +150°C Ambient Temperature Bit Rate Min Typ −40 25 5 Max +85 12.5 Units °C Gbps Electrical Characteristics (Note 6) Over recommended operating conditions unless other specified. All parameters are guaranteed by test, statistical analysis or design. Symbol VIN Parameter Conditions Min Typ (Note 2) Max Units 1000 3600 mVp-p Input voltage swing (Note 3) Equalization 6.25 GHz relative to 100MHz 6 dB RLI Differential input return loss 100 MHz – 6.25 GHz, with fixture's effect deembedded 15 dB RLO Differential output return loss 100 MHz – 6.25 GHz, with fixture's effect deembedded IOA+, or IOB+ = static high. 15 dB Input Impedance Differential across IOA+ and IOA-, or IOB+ and IOB-, ZLOAD = 100Ω 100 Ω Output Impedance Differential across IOA+ and IOA-, or IOB+ and IOB-, ZSOURCE = 100Ω Through Response Relative to ideal load, see Figure 2 for setup RIN RO Ω 100 See Figure 3 and Table 1 for limits R1 Resistance IOA+ to IOAand IOB+ to IOBNo load, high impedance on all ports 150 Ω R2 Resistance IOA+ to IOB+ and IOA- to IOBNo load, high impedance on all ports 50 Ω R3 Resistance IOA+ to IOBNo load, high impedance on all ports and IOA- to IOB+ 150 Ω DC Gain (IOA/IOB or IOB/IOA) ZLOAD 0.4 = 100Ω DJ1 Residual deterministic jitter 5 Gbps, 20 in of 6mil microstrip FR4 DJ2 Residual deterministic jitter 6.25 Gbps, 20 in of 6mil microstrip FR4 DJ3 Residual deterministic jitter 8 Gbps, 20 in of 6mil microstrip FR4 DJ4 Residual deterministic jitter 10 Gbps, 20 in of 6mil microstrip FR4 See (Note 4) 0.15 UIp-p DJ5 Residual deterministic jitter 12.5 Gbps, 14 in of 6mil microstrip FR4 See (Note 4) 0.15 UIp-p See (Note 4) See (Notes 4, 5) See (Notes 4, 5) 3 0.15 0.15 0.15 UIp-p 0.20 0.20 UIp-p UIp-p www.national.com DS80EP100 Lead Temperature Soldering, 4 sec ESD Rating Absolute Maximum Ratings (Note 1) DS80EP100 Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: Typical values represent most likely parametric norms, TA = +25 degC, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 3: Differential signal to Equalizer, measured at the input to a transmission line, see point A of Figure 1. The transmission line is Z0 = 100Ω, 6-mil, microstrip in FR4 material. Note 4: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1). Test pattern: PRBS- 7 . Note 5: Specification is guaranteed by characterization and is not tested in production. Note 6: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. www.national.com 4 DS80EP100 Test Setup Diagrams 30029403 FIGURE 1. Transient Test Setup Diagram 30029404 FIGURE 2. Frequency Response Test Circuit Typical Equalizer Transfer Function 30029406 FIGURE 3. Typical Equalizer Transfer Function 5 www.national.com DS80EP100 Table 1. Typical Through Response Frequency (GHz) DS80EP100 Attenuation Typ (dB) 0.1 -8.25 0.5 -7.64 1 -6.12 1.5 -4.68 2 -3.57 3 -2.22 4 -1.66 5 -1.53 6 -1.77 7 -2.28 8 -2.8 9 -3.47 10 -3.91 Block Diagram 30029402 FIGURE 4. Simplified Block Diagram Application Information path and will provide the same compensation at the receiving circuit. (See Simplified Application Diagram) DS80EP100 DEVICE DESCRIPTION The DS80EP100 Power-Saver equalizer is a passive network circuit composed of resistive, capacitive, and inductive components (See Figure 4). A Differential bridged T-network compensates for the transmission medium losses and minimizes medium-induced deterministic jitter with FR4 and cables. The equalizer attenuates low frequency signals and is a bandpass filter at the resonant frequency. The response is linear and symmetric. SYMMETRIC I/O STRUCTURES The symmetry of the passive equalization network allows bidirectional operation. Signals receive equal compensation regardless of the direction of data flow. (See Simplified Block Diagram). PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS AND NO CONNECT PADS The differential I/Os must have a controlled differential impedance of 100Ω. It is preferable to route all differential lines exclusively on one layer of the board. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Differential signals should be routed away from other signals and noise sources on the printed circuit board. Pin 2, Pin 5, and the center DAP have to be left as no connect. Therefore, do not connect the landing pads of these pins to the power or ground plane. See AN-1187 for additional information on the LLP package. I/O TERMINATIONS The DS80EP100 I/O impedance is 100Ω differential. The equalizer is designed for 100Ω-balanced differential signals and is not intended for single-ended transmission. LINEAR COMPENSATION The unique linear compensation feature of the DS80EP100 combined with the tiny package allows maximum flexibility in placement. The equalizer can be placed anywhere in the data www.national.com 6 DS80EP100 Typical Performance Characteristics 30029407 30029408 Residual Deterministic Jitter vs. FR4 Length Residual Deterministic Jitter vs. FR4 Length 30029409 30029410 Eye Height vs. FR4 Length Eye Height vs. FR4 Length 7 www.national.com DS80EP100 Typical Eye Diagrams — Includes Transmitter Setup, Interconnect, and Device Total Jitter 30029411 30029414 FIGURE 5. Unequalized Signal (20in FR4, 5Gbps, PRBS7) FIGURE 8. Unequalized Signal (20in FR4, 6.25Gbps, PRBS7) 30029412 30029415 FIGURE 6. Equalized Signal (20in FR4, 5Gbps, PRBS7) FIGURE 9. Equalized Signal (20in FR4, 6.25Gbps, PRBS7) 30029413 30029416 FIGURE 7. Equalized Signal (Zoom) (20in FR4, 5Gbps, PRBS7) www.national.com FIGURE 10. Equalized Signal (Zoom) (20in FR4, 6.26Gbps, PRBS7) 8 DS80EP100 30029420 30029417 FIGURE 11. Unequalized Signal (20in FR4, 8Gbps, PRBS7) FIGURE 14. Unequalized Signal (20in FR4, 10Gbps, PRBS7) 30029418 30029421 FIGURE 12. Equalized Signal (20in FR4, 8Gbps, PRBS7) FIGURE 15. Equalized Signal (20in FR4, 10Gbps, PRBS7) 30029419 30029422 FIGURE 13. Equalized Signal (Zoom) (20in FR4, 8Gbps, PRBS7) FIGURE 16. Equalized Signal (Zoom) (20in FR4, 10Gbps, PRBS7) 9 www.national.com DS80EP100 30029426 30029423 FIGURE 17. Unequalized Signal (14in FR4, 12.5Gbps, PRBS7) FIGURE 20. Unequalized Signal (5m 26AWG Twin-AX Cable, 5Gbps, PRBS7) 30029424 30029427 FIGURE 18. Equalized Signal (14in FR4, 12.5Gbps, PRBS7) FIGURE 21. Equalized Signal (5m 26AWG Twin-AX Cable, 5Gbps, PRBS7) 30029425 30029428 FIGURE 19. Equalized Signal (Zoom) (14in FR4, 12.5Gbps, PRBS7) www.national.com FIGURE 22. Equalized Signal (Zoom) (5m 26AWG TwinAX Cable, 5Gbps, PRBS7) 10 DS80EP100 30029432 30029429 FIGURE 23. Unequalized Signal (5m 26AWG Twin-AX Cable, 8Gbps, PRBS7) FIGURE 26. Unequalized Signal (5m 26AWG Twin-AX Cable, 10Gbps, PRBS7) 30029430 30029433 FIGURE 24. Equalized Signal (5m 26AWG Twin-AX Cable, 8Gbps, PRBS7) FIGURE 27. Equalized Signal (5m 26AWG Twin-AX Cable, 10Gbps, PRBS7) 30029431 30029434 FIGURE 25. Equalized Signal (Zoom) (5m 26AWG TwinAX Cable, 8Gbps, PRBS7) FIGURE 28. Equalized Signal (Zoom) (5m 26AWG TwinAX Cable, 10Gbps, PRBS7) 11 www.national.com DS80EP100 Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS80EP100 See NS Package SDB06A www.national.com 12 DS80EP100 Notes 13 www.national.com DS80EP100 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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