NSC DS10BR150TSD

DS10BR150
1.0 Gbps LVDS Buffer / Repeater
General Description
Features
The DS10BR150 is a single channel 1.0 Gbps LVDS buffer
optimized for high-speed signal transmission over lossy FR-4
printed circuit board backplanes and balanced cables. Fully
differential signal paths ensure exceptional signal integrity
and noise immunity.
Wide input common mode range allows the receiver to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. The differential inputs and outputs are internally
terminated with a 100Ω resistor to lower device input and output return losses, reduce component count and further minimize board space.
■ DC - 1.0 Gbps low jitter, high noise immunity, low power
operation
■ On-chip 100Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
■ 7 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 3 mm x 3 mm 8-LLP space saving package
Applications
■ Clock and data buffering
■ OC-12 / STM-4
■ FireWire 800
Typical Application
30001710
© 2007 National Semiconductor Corporation
300017
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DS10BR150 1.0 Gbps LVDS Buffer / Repeater
November 8, 2007
DS10BR150
Block Diagram
30001701
Pin Diagram
30001702
Pin Descriptions
Pin Name
Pin Name
Pin Type
Pin Description
NC
1
NA
"NO CONNECT" pin.
IN+
2
Input
Non-inverting LVDS input pin.
IN-
3
Input
Inverting LVDS input pin.
NC
4
NA
"NO CONNECT" pin.
NC
5
NA
"NO CONNECT" pin.
OUT-
6
Output
Inverting LVDS output pin.
OUT+
7
Output
Non-inverting LVDS Output pin.
VCC
8
Power
Power supply pin.
GND
DAP
Power
Ground pad (DAP - die attach pad)
Ordering Code
NSID
Function
DS10BR150TSD
Buffer / Repeater
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2
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
−0.3V to +4V
LVDS Input Voltage (IN+, IN−)
−0.3V to +4V
LVDS Differential Input Voltage ((IN+) - (IN−))
0V to 1V
LVDS Output Voltage (OUT+, OUT−)
−0.3V to (VCC +0.3V)
LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1V
LVDS Output Short Circuit Current
5 ms
Duration
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
SDA Package
2.08W
Derate SDA Package
16.7 mW/°C above +25°C
θJA
+60.0°C/W
θJC
ESD Susceptibility
HBM
+12.3°C/W
≥7 kV
≥250V
≥1250V
MM
CDM
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Supply Voltage (VCC)
Receiver Differential Input
Voltage (VID)
Operating Free Air
Temperature (TA)
Min
3.0
0
Typ
3.3
Max
3.6
1
Units
V
V
−40
+25
+85
°C
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
250
350
450
mV
35
mV
1.375
V
35
mV
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
RL = 100Ω
-35
1.05
1.2
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
RL = 100Ω
IOS
Output Short Circuit Current (Note 8)
OUT to GND
-30
-50
mA
OUT to VCC
7.5
50
mA
-35
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT- Pins
100
Ω
LVDS INPUT DC SPECIFICATIONS (IN+, IN-)
VID
Input Differential Voltage
0
VCM = +0.05V or VCC-0.05V
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCMR
Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = 3.6V or 0V
VCC = 3.6V or 0V
CIN
Input Capacitance
RIN
Input Termination Resistor
0
−100
Between IN+ and IN- Pins
1
V
+100
mV
0
0.05
±1
mV
VCC 0.05
V
±10
μA
1.7
pF
100
Ω
SUPPLY CURRENT
ICCD
Total Supply Current
16
3
21
mA
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DS10BR150
Package Thermal Resistance
Absolute Maximum Ratings (Note 4)
DS10BR150
AC Electrical Characteristics
(Note 9)
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 7)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
380
600
ps
410
600
ps
LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-)
tPHLD2
Differential Propagation Delay High to Low
tPLHD2
Differential Propagation Delay Low to High
tSKD1
Pulse Skew |tPLHD − tPHLD| (Note 10)
30
150
ps
tSKD2
Part to Part Skew (Note 11)
45
160
ps
tLHT
Rise Time
165
400
ps
tHLT
Fall Time
155
400
ps
RL = 100Ω
RL = 100Ω
JITTER PERFORMANCE (Figure 5)
tDJ
tRJ
tTJ
Deterministic Jitter (Peak-to-Peak Value )
(Note 13)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
622 Mbps
12
39
ps
1.06 Gbps
15
42
ps
Random Jitter (RMS Value)
(Note 12)
VID = 350 mV
VCM = 1.2V
Clock (NRZ)
311 MHz
0.6
1.3
ps
503 MHz
0.6
1.1
ps
Total Jitter (Peak to Peak Value)
(Note 14)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
622 Mbps
0.02
0.04
UIP-P
1.06 Gbps
0.02
0.05
UIP-P
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Note 9: Specification is guaranteed by characterization and is not tested in production.
Note 10: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 11: tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 12: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 13: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 14: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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DS10BR150
DC Test Circuits
30001720
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30001721
FIGURE 2. Differential Driver AC Test Circuit
30001722
FIGURE 3. Propagation Delay Timing Diagram
30001723
FIGURE 4. LVDS Output Transition Times
5
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DS10BR150
30001729
FIGURE 5. Jitter Measurements Test Circuit
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6
INPUT INTERFACING
The DS10BR150 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the
DS10BR150 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS10BR150 inputs are internally terminated with
a 100Ω resistor.
30001711
Typical LVDS Driver DC-Coupled Interface to DS10BR150 Input
30001712
Typical CML Driver DC-Coupled Interface to DS10BR150 Input
30001713
Typical LVPECL Driver DC-Coupled Interface to DS10BR150 Input
7
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DS10BR150
Device Operation
DS10BR150
OUTPUT INTERFACING
The DS10BR150 outputs signals are compliant to the LVDS standard. It can be DC-coupled to most common differential receivers.
The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have
high impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliant
signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation.
30001714
Typical DS10BR150 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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DS10BR150
Typical Performance
30001730
30001731
A 622 Mbps NRZ PRBS-7 Output Eye Diagram
V:100 mV / DIV, H:200 ps / DIV
A 1062.5 Mbps NRZ PRBS-7 Output Eye Diagram
V:100 mV / DIV, H:150 ps / DIV
30001732
30001733
Total Jitter as a Function of Input Amplitude
Total Jitter as a Function of Input Amplitude
9
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DS10BR150
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS10BR150TSD
NS Package Number SDA08A
(See AN-1187 for PCB Design and Assembly Recommendations)
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DS10BR150
Notes
11
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DS10BR150 1.0 Gbps LVDS Buffer / Repeater
Notes
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