AKM AK1548

[AK1548]
AK1548
8GHz Low Noise Integer-N Frequency Synthesizer
1. Overview
The AK1548 is an Integer-N PLL (Phase Locked Loop) frequency synthesizer, covering a wide range of frequency
from 1GHz to 8GHz. Consisting of a highly accurate charge pump, a reference divider, a programmable divider
and a dual-modulus prescaler (P/P+1), this product provides high performance, very low Phase Noise and small
footprints.
An ideal PLL can be achieved by combining the AK1548 with the external loop filter and VCO (Voltage Controlled
Oscillator). Access to the registers is controlled via a 3-wire serial interface. The operating supply voltage is from
2.7V to 3.3V, and the charge pump circuit and the serial interface can be driven by individual supply voltage.
2. Features
…
Operating frequency :
1GHz to 8GHz
…
Programmable charge pump current :
650μA to 5200μA typical with 8steps
The current range can be controlled by an external resistor.
…
Fast lock mode for improved lock time :
The programmable timer can switch two charge pump
current setting.
…
Supply Voltage :
2.7 to 3.3 V (PVDD, AVDD pins)
…
Separate Charge Pump Power Supply :
PVDD to 5.5V (CPVDD pin)
…
Excellent Phase Noise :
-226dBc/Hz
…
On-chip lock detection feature of PLL :
Selectable Phase Frequency Detector (PFD) Output or
Digital filtered lock detect
…
Package :
20pin QFN (0.5mm pitch, 4mm × 4mm × 0.75mm)
…
Operating temperature :
-40°C to 85°C
MS1364-E-00
1
2012/1
[AK1548]
- Table of Contents -
1.
Overview ____________________________________________________________________________ 1
2.
Features ____________________________________________________________________________ 1
3.
Block Diagram _______________________________________________________________________ 3
4.
Pin Functional Description and Assignments _____________________________________________ 4
5.
Absolute Maximum Ratings ____________________________________________________________ 6
6.
Recommended Operating Range ________________________________________________________ 6
7.
Electrical Characteristics ______________________________________________________________ 7
8.
Block Functional Descriptions _________________________________________________________ 11
9.
Register Map _______________________________________________________________________ 19
10.
Function Description - Registers _______________________________________________________ 21
11.
IC Interface Schematic _______________________________________________________________ 31
12.
Recommended Connection Schematic of Off-Chip Component _____________________________ 33
13.
Block Power-Up Timing Chart (Recommended Flow) ______________________________________ 36
14.
Frequency Change Timing Chart (Recommended Flow)____________________________________ 38
15.
Typical Evaluation Board Schematic ____________________________________________________ 39
16.
Outer Dimensions ___________________________________________________________________ 40
17.
Marking ____________________________________________________________________________ 41
In this specification, the following notations are used for specific signal and register names.
[Name]
: Pin name
<Name> : Register group name (Address name)
{Name}
: Register bit name
MS1364-E-00
2
2012/1
[AK1548]
CPVSS
CPVDD
PVDD
BIAS
R COUNTER
14 bit
REFIN
PVSS
LDO
AVDD
VREF1
VBG
AVSS
VREF2
3. Block Diagram
PHASE
FREQENCY
DETECTOR
CLK
CHARGE
PUMP
CP
REGISTER
24 bit
DATA
LE
LOCK DETECT
SWALLOW
COUNTER
6 bit
FAST
COUNTER
PROGRAMABLE
COUNTER
13 bit
N D IVIDER
-
8/9,16/17,32/33,64/65
MS1364-E-00
3
PDN
RFINN
LD
TEST2
+
TEST1
RFINP
PRESCALER
2012/1
[AK1548]
4. Pin Functional Description and Assignments
1. Pin Functions
Power down
(Note 1)
No.
Name
I/O
Pin Functions
Remarks
1
CPVSS
G
Charge pump ground
2
TEST1
DI
Test pin 1
3
AVSS
G
Analog ground
4
RFINN
AI
Complementary input to the RF Prescaler
5
RFINP
AI
Input to the RF Prescaler
6
AVDD
P
Power supply for analog blocks
7
VREF1
AO
Connect reference voltage capacitor for LDO
8
REFIN
AI
Reference signal input
9
PVSS
G
Peripherals ground
10
TEST2
DI
Test pin 2
11
PDN
DI
Power down
12
CLK
DI
Serial clock input
Schmidt trigger input
13
DATA
DI
Serial data input
Schmidt trigger input
14
LE
DI
Load enable input
Schmidt trigger input
15
LD
DO
Lock detect output
16
PVDD
P
17
VREF2
AO
18
CPVDD
P
19
BIAS
AIO
Resistance pin for setting charge pump current
20
CP
AO
Charge pump output
Internal pull-down,
Schmidt trigger input
“Low”
Internal pull-down,
Schmidt trigger input
“Low”
Power supply for peripherals
Connect reference voltage capacitor
“Low”
Power supply for charge pump
“Hi-Z”
Note 1)
“Power Down” means the state of [PDN]=”Low” after power on.
Note 2)
The exposed pad at the center of the backside should be connected to ground.
The following table shows the meaning of abbreviations used in the “I/O” column.
AI: Analog input pin
AO: Analog output pin
AIO: Analog I/O pin
DO: Digital output pin
P: Power supply pin
G: Ground pin
MS1364-E-00
4
DI: Digital input pin
2012/1
[AK1548]
CP
BIAS
CPVDD
VREF2
PVDD
2. Pin Assignments
20
19
18
17
16
CPVSS
1
15 LD
TEST1
2
14 LE
AVSS
3
TOP
13 DATA
VIEW
11 PDN
6
7
8
9
10
TEST2
5
PVSS
RFINP
REFIN
12 CLK
VREF1
4
AVDD
RFINN
20pin QFN (0.5mm pitch, 4mm × 4mm)
MS1364-E-00
5
2012/1
[AK1548]
5. Absolute Maximum Ratings
Parameter
Min.
Max.
Unit
VDD1
-0.3
3.6
V
[AVDD], [PVDD] (Note 1)
VDD2
-0.3
6.5
V
[CPVDD] (Note 1)
VSS1
0
0
V
[AVSS], [PVSS]
VSS2
0
0
V
[CPVSS]
Analog Input Voltage
VAIN
VSS1-0.3
VDD1+0.3
V
[RFINN], [RFINP], [REFIN] (Notes 1 & 2)
Digital Input Voltage
VDIN
VSS1-0.3
VDD1+0.3
V
Input Current
IIN
-10
10
mA
Storage Temperature
Tstg
-55
125
°C
Supply Voltage
Ground Level
Symbol
Note 1)
0V reference for all voltages.
Note 2)
Maximum must not be over 3.6V.
Remarks
[CLK], [DATA], [LE], [PDN], [TEST1],
[TEST2] (Notes 1 & 2)
Exceeding these maximum ratings may result in damage to the AK1548. Normal operation is not guaranteed at
these extremes.
6. Recommended Operating Range
Parameter
Operating Temperature
Supply Voltage
Symbol
Min.
Ta
-40
VDD1
2.7
VDD2
VDD1
Typ.
Max.
Unit
Remarks
85
°C
3.0
3.3
V
Applied to the [AVDD],[PVDD] pins
5.0
5.5
V
Applied to the [CPVDD] pin
Note 1)
VDD1 and VDD2 can be driven individually within the Recommended Operating Range.
Note 2)
All specifications are applicable within the Recommended Operating Range (Operating Temperature /
Supply Voltage) .
MS1364-E-00
6
2012/1
[AK1548]
7. Electrical Characteristics
1. Digital DC Characteristics
Parameter
Symbol
Conditions
Min.
High level input voltage
Vih
Low level input voltage
Vil
High level input current 1
Iih1
Vih = VDD1=3.3V
-1
High level input current 2
Iih2
Vih = VDD1=3.3V
17
Low level input current
Iil
Vil = 0V, VDD1=3.3V
-1
High level output voltage
Voh
Ioh = -500μA
Low level output voltage
Vol
Iol = 500μA
Typ.
33
0.2×VDD1
V
Note 1)
1
μA
Note 2)
66
μA
Note 3)
1
μA
Note 1)
V
Note 4)
V
Note 4)
0.4
Note 2)
Applied to the [ CLK ], [ DATA ], [ LE] and [ PDN ] pins.
Note 3)
Applied to the [ TEST1 ] and [ TEST2 ] pins.
Note 4)
Applied to the [ LD ] pin.
7
Remarks
Note 1)
VDD1-0.4
Applied to the [ CLK ], [ DATA ], [ LE ], [ PDN ], [ TEST1 ] and [ TEST2 ] pins.
Unit
V
0.8×VDD1
Note 1)
MS1364-E-00
Max.
2012/1
[AK1548]
2. Serial Interface Timing
<Write-In Timing>
Tcsu
Tle su
LE
(Input)
Tch
Tle
Tcl
CLK
(Input)
Tsu
DATA
(Input)
D21
Thd
D20
6
D2
D1
D0
A1
A0
Serial Interface Timing Chart
Serial Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
Clock L level hold time
Tcl
25
ns
Clock H level hold time
Tch
25
ns
Clock setup time
Tcsu
10
ns
Data setup time
Tsu
10
ns
Data hold time
Thd
10
ns
LE setup time
Tlesu
10
ns
LE pulse width
Tle
25
ns
MS1364-E-00
8
Remarks
2012/1
[AK1548]
3. Analog Circuit Characteristics
The resistance of 27kΩ is connected to the [BIAS] pin.
VDD1＝2.7V to 3.3V, VDD2=VDD1 to 5.5V,–40°C≤Ta≤85°C, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Remarks
RF Characteristics
Input Sensitivity
-5
5
dBm
Input Frequency
1000
8000
MHz
REFIN Characteristics
Input Sensitivity
Input Frequency
0.4
VDD1
Vpp
REFIN≤200MHz
0.4
2
Vpp
REFIN>200MHz
10
300
MHz
300
MHz
104
MHz
Maximum Allowable Prescaler Output
Frequency
Phase Detector
Phase Detector Frequency
Charge Pump
Charge Pump Maximum Value
5200
μA
Charge Pump Minimum Value
650
μA
Icp TRI-STATE Leak Current
1
nA
0.7≤Vcpo≤VDD2-0.7, Ta=25°C
Vcpo : CP terminal voltage
Mismatch between Source and Sink Currents
(Note 1)
10
%
Vcpo=VDD2/2, Ta=25°C
Icp vs. Vcpo (Note 2)
15
%
0.5≤Vcpo≤VDD2-0.5, Ta=25°C
VREF1 Rise Time
10
ms
VREF2 Rise Time
10
ms
Regulator
Connect 470nF Capacitance at
VREF2 Pin
Connect 470nF Capacitance at
VREF2 Pin
Current Consumption
IDD1
10
μA
[PDN]=“0”
IDD2
16
26
mA
[PDN]=”1”, {PD}=0, IDD for VDD1
IDD3 (Note 4)
0.8
1.6
mA
[PDN]=”1”, {PD}=0, IDD for VDD2
IDD4
0.55
0.9
mA
[PDN]=”1”, {PD}=1, IDD for VDD1
Note 1) Mismatch between Source and Sink Currents : [(|Isink|-|Isource|)/{(|Isink|+|Isource|)/2}] × 100 [%]
Note 2) See “Charge Pump Characteristics - Voltage vs. Current”. Vcpo is the output voltage at [CP].
Icp vs. Vcpo : [{1/2×(|I1|-|I2|)}/{1/2×(|I1|+|I2|)}]×100 [%]
MS1364-E-00
9
2012/1
[AK1548]
Note 3) When [PDN] is ”1”, the total power supply current of the AK1548 is “IDD2+IDD3+ Charge pump current”.
Note 4) The current depending on Phase Detector Frequency isn’t included. IDD3 is the stationary current that
charge pump circuit consumes.
Resistance Connected to the BIAS Pin for Setting Charge Pump Output Current
Parameter
BIAS resistance
Min.
Typ.
Max.
Unit
22
27
33
kΩ
Remarks
Icp
I1
I2
I2
I1
Isink
Isource
0.5
CPVDD/2
CPVDD-0.5
Vcpo
Charge Pump Characteristics - Voltage (Vcpo) vs. Current (Icp)
MS1364-E-00
10
2012/1
[AK1548]
8. Block Functional Descriptions
1. Frequency Setup
The following formula is used to calculate the frequency setting for the AK1548.
Frequency setting (external VCO output frequency) = FPFD x N
Where :
N
: Dividing number N = [ (P x B) + A ]
FPFD
: Phase detector frequency FPFD = [REFIN] pin input frequency / R counter dividing number
P
: Prescaler Value (See < Address2>:{Pre[1:0]})
B
: B (Programmable) counter value (See <Address1>:{B[12:0]})
A
: A (Swallow) counter value (See <Address1>:{A[5:0]})
Calculation example
The output frequency of external reference frequency oscillator is 10MHz, and FPFD is 1MHz and VCO
frequency is 7400MHz.
AK1548 setting :
R (Reference counter)=10000000/1000000 = 10 (<Address0>:{R[13:0]}= “10”)
P=32 (<Address2>:{PRE[1:0]}=”10Bin”)
B=231 (<Address1>:{B[12:0]}=”231”)
A=8 (<Address1>:{A[5:0]}=”8”)
Frequency setting = 1M × [ (32×231) + 8] = 7400MHz
Lower limit for setting consecutive dividing numbers
In the AK1548, it is not possible to set consecutive dividing numbers below the lower limit.
(The lower limit is determined by a dividing number set for the prescaler.)
The following table shows an example where consecutive dividing numbers below the lower limit cannot be set.
The consecutive dividing numbers can be set when B ≥ P-1.
MS1364-E-00
11
2012/1
[AK1548]
P=8 (Dual modulus prescaler 8/9)
P
B[12:0] A[5:0]
N [ (P×B) + A ]
Remarks
8
6
6
54 55 cannot be set as an N divider.
8
7
0
56
8
7
1
57
・
・
8
・
・
56 or over can consecutively be set as an N divider.
・
100
・
This is the lower limit.
9
・
809
・
8
8191
62
65590
8
8191
63
65591
P=16 (Dual modulus prescaler 16/17)
P
B[12:0] A[5:0]
N [ (P×B) + A ]
16
14
14
16
15
0
240
16
15
1
241
・
・
16
・
4099
・
・
Remarks
238 239 cannot be set as an N divider.
This is the lower limit.
240 or over can consecutively be set as an N divider.
・
7
・
65591
・
16
8191
62
131118
16
8191
63
131119
P=32 (Dual modulus prescaler 32/33)
P
B[12:0] A[5:0]
N [ (P×B) + A ]
32
30
30
32
31
0
992
32
31
1
993
・
・
32
・
・
4097
・
990 991 cannot be set as an N divider.
This is the lower limit.
992 or over can consecutively be set as an N divider.
・
15
・
131119
・
32
8191
62
262174
32
8191
63
262175
MS1364-E-00
Remarks
12
2012/1
[AK1548]
P=64 (Dual modulus prescaler 64/65)
P
B[12:0] A[5:0]
N [ (P×B) + A ]
64
62
62
64
63
0
4032
64
63
1
4033
・
・
64
・
・
4096
・
4030 4031 cannot be set as an N divider.
This is the lower limit.
4032 or over can consecutively be set as an N divider.
・
31
・
262175
・
64
8191
62
524286
64
8191
63
524287
MS1364-E-00
Remarks
13
2012/1
[AK1548]
2．Charge Pump, Loop Filter
The current setting of charge pump and loop filter can switch with the built-in timer for Fast Lock.
Phase Detector
up
down
Loop Filter
R3
CP
C1
R2
VCO
C3
Timer
C2
Loop Filter Schematic
The charge pump current for normal operation (CP1) is determined by the setting in {CP1[2:0]}, which is a 3-bit
address of {D[15:13]} in <Address2> and a value of the resistance connected to the [BIAS] pin. The charge pump
current for the Fast Lock Up mode operation (CP2) is determined by the setting in {CP2[2:0]}, which is a 3-bit
address of D[18:16] in <Address2> and a value of the resistance connected to the [BIAS] pin.
The following formula shows the relationship among the resistance value, the register setting and the electric
current value.
charge pump minimum current (Icp_min) [A] =17.46 / Resistance connected to the BIAS pin [Ω]
charge pump current (Icp) [A] = Icp_min [A] × ({CP1} or {CP2} setting +1)
The allowed value range for the resistance connected to the [BIAS] pin is from 22 to 33kΩ for both normal and
Fast Lock Up mode operations.
MS1364-E-00
14
2012/1
[AK1548]
3. Fast Lock Up Mode
Setting {FAST[1:0]} in <Address2> to “11Bin” and {CPGAIN} in <Address1> to “1” enables the Fast Lock Up mode
for the AK1548.
The Fast Lock Up mode is enabled only during the time period set by the timer according to the counter value in
{TIMER[3:0]} in <Address2>. The charge pump current is set to the value specified by {CP2}. When the specified
time period elapses, the Fast Lock Up mode operation is switched to the normal operation, and {CPGAIN} in
<Address1> is reset to “0”.
{TIMER[3:0]} in <Address2> is used to set the time period for this mode. The following formula is used to calculate
the time period :
Switchover time = 1 /FPFD × Counter Value
Counter Value = 3 + (Timer[3:0] setting × 4)
Fast Lock Up time
specified by the timer
Operation mode
Normal
Fast Lock Up
Normal
Charge pump current
CP1
CP2
CP1
Loop filter Switch
OFF
ON
OFF
Frequency setting （Write “1” into {CPGAIN} in <Address1>.）
Fast Lock Up Mode Timing Chart
MS1364-E-00
15
2012/1
[AK1548]
4．Lock Detect
Lock detect output can be selected by {LD[2:0]} in <Address2>. When {LD} is set to “101Bin", the phase detector
outputs an unmanipulated phase detection (comparison) result. (This is called “analog lock detect”.) When {LD} is
set to “001Bin”, the lock detect signal is output according to the on-chip logic. (This is called “digital lock detect”.)
The lock detect can be done as following:
The [LD] pin is in unlocked state (which outputs “LOW”) when a frequency setup is made.
In the digital lock detect, the [LD] pin outputs “HIGH” (which means the locked state) when a phase error smaller
than a cycle of [REFIN] clock (T) is detected for N times consecutively. When a phase error larger than T is
detected for N times consecutively while the [LD] pin outputs “HIGH”, then the [LD] pin outputs “LOW” (which
means the unlocked state). The counter value N can be set by {LDP} in <Address0>. The N is different between
“unlocked to locked” and “locked to unlocked”.
{LDP}
unlocked to locked
locked to unlocked
0
N=15
N=3
1
N=31
N=7
The lock detect signal is shown below:
Reference clock
PFD frequency signal
Divided clock of RF input signal
PFD output signal
This is ignored
because it cannot
be sampled.
ignored
Valid
Valid
ignored
The [LD] pin outputs HIGH when
a phase error smaller than T is
detected for N times consecutively.
LD Output
Case of “R = 1”
Reference clock
PFD frequency signal
Divided clock of RF input signal
Valid
PFD output signal
This is ignored
because it cannot
be sampled.
ignored
Valid
ignored
The [LD] pin outputs HIGH when
a phase error smaller than T is
detec ted for N times consecutively.
LD Output
Case of “R > 1”
Digital Lock Detect Operations
MS1364-E-00
16
2012/1
[AK1548]
Unlock ([LD]=LOW)
Flag=0
Phase Error < T
No
Yes
Flag = Flag+1
No
Flag > N
Yes
Lock ([LD]=HIGH)
Unlock to Lock Operation Flow
Address2 write
Lock ([LD]=HIGH)
Flag=0
Phase Error > T
No
Yes
Flag = Flag+1
No
Flag > N
Yes
Unlock ([LD]=LOW)
Lock to Unlock Operation Flow
MS1364-E-00
17
2012/1
[AK1548]
5．Reference counter
The reference input can be set with a dividing number in the range of 1 to 16383 using {R [13:0]}, which is an
14-bit address of {D[13:0]} in <Address0>. 0 cannot be set as a dividing number.
6．Prescaler
The dual modulus prescaler (P/P+1) and the swallow counter are used to provide a large dividing ratio.
The prescaler is set by {PRE[1:0]}, which is a 2-bit latch of {D[21:20]} in <Address2>.
{PRE[1:0]}=”00Bin”, P=8, Dual modulus prescaler 8/9
{PRE[1:0]}=”01Bin”, P=16, Dual modulus prescaler 16/17
{PRE[1:0]}=”10Bin”, P=32, Dual modulus prescaler 32/33
{PRE[1:0]}=”11Bin”, P=64, Dual modulus prescaler 64/65
The maximum prescaler output frequency is 300MHz. P should be set as “RF Input Frequency /P ≤ 300MHz”.
7．Power-down and Power-save mode
It is possible to operate in the power-down or power-save mode if necessary by using the external control pin.
Power On
Follow the power-up sequence.
Normal Operation
[PDN]
<Address2>
Function
{PD2}
{PD1}
“Low”
X
X
Power Down
“High”
X
0
Normal Operation
“High”
0
1
“High”
1
1
VBG & LDO : Power UP
Synthesizer Circuits : Asynchronous Power Down
VBG & LDO : Power UP
Synthesizer Circuits : Synchronous Power Down
X : Don’t care
MS1364-E-00
18
2012/1
[AK1548]
9. Register Map
Name
Data
Address
R Counter
0
0
0
1
Function
1
0
Initialization
1
1
N Counter (A and B)
D21 - D0
Name
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Addr
ess
R
Count
0
0
0
LDP
0
0
Low
Noise
0
R
[13]
R
[12]
R
[11]
R
[10]
R
[9]
R
[8]
R
[7]
R
[6]
R
[5]
R
[4]
R
[3]
R
[2]
R
[1]
R
[0]
0x0
N
Count
0
0
CP
GAIN
B
[12]
B
[11]
B
[10]
B
[9]
B
[8]
B
[7]
B
[6]
B
[5]
B
[4]
B
[3]
B
[2]
B
[1]
B
[0]
A
[5]
A
[4]
A
[3]
A
[2]
A
[1]
A
[0]
0x1
Func.
PRE
[1]
PRE
[0]
PD2
CP2
[2]
CP2
[1]
CP2
[0]
CP1
[2]
CP1
[1]
CP1
[0]
TIME TIME TIME TIME
FAST FAST
R
R
R
R
[1]
[0]
[3]
[2]
[1]
[0]
CP
HiZ
CP
POLA
LD
[2]
LD
[1]
LD
[0]
PD1
CNTR
0x2
RST
Initial.
PRE
[1]
PRE
[0]
PD2
CP2
[2]
CP2
[1]
CP2
[0]
CP1
[2]
CP1
[1]
CP1
[0]
TIME TIME TIME TIME
FAST FAST
R
R
R
R
[1]
[0]
[3]
[2]
[1]
[0]
CP
HiZ
CP
POLA
LD
[2]
LD
[1]
LD
[0]
PD1
CNTR
0x3
RST
MS1364-E-00
19
2012/1
[AK1548]
Notes for writing into registers
After powers on AK1548, the initial register value is not defined. It is required to write the data in all addresses in
order to commit it.
[Examples of writing into registers]
(Ex. 1) Power-On
-
Bring [PDN] to ”0 (Low)”
-
Apply VDD
-
Program Address0, Address1 and Address2
-
Bring [PDN] to ”1 (High)”
-
Program {PD1} in Address 2 to “0”
(Ex. 2) Changing frequency settings : Initialization
-
Program Address3
-
Program Address1
(Ex. 3) Changing frequency settings : Counter reset
-
Program Address2.
-
Program Address1
-
Program Address2.
As part of this, load “1” to both {PD1} and {CNTR_RST}.
As part of this, load “0” to both {PD1} and {CNTR_RST}.
(Ex. 4) Changing frequency settings : PDN pin method
-
Bring [PDN] to ”0 (Low)”
-
Program Address1
-
Bring [PDN] to ”1 (High)”
MS1364-E-00
20
2012/1
[AK1548]
10. Function Description - Registers
< Address0 : R Counter >
D[21:19]
D18
D[17:14]
D[13:0]
Address
0
LDP
0
R[13:0]
00
D[21:19], D[17:14] : These bits are set to the following for normal operation
D21
D20
D19
D17
D16
D15
D14
0
0
0
0
0
0
0
LDP : Lock Detect Precision
The counter value for digital lock detect can be set.
D18
0
1
MS1364-E-00
Function
Remarks
15 times Count
unlocked to locked
3 times Count
locked to unlocked
31 times Count
unlocked to locked
7 times Count
locked to unlocked
21
2012/1
[AK1548]
R[13:0] : Reference clock division number
The following settings can be selected for the reference clock division.
The allowed range is 1 (1/1 division) to 16383 (1/16383 division). 0 cannot be set.
The maximum frequency for FPFD is 104MHz.
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
Remarks
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Prohibited
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1/1 division
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1/2 division
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1/3 division
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1/4 division
1/16381
division
1/16382
division
1/16383
division
DATA
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MS1364-E-00
22
2012/1
[AK1548]
< Address1 : N Counter >
D[21:20]
D19
D[18:6]
D[5:0]
Address
0
CPGAIN
B[12:0]
A[5:0]
01
D21, D20 : These bits are set to the following for normal operation
D21
D20
0
0
CPGAIN : Sets the charge pump current
When {FAST[1:0]} is NOT ”11Bin” :
D19
Function
Remarks
0
CP1 is enabled
1
CP2 is enabled
When {FAST[1:0]} is ”11Bin” :
D19
Function
Remarks
0
CP1 is enabled
CP2 is enabled, also
1
Timer is enabled
B[12:0] : B (Programmable) counter value
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
Function
Remarks
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Prohibited
0
0
0
0
0
0
0
0
0
0
0
0
1
1 Dec
Prohibited
0
0
0
0
0
0
0
0
0
0
0
1
0
2 Dec
Prohibited
0
0
0
0
0
0
0
0
0
0
0
1
1
3 Dec
DATA
1
1
1
1
1
1
1
1
1
1
1
0
1
8189 Dec
1
1
1
1
1
1
1
1
1
1
1
1
0
8190 Dec
1
1
1
1
1
1
1
1
1
1
1
1
1
8191 Dec
MS1364-E-00
23
2012/1
[AK1548]
A[5:0] : A (Swallow) counter value
D5
D4
D3
D2
D1
D0
Function
0
0
0
0
0
0
0
0
0
0
0
0
1
1 Dec
0
0
0
0
1
0
2 Dec
0
0
0
0
1
1
3 Dec
Remarks
DATA
1
1
1
1
0
1
61 Dec
1
1
1
1
1
0
62 Dec
1
1
1
1
1
1
63 Dec
* Requirements for A[5:0] and B[12:0]
The data at A[5:0] and B[12:0] must meet the following requirements:
A[5:0] ≥ 0, B[12:0] ≥ 3, B[12:0] ≥ A[5:0]
See “Frequency Setup” in section “Block Functional Descriptions” for details of the relationship
between a frequency division number N and the data at A[5:0] and B[12:0].
MS1364-E-00
24
2012/1
[AK1548]
< Address2 : Function >
D[21:20]
D19
D[18:16]
D[15:13]
D[12:9]
D[8:7]
PRE[1:0]
PD2
CP2[2:0]
CP1[2:0]
TIMER[3:0]
FAST[1:0]
D6
D5
D[4:2]
D1
D0
Address
CPHIZ
CPPOLA
LD[2:0]
PD1
CNTR_RST
02
PRE[1:0] : Selects a dividing ratio for the prescaler
The prescaler value should be chosen so that the prescaler output frequency is always less than or
equal to 300MHz.
D21
D20
Function
Remarks
0
0
P=8, Dual modulus prescaler 8/9
0
1
P=16, Dual modulus prescaler 16/17
1
0
P=32, Dual modulus prescaler 32/33
1
1
P=64, Dual modulus prescaler 64/65
PD2, PD1 : Power Down Select
[PDN]
<Address2>
Function
{PD2}
{PD1}
“Low”
X
X
Power Down
“High”
X
0
Normal Operation
“High”
0
1
“High”
1
1
VBG & LDO : Power UP
Synthesizer Circuits : Asynchronous Power Down
VBG & LDO : Power UP
Synthesizer Circuits : Synchronous Power Down
X : Don’t care (recommended “0”)
{PD2}=1 and {PD1}=1 : Synthesizer circuits powers down at the timing when the Phase detector
frequency signal reverses.
{PD2}=0 and {PD1}=1 : Synthesizer circuits goes into Power Down during the rise up of LE signal that
latches 1 into {PD1}.
MS1364-E-00
25
2012/1
[AK1548]
CP2[2:0] : Charge pump current setting 2
CP1[2:0] : Charge pump current setting 1
AK1548 provides two setting for charge pump current. They can be set by {CP1} and {CP2}.
The following formula shows the relationship among the resistance value, the register setting and the
electric current that is used for LPF band calculation (tran_Icp).
tran_Icp [A] = Icp_min [A] × ({CP1} or {CP2} setting +1)
Charge pump minimum current (Icp_min)[A]
= (0.85×1.164×15) / Resistance connected to the BIAS pin [ohm]
The following table shows the typical tran_Icp for each status.
[Unit : μA]
tran_Icp (typical)
D18
D17
D16
Bias Resistance
D15
D14
D13
33 kΩ
27 kΩ
22 kΩ
0
0
0
450
550
675
0
0
1
900
1100
1350
0
1
0
1350
1650
2025
0
1
1
1800
2200
2700
1
0
0
2250
2750
3375
1
0
1
2700
3300
4050
1
1
0
3150
3850
4725
1
1
1
3600
4400
5400
Remarks
The following formula shows the relationship among the resistance value, the register setting and the
electric current that can be measured (Icp).
Icp [A] = Icp_min [A] × ({CP1} or {CP2} setting +1)
Charge pump minimum current (Icp_min)[A]
= (1.164×15) / Resistance connected to the BIAS pin [ohm]
The following table shows the typical tran_Icp for each status.
MS1364-E-00
26
2012/1
[AK1548]
[Unit : μA]
Icp (typical)
MS1364-E-00
D18
D17
D16
Bias Resistance
D15
D14
D13
33 kΩ
27 kΩ
22 kΩ
0
0
0
529
647
794
0
0
1
1058
1293
1587
0
1
0
1587
1940
2381
0
1
1
2116
2587
3175
1
0
0
2645
3233
3968
1
0
1
3175
3880
4762
1
1
0
3704
4527
5555
1
1
1
4233
5173
6349
27
Remarks
2012/1
[AK1548]
TIMER[3:0] : Sets the switchover time for CP2-to-CP1
This is enabled when {FAST[1:0]} is ”11Bin” and {[CPGAIN}=”1”.
The charge pump current is set into value {CP2[2:0]} designate during switchover time. It goes to be
{CP1[2:0]} setting value after the time out.
The following formula shows the relationship between the switchover time and the counter value.
Switchover time = 1/ FPFD × Counter Value
Counter Value = 3 + Timer[3:0] × 4
The following table shows the relationship between counter value and {TIMER[3:0]}.
MS1364-E-00
D12
D11
D10
D9
Function
0
0
0
0
3 Counts
0
0
0
1
7 Counts
0
0
1
0
11 Counts
0
0
1
1
15 Counts
0
1
0
0
19 Counts
0
1
0
1
23 Counts
0
1
1
0
27 Counts
0
1
1
1
31 Counts
1
0
0
0
35 Counts
1
0
0
1
39 Counts
1
0
1
0
43 Counts
1
0
1
1
47 Counts
1
1
0
0
51 Counts
1
1
0
1
55 Counts
1
1
1
0
59 Counts
1
1
1
1
63 Counts
28
Remarks
2012/1
[AK1548]
FAST[1:0] : Enables or disables the Fast Lock mode
When {FAST[1:0]} is ”11Bin”, {CPGAIN} of function latch is the Fast Lock mode bit. When Fast Lock is
enabled, charge pump current is set to the value of {CP2} setting during the switchover time under the
control of the timer counter. After the timeout, {CPGAIN} is reset into “0” and charge pump current goes
to be {CP1} setting value.
D8
D7
X
0
0
1
1
{CPGAIN}
Function
0
{CP1} is enabled
1
{CP2} is enabled
0
{CP1} is enabled
1
{CP2} is enabled
0
{CP1} is enabled
1
1
Remarks
{CP2} is enabled, and
{CPGAIN} is reset to “0” after
switchover operates.
timeout.
CPHIZ : TRI-STATE output setting for charge pump
D6
Function
0
Charge pumps are activated.
1
TRI-STATE
Note 1)
Remarks
Use this setting for normal operation.
Note 1)
The charge pump output is turned OFF and put in the high-impedance (Hi-Z)
state.
CPPOLA : Selects positive or negative output polarity for CP1 and CP2
MS1364-E-00
D5
Function
0
Negative
1
Positive
Remarks
29
2012/1
[AK1548]
High
VCO frequency
Positive
Negative
Low
Low
Charge pump output voltage
High
LD ： Selects output from [LD] pin
D4
D3
D2
Function
0
0
1
Digital lock detect
1
0
1
Analog lock detect
Remarks
CNTR_RST : Counter Reset
D0
Function
Remarks
0
Normal operation
1
R and N counters are reset.
< Address3 : Initialization >
This function is same as <Address2>.
When this register is accessed, the following occurs :
-
Address2 is loaded.
-
An internal pulse resets the R counter, N counter and {TIMER} settings to load-state conditions, and also
charge pump to Tri-state.
-
Writing Address1 activates the R and N counter, {TIMER} and charge pump. {TIMER} is enabled when
{FAST}=”11Bin” and {CPGAIN}=“1”.
MS1364-E-00
30
2012/1
[AK1548]
11. IC Interface Schematic
No.
Pin name
I/O
R0(Ω)
11
PDN
I
300
12
CLK
I
300
13
DATA
I
300
14
LE
I
300
2
TEST1
I
300
10
TEST2
I
300
Function
Cur(μA)
Digital input pin
R0
Digital input pin (Pull-Down)
R0
100kΩ
15
LD
O
8
REFIN
I
Digital output pin
300
Analog input pin
R0
19
BIAS
IO
300
7
VREF1
IO
300
17
VREF2
IO
300
MS1364-E-00
Analog input/output pin
R0
31
2012/1
[AK1548]
No.
Pin name
I/O
20
CP
O
4
RFINN
I
12k
20
5
RFINP
I
12k
20
R0(Ω)
Function
Cur(μA)
Analog output pin
Analog input pin (RF input pin)
R0
MS1364-E-00
32
2012/1
[AK1548]
12. Recommended Connection Schematic of Off-Chip Component
1.
Power Supply Pins
LSI
PVDD
0.01μF
100pF
10μF
CPVDD
0.01μF
100pF
10μF
AVDD
0.01μF
100pF
10μF
2.
VREF1, VREF2
LSI
VREF1
220nF±10%
VREF2
470nF±10%
MS1364-E-00
33
2012/1
[AK1548]
3.
TEST1, TEST2
LSI
TEST1,2
4.
REFIN
LSI
REFIN
100pF±10%
5.
RFINP、RFINN
LSI
VCO Output
RFINP
51Ω
100pF±10%
RFINN
100pF±10%
6.
BIAS
MS1364-E-00
34
2012/1
[AK1548]
LSI
BIAS
22kΩ~33kΩ
MS1364-E-00
35
2012/1
[AK1548]
13. Block Power-Up Timing Chart (Recommended Flow)
VDD1, VDD2
PDN should be risen up after {PD1}=1 write in.
PDN
10ms
LDO
1.9V
0V
Register value defined
Register Writing
Address2
Address0
Address1
Address2
{PD1}=1
Setting
Setting
{PD1}=0
Hi-Z
CP
{PD1}=0 write in
Output
Power-Up Sequence (PDN control case)
Note)
After powers on, the initial setting of registers is undefined. It is required to write in Address0,
1 and 2 to settle them. It is recommended that [PDN] pin is risen up after Address2 {PD1}=1
write in. It takes about 10ms from PDN rise-up to LDO rise-up. The power-up by register
({PD1}=0 write in) should be done after LDO rise-up.
MS1364-E-00
36
2012/1
[AK1548]
VDD1,VDD2
PDN
10ms
LDO
1.9V
0V
Register value defined
Register Writing
Address2
{PD1}=1
Address0 Address1
Setting
Setting
{PD1}=0 write in
Address2
{PD1}=0
Hi-Z
CP
Output
undefined
Power-Up Sequence (VDD1/VDD2/PDN simultaneous power-up)
Note)
After powers on, the initial setting of registers is undefined. It is required to write in Address0,
1 and 2 to settle them. It takes about10ms from PDN rise-up to LDO rise-up. The power-up
by register ({PD1}=0 write in) should be done after LDO rise-up.
MS1364-E-00
37
2012/1
[AK1548]
14. Frequency Change Timing Chart (Recommended Flow)
High
VDD1,VDD2
High
PDN
Register Writing
CP
Address2
Address0
Address1
Address2
{PD1}=1
Setting
Setting
{PD1}=0
Hi-Z
Output1
Output2
Frequency Change Sequence ({PD1} control)
High
VDD1,VDD2
High
PDN
Register Writing
Address3
Address0
Address1
{PD1}=0
Setting
Setting
Hi-Z
CP
Output2
Output1
Frequency Change Sequence (Initialization Register control)
Note)
The data on Address3 is same as Address2, but {PD1} should be set “0”. Writing in Address3
puts CP output to Hi-Z. The rise-up of LE signal at writing in Address1, which is subsequent
frequency setting up sequence, is trigger for CP Output.
MS1364-E-00
38
2012/1
[AK1548]
Typical Evaluation Board Schematic
RFOUT
AK1548
Loop Filter
REFIN
18Ω
VCO
CP
C1
R2
C3
VREF1
220nF
18Ω
R3
100pF
100pF
18Ω
C2
VREF2
470nF
BIAS
27kΩ
Note1)
RFINP
100pF
100pF
RFINN
51Ω
Although it is no problem that both of [TEST1] and [TEST2] are open, it is recommended that they should
be connected to ground.
Note2)
Although it is no problem that Exposed Pad at the center of the backside is open, it is recommended that it
should be connected to ground.
MS1364-E-00
39
2012/1
[AK1548]
15. Outer Dimensions
Note) The exposed pad at the center of the backside should be connected to ground.
MS1364-E-00
40
2012/1
[AK1548]
16. Marking
a.
Style
：
QFN
b.
Number of pins
：
20
c.
A1 pin marking
：
●
d.
Product number
：
1548
e.
Date code
：
YWWL (4 digits)
Y
： Lower 1 digit of calendar year
(Year 2012-> 2, 2013-> 3 ...)
WW ： Week
L
： Lot identification, given to each product lot which is made in a week
(A, B, C…)
→ LOT ID is given in alphabetical order
1548
YWWL
(d)
(e)
●(c)
MS1364-E-00
41
2012/1
[AK1548]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi
Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor
products. You are fully responsible for the incorporation of these external circuits, application circuits,
software and other related information in the design of your equipments. AKM assumes no responsibility for
any losses incurred by you or third parties arising from the use of these information herein. AKM assumes
no liability for infringement of any patent, intellectual property, or other rights in the application or use of
such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life
support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use,
except for the use approved with the express written consent by Representative Director of AKM. As used
here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage
to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold
AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
MS1364-E-00
42
2012/1