廖 R 19 ， 51 8 QQ : 71 44 IT6211 58 5 Single Chip LVDS Transmitter 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 Preliminary Datasheet IT6211 General Description The IT6211 LVDS transmitter converts 28 bits (8-bits/color, 3 control bits(DE, H/VSync and 1 dummy bit) of Low Voltage TTL data into 4 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock rate of 廖 R 150MHz, each LVDS differential data pair speed is 1050Mbps, providing a total throughput of 4.2Gbps. 19 ， Features 51 8 • Support 10MHz to 150MHz input clock rates • Up to 4.2Gbps bandwidth 71 44 • Narrow bus reduces cable size • Support Reduced swing LVDS for Low EMI • 200mV/350mV swing LVDS selectable QQ : • Supports single 3.3V power supply • 3.3V to 1.8V Low Voltage TTL tolerant Input 58 5 • Cycle-to-cycle jitter rejection 34 1 • PLL requires No external components • Support Spread Spectrum Clock Generator 66 4 • Power-Down Mode 18 • Clock Edge Programmable l: • Low profile 56 Lead TSSOP Package(8.1mm x 14mm), or 56 balls BGA Package (4.5mm x 7mm) 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te Block Diagram Feb.-2013 Rev:0.91 www.ite.com.tw 1 IT6211 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R Pin diagram (56 Lead TSSOP): 深 圳 市 金 合 讯 科 TTL inputs to LVDS outputs mapping Feb.-2013 Rev:0.91 www.ite.com.tw 2 IT6211 6 A GND PCLK TC6 TC4 TD6 TC3 B GND PVDD33 PDWN TC5 TC2 TC1 C TDB TD GND OVDD1833 GND TC0 D TCLKB TCLK GND RFCLK TB6 E TCB TC F AVDD33 GND G TBB TB H TAB TA J TD0 K QQ : TD5 TD4 GND TB4 RS TB2 TB3 GND TD2 VCC33 TD3 TA0 TA3 TA5 GND TB1 TA2 TA4 TD1 TA6 TB0 18 66 4 34 1 TB5 廖 R 5 19 ， 4 51 8 3 71 44 2 58 5 1 技 有 Ball diagram (56 Balls BGA): (Top View) 限 深 圳 市 金 合 讯 科 TA1 公 司 ， Te l: GND Feb.-2013 Rev:0.91 www.ite.com.tw 3 IT6211 RGB data inputs to TTL input pin mapping 8-bits (R[7:0], G[7:0], B[7:0]) VESA TA0 R2 R0 R0 TA1 R3 R1 R1 TA2 R4 R2 R2 TA3 R5 R3 R3 TA4 R6 R4 R4 TA5 R7 R5 R5 TA6 G2 G0 G0 TB0 G3 G1 G1 TB1 G4 G2 G2 TB2 G5 G3 G3 TB3 G6 G4 G4 TB4 G7 G5 G5 TB5 B2 B0 TB6 B3 B1 TC0 B4 B2 TC1 B5 B3 B3 TC2 B6 B4 B4 TC3 B7 B5 B5 TC4 HSYNC HSYNC HSYNC TC5 VSYNC VSYNC VSYNC DE DE DE R0 R6 TD1 R1 R7 TD2 G0 G6 TD3 G1 G7 TD4 B0 B6 TD5 B1 B7 TD6 RSVD RSVD 合 讯 科 19 ， 51 8 71 44 QQ : 58 5 34 1 66 4 B0 18 l: Te ， 公 限 技 有 TD0 廖 R JEIDA TC6 B1 B2 深 圳 市 金 6-bits[5:0] 司 Input Data pin Feb.-2013 Rev:0.91 www.ite.com.tw 4 IT6211 Pin Description Type TA+, TA- 47, 48 H2,H1 LVDS OUT TB+, TB- 45, 46 G2,G1 LVDS OUT TC+, TC- 41, 42 E2,E1 LVDS OUT TD+, TD- 37, 38 C2,C1 LVDS OUT TCLK+, TCLK- 39, 40 D2,D1 LVDS OUT 51, 52, 54, 55, J2,K1,K2,J3, 56, 3, 4 K3,J4,K5 6, 7, 11, 12, K6,J6,G5,G6, 14, 15, 19 F6,E5,D5 20, 22, 23, 24, C6,B6,B5,A6, 27, 28, 30 A4,B4,A3 50, 2, 8, 10, J1,K4,H4,H6, 16, 18, 25 E6,D6,A5 CLKIN 31 A2 /PDWN 32 B3 ENSSC 33 Description 廖 R Pin number 19 ， Pin name 公 1 34 1 IN 58 5 Pixel data inputs. 66 4 IN IN IN IN 讯 科 合 RFCLK H: Normal operation, L: Power down H: enable spread spectrum clock L: disable spread spectrum clock G4 IN VCC => 350mV GND => 200mV Input Clock Triggering Edge Select. 17 D4 IN H: Falling edge L: Rising edge (Please refer to the Note) VCC33 9 H5 Power 3.3v Power Supply Pin for regulator OVDD1833 26 C4 Power 1.8v to 3.3V Power Supply Pin for IO 5, 13, 21, A1,B1,C3, 29, 53 D3,C5 AVDD33 44 F1 Power Power Supply Pin for LVDS Outputs. AVSS 36, 43, 49 F2,F5,G3 Ground Ground Pins for LVDS Outputs. PVDD33 34 B2 Power Power Supply Pin for PLL circuitry. 市 金 圳 深 Pixel clock input. LVDS swing control. 技 有 限 RS 71 44 IN 18 -- QQ : IN 司 TD0 ~ TD6 l: TC0 ~ TC6 Te TB0 ~ TB6 ， TA0 ~ TA6 LVDS clock out. 51 8 LVDS data out. OVSS Ground Ground Pins for TTL inputs and digital circuitry. Feb.-2013 Rev:0.91 www.ite.com.tw 5 IT6211 PVSS 35 H3,J5 Ground Ground Pin for PLL circuitry. 廖 R Note : QQ : 71 44 51 8 19 ， Fig A: If input clock CLKIN is aligned rising edge with central part of input data (Fig A) , please set Pin 17 RFCLK = Low. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 Fig B: Feb.-2013 Rev:0.91 www.ite.com.tw 6 IT6211 Electrical Specifications 1. Absolute Maximum Ratings Max Unit 3.3v Power Supply Pin for regulator -0.3 4.0 V OVDD1833 1.8v to 3.3V Power Supply Pin for IO -0.3 4.0 AVDD33 Power Supply Pin for LVDS Outputs. -0.3 4.0 PVDD33 Power Supply Pin for PLL circuitry -0.3 4.0 VI Input voltage -0.3 OVDD+0.3 V VO Output voltage -0.3 OVDD+0.3 V TJ Junction Temperature 125 °C TSTG Storage Temperature 150 °C ESD_HB Human body mode ESD sensitivity V V V QQ : -65 4000 廖 R VCC33 Typ 19 ， Min. 51 8 Parameter 71 44 Symbol V 18 66 4 34 1 58 5 ESD_MM Machine mode ESD sensitivity 200 V Notes: 1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device. 2. Refer to Functional Operation Conditions for normal operation. 2. Functional Operation Conditions Parameter Min. Typ Max Unit VCC33 3.3v Power Supply Pin for regulator 2.97 3.3 3.63 V OVDD1833 1.8v to 3.3V Power Supply Pin for IO 1.62 1.8/2.5/3.3 3.63 V AVDD33 Power Supply Pin for LVDS Outputs. 2.97 3.3 3.63 V PVDD33 Power Supply Pin for PLL circuitry 2.97 3.3 3.63 V VCCNOISE Supply noise 100 mVpp TA Ambient temperature 75 °C 技 有 限 公 司 ， Te l: Symbol 25 °C/W 深 圳 市 金 合 讯 科 Junction to ambient thermal resistance Θja Notes: OVDD1833, AVDD33, PVDD33 and VCC33 should be regulated. 0 Feb.-2013 Rev:0.91 www.ite.com.tw 7 IT6211 Unit VCC33 current under normal/Reduced 25MHz 3.088 3.088 mA swing operation 75MHz 8.079 8.077 mA 108MHz 10.61 10.612 mA 135MHz 13.161 13.16 mA 148.5MHz 14.41 14.38 mA AVDD33 current under normal/Reduced 25MHz 45 33.81 mA swing operation 75MHz 44.93 33.73 mA 108MHz 44.9 33.8 mA 135MHz 44.9 33.8 mA 148.5MHz 44.9 33.75 mA 25MHz 3.195 3.195 mA 75MHz 10.055 10.058 mA 108MHz 8.234 8.234 mA 135MHz 10.753 10.751 mA 148.5MHz 12.09 12.09 mA IVDD33_SUM_OP = IVCC33_OP + IAVDD33_OP + 25MHz 51.283 40.093 mA IPVDD33_OP 75MHz 63.064 51.865 mA 108MHz 63.744 52.646 mA 135MHz 68.814 57.711 mA 148.5MHz 71.4 60.22 mA 25MHz 0.267 0.267 mA 75MHz 0.394 0.394 mA 108MHz 0.528 0.528 mA 135MHz 0.624 0.624 mA 148.5MHz 0.754 0.754 mA 25MHz 170.115 133.19 mW normal/Reduced swing operation 75MHz 209.411 172.45 mW ( OVDD1833=3.3 V ) 108MHz 212.098 175.47 mW 135MHz 229.145 192.51 mW 148.5MHz 238.108 201.21 mW OVDD1833 current under normal/Reduced 25MHz 0.107 0.107 mA swing operation ( OVDD1833=1.8 V ) 75MHz 0.157 0.157 mA 108MHz 0.211 0.211 mA 135MHz 0.249 0.249 mA PVDD33 current under normal/Reduced l: 司 ， Te IVDD33_SUM_OP 18 66 4 34 1 swing operation 限 公 OVDD1833 current under normal/Reduced 技 有 swing operation ( OVDD1833=3.3 V ) 讯 科 IOVDD33_OP 深 圳 市 金 合 PW TOTAL_OVDD33_OP Total power consumption under IOVDD18_OP 19 ， 廖 R RS=0 51 8 IVCC33_OP IPVDD33_OP RS=1 71 44 Parameter QQ : Symbol IAVDD33_OP PIXELCLK 58 5 Operation Supply Current Specification 1. Normal Active Mode: (Worst Case Pattern) Feb.-2013 Rev:0.91 www.ite.com.tw 8 IT6211 0.302 0.302 mA 25MHz 169.427 132.5 mW normal/Reduced swing operation 75MHz 208.394 171.44 mW ( OVDD1833=1.8 V ) 108MHz 210.735 174.11 mW 135MHz 227.534 190.89 mW 148.5MHz 236.164 199.27 19 ， PW TOTAL_OVDD18_OP Total power consumption under 廖 R 148.5MHz mW QQ : 71 44 51 8 Notes: 1. Typ: VCC33=3.3V, AVDD33=3.3V, PVDD33=3.3V, OVDD1833=1.8V~3.3V 2. PIXELCLK refer to the video clock PIXELCLK= 25.175MHz: 640x480@60Hz PIXELCLK=75MHz:1024x768@70Hz PIXELCLK=108MHz: 1280x1024@60Hz PIXELCLK=135MHz: 1280x1024@75Hz PIXELCLK=148.5MHz: 1920x1080p@60Hz 3. PW TOTAL_OVDD18_OP and PWTOTAL_OVDD33_OP are calculated by multiplying the supply currents with their corresponding supply voltage and summing up all the items. Typ Unit 0.301 mA OVDD1833 current under power done mode 0.004 mA IAVDD33_OP AVDD33 current under power done mode 0.115 mA IPVDD33_OP PVDD33 current under power done mode 0.276 mA PW TOTAL_OP Total power consumption power done mode 2.2968 mW Parameter IVCC33_OP VCC33 current under power done mode IOVDD1833_OP 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 Symbol 34 1 58 5 2. Stand By Mode: (PDWN set to low, Data input set to low) DC Electrical Specification Under functional operation conditions Feb.-2013 Rev:0.91 www.ite.com.tw 9 IT6211 Pin Type LVTTL VT Min. 2.0 Typ LVTTL Switching threshold 1 LVTTL all VIN=5.5V or 0 ±5 IOZ Tri-state output leakage current1 all VIN=5.5V or 0 ±10 250 Normal Swing RS=VCC RL = 100 Ω, Reduced swing RS=GND Common Mode Voltage LVDS IOS Output Short Circuit Current LVDS RL = 100 Ω 58 5 VOC V 100 V µA µA 200 450 mV 300 mV 1.375 V -24 mA QQ : LVDS 350 71 44 RL = 100 Ω, Differential Output Voltage 0.8 51 8 Input leakage current VOD Unit V 1.5 IIN 1 Max 廖 R Input low voltage1 VIL Conditions 19 ， Symbol Parameter VIH Input high voltage1 1.125 VOUT = 0V, 司 ， Te l: 18 66 4 34 1 RL = 100 Ω Temperature Range Package Type Green/Pb free Option IT6211N -20~70 56-pin TSSOP Green IT6211VG -20~70 56-ball BGA Green 深 圳 市 金 合 讯 科 Model 技 有 限 公 Ordering Information Physical Dimensions: 56 Lead TSSOP Feb.-2013 Rev:0.91 www.ite.com.tw 10 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R IT6211 Physical Dimensions: 56 balls BGA Feb.-2013 Rev:0.91 www.ite.com.tw 11 l: Te ， 司 公 限 技 有 讯 科 合 市 金 圳 深 58 5 34 1 66 4 18 QQ : 71 44 51 8 19 ， 廖 R IT6211 Feb.-2013 Rev:0.91 www.ite.com.tw 12