LVDS Interface ICs 35bit LVDS Transmitter 35:5 Serializer BU8254KVT ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI. ●Features ■35bits data of parallel LVCMOS level inputs are converted to five channels of LVDS data stream. ■30bits of RGB data and 5bits of timing and control data(HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted up to 784Mbps effective rate per LVDS channel. ■Support clock frequency from 8MHz up to 112MHz. ■Support consumer video format including 480i, 480P, 720P and 1080i as well. ■Clock edge selectable ■Power down mode ■Support spread spectrum clock generator. ■Support reduced swing LVDS for low EMI. ■30bit LVDS receiver is recommended to use BU8255KVT. ●Applications Flat Panel Display ●Precaution ■This chip is not designed to protect from radioactivity. ■The chip is made strictly for the specific application or equipment. Then it is necessary that the unit is measured as need. ■This document may be used as strategic technical data which subjects to COCOM regulations. Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If there is any uncertainty in translation version of this document, official version takes priority. Jun.2008 ●Block Diagram LVCMOS Input LVDS Output PLL ＋ － Parallel to Serial ＋ － TA P/N Parallel to Serial ＋ － TB P/N Parallel to Serial ＋ － TC P/N Parallel to Serial ＋ － TD P/N Parallel to Serial ＋ － TE P/N CLKIN (8～112MHz) 7 TA6-TA0 7 TB6-TB0 7 TC6-TC0 7 TD6-TD0 7 TE6-TE0 RS RF XRST Figure-1 Block Diagram 2 / 20 TCLK P/N (8～112MHz) ●TQFP64V Package Outline and Specification Product No. BU8254KVT Lot No. 1PIN MARK Figure–2 TQFP64V Package Outline and Specification 3 / 20 TB4 TB3 TB2 RS TB1 TB0 TA6 GND TA5 TA4 TA3 TA2 TA1 46 45 44 43 42 41 40 39 38 37 36 35 34 TA0 GND 47 33 TB5 48 ●Pin configuration TB6 49 32 LVDS GND TC0 50 31 TAN VDD 51 30 TAP TC1 52 29 TBN TC2 53 28 TBP TC3 54 27 LVDS VDD TC4 55 26 LVDS GND GND 56 25 TCN TC5 57 24 TCP TC6 58 23 TCLKN TDO 59 22 TCLKP RF 60 21 TDN TD1 61 20 TDP TD2 62 19 TEN TD3 63 18 TEP TD4 64 17 LVDS GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TD5 GND TD6 TE0 TE1 TE2 VDD TE3 TE4 GND TE5 CLK IN XRST PLL GND PLL VDD TE6 64-Pin TQFP (Top View) Figure-3 Pin Diagram (Top View) 4 / 20 ●Pin Description Table 1 : Pin Description Pin Name Pin No. TAP, TAN 30,31 TBP, TBN 28,29 TCP, TCN 24,25 TDP, TDN 20,21 TEP, TEN TCLKP, TCLKN TA0～TA6 18,19 33,34,35,36,37,38,40 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN TB0～TB6 41,42,44,45,46,48,49 IN TC0～TC6 50,52,53,54,55,57,58 IN TD0～TD6 59,61,62,63,64,1,3 IN TE0～TE6 4,5,6,8,9,11,16 IN XRST 13 IN RS 22,23 43 Descriptions LVDS data out. LVDS clock out. Pixel data inputs. H : Normal operation, L : Power down (all outputs are Hi-Z) LVDS swing mode, VREF *1select. IN RS LVDS Swing VDD 0.6～1.4V GND 350mV 350mV 200mV Small Swing Input Support N/A RS-VREF N/A *1 VREF is Input Reference Voltage. RF 60 IN VDD 51,7 Power CLKIN 12 IN GND 2,10,39,47,56 Ground LVDS VDD 27 Power Input clock triggering edge select. H : Rising edge, L : Falling edge. Power supply pins for LVCMOS inputs and digital core. Clock input. Ground pins for LVCMOS inputs and digital core. Power supply pins for LVDS outputs. LVDS GND 17,26,32 Ground Ground pins for LVDS outputs. PLLVDD 15 Power Power supply pin for PLL core. PLLGND 14 Ground Ground pins for PLL core. 5 / 20 ●Electrical characteristics ■Rating Table 2 : Absolute Maximum Rating Parameter Symbol Supply Voltage Rating Units Min Max VDD -0.3 4.0 V Input Voltage VIN -0.3 VDD+0.3 V Output Voltage VOUT -0.3 VDD+0.3 V Storage Temperature Range Tstg -55 125 ℃ Table 3 : Package Power PACKAGE Power Dissipation (mW) De-rating (mW/℃) *1 700 7.0 1000*2 10.0*2 TQFP64V *1:At temperature Ta >25℃ *2:Package power when mounting on the PCB board. The size of PCB board :70×70×1.6（mm3） The material of PCB board :The FR4 glass epoxy board.(3% or less copper foil area) (It is recommended to apply the above package power requirement to PCB board when the small swing input mode is used) Table 4 : Recommended Operating Conditions Parameter Supply Voltage Operating Temperature Range Rating Symbol VDD Topr Units Conditions Min Typ Max 3.0 3.3 3.6 V VDD,LVDSVDD,PLLVDD -20 - 85 ℃ Clock frequency from 8MHz up to 90MHz 0 - 70 ℃ Cock frequency from 90MHz up to 112MHz 6 / 20 ■DC characteristics Table 5 : LVCMOS DC Specifications（VDD=3.0V～3.6V, Ta=-20℃～85℃） Rating Symbol Parameter Units Min Typ Max Conditions VIH High Level Input Voltage VDD×0.8 - VDD V VIL Low Level Input Voltage GND - VDD×0.2 V VIHRS High Level Input Voltage VDD×0.8 - VDD VILRS Low Level Input Voltage GND - 0.2 VDDQ*1 Small Swing Voltage 1.2 - 2.8 V VREF Input Reference Voltage - VDDQ/2 - - Small Swing(RS=VDDQ/2) VDDQ/2 +200mV - - V VREF=VDDQ/2 VSL*2 Small Swing High Level Input Voltage Small Swing Low Level Input Voltage - - VDDQ/2 -200mV V VREF=VDDQ/2 IINC Input Current - - ±10 μA 0V≤VIN≤VDD VSH*2 exclude RS pin RS pin *1: VDDQ voltage defines max voltage of small swing input. It is not an actual input voltage. *2: Small swing signal is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0] TE[6:0], CLKIN. Table 6 : LVDS Transmitter DC Specifications（VDD=3.0V～3.6V, Ta=-20℃～85℃） Rating Symbol Parameter Units Conditions Min Typ Max 250 350 450 mV 100 200 300 mV Change in VOD between complementary output states - - 35 mV VOC Common Mode Voltage 1.125 1.25 1.375 V ΔVOC Change in VOC between complementary output states - - 35 mV IOS Output Short Circuit Current - - -24 mA VOUT=0V, RL=100Ω IOZ Output TRI-STATE Current - - ±10 μA XRST=0V, VOUT=0V to VDD VOD Differential Output Voltage ΔVOD 7 / 20 RL=100Ω Normal swing RS=VDD Reduced swing RS=GND RL=100Ω ■Supply Current Table 7 : Supply Current Symbol ITCCG ITCCW ITCCS Parameter Rating Units Typ Max 57 - mA 42 - mA 62 - mA 45 - mA - 10 μA Transmitter Supply Current Transmitter Supply Current Transmitter Power Down Supply Current 8 / 20 Conditions RL=100Ω,CL=5pF VDD=3.3V,RS=VDD Gray Scale Pattern RL=100Ω,CL=5pF VDD=3.3V,RS=GND Gray Scale Pattern RL=100Ω,CL=5pF VDD=3.3V,RS=VDD Worst Case pattern RL=100Ω,CL=5pF VDD=3.3V,RS=GND Worst Case pattern XRST=L f=85MHz f=85MHz f=85MHz f=85MHz Gray Scale Pattern CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 X=A,B,C,D,E Figure-4 Gray scale pattern Worst Case Pattern (Maximum Power condition) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 X=A,B,C,D,E Figure-5 Worst Case Pattern 9 / 20 ■AC characteristics Table 8 : Switching Characteristics Parameter Symbol Min Typ Max Units tTCIT CLK IN Transition time - - 5.0 ns tTCP CLK IN Period 8.93 - 125.0 ns tTCH CLK IN High Time 0.35tTCP 0.5tTCP 0.65tTCP ns tTCL CLK IN Low Time 0.35tTCP 0.5tTCP 0.65tTCP ns tTCD CLK IN to TCLK+/-Delay - tTCP - ns tTS LVSMOS Data Set up to CLK IN 2.5 - - ns tTH LVCMOS Data Hold from CLK IN 0 - - ns tLVT LVDS Transition Time - 0.6 1.5 ns tTOP1 Output Data Position 0 -0.2 0.0 +0.2 ns tTOP0 Output Data Position 1 tTOP6 Output Data Position 2 tTOP5 Output Data Position 3 tTOP4 Output Data Position 4 tTOP3 Output Data Position 5 tTOP2 Output Data Position 6 tTCP -0.2 7 tTCP -0.2 2 7 tTCP -0.2 3 7 tTCP -0.2 4 7 tTCP -0.2 5 7 tTCP 6 -0.2 7 tTCP 7 tTCP 2 7 tTCP 3 7 tTCP 4 7 tTCP 5 7 tTCP 6 7 tTCP +0.2 7 tTCP 2 +0.2 7 tTCP 3 +0.2 7 tTCP 4 +0.2 7 tTCP 5 +0.2 7 tTCP 6 +0.2 7 tTPLL Phase Locked Loop Set Time - - 10.0 10 / 20 ns ns ns ns ns ns ms ●AC Timing ■AC Timing Diagrams LVCMOS Input 90% 90% CLK IN 10% 10% tTCIT tTCIT LVDS Output Vdiff=(TAP)-(TAN) 80% TAP Vdiff CL RL 80% 20% 20% TAN tLVT LVDS Output Load LVCMOS Input tLVT tTCP tTCH CLKIN VDD/2 RF=L VDD/2 VDD/2 RF=H tTCL tTS Tx0-Tx6 VDD/2 tTH VDD/2 tTCD TCLKP VOC TCLKN Figure-6 AC Timing Diagrams 11 / 20 ■Small Swing Inputs tTCP tTCH RF=L CLKIN VDDQ/2 VDDQ/2 VDDQ/2 VREF RF=H tTCL tTS tTH VDDQ Tx0-Tx6 VDDQ/2 VDDQ/2 VREF GND tTCD TCLKP VOC TCLKN Figure-7 Small Swing Inputs 12 / 20 ■AC Timing Diagrams LVDS Output TCLK OUT (Differential) TAP/N TA6 TA5 TA4 TA3 TA2 TA1 TA0 TBP/N TB6 TB5 TB4 TB3 TB2 TB1 TB0 TCP/N TC6 TC5 TC4 TC3 TC2 TC1 TC0 TDP/N TD6 TD5 TD4 TD3 TD2 TD1 TD0 TEP/N TE6 TE5 TE4 TE3 TE2 TE1 TE0 Previous Cycle Next Cycle tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 Figure-8 AC Timing Diagrams ■Phase Locked Loop Set Time 2.0V XRST 3.6V 3.0V VDD tTPLL CLKIN Vdiff=0V TCLKP/N Figure-9 Phase Locked Loop Set Time 13 / 20 ●About the Power On Reset Power On Reset is not mandatory for this device. （The PD pin should be set to high level when Power On Reset procedure is not used.） VDD XRST BU8254KVT Figure–10 Terminal connection when Power On Reset is not used However, Power On Reset procedure is strongly recommend for internal logic initialization by following two methods. ① The method of using CR circuit. ② The method of using external specific IC. It is recommend to do enough examination for target application. V DD V DD VDD schottky barrier diode 10KΩ V T XRST 220Ω Be careful of temperature of the capacitor especially over and again. B characteristic ceramics and polymer aluminum are recommended. + XRST 2.2μF Internal Reset td td is approximately equal to 20ms when the left RC coleus are applied. Figure–11 Power On Reset by external a CR circuit V DD VDD power on IC (open drain output) V DD Detection voltage 220KΩ VDD XRST VOUT 0.1μF GND V T XRST Internal Reset B Characteristic ceramics. td Figure–12 Power On Reset by specific IC 14 / 20 + ●10bit LVCMOS Level Input Example: BU7986KUT ： Falling edge Normal swing Dual-in / Dual-out mode VDD 0.1uF 0.01uF VDD LVDS VDD 0.1uF 0.01uF GND R1[9:0] R1[9:0] G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 CONT21 CONT22 G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 LVDS GND TA1N TA1P TB1N TB1P TC1N BU7986KUT TC1P TCLKN CONT12 CONT21 CONT22 TCLKP TD1N TD1P TEST[3:0] TE1N TE1P TA2N MODE0 TA2P TB2N MODE1 TB2P TC2N XRST TC2P XRST TCLKN TCLKP VDD RS TD2N *1 TD2P TE2N R/F TE2P PCB(Transmitter) *1 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m V. 15 / 20 100Otwist pair Cable or PCB trace ●10bit LVCMOS Level Input Example: BU7986KUT ： Falling edge Normal swing Dual-in / Single-out mode VDD 0.1uF 0.01uF VDD LVDS VDD 0.1uF 0.01uF GND R1[9:0] R1[9:0] G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 CONT21 CONT22 G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 LVDS GND TA1N TA1P TB1N TB1P TC1N BU7986KUT TC1P CONT12 CONT21 CONT22 TCLKN TEST[3:0] TE1N TCLKP TD1N TD1P TE1P VDD TA2N MODE0 TA2P TB2N MODE1 TB2P TC2N XRST TC2P XRST TCLKN OPEN TCLKP VDD TD2N RS *1 TD2P TE2N R/F TE2P PCB(Transmitter) *1 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m V. 16 / 20 100Otwist pair Cable or PCB trace ●10bit LVCMOS Level Input Example: BU7986KUT ： Falling edge Normal swing Single-in / Dual-out mode VDD 0.1uF 0.01uF VDD LVDS VDD 0.1uF 0.01uF GND R1[9:0] R1[9:0] G1[9:0] B1[9:0] G1[9:0] B1[9:0] R2[9:0] LVDS GND TA1N G2[9:0] TA1P B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 HSYNC VSYNC DE CLK_IN CONT11 CONT12 TB1N TB1P TC1N BU7986KUT TC1P TCLKN TCLKP CONT21 CONT22 TD1N TD1P TE1N TEST[3:0] TE1P TA2N MODE0 TA2P TB2N VDD TB2P MODE1 TC2N TC2P XRST TCLKN XRST TCLKP VDD TD2N RS *1 TD2P TE2N TE2P R/F PCB(Transmitter) *1 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m V. 17 / 20 100Otwist pair Cable or PCB trace ●10bit LVCMOS Level Input Example: BU7986KUT ： Falling edge Normal swing Single-in / Single -out mode VDD 0.1uF 0.01uF VDD LVDS VDD 0.1uF 0.01uF GND R1[9:0] R1[9:0] G1[9:0] B1[9:0] G1[9:0] B1[9:0] R2[9:0] LVDS GND TA1N G2[9:0] TA1P B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 HSYNC VSYNC DE CLK_IN CONT11 CONT12 TB1N TB1P TC1N BU7986KUT TC1P TCLKN TCLKP CONT21 CONT22 TD1N TD1P TE1N TEST[3:0] TE1P TA2N VDD MODE0 TA2P TB2N VDD TB2P MODE1 TC2N TC2P XRST TCLKN XRST OPEN TCLKP VDD TD2N RS *1 TD2P TE2N TE2P R/F PCB(Transmitter) *1 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m V. 18 / 20 100Otwist pair Cable or PCB trace ●10bit Small Swing Input Example: BU8254KVT ： LVCMOS level input/Falling edge/Normal swing BU8255KVT ： Falling edge VDD F.Bead *3 VDD GND 0.1uF 0.01uF CLKIN R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 CLKIN TA0 TA1 TA2 TA3 TA4 TA5 TA6 TB0 TB1 TB2 TB3 TB4 TB5 TB6 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TE0 TE1 TE2 TE3 TE4 TE5 TE6 R0 R1 G0 G1 B0 B1 XRST LVDS VDD LVDD 0.1uF 0.01uF 0.1uF 0.01uF LVDS GND LGND PLL VDD PVDD PLL GND 0.1uF 0.01uF 0.1uF 0.01uF TAN 100Ω TAP TBN 100Ω TBP TCN 100Ω TCP BU8254KVT VDD F.Bead *3 TCLKN 100Ω TCLKP TDN 100Ω TDP TEN 100Ω TEP XRST RS *4 RA+ RBRB+ RCRC+ RCLKRCLK+ RDRD+ RERE+ 0.1uF 0.01uF CLKOUT R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 OPEN R0 R1 G0 G1 B0 B1 OPEN PD OE DK R/F R/F PCB(Transmitter) RA- CLKOUT RA0 RA1 RA2 RA3 RA4 RA5 RA6 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RD0 BU8255KVT RD1 RD2 RD3 RD4 RD5 RD6 RE0 RE1 RE2 RE3 RE4 RE5 RE6 PD OE 100Ωtwist pair Cable or PCB trace *4 PGND VDD GND PCB(Receiver) *3 : Recommended Parts: F.Bead : BLM18A-Series (Murata Manufacturing) *4 : RS pin acts as VREF input pin when input voltage is set to half of high level signal input. We recommend to locate by-pass condenser near the RS pin. VDD R1 15k RS pin. R2 5.6k C1=0.1uF Example for LVCMOS(1.8V input):(R1,R2)=(15kΩ,5.6kΩ) 19 / 20 TQFP64V <Dimension> <Packing information> 12.0 ± 0.3 10.0 ± 0.2 0.2 ± 0.1 1pin 17 16 0.125 ± 0.1 0.5 1000pcs Direction of product is fixed in a tray. 0.5 32 64 Tray(with dry pack) Quantity Direction of feed 33 49 1 1.0 ± 0.1 0.1 ± 0.1 12.0 ± 0.3 10.0 ± 0.2 48 Container 0.1 （Unit:mm) ※When you order , please order in times the amount of package quantity. Catalog No.08T240A '08.6 ROHM ©